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Merge branch 'refactor/rng_ll_c6' into 'master'

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refactor(rng): refactor to use hal/ll apis for c6

Closes IDF-12533

See merge request espressif/esp-idf!37319
This commit is contained in:
Gao Xu
2025-03-20 10:28:39 +08:00
parent ee87960c13 675fe44f1e
commit 728f95f498
10 changed files with 184 additions and 111 deletions
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112
components/bootloader_support/src/bootloader_random_esp32c6.c
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@@ -1,102 +1,58 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "esp_log.h"
static const uint32_t SAR2_CHANNEL = 9;
static const uint32_t PATTERN_BIT_WIDTH = 6;
static const uint32_t SAR1_ATTEN = 1;
static const uint32_t SAR2_ATTEN = 1;
#include "hal/regi2c_ctrl_ll.h"
#include "hal/adc_ll.h"
#include "hal/adc_types.h"
void bootloader_random_enable(void)
{
// pull SAR ADC out of reset
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
// enable SAR ADC APB clock
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
// enable ADC_CTRL_CLK (SAR ADC function clock)
REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
// set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
adc_ll_reset_register();
adc_ll_enable_bus_clock(true);
adc_ll_enable_func_clock(true);
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 2);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
adc_ll_regi2c_init();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
adc_digi_pattern_config_t pattern_config = {};
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_2_5;
pattern_config.channel = ADC_CHANNEL_1;
adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_2_5;
pattern_config.channel = ADC_CHANNEL_1;
adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, 2);
// create patterns and set them in pattern table
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
uint32_t pattern_two = (SAR2_CHANNEL << 2) | SAR1_ATTEN; // we want channel 9 with max attenuation
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
// Same as in C3
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
// set timer expiry (timer is ADC_CTRL_CLK)
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
// enable timer
REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
adc_ll_digi_set_clk_div(15);
adc_ll_digi_set_trigger_interval(200);
adc_ll_digi_trigger_enable();
}
void bootloader_random_disable(void)
{
// disable timer
REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
// Write reset value of this register
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
// Revert ADC I2C configuration and initial voltage source setting
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
adc_ll_digi_trigger_disable();
adc_ll_digi_reset_pattern_table();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
adc_ll_regi2c_adc_deinit();
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
// Set PCR_SARADC_CONF_REG to initial state
REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
adc_ll_digi_controller_clk_div(4, 0, 0);
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
}

4
components/bootloader_support/src/bootloader_random_esp32c61.c
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@@ -18,12 +18,12 @@ void bootloader_random_enable(void)
adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
regi2c_ctrl_ll_i2c_reset_set();
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
adc_ll_regi2c_adc_init();
adc_ll_regi2c_init();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);

2
components/bootloader_support/src/bootloader_random_esp32h2.c
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@@ -22,7 +22,7 @@ void bootloader_random_enable(void)
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
adc_ll_regi2c_adc_init();
adc_ll_regi2c_init();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);

7
components/esp_hw_support/port/esp32c6/pmu_init.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,7 @@
#include "soc/soc.h"
#include "soc/pmu_struct.h"
#include "hal/pmu_hal.h"
#include "hal/regi2c_ctrl_ll.h"
#include "pmu_param.h"
#include "esp_private/esp_pmu.h"
#include "soc/regi2c_dig_reg.h"
@@ -209,8 +210,8 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
void pmu_init(void)
{
/* Peripheral reg i2c power up */
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);

2
components/esp_hw_support/port/esp32c61/pmu_init.c
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@@ -210,7 +210,7 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
void pmu_init(void)
{
/* Peripheral reg i2c power up */
regi2c_ctrl_ll_i2c_reset_set();
regi2c_ctrl_ll_reset(false);
regi2c_ctrl_ll_i2c_periph_enable();
pmu_hp_system_init_default(PMU_instance());

91
components/hal/esp32c6/include/hal/adc_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -223,6 +223,15 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
}
}
/**
* Rest pattern table to default value
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = 0xffffff;
APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = 0xffffff;
}
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
*
@@ -613,6 +622,10 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
//Not used on ESP32C6
}
/*---------------------------------------------------------------
Calibration
---------------------------------------------------------------*/
/* ADC calibration code. */
/**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET).
@@ -665,11 +678,81 @@ static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
__attribute__((always_inline))
static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{
HAL_ASSERT(adc_n == ADC_UNIT_1);
uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF;
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else {
//C6 doesn't support ADC2, here is for backward compatibility for RNG
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
}
}
/**
* Set the SAR DTEST param
*
* @param param DTEST value
*/
__attribute__((always_inline))
static inline void adc_ll_set_dtest_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, param);
}
/**
* Set the SAR ENT param
*
* @param param ENT value
*/
__attribute__((always_inline))
static inline void adc_ll_set_ent_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, param);
}
/**
* Enable/disable the calibration voltage reference for ADC unit.
*
* @param adc_n ADC index number.
* @param en true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_calibration_ref(adc_unit_t adc_n, bool en)
{
//C6 doesn't support ADC2, here is for backward compatibility for RNG
if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, en);
} else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, en);
}
}
/**
* Init regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_init(void)
{
adc_ll_set_dtest_param(2);
adc_ll_set_ent_param(1);
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
adc_ll_enable_calibration_ref(ADC_UNIT_1, true);
adc_ll_enable_calibration_ref(ADC_UNIT_2, true);
}
/**
* Deinit regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_adc_deinit(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(0);
adc_ll_enable_calibration_ref(ADC_UNIT_1, false);
adc_ll_enable_calibration_ref(ADC_UNIT_2, false);
}
/*---------------------------------------------------------------

35
components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,6 +10,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#include "soc/pmu_reg.h"
#include "modem/modem_lpcon_struct.h"
#ifdef __cplusplus
@@ -111,6 +112,38 @@ static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
}
/**
* @brief Enable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
{
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Disable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
{
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Enter / Exit reset state
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_reset(bool enter)
{
if (enter) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {
// Normal working mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
}
#ifdef __cplusplus
}
#endif

18
components/hal/esp32c61/include/hal/adc_ll.h
View File

@@ -660,7 +660,7 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
__attribute__((always_inline))
static inline void adc_ll_set_dtest_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST , param);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, param);
}
/**
@@ -675,13 +675,13 @@ static inline void adc_ll_set_ent_param(uint32_t param)
}
/**
* Enable the SAR TOUT bus
* Enable/disable the calibration voltage reference for ADC unit.
*
* @param adc_n ADC index number.
* @param en true for enable
* @param en true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_encal_ref(adc_unit_t adc_n, bool en)
static inline void adc_ll_enable_calibration_ref(adc_unit_t adc_n, bool en)
{
//C61 doesn't support ADC2, here is for backward compatibility for RNG
if (adc_n == ADC_UNIT_1) {
@@ -695,13 +695,13 @@ __attribute__((always_inline))
/**
* Init regi2c SARADC registers
*/
static inline void adc_ll_regi2c_adc_init(void)
static inline void adc_ll_regi2c_init(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(1);
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
adc_ll_enable_encal_ref(ADC_UNIT_1, true);
adc_ll_enable_encal_ref(ADC_UNIT_2, true);
adc_ll_enable_calibration_ref(ADC_UNIT_1, true);
adc_ll_enable_calibration_ref(ADC_UNIT_2, true);
}
/**
@@ -712,8 +712,8 @@ static inline void adc_ll_regi2c_adc_deinit(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(0);
adc_ll_enable_encal_ref(ADC_UNIT_1, false);
adc_ll_enable_encal_ref(ADC_UNIT_2, false);
adc_ll_enable_calibration_ref(ADC_UNIT_1, false);
adc_ll_enable_calibration_ref(ADC_UNIT_2, false);
}
/*---------------------------------------------------------------

22
components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h
View File

@@ -129,19 +129,19 @@ static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
}
/**
* @brief Set regi2c reset
* @brief Enter / Exit reset state
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_i2c_reset_set(void)
static inline void regi2c_ctrl_ll_reset(bool reset_on)
{
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
/**
* @brief Clear regi2c reset
*/
static inline void regi2c_ctrl_ll_i2c_reset_clear(void)
{
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
if (reset_on) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {
// Normal working mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
}
#ifdef __cplusplus

2
components/hal/esp32h2/include/hal/adc_ll.h
View File

@@ -727,7 +727,7 @@ static inline void adc_ll_enable_tout_bus(adc_unit_t adc_n, bool en)
* Init regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_adc_init(void)
static inline void adc_ll_regi2c_init(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(1);