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Merge branch 'feature/update_esp32h2_memory_layout' into 'master'

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ESP32-H2: update esp32h2 memory layout

See merge request espressif/esp-idf!21930
This commit is contained in:
Wu Zheng Hui
2023-01-06 15:51:29 +08:00
parent ffea490cc7 05e37ba214
commit 751fa28919
3 changed files with 17 additions and 11 deletions
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16
components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -205,32 +205,34 @@ SECTIONS
}
/**
* 0x4083b6cc ------------------> _dram0_0_start
* Appendix: Memory Usage of ROM bootloader
*
* 0x4083ba78 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4084cfd0 ------------------> __stack_sentry
* 0x4084d380 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4084efd0 ------------------> __stack (pro cpu)
* 0x4084f380 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4084fb30 ------------------> _dram0_rtos_reserved_start
* 0x4084fee0 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4084fc04 ------------------> _dram0_rtos_reserved_end
* 0x4084ffc0 ------------------> _dram0_rtos_reserved_end
* | |
* 0x4084ffcc ------------------> _data_start_interface
* 0x4084ffc8 ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |

10
components/heap/port/esp32h2/memory_layout.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -65,8 +65,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x30000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //Block 4, can be remapped to ROM, can be used as trace memory
{ 0x40830000, 0x20000, SOC_MEMORY_TYPE_STACK_DRAM, 0x40830000}, //Block 9, can be used as trace memory
{ 0x40800000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level 0
{ 0x40810000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40810000}, //D/IRAM level 1
{ 0x40820000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level 2
{ 0x40830000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40830000}, //D/IRAM level 3
{ 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level 4
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level 4
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
#endif

2
components/soc/esp32h2/include/soc/soc.h
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@@ -211,7 +211,7 @@
#define SOC_DEBUG_HIGH 0x28000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4087c770
#define SOC_ROM_STACK_START 0x4084f380
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.