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Merge branch 'feat/h21_introduce_step2_3' into 'master'

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feat(esp32h21): add soc register header files (stage 2/8, part 3/3)

See merge request espressif/esp-idf!35492
This commit is contained in:
Gao Xu
2024-12-14 18:58:14 +08:00
parent e06c234625 d798f6f1a7
commit 7ff0a07d3d
49 changed files with 13751 additions and 4941 deletions
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4
components/bootloader_support/test_apps/.build-test-rules.yml
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@@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section:
enable:
- if: SOC_RTC_MEM_SUPPORTED == 1
reason: this feature is supported on chips that have RTC memory
disable:
- if: IDF_TARGET == "esp32h21"
temporary: true
reason: IDF-11534

692
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in Normal file
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@@ -0,0 +1,692 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_UART_SUPPORTED
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
config SOC_EFUSE_SUPPORTED
bool
default y
config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_PMU_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_32M
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_DIGI_RESULT_BYTES
int
default 4
config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_APB_BACKUP_DMA
bool
default n
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CACHE_FREEZE_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM
int
default 1
config SOC_CPU_INTR_NUM
int
default 32
config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
config SOC_INT_PLIC_SUPPORTED
bool
default y
config SOC_CPU_HAS_CSR_PC
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 4
config SOC_CPU_WATCHPOINTS_NUM
int
default 4
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex
default 0x80000000
config SOC_CPU_HAS_PMA
bool
default y
config SOC_CPU_IDRAM_SPLIT_USING_PMP
bool
default y
config SOC_CPU_PMP_REGION_GRANULARITY
int
default 4
config SOC_MMU_PERIPH_NUM
int
default 1
config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
int
default 1
config SOC_MMU_DI_VADDR_SHARED
bool
default y
config SOC_DS_SIGNATURE_MAX_BIT_LEN
int
default 3072
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
int
default 16
config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_AHB_GDMA_VERSION
int
default 1
config SOC_GDMA_NUM_GROUPS_MAX
int
default 1
config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 3
config SOC_ETM_GROUPS
int
default 1
config SOC_ETM_CHANNELS_PER_GROUP
int
default 50
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 28
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 27
config SOC_GPIO_OUT_RANGE_MAX
int
default 27
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000000FFF807F
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
config SOC_CLOCKOUT_HAS_SOURCE_GATE
bool
default y
config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_ANA_CMPR_NUM
int
default 1
config SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4
config SOC_MPI_OPERATIONS_NUM
int
default 3
config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_SPI_SUPPORT_CLK_PLL_F48M
bool
default y
config SOC_SPI_SUPPORT_CLK_RC_FAST
bool
default y
config SOC_SPI_SCT_SUPPORTED
bool
default y
config SOC_SPI_SCT_REG_NUM
int
default 14
config SOC_SPI_SCT_BUFFER_NUM_MAX
bool
default y
config SOC_SPI_SCT_CONF_BITLEN_MAX
hex
default 0x3FFFA
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
bool
default y
config SOC_SPI_MEM_SUPPORT_IDLE_INTR
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SPI_MEM_SUPPORT_WRAP
bool
default y
config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_DIVIDER
bool
default y
config SOC_SYSTIMER_SUPPORT_RC_FAST
bool
default y
config SOC_SYSTIMER_INT_LEVEL
bool
default y
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 1
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TIMER_GROUP_SUPPORT_RC_FAST
bool
default y
config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_MWDT_SUPPORT_XTAL
bool
default y
config SOC_EFUSE_DIS_PAD_JTAG
bool
default y
config SOC_EFUSE_DIS_USB_JTAG
bool
default y
config SOC_EFUSE_DIS_DIRECT_BOOT
bool
default y
config SOC_EFUSE_SOFT_DIS_JTAG
bool
default y
config SOC_EFUSE_DIS_ICACHE
bool
default y
config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
bool
default y
config SOC_EFUSE_ECDSA_USE_HARDWARE_K
bool
default y
config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
config SOC_SECURE_BOOT_V2_ECC
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 64
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_APM_CTRL_FILTER_SUPPORTED
bool
default y
config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
bool
default y
config SOC_ECDSA_USES_MPI
bool
default y
config SOC_UART_NUM
int
default 2
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_EXT1_WAKEUP
bool
default y
config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_MODEM_PD
bool
default y
config SOC_PM_SUPPORT_XTAL32K_PD
bool
default y
config SOC_PM_SUPPORT_RC32K_PD
bool
default y
config SOC_PM_SUPPORT_RC_FAST_PD
bool
default y
config SOC_PM_SUPPORT_VDDSDIO_PD
bool
default y
config SOC_PM_SUPPORT_TOP_PD
bool
default y
config SOC_PM_PAU_LINK_NUM
int
default 4
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default y
config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
config SOC_CLK_OSC_SLOW_SUPPORTED
bool
default y
config SOC_CLK_RC32K_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_LP_PLL
bool
default y
config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_RCC_IS_INDEPENDENT
bool
default y

91
components/soc/esp32h21/include/soc/boot_mode.h Normal file
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@@ -0,0 +1,91 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, SPI(or SDIO_V2)/UART0*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#define IS_0000(v) (((v)&0x0f)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
#define IS_0001(v) (((v)&0x0f)==0x01)
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
#define IS_0010(v) (((v)&0x0f)==0x02)
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
#define IS_0011(v) (((v)&0x0f)==0x03)
/*legacy SPI Boot*/
#define IS_0100(v) (((v)&0x0f)==0x04)
/*ATE/ANALOG Mode*/
#define IS_0101(v) (((v)&0x0f)==0x05)
/*SPI(or SDIO_V1) download Mode*/
#define IS_0110(v) (((v)&0x0f)==0x06)
/*Diagnostic Mode+UART0 download Mode*/
#define IS_0111(v) (((v)&0x0f)==0x07)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
/*do not include download mode*/
#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
/*all spi boot including spi/legacy*/
#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
/*all faster spi boot including spi*/
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
#if SUPPORT_SDIO_DOWNLOAD
/*all sdio V2 of failing edge input, failing edge output*/
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, raising edge output*/
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, raising edge output*/
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
/*all sdio V1 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
/*do not include joint download mode*/
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
#else
/*do not include joint download mode*/
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
#endif
/*joint download boot*/
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
/*ATE mode*/
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
/*used by ETS_IS_SDIO_UART_BOOT*/
#define SEL_NO_BOOT 0
#define SEL_SDIO_BOOT BIT0
#define SEL_UART_BOOT BIT1
#define SEL_SPI_SLAVE_BOOT BIT2
#endif /* _SOC_BOOT_MODE_H_ */

266
components/soc/esp32h21/include/soc/clk_tree_defs.h Normal file
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@@ -0,0 +1,266 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
************************* ESP32H21 Root Clock Source ****************************
* 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC in TRM and reg. description)
*
* This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK.
*
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
*
* 2) External 32MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as SOSC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
*
* 4) Internal 32kHz RC Oscillator: RC32K
*
* The exact frequency of this clock can be computed in runtime through calibration.
*
* 5) External 32kHz Crystal Clock (optional): XTAL32K
*
* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
* pins.
*
* XTAL32K_CLK can also be calibrated to get its exact frequency.
*
* 6) External Slow Clock (optional): OSC_SLOW
*
* A slow clock signal generated by an external circuit can be connected to GPIO13 to be the clock source for the
* RTC_SLOW_CLK.
*
* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
*/
/* With the default value of CK8M_DFREQ = 860, RC_FAST clock frequency is 8.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
/**
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is one of the outputs of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_FLASH_PLL = 3, /*!< Select FLASH_PLL_CLK as CPU_CLK source (FLASH_PLL_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
/**
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
} soc_rtc_slow_clk_src_t;
/**
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)*/
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
} soc_rtc_fast_clk_src_t;
/**
* @brief LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_LP_PLL_CLK_SRC_RC32K = 0, /*!< Select RC32K_CLK as LP_PLL_CLK source */
SOC_LP_PLL_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as LP_PLL_CLK source */
SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */
} soc_lp_pll_clk_src_t;
/**
* @brief Possible main XTAL frequency options on the target
* @note Enum values equal to the frequency value in MHz
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
* the supported ones.
*/
typedef enum {
SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */
} soc_xtal_freq_t;
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
/**
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
*
* @note enum starts from 1, to save 0 for special purpose
*/
typedef enum {
// For CPU domain
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or FLASH_PLL by configuring soc_cpu_clk_src_t */
// For RTC domain
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
SOC_MOD_CLK_PLL_F64M, /*!< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 32MHz crystal */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
/**
* @brief Type of SYSTIMER clock source
*/
typedef enum {
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of GPTimer
*
* The following code can be used to iterate all possible clocks:
* @code{c}
* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
* // Test GPTimer with the clock `clk`
* }
* @endcode
*/
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of GPTimer clock source
*/
typedef enum {
GPTIMER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */
} soc_periph_tg_clk_src_legacy_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of UART
*/
#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum {
UART_SCLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock is PLL_F48M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock default choice is PLL_F48M */
} soc_periph_uart_clk_src_legacy_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M}
/**
* @brief Type of SPI clock source.
*/
typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */
SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MWDT
*/
#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST}
/**
* @brief MWDT clock source
*/
typedef enum {
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MWDT_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL fixed 48 MHz as the source clock */
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MSPI digital controller
*/
#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M}
/**
* @brief MSPI digital controller clock source
*/
typedef enum {
MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MSPI_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */
MSPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_mspi_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
CLKOUT_SIG_APB = 18, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
* @brief Read a sequence of DPORT registers to the buffer.
*
* @param[out] buff_out Contains the read data.
* @param[in] address Initial address for reading registers.
* @param[in] num_words The number of words.
*/
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
// Write value to DPORT register (does not require protecting)
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
//get bit or get bits from register
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
//set bit or set bits to register
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
//clear bit or clear bits of register
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
//set bits of register controlled by mask
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
//get field from register, uses field _S & _V to determine mask
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
//write value to register
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
//clear bits of register controlled by mask
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
//get field of register
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
//}}
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW
#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH
#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW
#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
#define SOC_MMU_ACCESS_FLASH 0
#define SOC_MMU_VALID BIT(9)
#define SOC_MMU_SENSITIVE BIT(10)
#define SOC_MMU_INVALID_MASK BIT(9)
#define SOC_MMU_INVALID 0
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(9), so value bits are 0x1ff
*/
#define SOC_MMU_VALID_VAL_MASK 0x1ff
/**
* Max MMU available paddr page num.
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define SOC_MMU_MAX_PADDR_PAGE_NUM 256
//MMU entry num
#define SOC_MMU_ENTRY_NUM 256
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & SOC_MMU_VADDR_MASK
*/
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
#define SOC_MMU_DBUS_VADDR_BASE 0x42000000
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
/*------------------------------------------------------------------------------
* MMU Linear Address
*----------------------------------------------------------------------------*/
#if (SOC_MMU_PAGE_SIZE == 0x10000)
/**
* - 64KB MMU page size: the last 0xFFFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
*
* Therefore, 0x7F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF
#elif (SOC_MMU_PAGE_SIZE == 0x8000)
/**
* - 32KB MMU page size: the last 0x7FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
*
* Therefore, 0x3F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF
#elif (SOC_MMU_PAGE_SIZE == 0x4000)
/**
* - 16KB MMU page size: the last 0x3FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
*
* Therefore, 0x1F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF
#endif //SOC_MMU_PAGE_SIZE
/**
* - If high linear address isn't 0, this means MMU can recognize these addresses
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
* Under this condition, we use the max linear space.
*/
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
#else
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
#endif
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
#else
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
#endif
/**
* I/D share the MMU linear address range
*/
#ifndef __cplusplus
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO number
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
GPIO_NUM_3 = 3, /*!< GPIO3, input and output */
GPIO_NUM_4 = 4, /*!< GPIO4, input and output */
GPIO_NUM_5 = 5, /*!< GPIO5, input and output */
GPIO_NUM_6 = 6, /*!< GPIO6, input and output */
GPIO_NUM_7 = 7, /*!< GPIO7, input and output */
GPIO_NUM_8 = 8, /*!< GPIO8, input and output */
GPIO_NUM_9 = 9, /*!< GPIO9, input and output */
GPIO_NUM_10 = 10, /*!< GPIO10, input and output */
GPIO_NUM_11 = 11, /*!< GPIO11, input and output */
GPIO_NUM_12 = 12, /*!< GPIO12, input and output */
GPIO_NUM_13 = 13, /*!< GPIO13, input and output */
GPIO_NUM_14 = 14, /*!< GPIO14, input and output */
GPIO_NUM_15 = 15, /*!< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
GPIO_NUM_MAX,
} gpio_num_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11611
#define GPIO_MATRIX_CONST_ONE_INPUT (0x20)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#define GPIO_MATRIX_INVALID (0x3A)
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/include/soc/periph_defs.h Normal file
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: IDF-11855
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_RMT_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_SPI_MODULE, //SPI1
PERIPH_SPI2_MODULE, //SPI2
PERIPH_TWAI0_MODULE,
PERIPH_RNG_MODULE,
PERIPH_RSA_MODULE,
PERIPH_AES_MODULE,
PERIPH_SHA_MODULE,
PERIPH_ECC_MODULE,
PERIPH_HMAC_MODULE,
PERIPH_DS_MODULE,
PERIPH_ECDSA_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_MCPWM0_MODULE,
PERIPH_ETM_MODULE,
PERIPH_PARLIO_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_TEMPSENSOR_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
PERIPH_BT_MODULE,
PERIPH_IEEE802154_MODULE,
PERIPH_COEX_MODULE,
PERIPH_PHY_MODULE,
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/include/soc/regi2c_bbpll.h Normal file
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_bbpll.h
* @brief Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DIV 3
#define I2C_BBPLL_OC_DIV_MSB 5
#define I2C_BBPLL_OC_DIV_LSB 0
#define I2C_BBPLL_OC_DHREF_SEL 5
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 5
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_bias.h
* @brief Register definitions for bias
*
* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
* bootloader_hardware_init function in bootloader_esp32h21.c.
*/
#define I2C_BIAS 0X6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_0P8 0
#define I2C_BIAS_DREG_0P8_MSB 7
#define I2C_BIAS_DREG_0P8_LSB 4
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
// I2C_MST_ANA_CONF0_REG
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
// I2C_MST_ANA_CONF1_REG
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
// I2C_MST_ANA_CONF2_REG
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround for calibration error when waking up from light sleep
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_lp_bias.h
* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
*
* This file lists register fields of low power dbais, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_init function in rtc_init.c.
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_pmu.h
* @brief Register definitions for digital to get rtc voltage & digital voltage
* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
*/
#define I2C_PMU 0x6d
#define I2C_PMU_HOSTID 0
#define I2C_PMU_EN_I2C_RTC_DREG 8
#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0
#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0
#define I2C_PMU_EN_I2C_DIG_DREG 8
#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1
#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1
#define I2C_PMU_EN_I2C_RTC_DREG_SLP 8
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2
#define I2C_PMU_EN_I2C_DIG_DREG_SLP 8
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3
#define I2C_PMU_OR_XPD_RTC_REG 9
#define I2C_PMU_OR_XPD_RTC_REG_MSB 4
#define I2C_PMU_OR_XPD_RTC_REG_LSB 4
#define I2C_PMU_OR_XPD_DIG_REG 9
#define I2C_PMU_OR_XPD_DIG_REG_MSB 5
#define I2C_PMU_OR_XPD_DIG_REG_LSB 5
#define I2C_PMU_OC_SCK_DCAP 14
#define I2C_PMU_OC_SCK_DCAP_MSB 7
#define I2C_PMU_OC_SCK_DCAP_LSB 0
#define I2C_PMU_OR_XPD_TRX 15
#define I2C_PMU_OR_XPD_TRX_MSB 2
#define I2C_PMU_OR_XPD_TRX_LSB 2
#define I2C_PMU_SEL_PLL8M_REF 21
#define I2C_PMU_SEL_PLL8M_REF_MSB 6
#define I2C_PMU_SEL_PLL8M_REF_LSB 6

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_saradc.h
* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
*
* This file lists register fields of SAR, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* function in adc_ll.h.
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
// TODO: IDF-11856
#define DR_REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define DR_REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000)
#define DR_REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define DR_UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define DR_REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H21
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define DR_REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000)
#define DR_REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define DR_REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
//write value to register
#define REG_WRITE(_r, _v) do { \
(*(volatile uint32_t *)(_r)) = (_v); \
} while(0)
//read value from register
#define REG_READ(_r) ({ \
(*(volatile uint32_t *)(_r)); \
})
//get bit or get bits from register
#define REG_GET_BIT(_r, _b) ({ \
(*(volatile uint32_t*)(_r) & (_b)); \
})
//set bit or set bits to register
#define REG_SET_BIT(_r, _b) do { \
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
} while(0)
//clear bit or clear bits of register
#define REG_CLR_BIT(_r, _b) do { \
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
} while(0)
//set bits of register controlled by mask
#define REG_SET_BITS(_r, _b, _m) do { \
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
} while(0)
//get field from register, uses field _S & _V to determine mask
#define REG_GET_FIELD(_r, _f) ({ \
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
})
//set field of a register from variable, uses field _S & _V to determine mask
#define REG_SET_FIELD(_r, _f, _v) do { \
REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
} while(0)
//get field value from a variable, used when _f is not left shifted by _f##_S
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//read value from register
#define READ_PERI_REG(addr) ({ \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
})
//write value to register
#define WRITE_PERI_REG(addr, val) do { \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
} while(0)
//clear bits of register controlled by mask
#define CLEAR_PERI_REG_MASK(reg, mask) do { \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
} while(0)
//set bits of register controlled by mask
#define SET_PERI_REG_MASK(reg, mask) do { \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
} while(0)
//get bits of register controlled by mask
#define GET_PERI_REG_MASK(reg, mask) ({ \
(READ_PERI_REG(reg) & (mask)); \
})
//get bits of register controlled by highest bit and lowest bit
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
})
//set bits of register controlled by mask and shift
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
} while(0)
//get field of register
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
((READ_PERI_REG(reg)>>(shift))&(mask)); \
})
#endif /* !__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define CPU_CLK_FREQ_MHZ_BTLD (64) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define APB_CLK_FREQ ( 32*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 32*1000000 )
#define REF_CLK_FREQ ( 1000000 )
//}}
/* Overall memory map */
/* Note: We should not use MACROs similar in cache_memory.h
* those are defined during run-time. But the MACROs here
* should be defined statically!
*/
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH 0x43000000
#define SOC_DROM_LOW SOC_IROM_LOW
#define SOC_DROM_HIGH SOC_IROM_HIGH
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40020000
#define SOC_DROM_MASK_LOW 0x40000000
#define SOC_DROM_MASK_HIGH 0x40020000
#define SOC_IRAM_LOW 0x40800000
#define SOC_IRAM_HIGH 0x40850000
#define SOC_DRAM_LOW 0x40800000
#define SOC_DRAM_HIGH 0x40850000
#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H21 only has 16k LP memory
#define SOC_RTC_IRAM_HIGH 0x50001000
#define SOC_RTC_DRAM_LOW 0x50000000
#define SOC_RTC_DRAM_HIGH 0x50001000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50001000
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40800000
#define SOC_DIRAM_IRAM_HIGH 0x40850000
#define SOC_DIRAM_DRAM_LOW 0x40800000
#define SOC_DIRAM_DRAM_HIGH 0x40850000
#define MAP_DRAM_TO_IRAM(addr) (addr)
#define MAP_IRAM_TO_DRAM(addr) (addr)
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SOC_DMA_LOW 0x40800000
#define SOC_DMA_HIGH 0x40850000
// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40850000
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x40800000
#define SOC_MEM_INTERNAL_HIGH 0x40850000
#define SOC_MEM_INTERNAL_LOW1 0x40800000
#define SOC_MEM_INTERNAL_HIGH1 0x40850000
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
// Region of address space that holds peripherals
#define SOC_PERIPHERAL_LOW 0x60000000
#define SOC_PERIPHERAL_HIGH 0x60100000
// CPU sub-system region, contains interrupt config registers
#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
//TODO: [ESP32H21] IDF-11857
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4084f380
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM 26
#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated
//CPU0 Max valid interrupt number
#define ETS_MAX_INUM 31
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
#define ETS_SPI2_INUM 1
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
#define ETS_GPIO_INUM 4
//Other interrupt number should be managed by the user
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 0
//Interrupt medium level, used for INT WDT for example
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md`
*/
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11589, IDF-11592
// #define SOC_ANA_CMPR_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11621
#define SOC_UART_SUPPORTED 1 //TODO: [ESP32H21] IDF-11618
// #define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603
// #define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603
// #define SOC_GPTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11594
// #define SOC_BT_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1
// #define SOC_IEEE802154_BLE_ONLY 1
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11616
// #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32H21] IDF-11624
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
// #define SOC_ULP_SUPPORTED 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11507
// #define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548
// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608
// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573
// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32H21] IDF-11583, IDF-11584, IDF-11587
// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568
// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11578, IDF-11580
#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11596, IDF-11598
// #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660
// #define SOC_MPI_SUPPORTED 1
// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11501
// #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11495
// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32H21] IDF-11497
// #define SOC_ECC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502
// #define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502
// #define SOC_ECDSA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11496
#define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11499
// #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11500
// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32H21] IDF-11530
// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11494
#define SOC_PMU_SUPPORTED 1 //TODO: [ESP32H21] IDf-11522
// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11512
// #define SOC_LP_AON_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11521
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11545
// #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11528
#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526
// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503
// #define SOC_MODEM_CLOCK_SUPPORTED 1
// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11550
// #define SOC_PHY_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11566
// #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601
// #define SOC_TWAI_SUPPORTED 1 //TODO: [ESP32H21] IDF-11574
// #define SOC_ETM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11576
// #define SOC_PARLIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11570, IDF-11572
// #define SOC_RMT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11622
// #define SOC_AES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11504
// #define SOC_SDIO_SLAVE_SUPPORTED 1
// #define SOC_PAU_SUPPORTED 1
// #define SOC_LIGHT_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11517, IDF-11520
// #define SOC_DEEP_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11514
// #define SOC_MODEM_CLOCK_SUPPORTED 1
// #define SOC_PM_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_32M 1
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_AES_GDMA (1)
#define SOC_AES_SUPPORT_AES_128 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
// #define SOC_ADC_DIG_CTRL_SUPPORTED 1
// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
// #define SOC_ADC_MONITOR_SUPPORTED 1
// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
// #define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< Interrupt */
// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
/*!< ADC power control is shared by PWDET */
// #define SOC_ADC_SHARED_POWER 1
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (0)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
#define SOC_CACHE_FREEZE_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_CORES_NUM (1U)
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
#define SOC_CPU_HAS_CSR_PC 1
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_HAS_PMA 1
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
#define SOC_CPU_PMP_REGION_GRANULARITY 4
/*-------------------------- MMU CAPS ----------------------------------------*/
// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
// #define SOC_MMU_PAGE_SIZE_8KB_SUPPORTED (1)
#define SOC_MMU_PERIPH_NUM (1U)
#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U)
#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_AHB_GDMA_VERSION 1U
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups
#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-H21 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 28
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// #define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
// Digital IOs have their own registers to control pullup/down/capability
// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 27
#define SOC_GPIO_OUT_RANGE_MAX 27
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL
// Support to force hold all IOs
// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// The Clock Out signal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported
* for hold, wake & 32kHz crystal functions - via LP_AON registers */
// #define SOC_RTCIO_PIN_COUNT (8U)
// #define SOC_RTCIO_HOLD_SUPPORTED (1)
// #define SOC_RTCIO_VALID_RTCIO_MASK (0x7F80)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*------------------------- Analog Comparator CAPS ---------------------------*/
#define SOC_ANA_CMPR_NUM (1U)
#define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-H21 has 2 I2C
// #define SOC_I2C_NUM (2U)
// #define SOC_HP_I2C_NUM (2U)
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// #define SOC_I2C_SUPPORT_SLAVE (1)
// #define SOC_I2C_SUPPORT_HW_FSM_RST (1)
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
// #define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1)
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
// #define SOC_I2S_NUM (1U)
// #define SOC_I2S_HW_VERSION_2 (1)
// // #define SOC_I2S_SUPPORTS_ETM (1)
// #define SOC_I2S_SUPPORTS_XTAL (1)
// #define SOC_I2S_SUPPORTS_PLL_F96M (1)
// #define SOC_I2S_SUPPORTS_PLL_F64M (1)
// #define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
// #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- LEDC CAPS ---------------------------------------*/
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
// #define SOC_LEDC_CHANNEL_NUM (6)
// #define SOC_LEDC_TIMER_BIT_WIDTH (20)
// #define SOC_LEDC_SUPPORT_FADE_STOP (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
/*-------------------------- MPU CAPS ----------------------------------------*/
// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
// #define SOC_MPU_MIN_REGION_SIZE 0x20000000U
// #define SOC_MPU_REGIONS_MAX_NUM 8
// #define SOC_MPU_REGION_RO_SUPPORTED 0
// #define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
// #define SOC_PCNT_GROUPS 1U
// #define SOC_PCNT_UNITS_PER_GROUP 4
// #define SOC_PCNT_CHANNELS_PER_UNIT 2
// #define SOC_PCNT_THRES_POINT_PER_UNIT 2
// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
/*--------------------------- RMT CAPS ---------------------------------------*/
// #define SOC_RMT_GROUPS 1U /*!< One RMT group */
// #define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
// #define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
// #define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
// #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
// #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
// #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
// #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
// #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
// #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
// #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
// #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
// #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
// #define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
// #define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
// #define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
// #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
// #define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
/*--------------------------- MPI CAPS ---------------------------------------*/
#define SOC_MPI_MEM_BLOCKS_NUM (4)
#define SOC_MPI_OPERATIONS_NUM (3)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_PLL_F48M 1
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
#define SOC_SPI_SCT_SUPPORTED 1
#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer
#define SOC_SPI_SCT_REG_NUM 14
#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs
#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed to 2 when clock source is XTAL
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
// #define SOC_TIMER_SUPPORT_ETM (1)
// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
// #define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/
// #define SOC_TWAI_CONTROLLER_NUM 1UL
// #define SOC_TWAI_CLK_SUPPORT_XTAL 1
// #define SOC_TWAI_BRP_MIN 2
// #define SOC_TWAI_BRP_MAX 32768
// #define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_PAD_JTAG 1
#define SOC_EFUSE_DIS_USB_JTAG 1
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
#define SOC_EFUSE_SOFT_DIS_JTAG 1
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block
#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1
#define SOC_SECURE_BOOT_V2_ECC 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
/*-------------------------- APM CAPS ----------------------------------------*/
#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
/*------------------------- ECDSA CAPS -------------------------*/
#define SOC_ECDSA_USES_MPI (1)
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-H21 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_HP_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
// #define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 */
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
#define SOC_PM_SUPPORT_RC32K_PD (1)
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
#define SOC_PM_SUPPORT_TOP_PD (1)
#define SOC_PM_PAU_LINK_NUM (4)
// #define SOC_PM_CPU_RETENTION_BY_SW (1)
// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
// #define SOC_PM_RETENTION_SW_TRIGGER_REGDMA (1) /*!< In esp32H2, regdma will power off when entering sleep */
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
// #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1)
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM (1)
/*--------------------------------- RNG CAPS --------------------------------------------*/
// #define SOC_RNG_CLOCK_IS_INDEPENDENT (1)
/*---------------------------------- Bluetooth CAPS ----------------------------------*/
// #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
// #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
// #define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
// #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
* peripheral and include them here to avoid developing conflicts in those header files.
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
// MSPI IOMUX PINs
#define MSPI_FUNC_NUM 0
#define MSPI_IOMUX_PIN_NUM_HD 18
#define MSPI_IOMUX_PIN_NUM_WP 17
#define MSPI_IOMUX_PIN_NUM_CS0 15
#define MSPI_IOMUX_PIN_NUM_CLK 19
#define MSPI_IOMUX_PIN_NUM_MOSI 20
#define MSPI_IOMUX_PIN_NUM_MISO 16
// GPSPI2 IOMUX PINs
#define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 0
#define SPI2_IOMUX_PIN_NUM_HD 3
#define SPI2_IOMUX_PIN_NUM_WP 2
#define SPI2_IOMUX_PIN_NUM_CLK 4
#define SPI2_IOMUX_PIN_NUM_MOSI 5
#define SPI2_IOMUX_PIN_NUM_CS 1
#endif

18
components/soc/esp32h21/include/soc/uart_channel.h Normal file
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@@ -0,0 +1,18 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32H2.
#pragma once
//UART channels
#define UART_GPIO24_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 24
#define UART_GPIO23_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 23
#define UART_TXD_GPIO24_DIRECT_CHANNEL UART_GPIO24_DIRECT_CHANNEL
#define UART_RXD_GPIO23_DIRECT_CHANNEL UART_GPIO23_DIRECT_CHANNEL

37
components/soc/esp32h21/include/soc/uart_pins.h Normal file
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@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 15
#define U0TXD_GPIO_NUM 16
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)

13
components/soc/esp32h21/include/soc/wdev_reg.h Normal file
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@@ -0,0 +1,13 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#include "soc/lpperi_reg.h"
/* Hardware random number generator register */
#define WDEV_RND_REG LPPERI_RNG_DATA_REG

64
components/soc/esp32h21/register/soc/assist_debug_reg.h
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@@ -14,7 +14,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_BASE + 0x0)
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor enable
*/
@@ -89,7 +89,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_BASE + 0x4)
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt status
*/
@@ -164,7 +164,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
* core0 monitor interrupt enable register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_BASE + 0x8)
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
@@ -239,7 +239,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clr register
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_BASE + 0xc)
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt clr
*/
@@ -314,7 +314,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_BASE + 0x10)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region0 start addr
*/
@@ -326,7 +326,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_BASE + 0x14)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region0 end addr
*/
@@ -338,7 +338,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_BASE + 0x18)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region1 start addr
*/
@@ -350,7 +350,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_BASE + 0x1c)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region1 end addr
*/
@@ -362,7 +362,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_BASE + 0x20)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region0 start addr
*/
@@ -374,7 +374,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_BASE + 0x24)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region0 end addr
*/
@@ -386,7 +386,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_BASE + 0x28)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region1 start addr
*/
@@ -398,7 +398,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_BASE + 0x2c)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region1 end addr
*/
@@ -410,7 +410,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
* core0 area pc status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_BASE + 0x30)
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* the stackpointer when first touch region monitor interrupt
*/
@@ -422,7 +422,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
* core0 area sp status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_BASE + 0x34)
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* the PC when first touch region monitor interrupt
*/
@@ -434,7 +434,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* stack min value
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_BASE + 0x38)
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration register
*/
@@ -446,7 +446,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* stack max value
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_BASE + 0x3c)
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
@@ -458,7 +458,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* stack monitor pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_BASE + 0x40)
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* This register stores the PC when trigger stack monitor.
*/
@@ -470,7 +470,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* record enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_BASE + 0x44)
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
@@ -489,7 +489,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* record status register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_BASE + 0x48)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
@@ -501,7 +501,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* record status register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_BASE + 0x4c)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
@@ -513,7 +513,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_BASE + 0x50)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
@@ -539,7 +539,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_BASE + 0x54)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
@@ -565,7 +565,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register2
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_BASE + 0x58)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
@@ -591,7 +591,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register3
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_BASE + 0x5c)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
@@ -603,7 +603,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
* exception monitor status register4
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_BASE + 0x60)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
@@ -629,7 +629,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
* exception monitor status register5
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_BASE + 0x64)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
@@ -641,7 +641,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register6
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_BASE + 0x68)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
@@ -653,7 +653,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register7
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_BASE + 0x6c)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
@@ -665,7 +665,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_BASE + 0x70)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
@@ -677,7 +677,7 @@ extern "C" {
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_BASE + 0x74)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
@@ -696,7 +696,7 @@ extern "C" {
/** ASSIST_DEBUG_CLOCK_GATE_REG register
* clock register
*/
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_BASE + 0x78)
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 force on the clock gate
*/
@@ -708,7 +708,7 @@ extern "C" {
/** ASSIST_DEBUG_DATE_REG register
* version register
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_BASE + 0x3fc)
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 35660096;
* version register
*/

1937
components/soc/esp32h21/register/soc/efuse_reg.h
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2363
components/soc/esp32h21/register/soc/efuse_struct.h
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3161
components/soc/esp32h21/register/soc/gdma_reg.h Normal file
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1090
components/soc/esp32h21/register/soc/gdma_struct.h Normal file
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220
components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h Normal file
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@@ -0,0 +1,220 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11858
#define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C0_CTRL 0x01FFFFFFU
#define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTRL_V << I2C_MST_I2C0_CTRL_S)
#define I2C_MST_I2C0_CTRL_V 0x01FFFFFFU
#define I2C_MST_I2C0_CTRL_S 0
/* I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C0_BUSY (BIT(25))
#define I2C_MST_I2C0_BUSY_M (I2C_MST_I2C0_BUSY_V << I2C_MST_I2C0_BUSY_S)
#define I2C_MST_I2C0_BUSY_V 0x00000001U
#define I2C_MST_I2C0_BUSY_S 25
#define I2C_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
/* I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C1_CTRL 0x01FFFFFFU
#define I2C_MST_I2C1_CTRL_M (I2C_MST_I2C1_CTRL_V << I2C_MST_I2C1_CTRL_S)
#define I2C_MST_I2C1_CTRL_V 0x01FFFFFFU
#define I2C_MST_I2C1_CTRL_S 0
/* I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C1_BUSY (BIT(25))
#define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S)
#define I2C_MST_I2C1_BUSY_V 0x00000001U
#define I2C_MST_I2C1_BUSY_S 25
#define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C0_CONF 0x00FFFFFFU
#define I2C_MST_I2C0_CONF_M (I2C_MST_I2C0_CONF_V << I2C_MST_I2C0_CONF_S)
#define I2C_MST_I2C0_CONF_V 0x00FFFFFFU
#define I2C_MST_I2C0_CONF_S 0
/* I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C0_STATUS 0x000000FFU
#define I2C_MST_I2C0_STATUS_M (I2C_MST_I2C0_STATUS_V << I2C_MST_I2C0_STATUS_S)
#define I2C_MST_I2C0_STATUS_V 0x000000FFU
#define I2C_MST_I2C0_STATUS_S 24
#define I2C_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc)
/* I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C1_CONF 0x00FFFFFFU
#define I2C_MST_I2C1_CONF_M (I2C_MST_I2C1_CONF_V << I2C_MST_I2C1_CONF_S)
#define I2C_MST_I2C1_CONF_V 0x00FFFFFFU
#define I2C_MST_I2C1_CONF_S 0
/* I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C1_STATUS 0x000000FFU
#define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S)
#define I2C_MST_I2C1_STATUS_V 0x000000FFU
#define I2C_MST_I2C1_STATUS_S 24
#define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
/* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;*/
/* description: .*/
#define I2C_MST_BURST_CTRL 0xFFFFFFFFU
#define I2C_MST_BURST_CTRL_M (I2C_MST_BURST_CTRL_V << I2C_MST_BURST_CTRL_S)
#define I2C_MST_BURST_CTRL_V 0xFFFFFFFFU
#define I2C_MST_BURST_CTRL_S 0
#define I2C_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
/* I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C_MST_BURST_DONE (BIT(0))
#define I2C_MST_I2C_MST_BURST_DONE_M (I2C_MST_I2C_MST_BURST_DONE_V << I2C_MST_I2C_MST_BURST_DONE_S)
#define I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U
#define I2C_MST_I2C_MST_BURST_DONE_S 0
/* I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S)
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1
/* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_MST_I2C_MST1_BURST_ERR_FLAG_S)
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2
/* I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0;*/
/* description: .*/
#define I2C_MST_BURST_TIMEOUT_CNT 0x0001FFFFU
#define I2C_MST_BURST_TIMEOUT_CNT_M (I2C_MST_BURST_TIMEOUT_CNT_V << I2C_MST_BURST_TIMEOUT_CNT_S)
#define I2C_MST_BURST_TIMEOUT_CNT_V 0x0001FFFFU
#define I2C_MST_BURST_TIMEOUT_CNT_S 3
#define I2C_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
/* I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_CONF0 0x00FFFFFFU
#define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S)
#define I2C_MST_ANA_CONF0_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF0_S 0
/* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS0 0x000000FFU
#define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S)
#define I2C_MST_ANA_STATUS0_V 0x000000FFU
#define I2C_MST_ANA_STATUS0_S 24
#define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c)
/* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_CONF1 0x00FFFFFFU
#define I2C_MST_ANA_CONF1_M (I2C_MST_ANA_CONF1_V << I2C_MST_ANA_CONF1_S)
#define I2C_MST_ANA_CONF1_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF1_S 0
/* I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS1 0x000000FFU
#define I2C_MST_ANA_STATUS1_M (I2C_MST_ANA_STATUS1_V << I2C_MST_ANA_STATUS1_S)
#define I2C_MST_ANA_STATUS1_V 0x000000FFU
#define I2C_MST_ANA_STATUS1_S 24
#define I2C_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
/* I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_CONF2 0x00FFFFFFU
#define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S)
#define I2C_MST_ANA_CONF2_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF2_S 0
/* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS2 0x000000FFU
#define I2C_MST_ANA_STATUS2_M (I2C_MST_ANA_STATUS2_V << I2C_MST_ANA_STATUS2_S)
#define I2C_MST_ANA_STATUS2_V 0x000000FFU
#define I2C_MST_ANA_STATUS2_S 24
#define I2C_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
/* description: .*/
#define I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU
#define I2C_MST_I2C0_SCL_PULSE_DUR_M (I2C_MST_I2C0_SCL_PULSE_DUR_V << I2C_MST_I2C0_SCL_PULSE_DUR_S)
#define I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_MST_I2C0_SCL_PULSE_DUR_S 0
/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
/* description: .*/
#define I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU
#define I2C_MST_I2C0_SDA_SIDE_GUARD_M (I2C_MST_I2C0_SDA_SIDE_GUARD_V << I2C_MST_I2C0_SDA_SIDE_GUARD_S)
#define I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_MST_I2C0_SDA_SIDE_GUARD_S 6
#define I2C_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
/* description: .*/
#define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU
#define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S)
#define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_MST_I2C1_SCL_PULSE_DUR_S 0
/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
/* description: .*/
#define I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU
#define I2C_MST_I2C1_SDA_SIDE_GUARD_M (I2C_MST_I2C1_SDA_SIDE_GUARD_V << I2C_MST_I2C1_SDA_SIDE_GUARD_S)
#define I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_MST_I2C1_SDA_SIDE_GUARD_S 6
#define I2C_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c)
/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
/* description: .*/
#define I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_MST_HW_I2C_SCL_PULSE_DUR_S)
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
/* description: .*/
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6
/* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/
/* description: .*/
#define I2C_MST_ARBITER_DIS (BIT(11))
#define I2C_MST_ARBITER_DIS_M (I2C_MST_ARBITER_DIS_V << I2C_MST_ARBITER_DIS_S)
#define I2C_MST_ARBITER_DIS_V 0x00000001U
#define I2C_MST_ARBITER_DIS_S 11
#define I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
/* I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;*/
/* description: .*/
#define I2C_MST_NOUSE 0xFFFFFFFFU
#define I2C_MST_NOUSE_M (I2C_MST_NOUSE_V << I2C_MST_NOUSE_S)
#define I2C_MST_NOUSE_V 0xFFFFFFFFU
#define I2C_MST_NOUSE_S 0
#define I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/* I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;*/
/* description: .*/
#define I2C_MST_DATE 0x0FFFFFFFU
#define I2C_MST_DATE_M (I2C_MST_DATE_V << I2C_MST_DATE_S)
#define I2C_MST_DATE_V 0x0FFFFFFFU
#define I2C_MST_DATE_S 0
/* I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;*/
/* description: .*/
#define I2C_MST_CLK_EN (BIT(28))
#define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S)
#define I2C_MST_CLK_EN_V 0x00000001U
#define I2C_MST_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

1
components/soc/esp32h21/register/soc/interrupt_matrix_reg.h
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@@ -5,7 +5,6 @@
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {

24
components/soc/esp32h21/register/soc/interrupt_reg.h Normal file
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@@ -0,0 +1,24 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "interrupt_matrix_reg.h"
#include "plic_reg.h"
#include "soc/soc_caps.h"
#define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_MXINT_THRESH_REG
/**
* ESP32H21 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y)
* Keep the following macros for backward compatibility reasons
*/
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG
#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE

365
components/soc/esp32h21/register/soc/io_mux_reg.h Normal file
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@@ -0,0 +1,365 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
#define FILTER_EN (BIT(15))
#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
#define FILTER_EN_V 1
#define FILTER_EN_S 15
/* HYS_EN : R/W; bitpos: [16]; default: 0;
* Software enables hysteresis function for the pad.
* 1: Hysteresis enabled. 0: Hysteresis disabled.
*/
#define HYS_EN (BIT(16))
#define HYS_EN_M (HYS_EN_V << HYS_EN_S)
#define HYS_EN_V 0x00000001
#define HYS_EN_S 16
/* HYS_SEL : R/W; bitpos: [17]; default: 0;
* Select enabling signals of the pad from software and efuse hardware.
* 1: Select enabling signal from software.
* 0: Select enabling signal from efuse hardware.
*/
#define HYS_SEL (BIT(17))
#define HYS_SEL_M (HYS_SEL_V << HYS_SEL_S)
#define HYS_SEL_V 0x00000001
#define HYS_SEL_S 17
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
#define PIN_HYS_EN_SEL_EFUSE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_SEL)
#define PIN_HYS_EN_SEL_SOFT(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_SEL)
#define PIN_HYS_SOFT_ENABLE(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_EN)
#define PIN_HYS_SOFT_DISABLE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_EN)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_MTMS
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_MTDO
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_MTCK
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTDI
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_GPIO4
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_GPIO5
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_GPIO6
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_GPIO14
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_U0RXD
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_U0TXD
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_GPIO17
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_GPIO18
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICS0
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPIQ
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_SPIWP
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_SPID
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U0RXD_GPIO_NUM 15
#define U0TXD_GPIO_NUM 16
#define SPI_HD_GPIO_NUM 23
#define SPI_WP_GPIO_NUM 22
#define SPI_CS0_GPIO_NUM 20
#define SPI_CLK_GPIO_NUM 24
#define SPI_D_GPIO_NUM 25
#define SPI_Q_GPIO_NUM 21
#define USB_INT_PHY0_DM_GPIO_NUM 26
#define USB_INT_PHY0_DP_GPIO_NUM 27
#define EXT_OSC_SLOW_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function
#define MAX_PAD_GPIO_NUM 25
#define MAX_GPIO_NUM 29
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define GPIO_NUM_IN_INVALID 0x28
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 IO_MUX_CLK_OUT3
#define CLK_OUT3_V IO_MUX_CLK_OUT3_V
#define CLK_OUT3_S IO_MUX_CLK_OUT3_S
#define CLK_OUT3_M IO_MUX_CLK_OUT3_M
#define CLK_OUT2 IO_MUX_CLK_OUT2
#define CLK_OUT2_V IO_MUX_CLK_OUT2_V
#define CLK_OUT2_S IO_MUX_CLK_OUT2_S
#define CLK_OUT2_M IO_MUX_CLK_OUT2_M
#define CLK_OUT1 IO_MUX_CLK_OUT1
#define CLK_OUT1_V IO_MUX_CLK_OUT1_V
#define CLK_OUT1_S IO_MUX_CLK_OUT1_S
#define CLK_OUT1_M IO_MUX_CLK_OUT1_M
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x0)
#define FUNC_MTMS_FSPIWP 2
#define FUNC_MTMS_GPIO0 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x4)
#define FUNC_MTDO_FSPIHD 2
#define FUNC_MTDO_GPIO1 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x8)
#define FUNC_MTCK_FSPICLK 2
#define FUNC_MTCK_GPIO2 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0xC)
#define FUNC_MTDI_FSPID 2
#define FUNC_MTDI_GPIO3 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x10)
#define FUNC_GPIO4_FSPIQ 2
#define FUNC_GPIO4_GPIO4 1
#define FUNC_GPIO4_GPIO4_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x14)
#define FUNC_GPIO5_GPIO5 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x18)
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C)
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x28)
#define FUNC_XTAL_32K_N_GPIO10 1
#define FUNC_XTAL_32K_N_GPIO10_0 0
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x2C)
#define FUNC_XTAL_32K_P_GPIO11 1
#define FUNC_XTAL_32K_P_GPIO11_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30)
#define FUNC_GPIO12_FSPICS0 2
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x38)
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x3C)
#define FUNC_U0RXD_GPIO15 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x40)
#define FUNC_U0TXD_GPIO16 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x44)
#define FUNC_GPIO17_GPIO17 1
#define FUNC_GPIO17_GPIO17_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x48)
#define FUNC_GPIO18_GPIO18 1
#define FUNC_GPIO18_GPIO18_0 0
#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x4C)
#define FUNC_VDD_SPI_GPIO19 1
#define FUNC_VDD_SPI_GPIO19_0 0
#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x50)
#define FUNC_SPICS0_GPIO20 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x54)
#define FUNC_SPIQ_GPIO21 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x58)
#define FUNC_SPIWP_GPIO22 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x5C)
#define FUNC_SPIHD_GPIO23 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x60)
#define FUNC_SPICLK_GPIO24 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x64)
#define FUNC_SPID_GPIO25 1
#define FUNC_SPID_SPID 0
/** IO_MUX_PIN_CTRL_REG register
* Clock Output Configuration
* Register
*/
#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
/* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out1, set this register
* to 0x0. CLK_OUT_out1 can be found in peripheral output
* signals.
*/
#define IO_MUX_CLK_OUT1 0x0000001F
#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
#define IO_MUX_CLK_OUT1_V 0x0000001F
#define IO_MUX_CLK_OUT1_S 0
/* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out2, set this register
* to 0x0. CLK_OUT_out2 can be found in peripheral output
* signals.
*/
#define IO_MUX_CLK_OUT2 0x0000001F
#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
#define IO_MUX_CLK_OUT2_V 0x0000001F
#define IO_MUX_CLK_OUT2_S 5
/* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7;
* If you want to output clock for I2S to CLK_OUT_out3, set this register
* to 0x0. CLK_OUT_out3 can be found in peripheral output
* signals.
*/
#define IO_MUX_CLK_OUT3 0x0000001F
#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
#define IO_MUX_CLK_OUT3_V 0x0000001F
#define IO_MUX_CLK_OUT3_S 10
/** IO_MUX_MODEM_DIAG_EN_REG register
* GPIO MATRIX Configure Register for modem
* diag
*/
#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
/* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0;
* bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i]
* into gpio matrix. 0:enable other signals into gpio
* matrix
*/
#define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFF
#define IO_MUX_MODEM_DIAG_EN_M (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
#define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFF
#define IO_MUX_MODEM_DIAG_EN_S 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x1FC)
/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2409110 ; */
/*description: Version control register.*/
#define IO_MUX_REG_DATE 0x0FFFFFFF
#define IO_MUX_REG_DATE_M ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S))
#define IO_MUX_REG_DATE_V 0xFFFFFFF
#define IO_MUX_REG_DATE_S 0

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** LP_TIMER_TAR0_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** LP_TIMER_UPDATE_REG register
* need_des
*/
#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [27]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(27))
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_UPDATE_S 27
/** LP_TIMER_MAIN_TIMER_REGDMA_WORK : R/W; bitpos: [28]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when regdma working
*/
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK (BIT(28))
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_M (LP_TIMER_MAIN_TIMER_REGDMA_WORK_V << LP_TIMER_MAIN_TIMER_REGDMA_WORK_S)
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_S 28
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
/** LP_TIMER_MAIN_BUF0_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** LP_TIMER_MAIN_BUF1_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** LP_TIMER_MAIN_OVERFLOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
/** LP_TIMER_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
#define LP_TIMER_OVERFLOW_RAW_S 30
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** LP_TIMER_INT_ST_REG register
* need_des
*/
#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ST (BIT(30))
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
#define LP_TIMER_OVERFLOW_ST_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
/** LP_TIMER_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
#define LP_TIMER_OVERFLOW_ENA_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** LP_TIMER_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
#define LP_TIMER_OVERFLOW_CLR_S 30
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** LP_TIMER_DATE_REG register
* need_des
*/
#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 37785904;
* need_des
*/
#define LP_TIMER_DATE 0x7FFFFFFFU
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
#define LP_TIMER_DATE_V 0x7FFFFFFFU
#define LP_TIMER_DATE_S 0
/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_CLK_EN (BIT(31))
#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
#define LP_TIMER_CLK_EN_V 0x00000001U
#define LP_TIMER_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/lp_timer_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of timer_tar0_low register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_tar_low0:32;
};
uint32_t val;
} lp_timer_tar0_low_reg_t;
/** Type of timer_tar0_high register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** timer_main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_main_timer_tar_en0:1;
};
uint32_t val;
} lp_timer_tar0_high_reg_t;
/** Type of timer_update register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** timer_main_timer_update : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t timer_main_timer_update:1;
/** timer_main_timer_regdma_work : R/W; bitpos: [28]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when regdma working
*/
uint32_t timer_main_timer_regdma_work:1;
/** timer_main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t timer_main_timer_xtal_off:1;
/** timer_main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_main_timer_sys_stall:1;
/** timer_main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_main_timer_sys_rst:1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of timer_main_buf0_low register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf0_low:32;
};
uint32_t val;
} lp_timer_main_buf0_low_reg_t;
/** Type of timer_main_buf0_high register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf0_high_reg_t;
/** Type of timer_main_buf1_low register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf1_low:32;
};
uint32_t val;
} lp_timer_main_buf1_low_reg_t;
/** Type of timer_main_buf1_high register
* need_des
*/
typedef union {
struct {
/** timer_main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t timer_main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf1_high_reg_t;
/** Type of timer_main_overflow register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** timer_main_timer_alarm_load : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_main_timer_alarm_load:1;
};
uint32_t val;
} lp_timer_main_overflow_reg_t;
/** Type of timer_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_raw:1;
/** timer_soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of timer_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_st:1;
/** timer_soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of timer_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_ena:1;
/** timer_soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of timer_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t timer_overflow_clr:1;
/** timer_soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of timer_date register
* need_des
*/
typedef union {
struct {
/** timer_date : R/W; bitpos: [30:0]; default: 37785904;
* need_des
*/
uint32_t timer_date:31;
/** timer_clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t timer_clk_en:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct {
volatile lp_timer_tar0_low_reg_t timer_tar0_low;
volatile lp_timer_tar0_high_reg_t timer_tar0_high;
uint32_t reserved_008[2];
volatile lp_timer_update_reg_t timer_update;
volatile lp_timer_main_buf0_low_reg_t timer_main_buf0_low;
volatile lp_timer_main_buf0_high_reg_t timer_main_buf0_high;
volatile lp_timer_main_buf1_low_reg_t timer_main_buf1_low;
volatile lp_timer_main_buf1_high_reg_t timer_main_buf1_high;
volatile lp_timer_main_overflow_reg_t timer_main_overflow;
volatile lp_timer_int_raw_reg_t timer_int_raw;
volatile lp_timer_int_st_reg_t timer_int_st;
volatile lp_timer_int_ena_reg_t timer_int_ena;
volatile lp_timer_int_clr_reg_t timer_int_clr;
uint32_t reserved_038[241];
volatile lp_timer_date_reg_t timer_date;
} lp_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lp_dev_t) == 0x400, "Invalid size of lp_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

388
components/soc/esp32h21/register/soc/lpperi_reg.h Normal file
View File

@@ -0,0 +1,388 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
* need_des
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
* need_des
*/
#define LPPERI_RNG_CK_EN (BIT(24))
#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
#define LPPERI_RNG_CK_EN_V 0x00000001U
#define LPPERI_RNG_CK_EN_S 24
/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
* need_des
*/
#define LPPERI_OTP_DBG_CK_EN (BIT(25))
#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
#define LPPERI_OTP_DBG_CK_EN_S 25
/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
* need_des
*/
#define LPPERI_LP_UART_CK_EN (BIT(26))
#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
#define LPPERI_LP_UART_CK_EN_V 0x00000001U
#define LPPERI_LP_UART_CK_EN_S 26
/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
* need_des
*/
#define LPPERI_LP_IO_CK_EN (BIT(27))
#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
#define LPPERI_LP_IO_CK_EN_V 0x00000001U
#define LPPERI_LP_IO_CK_EN_S 27
/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_CK_EN_S 28
/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_CK_EN_S 29
/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LPPERI_EFUSE_CK_EN (BIT(30))
#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
#define LPPERI_EFUSE_CK_EN_V 0x00000001U
#define LPPERI_EFUSE_CK_EN_S 30
/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_CK_EN (BIT(31))
#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
#define LPPERI_LP_CPU_CK_EN_V 0x00000001U
#define LPPERI_LP_CPU_CK_EN_S 31
/** LPPERI_RESET_EN_REG register
* need_des
*/
#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
* need_des
*/
#define LPPERI_BUS_RESET_EN (BIT(23))
#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
#define LPPERI_BUS_RESET_EN_V 0x00000001U
#define LPPERI_BUS_RESET_EN_S 23
/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0;
* need_des
*/
#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24))
#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S)
#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U
#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24
/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
#define LPPERI_OTP_DBG_RESET_EN_S 25
/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_RESET_EN (BIT(26))
#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
#define LPPERI_LP_UART_RESET_EN_V 0x00000001U
#define LPPERI_LP_UART_RESET_EN_S 26
/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LPPERI_LP_IO_RESET_EN (BIT(27))
#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
#define LPPERI_LP_IO_RESET_EN_S 27
/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_RESET_EN_S 28
/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_RESET_EN_S 29
/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_EFUSE_RESET_EN (BIT(30))
#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
#define LPPERI_EFUSE_RESET_EN_S 30
/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_RESET_EN (BIT(31))
#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U
#define LPPERI_LP_CPU_RESET_EN_S 31
/** LPPERI_RNG_CFG_REG register
* need_des
*/
#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8)
/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
* need des
*/
#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0))
#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S)
#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U
#define LPPERI_RNG_SAMPLE_ENABLE_S 0
/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
* need des
*/
#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S)
#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_S 1
/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
* need des
*/
#define LPPERI_RNG_TIMER_EN (BIT(9))
#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S)
#define LPPERI_RNG_TIMER_EN_V 0x00000001U
#define LPPERI_RNG_TIMER_EN_S 9
/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3;
* need des
*/
#define LPPERI_RTC_TIMER_EN 0x00000003U
#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S)
#define LPPERI_RTC_TIMER_EN_V 0x00000003U
#define LPPERI_RTC_TIMER_EN_S 10
/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S)
#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_S 24
/** LPPERI_RNG_DATA_REG register
* need_des
*/
#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0xc)
/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_RND_DATA 0xFFFFFFFFU
#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
#define LPPERI_RND_DATA_V 0xFFFFFFFFU
#define LPPERI_RND_DATA_S 0
/** LPPERI_CPU_REG register
* need_des
*/
#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0x10)
/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31))
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31
/** LPPERI_BUS_TIMEOUT_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x14)
/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14
/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30))
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30
/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31))
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31
/** LPPERI_BUS_TIMEOUT_ADDR_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x18)
/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0
/** LPPERI_BUS_TIMEOUT_UID_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x1c)
/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_S 0
/** LPPERI_MEM_CTRL_REG register
* need_des
*/
#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x20)
/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0))
#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0
/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG (BIT(1))
#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_S 1
/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_EN (BIT(29))
#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
#define LPPERI_UART_WAKEUP_EN_V 0x00000001U
#define LPPERI_UART_WAKEUP_EN_S 29
/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PD (BIT(30))
#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PD_S 30
/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PU (BIT(31))
#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PU_S 31
/** LPPERI_INTERRUPT_SOURCE_REG register
* need_des
*/
#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x24)
/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_S 0
/** LPPERI_DEBUG_SEL0_REG register
* need des
*/
#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x28)
/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
#define LPPERI_DEBUG_SEL0 0x0000007FU
#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S)
#define LPPERI_DEBUG_SEL0_V 0x0000007FU
#define LPPERI_DEBUG_SEL0_S 0
/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
#define LPPERI_DEBUG_SEL1 0x0000007FU
#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S)
#define LPPERI_DEBUG_SEL1_V 0x0000007FU
#define LPPERI_DEBUG_SEL1_S 7
/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
#define LPPERI_DEBUG_SEL2 0x0000007FU
#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S)
#define LPPERI_DEBUG_SEL2_V 0x0000007FU
#define LPPERI_DEBUG_SEL2_S 14
/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
#define LPPERI_DEBUG_SEL3 0x0000007FU
#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S)
#define LPPERI_DEBUG_SEL3_V 0x0000007FU
#define LPPERI_DEBUG_SEL3_S 21
/** LPPERI_DEBUG_SEL1_REG register
* need des
*/
#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x2c)
/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
#define LPPERI_DEBUG_SEL4 0x0000007FU
#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S)
#define LPPERI_DEBUG_SEL4_V 0x0000007FU
#define LPPERI_DEBUG_SEL4_S 0
/** LPPERI_RNG_DATA_SYNC_REG register
* rng result sync register
*/
#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x30)
/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0;
* get rng sync result
*/
#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU
#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S)
#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU
#define LPPERI_RND_SYNC_DATA_S 0
/** LPPERI_DATE_REG register
* need_des
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37781793;
* need_des
*/
#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_S 0
/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_CLK_EN (BIT(31))
#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
#define LPPERI_CLK_EN_V 0x00000001U
#define LPPERI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

352
components/soc/esp32h21/register/soc/lpperi_struct.h Normal file
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@@ -0,0 +1,352 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
* need_des
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
* need_des
*/
uint32_t otp_dbg_ck_en:1;
/** lp_uart_ck_en : R/W; bitpos: [26]; default: 1;
* need_des
*/
uint32_t lp_uart_ck_en:1;
/** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
* need_des
*/
uint32_t lp_io_ck_en:1;
/** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t lp_ext_i2c_ck_en:1;
/** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t lp_ana_i2c_ck_en:1;
/** efuse_ck_en : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t efuse_ck_en:1;
/** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_ck_en:1;
};
uint32_t val;
} lpperi_clk_en_reg_t;
/** Type of reset_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** bus_reset_en : WT; bitpos: [23]; default: 0;
* need_des
*/
uint32_t bus_reset_en:1;
/** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0;
* need_des
*/
uint32_t lp_ble_timer_reset_en:1;
/** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t otp_dbg_reset_en:1;
/** lp_uart_reset_en : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t lp_uart_reset_en:1;
/** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t lp_io_reset_en:1;
/** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t lp_ext_i2c_reset_en:1;
/** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_ana_i2c_reset_en:1;
/** efuse_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t efuse_reset_en:1;
/** lp_cpu_reset_en : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_reset_en:1;
};
uint32_t val;
} lpperi_reset_en_reg_t;
/** Type of rng_cfg register
* need_des
*/
typedef union {
struct {
/** rng_sample_enable : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t rng_sample_enable:1;
/** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255;
* need des
*/
uint32_t rng_timer_pscale:8;
/** rng_timer_en : R/W; bitpos: [9]; default: 1;
* need des
*/
uint32_t rng_timer_en:1;
/** rtc_timer_en : R/W; bitpos: [11:10]; default: 3;
* need des
*/
uint32_t rtc_timer_en:2;
uint32_t reserved_12:12;
/** rng_sample_cnt : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t rng_sample_cnt:8;
};
uint32_t val;
} lpperi_rng_cfg_reg_t;
/** Type of rng_data register
* need_des
*/
typedef union {
struct {
/** rnd_data : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t rnd_data:32;
};
uint32_t val;
} lpperi_rng_data_reg_t;
/** Type of cpu register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lpcore_dbgm_unavaliable:1;
};
uint32_t val;
} lpperi_cpu_reg_t;
/** Type of bus_timeout register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
uint32_t lp_peri_timeout_thres:16;
/** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_int_clear:1;
/** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lp_peri_timeout_protect_en:1;
};
uint32_t val;
} lpperi_bus_timeout_reg_t;
/** Type of bus_timeout_addr register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_addr:32;
};
uint32_t val;
} lpperi_bus_timeout_addr_reg_t;
/** Type of bus_timeout_uid register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lpperi_bus_timeout_uid_reg_t;
/** Type of mem_ctrl register
* need_des
*/
typedef union {
struct {
/** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag_clr:1;
/** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag:1;
uint32_t reserved_2:27;
/** uart_wakeup_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t uart_wakeup_en:1;
/** uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t uart_mem_force_pd:1;
/** uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t uart_mem_force_pu:1;
};
uint32_t val;
} lpperi_mem_ctrl_reg_t;
/** Type of interrupt_source register
* need_des
*/
typedef union {
struct {
/** lp_interrupt_source : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
uint32_t lp_interrupt_source:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lpperi_interrupt_source_reg_t;
/** Type of debug_sel0 register
* need des
*/
typedef union {
struct {
/** debug_sel0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t debug_sel0:7;
/** debug_sel1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
uint32_t debug_sel1:7;
/** debug_sel2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
uint32_t debug_sel2:7;
/** debug_sel3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
uint32_t debug_sel3:7;
uint32_t reserved_28:4;
};
uint32_t val;
} lpperi_debug_sel0_reg_t;
/** Type of debug_sel1 register
* need des
*/
typedef union {
struct {
/** debug_sel4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t debug_sel4:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lpperi_debug_sel1_reg_t;
/** Type of rng_data_sync register
* rng result sync register
*/
typedef union {
struct {
/** rnd_sync_data : RO; bitpos: [31:0]; default: 0;
* get rng sync result
*/
uint32_t rnd_sync_data:32;
};
uint32_t val;
} lpperi_rng_data_sync_reg_t;
/** Group: Version register */
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lpperi_date : R/W; bitpos: [30:0]; default: 37781793;
* need_des
*/
uint32_t lpperi_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpperi_date_reg_t;
typedef struct {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_reset_en_reg_t reset_en;
volatile lpperi_rng_cfg_reg_t rng_cfg;
volatile lpperi_rng_data_reg_t rng_data;
volatile lpperi_cpu_reg_t cpu;
volatile lpperi_bus_timeout_reg_t bus_timeout;
volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr;
volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid;
volatile lpperi_mem_ctrl_reg_t mem_ctrl;
volatile lpperi_interrupt_source_reg_t interrupt_source;
volatile lpperi_debug_sel0_reg_t debug_sel0;
volatile lpperi_debug_sel1_reg_t debug_sel1;
volatile lpperi_rng_data_sync_reg_t rng_data_sync;
uint32_t reserved_034[242];
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
extern lpperi_dev_t LPPERI;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

4
components/soc/esp32h21/register/soc/pcr_struct.h
View File

@@ -1784,12 +1784,12 @@ typedef union {
* This field indicates which one 32KHz clock will be used by timergroup. 1: XTAL32K
* (default), 2/3: 32KHz from pad GPIO0.
*/
uint32_t 32k_sel:2;
uint32_t clk_32k_sel:2;
/** 32k_modem_sel : R/W; bitpos: [3:2]; default: 1;
* This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 1:
* XTAL32K(default), 2/3: 32KHz from pad GPIO0.
*/
uint32_t 32k_modem_sel:2;
uint32_t clk_32k_modem_sel:2;
uint32_t reserved_4:28;
};
uint32_t val;

635
components/soc/esp32h21/register/soc/plic_reg.h Normal file
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@@ -0,0 +1,635 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11859
#define DR_REG_PLIC_MX_BASE ( 0x20001000 )
#define DR_REG_PLIC_UX_BASE ( 0x20001400 )
#define PLIC_MXINT_CONF_REG ( 0x200013FC )
#define PLIC_UXINT_CONF_REG ( 0x200017FC )
#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
/*PLIC MX*/
#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0)
/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF
#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S))
#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_ENABLE_S 0
#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4)
/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF
#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S))
#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_TYPE_S 0
#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8)
/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S))
#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_S 0
#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC)
/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_S 0
#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10)
/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT0_PRI 0x0000000F
#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S))
#define PLIC_CPU_MXINT0_PRI_V 0xF
#define PLIC_CPU_MXINT0_PRI_S 0
#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14)
/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT1_PRI 0x0000000F
#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S))
#define PLIC_CPU_MXINT1_PRI_V 0xF
#define PLIC_CPU_MXINT1_PRI_S 0
#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18)
/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT2_PRI 0x0000000F
#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S))
#define PLIC_CPU_MXINT2_PRI_V 0xF
#define PLIC_CPU_MXINT2_PRI_S 0
#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C)
/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT3_PRI 0x0000000F
#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S))
#define PLIC_CPU_MXINT3_PRI_V 0xF
#define PLIC_CPU_MXINT3_PRI_S 0
#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20)
/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT4_PRI 0x0000000F
#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S))
#define PLIC_CPU_MXINT4_PRI_V 0xF
#define PLIC_CPU_MXINT4_PRI_S 0
#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24)
/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT5_PRI 0x0000000F
#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S))
#define PLIC_CPU_MXINT5_PRI_V 0xF
#define PLIC_CPU_MXINT5_PRI_S 0
#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28)
/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT6_PRI 0x0000000F
#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S))
#define PLIC_CPU_MXINT6_PRI_V 0xF
#define PLIC_CPU_MXINT6_PRI_S 0
#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C)
/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT7_PRI 0x0000000F
#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S))
#define PLIC_CPU_MXINT7_PRI_V 0xF
#define PLIC_CPU_MXINT7_PRI_S 0
#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30)
/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT8_PRI 0x0000000F
#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S))
#define PLIC_CPU_MXINT8_PRI_V 0xF
#define PLIC_CPU_MXINT8_PRI_S 0
#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34)
/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT9_PRI 0x0000000F
#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S))
#define PLIC_CPU_MXINT9_PRI_V 0xF
#define PLIC_CPU_MXINT9_PRI_S 0
#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38)
/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT10_PRI 0x0000000F
#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S))
#define PLIC_CPU_MXINT10_PRI_V 0xF
#define PLIC_CPU_MXINT10_PRI_S 0
#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C)
/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT11_PRI 0x0000000F
#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S))
#define PLIC_CPU_MXINT11_PRI_V 0xF
#define PLIC_CPU_MXINT11_PRI_S 0
#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40)
/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT12_PRI 0x0000000F
#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S))
#define PLIC_CPU_MXINT12_PRI_V 0xF
#define PLIC_CPU_MXINT12_PRI_S 0
#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44)
/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT13_PRI 0x0000000F
#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S))
#define PLIC_CPU_MXINT13_PRI_V 0xF
#define PLIC_CPU_MXINT13_PRI_S 0
#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48)
/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT14_PRI 0x0000000F
#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S))
#define PLIC_CPU_MXINT14_PRI_V 0xF
#define PLIC_CPU_MXINT14_PRI_S 0
#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C)
/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT15_PRI 0x0000000F
#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S))
#define PLIC_CPU_MXINT15_PRI_V 0xF
#define PLIC_CPU_MXINT15_PRI_S 0
#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50)
/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT16_PRI 0x0000000F
#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S))
#define PLIC_CPU_MXINT16_PRI_V 0xF
#define PLIC_CPU_MXINT16_PRI_S 0
#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54)
/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT17_PRI 0x0000000F
#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S))
#define PLIC_CPU_MXINT17_PRI_V 0xF
#define PLIC_CPU_MXINT17_PRI_S 0
#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58)
/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT18_PRI 0x0000000F
#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S))
#define PLIC_CPU_MXINT18_PRI_V 0xF
#define PLIC_CPU_MXINT18_PRI_S 0
#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C)
/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT19_PRI 0x0000000F
#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S))
#define PLIC_CPU_MXINT19_PRI_V 0xF
#define PLIC_CPU_MXINT19_PRI_S 0
#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60)
/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT20_PRI 0x0000000F
#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S))
#define PLIC_CPU_MXINT20_PRI_V 0xF
#define PLIC_CPU_MXINT20_PRI_S 0
#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64)
/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT21_PRI 0x0000000F
#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S))
#define PLIC_CPU_MXINT21_PRI_V 0xF
#define PLIC_CPU_MXINT21_PRI_S 0
#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68)
/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT22_PRI 0x0000000F
#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S))
#define PLIC_CPU_MXINT22_PRI_V 0xF
#define PLIC_CPU_MXINT22_PRI_S 0
#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C)
/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT23_PRI 0x0000000F
#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S))
#define PLIC_CPU_MXINT23_PRI_V 0xF
#define PLIC_CPU_MXINT23_PRI_S 0
#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70)
/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT24_PRI 0x0000000F
#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S))
#define PLIC_CPU_MXINT24_PRI_V 0xF
#define PLIC_CPU_MXINT24_PRI_S 0
#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74)
/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT25_PRI 0x0000000F
#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S))
#define PLIC_CPU_MXINT25_PRI_V 0xF
#define PLIC_CPU_MXINT25_PRI_S 0
#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78)
/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT26_PRI 0x0000000F
#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S))
#define PLIC_CPU_MXINT26_PRI_V 0xF
#define PLIC_CPU_MXINT26_PRI_S 0
#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C)
/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT27_PRI 0x0000000F
#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S))
#define PLIC_CPU_MXINT27_PRI_V 0xF
#define PLIC_CPU_MXINT27_PRI_S 0
#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80)
/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT28_PRI 0x0000000F
#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S))
#define PLIC_CPU_MXINT28_PRI_V 0xF
#define PLIC_CPU_MXINT28_PRI_S 0
#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84)
/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT29_PRI 0x0000000F
#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S))
#define PLIC_CPU_MXINT29_PRI_V 0xF
#define PLIC_CPU_MXINT29_PRI_S 0
#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88)
/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT30_PRI 0x0000000F
#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S))
#define PLIC_CPU_MXINT30_PRI_V 0xF
#define PLIC_CPU_MXINT30_PRI_S 0
#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C)
/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT31_PRI 0x0000000F
#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S))
#define PLIC_CPU_MXINT31_PRI_V 0xF
#define PLIC_CPU_MXINT31_PRI_S 0
#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90)
/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_THRESH 0x000000FF
#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S))
#define PLIC_CPU_MXINT_THRESH_V 0xFF
#define PLIC_CPU_MXINT_THRESH_S 0
#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94)
/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/
#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S))
#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLAIM_S 0
/*PLIC UX*/
#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0)
/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S))
#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_S 0
#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4)
/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF
#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S))
#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_TYPE_S 0
#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8)
/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S))
#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLEAR_S 0
#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC)
/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_S 0
#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10)
/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT0_PRI 0x0000000F
#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S))
#define PLIC_CPU_UXINT0_PRI_V 0xF
#define PLIC_CPU_UXINT0_PRI_S 0
#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14)
/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT1_PRI 0x0000000F
#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S))
#define PLIC_CPU_UXINT1_PRI_V 0xF
#define PLIC_CPU_UXINT1_PRI_S 0
#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18)
/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT2_PRI 0x0000000F
#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S))
#define PLIC_CPU_UXINT2_PRI_V 0xF
#define PLIC_CPU_UXINT2_PRI_S 0
#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C)
/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT3_PRI 0x0000000F
#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S))
#define PLIC_CPU_UXINT3_PRI_V 0xF
#define PLIC_CPU_UXINT3_PRI_S 0
#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20)
/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT4_PRI 0x0000000F
#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S))
#define PLIC_CPU_UXINT4_PRI_V 0xF
#define PLIC_CPU_UXINT4_PRI_S 0
#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24)
/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT5_PRI 0x0000000F
#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S))
#define PLIC_CPU_UXINT5_PRI_V 0xF
#define PLIC_CPU_UXINT5_PRI_S 0
#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28)
/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT6_PRI 0x0000000F
#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S))
#define PLIC_CPU_UXINT6_PRI_V 0xF
#define PLIC_CPU_UXINT6_PRI_S 0
#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C)
/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT7_PRI 0x0000000F
#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S))
#define PLIC_CPU_UXINT7_PRI_V 0xF
#define PLIC_CPU_UXINT7_PRI_S 0
#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30)
/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT8_PRI 0x0000000F
#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S))
#define PLIC_CPU_UXINT8_PRI_V 0xF
#define PLIC_CPU_UXINT8_PRI_S 0
#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34)
/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT9_PRI 0x0000000F
#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S))
#define PLIC_CPU_UXINT9_PRI_V 0xF
#define PLIC_CPU_UXINT9_PRI_S 0
#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38)
/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT10_PRI 0x0000000F
#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S))
#define PLIC_CPU_UXINT10_PRI_V 0xF
#define PLIC_CPU_UXINT10_PRI_S 0
#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C)
/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT11_PRI 0x0000000F
#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S))
#define PLIC_CPU_UXINT11_PRI_V 0xF
#define PLIC_CPU_UXINT11_PRI_S 0
#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40)
/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT12_PRI 0x0000000F
#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S))
#define PLIC_CPU_UXINT12_PRI_V 0xF
#define PLIC_CPU_UXINT12_PRI_S 0
#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44)
/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT13_PRI 0x0000000F
#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S))
#define PLIC_CPU_UXINT13_PRI_V 0xF
#define PLIC_CPU_UXINT13_PRI_S 0
#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48)
/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT14_PRI 0x0000000F
#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S))
#define PLIC_CPU_UXINT14_PRI_V 0xF
#define PLIC_CPU_UXINT14_PRI_S 0
#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C)
/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT15_PRI 0x0000000F
#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S))
#define PLIC_CPU_UXINT15_PRI_V 0xF
#define PLIC_CPU_UXINT15_PRI_S 0
#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50)
/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT16_PRI 0x0000000F
#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S))
#define PLIC_CPU_UXINT16_PRI_V 0xF
#define PLIC_CPU_UXINT16_PRI_S 0
#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54)
/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT17_PRI 0x0000000F
#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S))
#define PLIC_CPU_UXINT17_PRI_V 0xF
#define PLIC_CPU_UXINT17_PRI_S 0
#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58)
/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT18_PRI 0x0000000F
#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S))
#define PLIC_CPU_UXINT18_PRI_V 0xF
#define PLIC_CPU_UXINT18_PRI_S 0
#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C)
/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT19_PRI 0x0000000F
#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S))
#define PLIC_CPU_UXINT19_PRI_V 0xF
#define PLIC_CPU_UXINT19_PRI_S 0
#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60)
/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT20_PRI 0x0000000F
#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S))
#define PLIC_CPU_UXINT20_PRI_V 0xF
#define PLIC_CPU_UXINT20_PRI_S 0
#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64)
/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT21_PRI 0x0000000F
#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S))
#define PLIC_CPU_UXINT21_PRI_V 0xF
#define PLIC_CPU_UXINT21_PRI_S 0
#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68)
/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT22_PRI 0x0000000F
#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S))
#define PLIC_CPU_UXINT22_PRI_V 0xF
#define PLIC_CPU_UXINT22_PRI_S 0
#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C)
/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT23_PRI 0x0000000F
#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S))
#define PLIC_CPU_UXINT23_PRI_V 0xF
#define PLIC_CPU_UXINT23_PRI_S 0
#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70)
/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT24_PRI 0x0000000F
#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S))
#define PLIC_CPU_UXINT24_PRI_V 0xF
#define PLIC_CPU_UXINT24_PRI_S 0
#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74)
/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT25_PRI 0x0000000F
#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S))
#define PLIC_CPU_UXINT25_PRI_V 0xF
#define PLIC_CPU_UXINT25_PRI_S 0
#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78)
/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT26_PRI 0x0000000F
#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S))
#define PLIC_CPU_UXINT26_PRI_V 0xF
#define PLIC_CPU_UXINT26_PRI_S 0
#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C)
/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT27_PRI 0x0000000F
#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S))
#define PLIC_CPU_UXINT27_PRI_V 0xF
#define PLIC_CPU_UXINT27_PRI_S 0
#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80)
/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT28_PRI 0x0000000F
#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S))
#define PLIC_CPU_UXINT28_PRI_V 0xF
#define PLIC_CPU_UXINT28_PRI_S 0
#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84)
/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT29_PRI 0x0000000F
#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S))
#define PLIC_CPU_UXINT29_PRI_V 0xF
#define PLIC_CPU_UXINT29_PRI_S 0
#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88)
/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT30_PRI 0x0000000F
#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S))
#define PLIC_CPU_UXINT30_PRI_V 0xF
#define PLIC_CPU_UXINT30_PRI_S 0
#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C)
/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT31_PRI 0x0000000F
#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S))
#define PLIC_CPU_UXINT31_PRI_V 0xF
#define PLIC_CPU_UXINT31_PRI_S 0
#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90)
/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_THRESH 0x000000FF
#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S))
#define PLIC_CPU_UXINT_THRESH_V 0xFF
#define PLIC_CPU_UXINT_THRESH_S 0
#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94)
/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S))
#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLAIM_S 0
#ifdef __cplusplus
}
#endif

460
components/soc/esp32h21/register/soc/pmu_reg.h
View File

@@ -503,6 +503,442 @@ extern "C" {
#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U
#define PMU_HP_ACTIVE_XPD_XTAL_S 31
/** PMU_HP_MODEM_DIG_POWER_REG register
* need_des
*/
#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34)
/** PMU_HP_MODEM_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_VDD_FLASH_MODE 0x0000000FU
#define PMU_HP_MODEM_VDD_FLASH_MODE_M (PMU_HP_MODEM_VDD_FLASH_MODE_V << PMU_HP_MODEM_VDD_FLASH_MODE_S)
#define PMU_HP_MODEM_VDD_FLASH_MODE_V 0x0000000FU
#define PMU_HP_MODEM_VDD_FLASH_MODE_S 18
/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22))
#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S)
#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U
#define PMU_HP_MODEM_HP_MEM_DSLP_S 22
/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU
#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S)
#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU
#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23
/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27))
#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S)
#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U
#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27
/** PMU_HP_MODEM_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_PD_HP_PERI_PD_EN (BIT(28))
#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_M (PMU_HP_MODEM_PD_HP_PERI_PD_EN_V << PMU_HP_MODEM_PD_HP_PERI_PD_EN_S)
#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_V 0x00000001U
#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28
/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29))
#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S)
#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U
#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29
/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30))
#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S)
#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U
#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30
/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31))
#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S)
#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U
#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31
/** PMU_HP_MODEM_ICG_HP_FUNC_REG register
* need_des
*/
#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38)
/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU
#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S)
#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU
#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0
/** PMU_HP_MODEM_ICG_HP_APB_REG register
* need_des
*/
#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c)
/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU
#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S)
#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU
#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0
/** PMU_HP_MODEM_ICG_MODEM_REG register
* need_des
*/
#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40)
/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U
#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S)
#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U
#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30
/** PMU_HP_MODEM_HP_SYS_CNTL_REG register
* need_des
*/
#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44)
/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24))
#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S)
#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U
#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24
/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25))
#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S)
#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U
#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25
/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26))
#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S)
#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U
#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26
/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27))
#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S)
#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U
#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27
/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28))
#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S)
#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U
#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28
/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29))
#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S)
#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U
#define PMU_HP_MODEM_DIG_CPU_STALL_S 29
/** PMU_HP_MODEM_HP_CK_POWER_REG register
* need_des
*/
#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48)
/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26))
#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S)
#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U
#define PMU_HP_MODEM_I2C_ISO_EN_S 26
/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_I2C_RETENTION (BIT(27))
#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S)
#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U
#define PMU_HP_MODEM_I2C_RETENTION_S 27
/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28))
#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S)
#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U
#define PMU_HP_MODEM_XPD_BB_I2C_S 28
/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29))
#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S)
#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U
#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29
/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_XPD_BBPLL (BIT(30))
#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S)
#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U
#define PMU_HP_MODEM_XPD_BBPLL_S 30
/** PMU_HP_MODEM_BIAS_REG register
* need_des
*/
#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c)
/** PMU_HP_MODEM_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_DCDC_CCM_ENB (BIT(9))
#define PMU_HP_MODEM_DCDC_CCM_ENB_M (PMU_HP_MODEM_DCDC_CCM_ENB_V << PMU_HP_MODEM_DCDC_CCM_ENB_S)
#define PMU_HP_MODEM_DCDC_CCM_ENB_V 0x00000001U
#define PMU_HP_MODEM_DCDC_CCM_ENB_S 9
/** PMU_HP_MODEM_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DCDC_CLEAR_RDY (BIT(10))
#define PMU_HP_MODEM_DCDC_CLEAR_RDY_M (PMU_HP_MODEM_DCDC_CLEAR_RDY_V << PMU_HP_MODEM_DCDC_CLEAR_RDY_S)
#define PMU_HP_MODEM_DCDC_CLEAR_RDY_V 0x00000001U
#define PMU_HP_MODEM_DCDC_CLEAR_RDY_S 10
/** PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS 0x00000003U
#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_M (PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V << PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S)
#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V 0x00000003U
#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S 11
/** PMU_HP_MODEM_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4;
* need_des
*/
#define PMU_HP_MODEM_DIG_PMU_DSFMOS 0x0000000FU
#define PMU_HP_MODEM_DIG_PMU_DSFMOS_M (PMU_HP_MODEM_DIG_PMU_DSFMOS_V << PMU_HP_MODEM_DIG_PMU_DSFMOS_S)
#define PMU_HP_MODEM_DIG_PMU_DSFMOS_V 0x0000000FU
#define PMU_HP_MODEM_DIG_PMU_DSFMOS_S 13
/** PMU_HP_MODEM_DCM_VSET : R/W; bitpos: [21:17]; default: 23;
* need_des
*/
#define PMU_HP_MODEM_DCM_VSET 0x0000001FU
#define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S)
#define PMU_HP_MODEM_DCM_VSET_V 0x0000001FU
#define PMU_HP_MODEM_DCM_VSET_S 17
/** PMU_HP_MODEM_DCM_MODE : R/W; bitpos: [23:22]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DCM_MODE 0x00000003U
#define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S)
#define PMU_HP_MODEM_DCM_MODE_V 0x00000003U
#define PMU_HP_MODEM_DCM_MODE_S 22
/** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_XPD_TRX (BIT(24))
#define PMU_HP_MODEM_XPD_TRX_M (PMU_HP_MODEM_XPD_TRX_V << PMU_HP_MODEM_XPD_TRX_S)
#define PMU_HP_MODEM_XPD_TRX_V 0x00000001U
#define PMU_HP_MODEM_XPD_TRX_S 24
/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_XPD_BIAS (BIT(25))
#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S)
#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U
#define PMU_HP_MODEM_XPD_BIAS_S 25
/** PMU_HP_MODEM_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DISCNNT_DIG_RTC (BIT(29))
#define PMU_HP_MODEM_DISCNNT_DIG_RTC_M (PMU_HP_MODEM_DISCNNT_DIG_RTC_V << PMU_HP_MODEM_DISCNNT_DIG_RTC_S)
#define PMU_HP_MODEM_DISCNNT_DIG_RTC_V 0x00000001U
#define PMU_HP_MODEM_DISCNNT_DIG_RTC_S 29
/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_PD_CUR (BIT(30))
#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S)
#define PMU_HP_MODEM_PD_CUR_V 0x00000001U
#define PMU_HP_MODEM_PD_CUR_S 30
/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31))
#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S)
#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U
#define PMU_HP_MODEM_BIAS_SLEEP_S 31
/** PMU_HP_MODEM_BACKUP_REG register
* need_des
*/
#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50)
/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0;
* need_des
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U
#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S)
#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U
#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4
/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0;
* need_des
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U
#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S)
#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U
#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14
/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0;
* need_des
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x0000001FU
#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S)
#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x0000001FU
#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20
/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29))
#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S)
#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U
#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29
/** PMU_HP_MODEM_BACKUP_CLK_REG register
* need_des
*/
#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54)
/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU
#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S)
#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU
#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0
/** PMU_HP_MODEM_SYSCLK_REG register
* need_des
*/
#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58)
/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26))
#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S)
#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U
#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26
/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27))
#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S)
#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U
#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27
/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28))
#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S)
#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U
#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28
/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29))
#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S)
#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U
#define PMU_HP_MODEM_ICG_SLP_SEL_S 29
/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U
#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S)
#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U
#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30
/** PMU_HP_MODEM_HP_REGULATOR0_REG register
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c)
/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(0))
#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S)
#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V 0x00000001U
#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 0
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16))
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17))
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17
/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18))
#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S)
#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U
#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23
/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU
#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S)
#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU
#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27
/** PMU_HP_MODEM_HP_REGULATOR1_REG register
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60)
/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU
#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S)
#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU
#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8
/** PMU_HP_MODEM_XTAL_REG register
* need_des
*/
#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64)
/** PMU_HP_MODEM_XPD_XTALX2 : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_XPD_XTALX2 (BIT(30))
#define PMU_HP_MODEM_XPD_XTALX2_M (PMU_HP_MODEM_XPD_XTALX2_V << PMU_HP_MODEM_XPD_XTALX2_S)
#define PMU_HP_MODEM_XPD_XTALX2_V 0x00000001U
#define PMU_HP_MODEM_XPD_XTALX2_S 30
/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define PMU_HP_MODEM_XPD_XTAL (BIT(31))
#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S)
#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U
#define PMU_HP_MODEM_XPD_XTAL_S 31
/** PMU_HP_SLEEP_DIG_POWER_REG register
* need_des
*/
@@ -1012,6 +1448,18 @@ extern "C" {
#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU
#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28
/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register
* need_des
*/
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4)
/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S)
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0
/** PMU_HP_SLEEP_LP_DIG_POWER_REG register
* need_des
*/
@@ -1092,6 +1540,18 @@ extern "C" {
#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U
#define PMU_HP_SLEEP_PD_OSC_CLK_S 31
/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register
* need_des
*/
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0)
/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S)
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0
/** PMU_LP_SLEEP_LP_REGULATOR0_REG register
* need_des
*/

3498
components/soc/esp32h21/register/soc/pmu_struct.h
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File diff suppressed because it is too large Load Diff

88
components/soc/esp32h21/register/soc/spi1_mem_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** SPI_MEM_CMD_REG register
* SPI1 memory command register
*/
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)
#define SPI_MEM_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x0)
/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
* The current status of SPI1 master FSM.
*/
@@ -172,7 +172,7 @@ extern "C" {
/** SPI_MEM_ADDR_REG register
* SPI1 address register
*/
#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)
#define SPI_MEM_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x4)
/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
* In user mode, it is the memory address. other then the bit0-bit23 is the memory
* address, the bit24-bit31 are the byte length of a transfer.
@@ -185,7 +185,7 @@ extern "C" {
/** SPI_MEM_CTRL_REG register
* SPI1 control register.
*/
#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)
#define SPI_MEM_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8)
/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
* In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
* level of SPI bus is output by the MSPI controller.
@@ -335,7 +335,7 @@ extern "C" {
/** SPI_MEM_CTRL1_REG register
* SPI1 control1 register.
*/
#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc)
#define SPI_MEM_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc)
/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -365,7 +365,7 @@ extern "C" {
/** SPI_MEM_CTRL2_REG register
* SPI1 control2 register.
*/
#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)
#define SPI_MEM_CTRL2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x10)
/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
* The FSM will be reset.
*/
@@ -377,7 +377,7 @@ extern "C" {
/** SPI_MEM_CLOCK_REG register
* SPI1 clock division control register.
*/
#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)
#define SPI_MEM_CLOCK_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x14)
/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to SPI_MEM_CLKCNT_N.
*/
@@ -411,7 +411,7 @@ extern "C" {
/** SPI_MEM_USER_REG register
* SPI1 user register.
*/
#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)
#define SPI_MEM_USER_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x18)
/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
* the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
*/
@@ -511,7 +511,7 @@ extern "C" {
/** SPI_MEM_USER1_REG register
* SPI1 user1 register.
*/
#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c)
#define SPI_MEM_USER1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x1c)
/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
* The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1).
@@ -531,7 +531,7 @@ extern "C" {
/** SPI_MEM_USER2_REG register
* SPI1 user2 register.
*/
#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)
#define SPI_MEM_USER2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x20)
/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
* The value of command.
*/
@@ -550,7 +550,7 @@ extern "C" {
/** SPI_MEM_MOSI_DLEN_REG register
* SPI1 send data bit length control register.
*/
#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)
#define SPI_MEM_MOSI_DLEN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x24)
/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
* The length in bits of write-data. The register value shall be (bit_num-1).
*/
@@ -562,7 +562,7 @@ extern "C" {
/** SPI_MEM_MISO_DLEN_REG register
* SPI1 receive data bit length control register.
*/
#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28)
#define SPI_MEM_MISO_DLEN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x28)
/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
* The length in bits of read-data. The register value shall be (bit_num-1).
*/
@@ -574,7 +574,7 @@ extern "C" {
/** SPI_MEM_RD_STATUS_REG register
* SPI1 status register.
*/
#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c)
#define SPI_MEM_RD_STATUS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c)
/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
* The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
*/
@@ -610,7 +610,7 @@ extern "C" {
/** SPI_MEM_MISC_REG register
* SPI1 misc register
*/
#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34)
#define SPI_MEM_MISC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x34)
/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
* SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
* device, such as flash, external RAM and so on.
@@ -647,7 +647,7 @@ extern "C" {
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38)
#define SPI_MEM_TX_CRC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x38)
/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
* For SPI1, the value of crc32.
* This field is only for internal debugging purposes. Do not use it in applications.
@@ -662,7 +662,7 @@ extern "C" {
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c)
#define SPI_MEM_CACHE_FCTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3c)
/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
@@ -729,7 +729,7 @@ extern "C" {
/** SPI_MEM_W0_REG register
* SPI1 memory data buffer0
*/
#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58)
#define SPI_MEM_W0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x58)
/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -741,7 +741,7 @@ extern "C" {
/** SPI_MEM_W1_REG register
* SPI1 memory data buffer1
*/
#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5c)
#define SPI_MEM_W1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x5c)
/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -753,7 +753,7 @@ extern "C" {
/** SPI_MEM_W2_REG register
* SPI1 memory data buffer2
*/
#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60)
#define SPI_MEM_W2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x60)
/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -765,7 +765,7 @@ extern "C" {
/** SPI_MEM_W3_REG register
* SPI1 memory data buffer3
*/
#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64)
#define SPI_MEM_W3_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x64)
/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -777,7 +777,7 @@ extern "C" {
/** SPI_MEM_W4_REG register
* SPI1 memory data buffer4
*/
#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68)
#define SPI_MEM_W4_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x68)
/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -789,7 +789,7 @@ extern "C" {
/** SPI_MEM_W5_REG register
* SPI1 memory data buffer5
*/
#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6c)
#define SPI_MEM_W5_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x6c)
/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -801,7 +801,7 @@ extern "C" {
/** SPI_MEM_W6_REG register
* SPI1 memory data buffer6
*/
#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70)
#define SPI_MEM_W6_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x70)
/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -813,7 +813,7 @@ extern "C" {
/** SPI_MEM_W7_REG register
* SPI1 memory data buffer7
*/
#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74)
#define SPI_MEM_W7_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x74)
/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -825,7 +825,7 @@ extern "C" {
/** SPI_MEM_W8_REG register
* SPI1 memory data buffer8
*/
#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78)
#define SPI_MEM_W8_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x78)
/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -837,7 +837,7 @@ extern "C" {
/** SPI_MEM_W9_REG register
* SPI1 memory data buffer9
*/
#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7c)
#define SPI_MEM_W9_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x7c)
/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -849,7 +849,7 @@ extern "C" {
/** SPI_MEM_W10_REG register
* SPI1 memory data buffer10
*/
#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80)
#define SPI_MEM_W10_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x80)
/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -861,7 +861,7 @@ extern "C" {
/** SPI_MEM_W11_REG register
* SPI1 memory data buffer11
*/
#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84)
#define SPI_MEM_W11_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x84)
/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -873,7 +873,7 @@ extern "C" {
/** SPI_MEM_W12_REG register
* SPI1 memory data buffer12
*/
#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88)
#define SPI_MEM_W12_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x88)
/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -885,7 +885,7 @@ extern "C" {
/** SPI_MEM_W13_REG register
* SPI1 memory data buffer13
*/
#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8c)
#define SPI_MEM_W13_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8c)
/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -897,7 +897,7 @@ extern "C" {
/** SPI_MEM_W14_REG register
* SPI1 memory data buffer14
*/
#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90)
#define SPI_MEM_W14_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x90)
/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -909,7 +909,7 @@ extern "C" {
/** SPI_MEM_W15_REG register
* SPI1 memory data buffer15
*/
#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94)
#define SPI_MEM_W15_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x94)
/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -921,7 +921,7 @@ extern "C" {
/** SPI_MEM_FLASH_WAITI_CTRL_REG register
* SPI1 wait idle control register
*/
#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98)
#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x98)
/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
* 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
* Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
@@ -980,7 +980,7 @@ extern "C" {
/** SPI_MEM_FLASH_SUS_CTRL_REG register
* SPI1 flash suspend control register
*/
#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9c)
#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x9c)
/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
* program erase resume bit, program erase suspend operation will be triggered when
* the bit is set. The bit will be cleared once the operation done.1: enable 0:
@@ -1078,7 +1078,7 @@ extern "C" {
/** SPI_MEM_FLASH_SUS_CMD_REG register
* SPI1 flash suspend command register
*/
#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xa0)
#define SPI_MEM_FLASH_SUS_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xa0)
/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
* Program/Erase suspend command.
*/
@@ -1098,7 +1098,7 @@ extern "C" {
/** SPI_MEM_SUS_STATUS_REG register
* SPI1 flash suspend status register
*/
#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xa4)
#define SPI_MEM_SUS_STATUS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xa4)
/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
* The status of flash suspend, only used in SPI1.
*/
@@ -1187,7 +1187,7 @@ extern "C" {
/** SPI_MEM_FLASH_WAITI_CTRL1_REG register
* SPI1 wait idle control register
*/
#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xac)
#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xac)
/** SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W; bitpos: [9:0]; default: 0;
* SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE.
*/
@@ -1206,7 +1206,7 @@ extern "C" {
/** SPI_MEM_INT_ENA_REG register
* SPI1 interrupt enable register
*/
#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0)
#define SPI_MEM_INT_ENA_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc0)
/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
* The enable bit for SPI_MEM_PER_END_INT interrupt.
*/
@@ -1253,7 +1253,7 @@ extern "C" {
/** SPI_MEM_INT_CLR_REG register
* SPI1 interrupt clear register
*/
#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4)
#define SPI_MEM_INT_CLR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc4)
/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
* The clear bit for SPI_MEM_PER_END_INT interrupt.
*/
@@ -1300,7 +1300,7 @@ extern "C" {
/** SPI_MEM_INT_RAW_REG register
* SPI1 interrupt raw register
*/
#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8)
#define SPI_MEM_INT_RAW_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc8)
/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
* command (0x7A) is sent and flash is resumed successfully. 0: Others.
@@ -1356,7 +1356,7 @@ extern "C" {
/** SPI_MEM_INT_ST_REG register
* SPI1 interrupt status register
*/
#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc)
#define SPI_MEM_INT_ST_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xcc)
/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
* The status bit for SPI_MEM_PER_END_INT interrupt.
*/
@@ -1403,7 +1403,7 @@ extern "C" {
/** SPI_MEM_DDR_REG register
* SPI1 DDR control register
*/
#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4)
#define SPI_MEM_DDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xd4)
/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
* 1: in ddr mode, 0 in sdr mode
*/
@@ -1512,7 +1512,7 @@ extern "C" {
/** SPI_MEM_TIMING_CALI_REG register
* SPI1 timing control register
*/
#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180)
#define SPI_MEM_TIMING_CALI_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x180)
/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
* The bit is used to enable timing auto-calibration for all reading operations.
*/
@@ -1531,7 +1531,7 @@ extern "C" {
/** SPI_MEM_CLOCK_GATE_REG register
* SPI1 clk_gate register
*/
#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200)
#define SPI_MEM_CLOCK_GATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x200)
/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
* Register clock gate enable signal. 1: Enable. 0: Disable.
*/
@@ -1543,7 +1543,7 @@ extern "C" {
/** SPI_MEM_DATE_REG register
* Version control register
*/
#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc)
#define SPI_MEM_DATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3fc)
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37786176;
* Version control register
*/

260
components/soc/esp32h21/register/soc/spi_mem_c_reg.h
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221
components/soc/esp32h21/register/soc/spi_struct.h
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@@ -1550,214 +1550,18 @@ typedef union {
/** Group: CPU-controlled data buffer */
/** Type of w0 register
* SPI CPU-controlled buffer0
/** Type of wn register
* SPI CPU-controlled buffer
*/
typedef union {
struct {
/** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf0:32;
uint32_t buf:32;
};
uint32_t val;
} spi_w0_reg_t;
/** Type of w1 register
* SPI CPU-controlled buffer1
*/
typedef union {
struct {
/** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf1:32;
};
uint32_t val;
} spi_w1_reg_t;
/** Type of w2 register
* SPI CPU-controlled buffer2
*/
typedef union {
struct {
/** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf2:32;
};
uint32_t val;
} spi_w2_reg_t;
/** Type of w3 register
* SPI CPU-controlled buffer3
*/
typedef union {
struct {
/** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf3:32;
};
uint32_t val;
} spi_w3_reg_t;
/** Type of w4 register
* SPI CPU-controlled buffer4
*/
typedef union {
struct {
/** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf4:32;
};
uint32_t val;
} spi_w4_reg_t;
/** Type of w5 register
* SPI CPU-controlled buffer5
*/
typedef union {
struct {
/** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf5:32;
};
uint32_t val;
} spi_w5_reg_t;
/** Type of w6 register
* SPI CPU-controlled buffer6
*/
typedef union {
struct {
/** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf6:32;
};
uint32_t val;
} spi_w6_reg_t;
/** Type of w7 register
* SPI CPU-controlled buffer7
*/
typedef union {
struct {
/** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf7:32;
};
uint32_t val;
} spi_w7_reg_t;
/** Type of w8 register
* SPI CPU-controlled buffer8
*/
typedef union {
struct {
/** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf8:32;
};
uint32_t val;
} spi_w8_reg_t;
/** Type of w9 register
* SPI CPU-controlled buffer9
*/
typedef union {
struct {
/** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf9:32;
};
uint32_t val;
} spi_w9_reg_t;
/** Type of w10 register
* SPI CPU-controlled buffer10
*/
typedef union {
struct {
/** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf10:32;
};
uint32_t val;
} spi_w10_reg_t;
/** Type of w11 register
* SPI CPU-controlled buffer11
*/
typedef union {
struct {
/** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf11:32;
};
uint32_t val;
} spi_w11_reg_t;
/** Type of w12 register
* SPI CPU-controlled buffer12
*/
typedef union {
struct {
/** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf12:32;
};
uint32_t val;
} spi_w12_reg_t;
/** Type of w13 register
* SPI CPU-controlled buffer13
*/
typedef union {
struct {
/** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf13:32;
};
uint32_t val;
} spi_w13_reg_t;
/** Type of w14 register
* SPI CPU-controlled buffer14
*/
typedef union {
struct {
/** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf14:32;
};
uint32_t val;
} spi_w14_reg_t;
/** Type of w15 register
* SPI CPU-controlled buffer15
*/
typedef union {
struct {
/** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf15:32;
};
uint32_t val;
} spi_w15_reg_t;
} spi_wn_reg_t;
/** Group: Version register */
/** Type of date register
@@ -1795,22 +1599,7 @@ typedef struct {
volatile spi_dma_int_st_reg_t dma_int_st;
volatile spi_dma_int_set_reg_t dma_int_set;
uint32_t reserved_048[20];
volatile spi_w0_reg_t w0;
volatile spi_w1_reg_t w1;
volatile spi_w2_reg_t w2;
volatile spi_w3_reg_t w3;
volatile spi_w4_reg_t w4;
volatile spi_w5_reg_t w5;
volatile spi_w6_reg_t w6;
volatile spi_w7_reg_t w7;
volatile spi_w8_reg_t w8;
volatile spi_w9_reg_t w9;
volatile spi_w10_reg_t w10;
volatile spi_w11_reg_t w11;
volatile spi_w12_reg_t w12;
volatile spi_w13_reg_t w13;
volatile spi_w14_reg_t w14;
volatile spi_w15_reg_t w15;
volatile spi_wn_reg_t data_buf[16];
uint32_t reserved_0d8[2];
volatile spi_slave_reg_t slave;
volatile spi_slave1_reg_t slave1;

11
components/soc/esp32h21/register/soc/system_reg.h Normal file
View File

@@ -0,0 +1,11 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/hp_system_reg.h"
#include "intpri_reg.h"
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0

229
components/soc/esp32h21/register/soc/systimer_struct.h
View File

@@ -68,24 +68,24 @@ typedef union {
/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */
/** Type of unit0_op register
* system timer unit0 value update register
/** Type of unit_op register
* system timer unit value update register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
/** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
uint32_t timer_unit0_value_valid:1;
/** timer_unit0_update : WT; bitpos: [30]; default: 0;
uint32_t timer_unit_value_valid:1;
/** timer_unit_update : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
uint32_t timer_unit0_update:1;
uint32_t timer_unit_update:1;
uint32_t reserved_31:1;
};
uint32_t val;
} systimer_unit0_op_reg_t;
} systimer_unit_op_reg_t;
/** Type of unit0_load_hi register
* system timer unit0 value high load register
@@ -95,7 +95,7 @@ typedef union {
/** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 20 bits
*/
uint32_t timer_unit0_load_hi:20;
uint32_t timer_unit_load_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
@@ -106,10 +106,10 @@ typedef union {
*/
typedef union {
struct {
/** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bits
/** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit load low 32 bits
*/
uint32_t timer_unit0_load_lo:32;
uint32_t timer_unit_load_lo:32;
};
uint32_t val;
} systimer_unit0_load_lo_reg_t;
@@ -119,10 +119,10 @@ typedef union {
*/
typedef union {
struct {
/** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0;
/** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
uint32_t timer_unit0_value_hi:20;
uint32_t timer_unit_value_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
@@ -133,48 +133,27 @@ typedef union {
*/
typedef union {
struct {
/** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0;
/** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
uint32_t timer_unit0_value_lo:32;
uint32_t timer_unit_value_lo:32;
};
uint32_t val;
} systimer_unit0_value_lo_reg_t;
/** Type of unit0_load register
* system timer unit0 conf sync register
/** Type of unit_load register
* system timer unit conf sync register
*/
typedef union {
struct {
/** timer_unit0_load : WT; bitpos: [0]; default: 0;
* timer unit0 sync enable signal
/** timer_unit_load : WT; bitpos: [0]; default: 0;
* timer unit sync enable signal
*/
uint32_t timer_unit0_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_unit0_load_reg_t;
/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */
/** Type of unit1_op register
* system timer unit1 value update register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
uint32_t timer_unit1_value_valid:1;
/** timer_unit1_update : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
uint32_t timer_unit1_update:1;
uint32_t reserved_31:1;
};
uint32_t val;
} systimer_unit1_op_reg_t;
} systimer_unit_load_reg_t;
/** Type of unit1_load_hi register
* system timer unit1 value high load register
@@ -230,31 +209,16 @@ typedef union {
uint32_t val;
} systimer_unit1_value_lo_reg_t;
/** Type of unit1_load register
* system timer unit1 conf sync register
*/
typedef union {
struct {
/** timer_unit1_load : WT; bitpos: [0]; default: 0;
* timer unit1 sync enable signal
*/
uint32_t timer_unit1_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_unit1_load_reg_t;
/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */
/** Type of target0_hi register
* system timer comp0 value high register
*/
typedef union {
struct {
/** timer_target0_hi : R/W; bitpos: [19:0]; default: 0;
/** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 20 bits
*/
uint32_t timer_target0_hi:20;
uint32_t timer_target_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
@@ -265,49 +229,49 @@ typedef union {
*/
typedef union {
struct {
/** timer_target0_lo : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bits
/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
* timer target low 32 bits
*/
uint32_t timer_target0_lo:32;
uint32_t timer_target_lo:32;
};
uint32_t val;
} systimer_target0_lo_reg_t;
/** Type of target0_conf register
/** Type of target_conf register
* system timer comp0 target mode register
*/
typedef union {
struct {
/** target0_period : R/W; bitpos: [25:0]; default: 0;
* target0 period
/** target_period : R/W; bitpos: [25:0]; default: 0;
* target period
*/
uint32_t target0_period:26;
uint32_t target_period:26;
uint32_t reserved_26:4;
/** target0_period_mode : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
/** target_period_mode : R/W; bitpos: [30]; default: 0;
* Set target to period mode
*/
uint32_t target0_period_mode:1;
uint32_t target_period_mode:1;
/** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target0_timer_unit_sel:1;
uint32_t target_timer_unit_sel:1;
};
uint32_t val;
} systimer_target0_conf_reg_t;
} systimer_target_conf_reg_t;
/** Type of comp0_load register
* system timer comp0 conf sync register
/** Type of comp_load register
* system timer comp conf sync register
*/
typedef union {
struct {
/** timer_comp0_load : WT; bitpos: [0]; default: 0;
* timer comp0 sync enable signal
/** timer_comp_load : WT; bitpos: [0]; default: 0;
* timer comp sync enable signal
*/
uint32_t timer_comp0_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp0_load_reg_t;
} systimer_comp_load_reg_t;
/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */
@@ -360,21 +324,6 @@ typedef union {
uint32_t val;
} systimer_target1_conf_reg_t;
/** Type of comp1_load register
* system timer comp1 conf sync register
*/
typedef union {
struct {
/** timer_comp1_load : WT; bitpos: [0]; default: 0;
* timer comp1 sync enable signal
*/
uint32_t timer_comp1_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp1_load_reg_t;
/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */
/** Type of target2_hi register
* system timer comp2 value high register
@@ -403,43 +352,6 @@ typedef union {
uint32_t val;
} systimer_target2_lo_reg_t;
/** Type of target2_conf register
* system timer comp2 target mode register
*/
typedef union {
struct {
/** target2_period : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
uint32_t target2_period:26;
uint32_t reserved_26:4;
/** target2_period_mode : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
uint32_t target2_period_mode:1;
/** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target2_timer_unit_sel:1;
};
uint32_t val;
} systimer_target2_conf_reg_t;
/** Type of comp2_load register
* system timer comp2 conf sync register
*/
typedef union {
struct {
/** timer_comp2_load : WT; bitpos: [0]; default: 0;
* timer comp2 sync enable signal
*/
uint32_t timer_comp2_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp2_load_reg_t;
/** Group: SYSTEM TIMER INTERRUPT REGISTER */
/** Type of int_ena register
* systimer interrupt enable register
@@ -631,43 +543,44 @@ typedef union {
uint32_t val;
} systimer_date_reg_t;
typedef struct systimer_unit_load_val_reg
{
systimer_unit0_load_hi_reg_t hi;
systimer_unit0_load_lo_reg_t lo;
} systimer_unit_load_val_reg_t;
typedef struct {
typedef struct systimer_target_val_reg
{
systimer_target0_hi_reg_t hi;
systimer_target0_lo_reg_t lo;
} systimer_target_val_reg_t;
typedef struct systimer_unit_value_reg
{
systimer_unit0_value_hi_reg_t hi;
systimer_unit0_value_lo_reg_t lo;
} systimer_unit_value_reg_t;
typedef struct systimer_real_target_reg
{
systimer_real_target0_lo_reg_t lo;
systimer_real_target0_hi_reg_t hi;
} systimer_real_target_reg_t;
typedef struct systimer_dev_t{
volatile systimer_conf_reg_t conf;
volatile systimer_unit0_op_reg_t unit0_op;
volatile systimer_unit1_op_reg_t unit1_op;
volatile systimer_unit0_load_hi_reg_t unit0_load_hi;
volatile systimer_unit0_load_lo_reg_t unit0_load_lo;
volatile systimer_unit1_load_hi_reg_t unit1_load_hi;
volatile systimer_unit1_load_lo_reg_t unit1_load_lo;
volatile systimer_target0_hi_reg_t target0_hi;
volatile systimer_target0_lo_reg_t target0_lo;
volatile systimer_target1_hi_reg_t target1_hi;
volatile systimer_target1_lo_reg_t target1_lo;
volatile systimer_target2_hi_reg_t target2_hi;
volatile systimer_target2_lo_reg_t target2_lo;
volatile systimer_target0_conf_reg_t target0_conf;
volatile systimer_target1_conf_reg_t target1_conf;
volatile systimer_target2_conf_reg_t target2_conf;
volatile systimer_unit0_value_hi_reg_t unit0_value_hi;
volatile systimer_unit0_value_lo_reg_t unit0_value_lo;
volatile systimer_unit1_value_hi_reg_t unit1_value_hi;
volatile systimer_unit1_value_lo_reg_t unit1_value_lo;
volatile systimer_comp0_load_reg_t comp0_load;
volatile systimer_comp1_load_reg_t comp1_load;
volatile systimer_comp2_load_reg_t comp2_load;
volatile systimer_unit0_load_reg_t unit0_load;
volatile systimer_unit1_load_reg_t unit1_load;
volatile systimer_unit_op_reg_t unit_op[2];
volatile systimer_unit_load_val_reg_t unit_load_val[2];
volatile systimer_target_val_reg_t target_val[3];
volatile systimer_target_conf_reg_t target_conf[3];
volatile systimer_unit_value_reg_t unit_val[2];
volatile systimer_comp_load_reg_t comp_load[3];
volatile systimer_unit_load_reg_t unit_load[2];
volatile systimer_int_ena_reg_t int_ena;
volatile systimer_int_raw_reg_t int_raw;
volatile systimer_int_clr_reg_t int_clr;
volatile systimer_int_st_reg_t int_st;
volatile systimer_real_target0_lo_reg_t real_target0_lo;
volatile systimer_real_target0_hi_reg_t real_target0_hi;
volatile systimer_real_target1_lo_reg_t real_target1_lo;
volatile systimer_real_target1_hi_reg_t real_target1_hi;
volatile systimer_real_target2_lo_reg_t real_target2_lo;
volatile systimer_real_target2_hi_reg_t real_target2_hi;
volatile systimer_real_target_reg_t real_target[3];
uint32_t reserved_08c[28];
volatile systimer_date_reg_t date;
} systimer_dev_t;

21
components/soc/esp32h21/register/soc/timer_group_struct.h
View File

@@ -519,17 +519,20 @@ typedef union {
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t config;
volatile timg_txlo_reg_t lo;
volatile timg_txhi_reg_t hi;
volatile timg_txupdate_reg_t update;
volatile timg_txalarmlo_reg_t alarmlo;
volatile timg_txalarmhi_reg_t alarmhi;
volatile timg_txloadlo_reg_t loadlo;
volatile timg_txloadhi_reg_t loadhi;
volatile timg_txload_reg_t load;
} timg_hwtimer_reg_t;
typedef struct {
volatile timg_txconfig_reg_t t0config;
volatile timg_txlo_reg_t t0lo;
volatile timg_txhi_reg_t t0hi;
volatile timg_txupdate_reg_t t0update;
volatile timg_txalarmlo_reg_t t0alarmlo;
volatile timg_txalarmhi_reg_t t0alarmhi;
volatile timg_txloadlo_reg_t t0loadlo;
volatile timg_txloadhi_reg_t t0loadhi;
volatile timg_txload_reg_t t0load;
volatile timg_hwtimer_reg_t hw_timer[1];
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;

76
components/soc/esp32h21/register/soc/uart_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** UART_FIFO_REG register
* FIFO data register
*/
#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
#define UART_FIFO_REG(i) (DR_REG_UART_BASE(i) + 0x0)
/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
* UART $n accesses FIFO via this register.
*/
@@ -26,7 +26,7 @@ extern "C" {
/** UART_INT_RAW_REG register
* Raw interrupt status
*/
#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
#define UART_INT_RAW_REG(i) (DR_REG_UART_BASE(i) + 0x4)
/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when receiver receives more data than
* what rxfifo_full_thrhd specifies.
@@ -191,7 +191,7 @@ extern "C" {
/** UART_INT_ST_REG register
* Masked interrupt status
*/
#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
#define UART_INT_ST_REG(i) (DR_REG_UART_BASE(i) + 0x8)
/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
* This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
*/
@@ -341,7 +341,7 @@ extern "C" {
/** UART_INT_ENA_REG register
* Interrupt enable bits
*/
#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
#define UART_INT_ENA_REG(i) (DR_REG_UART_BASE(i) + 0xc)
/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
* This is the enable bit for rxfifo_full_int_st register.
*/
@@ -486,7 +486,7 @@ extern "C" {
/** UART_INT_CLR_REG register
* Interrupt clear bits
*/
#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
#define UART_INT_CLR_REG(i) (DR_REG_UART_BASE(i) + 0x10)
/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the rxfifo_full_int_raw interrupt.
*/
@@ -631,7 +631,7 @@ extern "C" {
/** UART_CLKDIV_SYNC_REG register
* Clock divider configuration
*/
#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
#define UART_CLKDIV_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x14)
/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
* The integral part of the frequency divider factor.
*/
@@ -650,7 +650,7 @@ extern "C" {
/** UART_RX_FILT_REG register
* Rx Filter configuration
*/
#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
#define UART_RX_FILT_REG(i) (DR_REG_UART_BASE(i) + 0x18)
/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
* when input pulse width is lower than this value the pulse is ignored.
*/
@@ -669,7 +669,7 @@ extern "C" {
/** UART_STATUS_REG register
* UART status register
*/
#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
#define UART_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x1c)
/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
* Stores the byte number of valid data in Rx-FIFO.
*/
@@ -730,7 +730,7 @@ extern "C" {
/** UART_CONF0_SYNC_REG register
* a
*/
#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
#define UART_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x20)
/** UART_PARITY : R/W; bitpos: [0]; default: 0;
* This register is used to configure the parity check mode.
*/
@@ -893,7 +893,7 @@ extern "C" {
/** UART_CONF1_REG register
* Configuration register 1
*/
#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
#define UART_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x24)
/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
* It will produce rxfifo_full_int interrupt when receiver receives more data than
* this register value.
@@ -958,7 +958,7 @@ extern "C" {
/** UART_HWFC_CONF_SYNC_REG register
* Hardware flow-control configuration
*/
#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
#define UART_HWFC_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x2c)
/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
* This register is used to configure the maximum amount of data that can be received
* when hardware flow control works.
@@ -978,7 +978,7 @@ extern "C" {
/** UART_SLEEP_CONF0_REG register
* UART sleep configure register 0
*/
#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
#define UART_SLEEP_CONF0_REG(i) (DR_REG_UART_BASE(i) + 0x30)
/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
* This register restores the specified wake up char1 to wake up
*/
@@ -1011,7 +1011,7 @@ extern "C" {
/** UART_SLEEP_CONF1_REG register
* UART sleep configure register 1
*/
#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
#define UART_SLEEP_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x34)
/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
* This register restores the specified char0 to wake up
*/
@@ -1023,7 +1023,7 @@ extern "C" {
/** UART_SLEEP_CONF2_REG register
* UART sleep configure register 2
*/
#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
#define UART_SLEEP_CONF2_REG(i) (DR_REG_UART_BASE(i) + 0x38)
/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
* The uart is activated from light sleeping mode when the input rxd edge changes more
* times than this register value.
@@ -1066,7 +1066,7 @@ extern "C" {
/** UART_SWFC_CONF0_SYNC_REG register
* Software flow-control character configuration
*/
#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
#define UART_SWFC_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x3c)
/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
* This register stores the Xon flow control char.
*/
@@ -1138,7 +1138,7 @@ extern "C" {
/** UART_SWFC_CONF1_REG register
* Software flow-control character configuration
*/
#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
#define UART_SWFC_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x40)
/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
* When the data amount in Rx-FIFO is less than this register value with
* uart_sw_flow_con_en set to 1 it will send a Xon char.
@@ -1159,7 +1159,7 @@ extern "C" {
/** UART_TXBRK_CONF_SYNC_REG register
* Tx Break character configuration
*/
#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
#define UART_TXBRK_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x44)
/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
* This register is used to configure the number of 0 to be sent after the process of
* sending data is done. It is active when txd_brk is set to 1.
@@ -1172,7 +1172,7 @@ extern "C" {
/** UART_IDLE_CONF_SYNC_REG register
* Frame-end idle configuration
*/
#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
#define UART_IDLE_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x48)
/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
* It will produce frame end signal when receiver takes more time to receive one byte
* data than this register value.
@@ -1192,7 +1192,7 @@ extern "C" {
/** UART_RS485_CONF_SYNC_REG register
* RS485 mode configuration
*/
#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
#define UART_RS485_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x4c)
/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
* Set this bit to choose the rs485 mode.
*/
@@ -1247,7 +1247,7 @@ extern "C" {
/** UART_AT_CMD_PRECNT_SYNC_REG register
* Pre-sequence timing configuration
*/
#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
#define UART_AT_CMD_PRECNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x50)
/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
* This register is used to configure the idle duration time before the first at_cmd
* is received by receiver.
@@ -1260,7 +1260,7 @@ extern "C" {
/** UART_AT_CMD_POSTCNT_SYNC_REG register
* Post-sequence timing configuration
*/
#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x54)
/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
* This register is used to configure the duration time between the last at_cmd and
* the next data.
@@ -1273,7 +1273,7 @@ extern "C" {
/** UART_AT_CMD_GAPTOUT_SYNC_REG register
* Timeout configuration
*/
#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x58)
/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
* This register is used to configure the duration time between the at_cmd chars.
*/
@@ -1285,7 +1285,7 @@ extern "C" {
/** UART_AT_CMD_CHAR_SYNC_REG register
* AT escape sequence detection configuration
*/
#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
#define UART_AT_CMD_CHAR_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x5c)
/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
* This register is used to configure the content of at_cmd char.
*/
@@ -1305,7 +1305,7 @@ extern "C" {
/** UART_MEM_CONF_REG register
* UART memory power configuration
*/
#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
#define UART_MEM_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x60)
/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
* Set this bit to force power down UART memory.
*/
@@ -1324,7 +1324,7 @@ extern "C" {
/** UART_TOUT_CONF_SYNC_REG register
* UART threshold and allocation configuration
*/
#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
#define UART_TOUT_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x64)
/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
* This is the enable bit for uart receiver's timeout function.
*/
@@ -1352,7 +1352,7 @@ extern "C" {
/** UART_MEM_TX_STATUS_REG register
* Tx-SRAM write and read offset address.
*/
#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
#define UART_MEM_TX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x68)
/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
* This register stores the offset write address in Tx-SRAM.
*/
@@ -1371,7 +1371,7 @@ extern "C" {
/** UART_MEM_RX_STATUS_REG register
* Rx-SRAM write and read offset address.
*/
#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
#define UART_MEM_RX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x6c)
/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
* This register stores the offset read address in RX-SRAM.
*/
@@ -1390,7 +1390,7 @@ extern "C" {
/** UART_FSM_STATUS_REG register
* UART transmit and receive status.
*/
#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
#define UART_FSM_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x70)
/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
* This is the status register of receiver.
*/
@@ -1409,7 +1409,7 @@ extern "C" {
/** UART_POSPULSE_REG register
* Autobaud high pulse register
*/
#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
#define UART_POSPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x74)
/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the minimal input clock count between two positive edges. It
* is used in boudrate-detect process.
@@ -1422,7 +1422,7 @@ extern "C" {
/** UART_NEGPULSE_REG register
* Autobaud low pulse register
*/
#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
#define UART_NEGPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x78)
/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the minimal input clock count between two negative edges. It
* is used in boudrate-detect process.
@@ -1435,7 +1435,7 @@ extern "C" {
/** UART_LOWPULSE_REG register
* Autobaud minimum low pulse duration register
*/
#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
#define UART_LOWPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x7c)
/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the minimum duration time of the low level pulse.
* It is used in baud rate-detect process.
@@ -1448,7 +1448,7 @@ extern "C" {
/** UART_HIGHPULSE_REG register
* Autobaud minimum high pulse duration register
*/
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
#define UART_HIGHPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x80)
/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the maximum duration time for the high level
* pulse. It is used in baud rate-detect process.
@@ -1461,7 +1461,7 @@ extern "C" {
/** UART_RXD_CNT_REG register
* Autobaud edge change count register
*/
#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
#define UART_RXD_CNT_REG(i) (DR_REG_UART_BASE(i) + 0x84)
/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
* This register stores the count of rxd edge change. It is used in baud rate-detect
* process.
@@ -1474,7 +1474,7 @@ extern "C" {
/** UART_CLK_CONF_REG register
* UART core clock configuration
*/
#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
#define UART_CLK_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x88)
/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/
@@ -1507,7 +1507,7 @@ extern "C" {
/** UART_DATE_REG register
* UART Version register
*/
#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
#define UART_DATE_REG(i) (DR_REG_UART_BASE(i) + 0x8c)
/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848;
* This is the version register.
*/
@@ -1519,7 +1519,7 @@ extern "C" {
/** UART_AFIFO_STATUS_REG register
* UART AFIFO Status
*/
#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
#define UART_AFIFO_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x90)
/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
* Full signal of APB TX AFIFO.
*/
@@ -1552,7 +1552,7 @@ extern "C" {
/** UART_REG_UPDATE_REG register
* UART Registers Configuration Update register
*/
#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
#define UART_REG_UPDATE_REG(i) (DR_REG_UART_BASE(i) + 0x98)
/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
* Software write 1 would synchronize registers into UART Core clock domain and would
* be cleared by hardware after synchronization is done.
@@ -1565,7 +1565,7 @@ extern "C" {
/** UART_ID_REG register
* UART ID register
*/
#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
#define UART_ID_REG(i) (DR_REG_UART_BASE(i) + 0x9c)
/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
* This register is used to configure the uart_id.
*/

129
components/soc/esp32h21/register/soc/xts_aes_reg.h Normal file
View File

@@ -0,0 +1,129 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)
/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: This field is only used to generate include file in c case. This field is useles
s. Please do not use this field..*/
#define XTS_AES_PLAIN 0xFFFFFFFF
#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
#define XTS_AES_PLAIN_V 0xFFFFFFFF
#define XTS_AES_PLAIN_S 0
#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)
/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: This bits stores the line-size parameter which will be used in manual encryption
calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
1: 32-bytes, 2: 64-bytes, 3:reserved..*/
#define XTS_AES_LINESIZE 0x00000003
#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
#define XTS_AES_LINESIZE_V 0x3
#define XTS_AES_LINESIZE_S 0
#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: This bit stores the destination parameter which will be used in manual encryption
n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
used..*/
#define XTS_AES_DESTINATION (BIT(0))
#define XTS_AES_DESTINATION_M (BIT(0))
#define XTS_AES_DESTINATION_V 0x1
#define XTS_AES_DESTINATION_S 0
#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: This bits stores the physical-address parameter which will be used in manual enc
ryption calculation. This value should aligned with byte number decided by line-
size parameter..*/
#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF
#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF
#define XTS_AES_PHYSICAL_ADDRESS_S 0
#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)
/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to trigger the process of manual encryption calculation. This actio
n should only be asserted when manual encryption status is 0. After this action,
manual encryption status becomes 1. After calculation is done, manual encryption
n status becomes 2..*/
#define XTS_AES_TRIGGER (BIT(0))
#define XTS_AES_TRIGGER_M (BIT(0))
#define XTS_AES_TRIGGER_V 0x1
#define XTS_AES_TRIGGER_S 0
#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)
/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to release encrypted result to mspi. This action should only be ass
erted when manual encryption status is 2. After this action, manual encryption s
tatus will become 3..*/
#define XTS_AES_RELEASE (BIT(0))
#define XTS_AES_RELEASE_M (BIT(0))
#define XTS_AES_RELEASE_V 0x1
#define XTS_AES_RELEASE_S 0
#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)
/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
en manual encryption status is 3. After this action, manual encryption status wi
ll become 0..*/
#define XTS_AES_DESTROY (BIT(0))
#define XTS_AES_DESTROY_M (BIT(0))
#define XTS_AES_DESTROY_V 0x1
#define XTS_AES_DESTROY_S 0
#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
calculation, 2: encryption calculation is done but the encrypted result is invi
sible to mspi, 3: the encrypted result is visible to mspi..*/
#define XTS_AES_STATE 0x00000003
#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
#define XTS_AES_STATE_V 0x3
#define XTS_AES_STATE_S 0
#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)
/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
/*description: This bits stores the last modified-time of manual encryption feature..*/
#define XTS_AES_DATE 0x3FFFFFFF
#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
#define XTS_AES_DATE_V 0x3FFFFFFF
#define XTS_AES_DATE_S 0
#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4))
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4
/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
ing key 1..*/
#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3))
#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3))
#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1
#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3
/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
7: The bigger the number is, the more secure the cryption is. (Note that the per
formance of cryption will decrease together with this number increasing).*/
#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007
#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7
#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0
#ifdef __cplusplus
}
#endif