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change(soc): correct esp32p4 regi2c related registers

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This commit is contained in:
Song Ruo Jing
2023-12-11 14:44:18 +08:00
parent 5d8fb281e7
commit 80c5cf27e8
6 changed files with 329 additions and 51 deletions
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16
components/soc/esp32p4/include/soc/regi2c_bbpll.h
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@@ -1,16 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_bbpll.h
* @brief Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_clk_cpu_freq_set function in rtc_clk.c.
*/

23
components/soc/esp32p4/include/soc/regi2c_bias.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,5 +11,24 @@
* @brief Register definitions for bias
*
* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
* bootloader_hardware_init function in bootloader_esp32c6.c.
* rtc_clk_init function in esp32p4/rtc_clk_init.c.
*/
#define I2C_BIAS 0x6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_OR_FORCE_XPD_CK 4
#define I2C_BIAS_OR_FORCE_XPD_CK_MSB 0
#define I2C_BIAS_OR_FORCE_XPD_CK_LSB 0
#define I2C_BIAS_OR_FORCE_XPD_REF_OUT_BUF 4
#define I2C_BIAS_OR_FORCE_XPD_REF_OUT_BUF_MSB 1
#define I2C_BIAS_OR_FORCE_XPD_REF_OUT_BUF_LSB 1
#define I2C_BIAS_OR_FORCE_XPD_IPH 4
#define I2C_BIAS_OR_FORCE_XPD_IPH_MSB 2
#define I2C_BIAS_OR_FORCE_XPD_IPH_LSB 2
#define I2C_BIAS_OR_FORCE_XPD_VGATE_BUF 4
#define I2C_BIAS_OR_FORCE_XPD_VGATE_BUF_MSB 3
#define I2C_BIAS_OR_FORCE_XPD_VGATE_BUF_LSB 3

139
components/soc/esp32p4/include/soc/regi2c_cpll.h Normal file
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@@ -0,0 +1,139 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_cpll.h
* @brief Register definitions for CPU_PLL (CPLL)
*
* This file lists register fields of CPLL, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_CPLL 0x67
#define I2C_CPLL_HOSTID 0
#define I2C_CPLL_IR_CAL_DELAY 0
#define I2C_CPLL_IR_CAL_DELAY_MSB 3
#define I2C_CPLL_IR_CAL_DELAY_LSB 0
#define I2C_CPLL_IR_CAL_CK_DIV 0
#define I2C_CPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_CPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_CPLL_IR_CAL_EXT_CAP 1
#define I2C_CPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_CPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_CPLL_IR_CAL_ENX_CAP 1
#define I2C_CPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_CPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_CPLL_IR_CAL_RSTB 1
#define I2C_CPLL_IR_CAL_RSTB_MSB 5
#define I2C_CPLL_IR_CAL_RSTB_LSB 5
#define I2C_CPLL_IR_CAL_START 1
#define I2C_CPLL_IR_CAL_START_MSB 6
#define I2C_CPLL_IR_CAL_START_LSB 6
#define I2C_CPLL_IR_CAL_UNSTOP 1
#define I2C_CPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_CPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_CPLL_OC_REF_DIV 2
#define I2C_CPLL_OC_REF_DIV_MSB 3
#define I2C_CPLL_OC_REF_DIV_LSB 0
#define I2C_CPLL_OC_DCHGP 2
#define I2C_CPLL_OC_DCHGP_MSB 6
#define I2C_CPLL_OC_DCHGP_LSB 4
#define I2C_CPLL_OC_ENB_FCAL 2
#define I2C_CPLL_OC_ENB_FCAL_MSB 7
#define I2C_CPLL_OC_ENB_FCAL_LSB 7
#define I2C_CPLL_OC_DIV_7_0 3
#define I2C_CPLL_OC_DIV_7_0_MSB 7
#define I2C_CPLL_OC_DIV_7_0_LSB 0
#define I2C_CPLL_MODE_HF 4
#define I2C_CPLL_MODE_HF_MSB 1
#define I2C_CPLL_MODE_HF_LSB 1
#define I2C_CPLL_DIV_CPU 4
#define I2C_CPLL_DIV_CPU_MSB 5
#define I2C_CPLL_DIV_CPU_LSB 5
#define I2C_CPLL_OC_ENB_VCON 4
#define I2C_CPLL_OC_ENB_VCON_MSB 6
#define I2C_CPLL_OC_ENB_VCON_LSB 6
#define I2C_CPLL_OC_TSCHGP 4
#define I2C_CPLL_OC_TSCHGP_MSB 7
#define I2C_CPLL_OC_TSCHGP_LSB 7
#define I2C_CPLL_OC_DR1 5
#define I2C_CPLL_OC_DR1_MSB 2
#define I2C_CPLL_OC_DR1_LSB 0
#define I2C_CPLL_OC_DR3 5
#define I2C_CPLL_OC_DR3_MSB 6
#define I2C_CPLL_OC_DR3_LSB 4
#define I2C_CPLL_EN_USB 5
#define I2C_CPLL_EN_USB_MSB 7
#define I2C_CPLL_EN_USB_LSB 7
#define I2C_CPLL_OC_DCUR 6
#define I2C_CPLL_OC_DCUR_MSB 2
#define I2C_CPLL_OC_DCUR_LSB 0
#define I2C_CPLL_INC_CUR 6
#define I2C_CPLL_INC_CUR_MSB 3
#define I2C_CPLL_INC_CUR_LSB 3
#define I2C_CPLL_OC_DHREF_SEL 6
#define I2C_CPLL_OC_DHREF_SEL_MSB 5
#define I2C_CPLL_OC_DHREF_SEL_LSB 4
#define I2C_CPLL_OC_DLREF_SEL 6
#define I2C_CPLL_OC_DLREF_SEL_MSB 7
#define I2C_CPLL_OC_DLREF_SEL_LSB 6
#define I2C_CPLL_OR_CAL_CAP 8
#define I2C_CPLL_OR_CAL_CAP_MSB 3
#define I2C_CPLL_OR_CAL_CAP_LSB 0
#define I2C_CPLL_OR_CAL_UDF 8
#define I2C_CPLL_OR_CAL_UDF_MSB 4
#define I2C_CPLL_OR_CAL_UDF_LSB 4
#define I2C_CPLL_OR_CAL_OVF 8
#define I2C_CPLL_OR_CAL_OVF_MSB 5
#define I2C_CPLL_OR_CAL_OVF_LSB 5
#define I2C_CPLL_OR_CAL_END 8
#define I2C_CPLL_OR_CAL_END_MSB 6
#define I2C_CPLL_OR_CAL_END_LSB 6
#define I2C_CPLL_OR_LOCK 8
#define I2C_CPLL_OR_LOCK_MSB 7
#define I2C_CPLL_OR_LOCK_LSB 7
#define I2C_CPLL_OC_VCO_DBIAS 9
#define I2C_CPLL_OC_VCO_DBIAS_MSB 1
#define I2C_CPLL_OC_VCO_DBIAS_LSB 0
#define I2C_CPLL_ENT_PLL 10
#define I2C_CPLL_ENT_PLL_MSB 3
#define I2C_CPLL_ENT_PLL_LSB 3
#define I2C_CPLL_DTEST 10
#define I2C_CPLL_DTEST_MSB 5
#define I2C_CPLL_DTEST_LSB 4

12
components/soc/esp32p4/include/soc/regi2c_defs.h
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@@ -1,27 +1,17 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x600AF818
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x5012401C
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_CONFIG2_REG 0x50124020

52
components/soc/esp32p4/include/soc/regi2c_dig_reg.h
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@@ -15,50 +15,58 @@
#define I2C_DIG_REG 0x6D
#define I2C_DIG_REG_HOSTID 0
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
#define I2C_DIG_REG_ENX_RTC_DREG 4
#define I2C_DIG_REG_ENX_RTC_DREG 4
#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_ENIF_RTC_DREG 5
#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7
#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7
#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP 5
#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP_MSB 7
#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP_LSB 7
#define I2C_DIG_REG_EXT_DIG_DREG 6
#define I2C_DIG_REG_EXT_DIG_DREG 6
#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
#define I2C_DIG_REG_ENX_DIG_DREG 6
#define I2C_DIG_REG_ENX_DIG_DREG 6
#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7
#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_ENIF_DIG_DREG 7
#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7
#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7
#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_OR_EN_CONT_CAL 9
#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
#define I2C_DIG_REG_OR_EN_CONT_CAL 9
#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
#define I2C_DIG_REG_XPD_RTC_REG 13
#define I2C_DIG_REG_FORCE_RTC_DREG 10
#define I2C_DIG_REG_FORCE_RTC_DREG_MSB 0
#define I2C_DIG_REG_FORCE_RTC_DREG_LSB 0
#define I2C_DIG_REG_FORCE_DIG_DREG 10
#define I2C_DIG_REG_FORCE_DIG_DREG_MSB 1
#define I2C_DIG_REG_FORCE_DIG_DREG_LSB 1
#define I2C_DIG_REG_XPD_RTC_REG 13
#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
#define I2C_DIG_REG_XPD_DIG_REG 13
#define I2C_DIG_REG_XPD_DIG_REG 13
#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
#define I2C_DIG_REG_SCK_DCAP 14
#define I2C_DIG_REG_SCK_DCAP 14
#define I2C_DIG_REG_SCK_DCAP_MSB 7
#define I2C_DIG_REG_SCK_DCAP_LSB 0

138
components/soc/esp32p4/include/soc/regi2c_syspll.h Normal file
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@@ -0,0 +1,138 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_syspll.h
* @brief Register definitions for SYS PLL (SPLL)
*
* This file lists register fields of SPLL, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h.
*/
#define I2C_SYSPLL 0x66
#define I2C_SYSPLL_HOSTID 0
#define I2C_SYSPLL_IR_CAL_DELAY 0
#define I2C_SYSPLL_IR_CAL_DELAY_MSB 3
#define I2C_SYSPLL_IR_CAL_DELAY_LSB 0
#define I2C_SYSPLL_IR_CAL_CK_DIV 0
#define I2C_SYSPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_SYSPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_SYSPLL_IR_CAL_EXT_CAP 1
#define I2C_SYSPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_SYSPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_SYSPLL_IR_CAL_ENX_CAP 1
#define I2C_SYSPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_SYSPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_SYSPLL_IR_CAL_RSTB 1
#define I2C_SYSPLL_IR_CAL_RSTB_MSB 5
#define I2C_SYSPLL_IR_CAL_RSTB_LSB 5
#define I2C_SYSPLL_IR_CAL_START 1
#define I2C_SYSPLL_IR_CAL_START_MSB 6
#define I2C_SYSPLL_IR_CAL_START_LSB 6
#define I2C_SYSPLL_IR_CAL_UNSTOP 1
#define I2C_SYSPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_SYSPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_SYSPLL_OC_REF_DIV 2
#define I2C_SYSPLL_OC_REF_DIV_MSB 3
#define I2C_SYSPLL_OC_REF_DIV_LSB 0
#define I2C_SYSPLL_OC_DCHGP 2
#define I2C_SYSPLL_OC_DCHGP_MSB 6
#define I2C_SYSPLL_OC_DCHGP_LSB 4
#define I2C_SYSPLL_OC_ENB_FCAL 2
#define I2C_SYSPLL_OC_ENB_FCAL_MSB 7
#define I2C_SYSPLL_OC_ENB_FCAL_LSB 7
#define I2C_SYSPLL_OC_DIV_7_0 3
#define I2C_SYSPLL_OC_DIV_7_0_MSB 7
#define I2C_SYSPLL_OC_DIV_7_0_LSB 0
#define I2C_SYSPLL_MODE_HF 4
#define I2C_SYSPLL_MODE_HF_MSB 1
#define I2C_SYSPLL_MODE_HF_LSB 1
#define I2C_SYSPLL_DIV_CPU 4
#define I2C_SYSPLL_DIV_CPU_MSB 5
#define I2C_SYSPLL_DIV_CPU_LSB 5
#define I2C_SYSPLL_OC_ENB_VCON 4
#define I2C_SYSPLL_OC_ENB_VCON_MSB 6
#define I2C_SYSPLL_OC_ENB_VCON_LSB 6
#define I2C_SYSPLL_OC_TSCHGP 4
#define I2C_SYSPLL_OC_TSCHGP_MSB 7
#define I2C_SYSPLL_OC_TSCHGP_LSB 7
#define I2C_SYSPLL_OC_DR1 5
#define I2C_SYSPLL_OC_DR1_MSB 2
#define I2C_SYSPLL_OC_DR1_LSB 0
#define I2C_SYSPLL_OC_DR3 5
#define I2C_SYSPLL_OC_DR3_MSB 6
#define I2C_SYSPLL_OC_DR3_LSB 4
#define I2C_SYSPLL_EN_USB 5
#define I2C_SYSPLL_EN_USB_MSB 7
#define I2C_SYSPLL_EN_USB_LSB 7
#define I2C_SYSPLL_OC_DCUR 6
#define I2C_SYSPLL_OC_DCUR_MSB 2
#define I2C_SYSPLL_OC_DCUR_LSB 0
#define I2C_SYSPLL_INC_CUR 6
#define I2C_SYSPLL_INC_CUR_MSB 3
#define I2C_SYSPLL_INC_CUR_LSB 3
#define I2C_SYSPLL_OC_DHREF_SEL 6
#define I2C_SYSPLL_OC_DHREF_SEL_MSB 5
#define I2C_SYSPLL_OC_DHREF_SEL_LSB 4
#define I2C_SYSPLL_OC_DLREF_SEL 6
#define I2C_SYSPLL_OC_DLREF_SEL_MSB 7
#define I2C_SYSPLL_OC_DLREF_SEL_LSB 6
#define I2C_SYSPLL_OR_CAL_CAP 8
#define I2C_SYSPLL_OR_CAL_CAP_MSB 3
#define I2C_SYSPLL_OR_CAL_CAP_LSB 0
#define I2C_SYSPLL_OR_CAL_UDF 8
#define I2C_SYSPLL_OR_CAL_UDF_MSB 4
#define I2C_SYSPLL_OR_CAL_UDF_LSB 4
#define I2C_SYSPLL_OR_CAL_OVF 8
#define I2C_SYSPLL_OR_CAL_OVF_MSB 5
#define I2C_SYSPLL_OR_CAL_OVF_LSB 5
#define I2C_SYSPLL_OR_CAL_END 8
#define I2C_SYSPLL_OR_CAL_END_MSB 6
#define I2C_SYSPLL_OR_CAL_END_LSB 6
#define I2C_SYSPLL_OR_LOCK 8
#define I2C_SYSPLL_OR_LOCK_MSB 7
#define I2C_SYSPLL_OR_LOCK_LSB 7
#define I2C_SYSPLL_OC_VCO_DBIAS 9
#define I2C_SYSPLL_OC_VCO_DBIAS_MSB 1
#define I2C_SYSPLL_OC_VCO_DBIAS_LSB 0
#define I2C_SYSPLL_ENT_PLL 10
#define I2C_SYSPLL_ENT_PLL_MSB 3
#define I2C_SYSPLL_ENT_PLL_LSB 3
#define I2C_SYSPLL_DTEST 10
#define I2C_SYSPLL_DTEST_MSB 5
#define I2C_SYSPLL_DTEST_LSB 4