forked from espressif/esp-idf
Merge branch 'refactor/remove_esp32h4_target_v5.1' into 'release/v5.1'
esp32h4: remove esp32h4 target (v5.1) See merge request espressif/esp-idf!23422
This commit is contained in:
Shu Chen
@@ -215,14 +215,6 @@ build_pytest_examples_esp32c2:
|
||||
IDF_TARGET: esp32c2
|
||||
TEST_DIR: examples
|
||||
|
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build_pytest_examples_esp32h4:
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extends:
|
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- .build_pytest_no_jtag_template
|
||||
- .rules:build:example_test-esp32h4
|
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variables:
|
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IDF_TARGET: esp32h4
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||||
TEST_DIR: examples
|
||||
|
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build_pytest_examples_jtag: # for all targets
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extends:
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- .build_pytest_jtag_template
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@@ -649,14 +641,6 @@ build_examples_cmake_esp32c3:
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IDF_TARGET: esp32c3
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TEST_DIR: examples
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build_examples_cmake_esp32h4:
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extends:
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- .build_cmake_template
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- .rules:build:example_test-esp32h4
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variables:
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IDF_TARGET: esp32h4
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TEST_DIR: examples
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build_examples_cmake_esp32c6:
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extends:
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- .build_cmake_template
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@@ -729,13 +713,6 @@ build_clang_test_apps_esp32c6:
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variables:
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IDF_TARGET: esp32c6
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build_clang_test_apps_esp32h4:
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extends:
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- .build_clang_test_apps_riscv
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- .rules:build:custom_test-esp32h4
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variables:
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IDF_TARGET: esp32h4
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.test_build_system_template:
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stage: host_test
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extends:
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@@ -3,7 +3,6 @@
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- esp32s2
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- esp32s3
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- esp32c3
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- esp32h4
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- esp32c2
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- esp32c6
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- esp32h2
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@@ -185,11 +185,6 @@ test_efuse_table_on_host_esp32c6:
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variables:
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IDF_TARGET: esp32c6
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test_efuse_table_on_host_esp32h4:
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extends: .test_efuse_table_on_host_template
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variables:
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IDF_TARGET: esp32h4
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test_espcoredump:
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extends: .host_test_template
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artifacts:
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@@ -447,9 +447,6 @@
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.if-label-component_ut_esp32h2: &if-label-component_ut_esp32h2
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if: '$BOT_LABEL_COMPONENT_UT_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h2(?:,[^,\n\r]+)*$/i'
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.if-label-component_ut_esp32h4: &if-label-component_ut_esp32h4
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if: '$BOT_LABEL_COMPONENT_UT_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h4(?:,[^,\n\r]+)*$/i'
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.if-label-component_ut_esp32s2: &if-label-component_ut_esp32s2
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if: '$BOT_LABEL_COMPONENT_UT_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32s2(?:,[^,\n\r]+)*$/i'
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@@ -474,9 +471,6 @@
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.if-label-custom_test_esp32h2: &if-label-custom_test_esp32h2
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if: '$BOT_LABEL_CUSTOM_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h2(?:,[^,\n\r]+)*$/i'
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.if-label-custom_test_esp32h4: &if-label-custom_test_esp32h4
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if: '$BOT_LABEL_CUSTOM_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h4(?:,[^,\n\r]+)*$/i'
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.if-label-custom_test_esp32s2: &if-label-custom_test_esp32s2
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if: '$BOT_LABEL_CUSTOM_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32s2(?:,[^,\n\r]+)*$/i'
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@@ -504,9 +498,6 @@
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.if-label-example_test_esp32h2: &if-label-example_test_esp32h2
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if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h2(?:,[^,\n\r]+)*$/i'
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.if-label-example_test_esp32h4: &if-label-example_test_esp32h4
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if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h4(?:,[^,\n\r]+)*$/i'
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.if-label-example_test_esp32s2: &if-label-example_test_esp32s2
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if: '$BOT_LABEL_EXAMPLE_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32s2(?:,[^,\n\r]+)*$/i'
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@@ -567,9 +558,6 @@
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.if-label-unit_test_esp32h2: &if-label-unit_test_esp32h2
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if: '$BOT_LABEL_UNIT_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h2(?:,[^,\n\r]+)*$/i'
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.if-label-unit_test_esp32h4: &if-label-unit_test_esp32h4
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if: '$BOT_LABEL_UNIT_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h4(?:,[^,\n\r]+)*$/i'
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.if-label-unit_test_esp32s2: &if-label-unit_test_esp32s2
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if: '$BOT_LABEL_UNIT_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32s2(?:,[^,\n\r]+)*$/i'
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@@ -607,7 +595,6 @@
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- <<: *if-label-component_ut_esp32c3
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- <<: *if-label-component_ut_esp32c6
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- <<: *if-label-component_ut_esp32h2
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- <<: *if-label-component_ut_esp32h4
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- <<: *if-label-component_ut_esp32s2
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- <<: *if-label-component_ut_esp32s3
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- <<: *if-label-lan8720
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@@ -618,7 +605,6 @@
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- <<: *if-label-unit_test_esp32c3
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- <<: *if-label-unit_test_esp32c6
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- <<: *if-label-unit_test_esp32h2
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- <<: *if-label-unit_test_esp32h4
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- <<: *if-label-unit_test_esp32s2
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- <<: *if-label-unit_test_esp32s3
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- <<: *if-dev-push
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@@ -879,7 +865,6 @@
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- <<: *if-label-custom_test_esp32c3
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- <<: *if-label-custom_test_esp32c6
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- <<: *if-label-custom_test_esp32h2
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- <<: *if-label-custom_test_esp32h4
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- <<: *if-label-custom_test_esp32s2
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- <<: *if-label-custom_test_esp32s3
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- <<: *if-label-target_test
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@@ -1020,30 +1005,6 @@
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- <<: *if-dev-push
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changes: *patterns-target_test-wifi
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.rules:build:custom_test-esp32h4:
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rules:
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- <<: *if-revert-branch
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when: never
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- <<: *if-protected
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- <<: *if-label-build
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- <<: *if-label-custom_test
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- <<: *if-label-custom_test_esp32h4
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- <<: *if-label-target_test
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- <<: *if-dev-push
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||||
changes: *patterns-build_components
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- <<: *if-dev-push
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changes: *patterns-build_system
|
||||
- <<: *if-dev-push
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||||
changes: *patterns-custom_test
|
||||
- <<: *if-dev-push
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||||
changes: *patterns-downloadable-tools
|
||||
- <<: *if-dev-push
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||||
changes: *patterns-target_test-adc
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||||
- <<: *if-dev-push
|
||||
changes: *patterns-target_test-i154
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||||
- <<: *if-dev-push
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||||
changes: *patterns-target_test-wifi
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||||
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||||
.rules:build:custom_test-esp32s2:
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rules:
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||||
- <<: *if-revert-branch
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@@ -1121,7 +1082,6 @@
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- <<: *if-label-example_test_esp32c3
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- <<: *if-label-example_test_esp32c6
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- <<: *if-label-example_test_esp32h2
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- <<: *if-label-example_test_esp32h4
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- <<: *if-label-example_test_esp32s2
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- <<: *if-label-example_test_esp32s3
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- <<: *if-label-iperf_stress_test
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@@ -1348,44 +1308,6 @@
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- <<: *if-dev-push
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changes: *patterns-target_test-wifi
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.rules:build:example_test-esp32h4:
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rules:
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- <<: *if-revert-branch
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when: never
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- <<: *if-protected
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||||
- <<: *if-label-build
|
||||
- <<: *if-label-example_test
|
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- <<: *if-label-example_test_esp32h4
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||||
- <<: *if-label-target_test
|
||||
- <<: *if-dev-push
|
||||
changes: *patterns-build-example_test
|
||||
- <<: *if-dev-push
|
||||
changes: *patterns-build_components
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- <<: *if-dev-push
|
||||
changes: *patterns-build_system
|
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- <<: *if-dev-push
|
||||
changes: *patterns-downloadable-tools
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||||
- <<: *if-dev-push
|
||||
changes: *patterns-example_test
|
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- <<: *if-dev-push
|
||||
changes: *patterns-example_test-bt
|
||||
- <<: *if-dev-push
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||||
changes: *patterns-example_test-ethernet
|
||||
- <<: *if-dev-push
|
||||
changes: *patterns-example_test-i154
|
||||
- <<: *if-dev-push
|
||||
changes: *patterns-example_test-sdio
|
||||
- <<: *if-dev-push
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changes: *patterns-example_test-usb
|
||||
- <<: *if-dev-push
|
||||
changes: *patterns-example_test-wifi
|
||||
- <<: *if-dev-push
|
||||
changes: *patterns-target_test-adc
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- <<: *if-dev-push
|
||||
changes: *patterns-target_test-i154
|
||||
- <<: *if-dev-push
|
||||
changes: *patterns-target_test-wifi
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||||
|
||||
.rules:build:example_test-esp32s2:
|
||||
rules:
|
||||
- <<: *if-revert-branch
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@@ -1509,7 +1431,6 @@
|
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- <<: *if-label-component_ut_esp32c3
|
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- <<: *if-label-component_ut_esp32c6
|
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- <<: *if-label-component_ut_esp32h2
|
||||
- <<: *if-label-component_ut_esp32h4
|
||||
- <<: *if-label-component_ut_esp32s2
|
||||
- <<: *if-label-component_ut_esp32s3
|
||||
- <<: *if-label-custom_test
|
||||
@@ -1518,7 +1439,6 @@
|
||||
- <<: *if-label-custom_test_esp32c3
|
||||
- <<: *if-label-custom_test_esp32c6
|
||||
- <<: *if-label-custom_test_esp32h2
|
||||
- <<: *if-label-custom_test_esp32h4
|
||||
- <<: *if-label-custom_test_esp32s2
|
||||
- <<: *if-label-custom_test_esp32s3
|
||||
- <<: *if-label-example_test
|
||||
@@ -1527,7 +1447,6 @@
|
||||
- <<: *if-label-example_test_esp32c3
|
||||
- <<: *if-label-example_test_esp32c6
|
||||
- <<: *if-label-example_test_esp32h2
|
||||
- <<: *if-label-example_test_esp32h4
|
||||
- <<: *if-label-example_test_esp32s2
|
||||
- <<: *if-label-example_test_esp32s3
|
||||
- <<: *if-label-integration_test
|
||||
@@ -1542,7 +1461,6 @@
|
||||
- <<: *if-label-unit_test_esp32c3
|
||||
- <<: *if-label-unit_test_esp32c6
|
||||
- <<: *if-label-unit_test_esp32h2
|
||||
- <<: *if-label-unit_test_esp32h4
|
||||
- <<: *if-label-unit_test_esp32s2
|
||||
- <<: *if-label-unit_test_esp32s3
|
||||
- <<: *if-label-weekend_test
|
||||
@@ -1609,7 +1527,6 @@
|
||||
- <<: *if-label-unit_test_esp32c3
|
||||
- <<: *if-label-unit_test_esp32c6
|
||||
- <<: *if-label-unit_test_esp32h2
|
||||
- <<: *if-label-unit_test_esp32h4
|
||||
- <<: *if-label-unit_test_esp32s2
|
||||
- <<: *if-label-unit_test_esp32s3
|
||||
- <<: *if-dev-push
|
||||
|
||||
24
Kconfig
24
Kconfig
@@ -66,28 +66,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
||||
select FREERTOS_UNICORE
|
||||
select IDF_TARGET_ARCH_RISCV
|
||||
|
||||
config IDF_TARGET_ESP32H4
|
||||
bool
|
||||
default "y" if IDF_TARGET="esp32h4"
|
||||
select FREERTOS_UNICORE
|
||||
select IDF_TARGET_ARCH_RISCV
|
||||
|
||||
choice IDF_TARGET_ESP32H4_BETA_VERSION
|
||||
prompt "ESP32-H4 beta version"
|
||||
depends on IDF_TARGET_ESP32H4
|
||||
default IDF_TARGET_ESP32H4_BETA_VERSION_2
|
||||
help
|
||||
Currently ESP32-H4 has several beta versions for internal use only.
|
||||
Select the one that matches your chip model.
|
||||
|
||||
config IDF_TARGET_ESP32H4_BETA_VERSION_1
|
||||
bool
|
||||
prompt "ESP32-H4 beta1"
|
||||
config IDF_TARGET_ESP32H4_BETA_VERSION_2
|
||||
bool
|
||||
prompt "ESP32-H4 beta2"
|
||||
endchoice
|
||||
|
||||
config IDF_TARGET_ESP32C2
|
||||
bool
|
||||
default "y" if IDF_TARGET="esp32c2"
|
||||
@@ -116,10 +94,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
||||
default 0x0002 if IDF_TARGET_ESP32S2
|
||||
default 0x0005 if IDF_TARGET_ESP32C3
|
||||
default 0x0009 if IDF_TARGET_ESP32S3
|
||||
default 0x000A if IDF_TARGET_ESP32H4_BETA_VERSION_1
|
||||
default 0x000C if IDF_TARGET_ESP32C2
|
||||
default 0x000D if IDF_TARGET_ESP32C6
|
||||
default 0x000E if IDF_TARGET_ESP32H4_BETA_VERSION_2 # ESP32-TODO: IDF-3475
|
||||
default 0x0010 if IDF_TARGET_ESP32H2
|
||||
default 0xFFFF
|
||||
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
#include "esp32c3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
|
||||
@@ -334,7 +334,7 @@ typedef enum {
|
||||
/**
|
||||
* @brief Revokes the old signature digest. To be called in the application after the rollback logic.
|
||||
*
|
||||
* Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-H4 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1).
|
||||
* Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C6, ESP32-H2 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1).
|
||||
* When key \#N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key \#N-1 & Key \#N.
|
||||
* After successfully booting the OTA app should call this function to revoke Key \#N-1.
|
||||
*
|
||||
|
||||
@@ -1,240 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/** Simplified memory map for the bootloader.
|
||||
* Make sure the bootloader can load into main memory without overwriting itself.
|
||||
*
|
||||
* ESP32-H4 ROM static data usage is as follows:
|
||||
* - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only
|
||||
* - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup
|
||||
* - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
|
||||
*
|
||||
* The 2nd stage bootloader can take space up to the end of ROM shared
|
||||
* buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700).
|
||||
*/
|
||||
|
||||
/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
|
||||
iram_dram_offset = 0x700000;
|
||||
|
||||
/* We consider 0x3fce9700 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
|
||||
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
|
||||
*/
|
||||
|
||||
/* These lengths can be adjusted, if necessary: */
|
||||
bootloader_usable_dram_end = 0x3fcdd120;
|
||||
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
|
||||
bootloader_dram_seg_len = 0x5000;
|
||||
bootloader_iram_loader_seg_len = 0x7000;
|
||||
bootloader_iram_seg_len = 0x2000;
|
||||
|
||||
/* Start of the lower region is determined by region size and the end of the higher region */
|
||||
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
|
||||
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
|
||||
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
|
||||
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
|
||||
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
|
||||
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(call_start_cpu0);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.iram_loader.text :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_loader_text_start = ABSOLUTE(.);
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
|
||||
*liblog.a:(.literal .text .literal.* .text.*)
|
||||
*libgcc.a:(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
|
||||
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
|
||||
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
|
||||
*libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
|
||||
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
|
||||
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
|
||||
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
|
||||
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
|
||||
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
|
||||
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
|
||||
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
|
||||
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
|
||||
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
|
||||
*libefuse.a:*.*(.literal .text .literal.* .text.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_loader_text_end = ABSOLUTE(.);
|
||||
} > iram_loader_seg
|
||||
|
||||
.iram.text :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
} > iram_seg
|
||||
|
||||
|
||||
/* Shared RAM */
|
||||
.dram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_dram_start = ABSOLUTE(.);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} > dram_seg
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.jcr)
|
||||
_data_end = ABSOLUTE(.);
|
||||
} > dram_seg
|
||||
|
||||
.dram0.rodata :
|
||||
{
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
*(.sdata2 .sdata2.* .srodata .srodata.*)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
*(.eh_frame)
|
||||
. = (. + 3) & ~ 3;
|
||||
/* C++ constructor and destructor tables, properly ordered: */
|
||||
__init_array_start = ABSOLUTE(.);
|
||||
KEEP (*crtbegin.*(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__init_array_end = ABSOLUTE(.);
|
||||
KEEP (*crtbegin.*(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_dram_end = ABSOLUTE(.);
|
||||
} > dram_seg
|
||||
|
||||
.iram.text :
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.iram .iram.*) /* catch stray IRAM_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
|
||||
/** CPU will try to prefetch up to 16 bytes of
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
* dummy bytes to ensure this
|
||||
*/
|
||||
. += 16;
|
||||
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} > iram_seg
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Appendix: Memory Usage of ROM bootloader
|
||||
*
|
||||
* 0x3fccb81c ------------------> _dram0_0_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fcdd120 ------------------> __stack_sentry
|
||||
* | |
|
||||
* | | 2. Startup pro cpu stack (freed when IDF app is running)
|
||||
* | |
|
||||
* 0x3fcdf120 ------------------> __stack (pro cpu)
|
||||
* | |
|
||||
* | |
|
||||
* | | 3. Shared memory only used in startup code or nonos/early boot*
|
||||
* | | (can be freed when IDF runs)
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fcdfa6c ------------------> _dram0_rtos_reserved_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 4. Shared memory used in startup code and when IDF runs
|
||||
* | |
|
||||
* | |
|
||||
* 0x3fcdfe40 ------------------> _dram0_rtos_reserved_end
|
||||
* | |
|
||||
* 0x3fcdfe4c ------------------> _data_start_interface
|
||||
* | |
|
||||
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
|
||||
* | |
|
||||
* 0x3fce0000 ------------------> _data_end_interface
|
||||
*/
|
||||
@@ -1,6 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* No definition for ESP32-H4 target */
|
||||
@@ -1,250 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include "string.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "esp32h4/rom/gpio.h"
|
||||
#include "esp32h4/rom/spi_flash.h"
|
||||
#include "esp32h4/rom/efuse.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "soc/spi_reg.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "flash_qio_mode.h"
|
||||
#include "bootloader_flash_config.h"
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader_flash_priv.h"
|
||||
#include "bootloader_init.h"
|
||||
#include "hal/mmu_hal.h"
|
||||
#include "hal/cache_hal.h"
|
||||
#include "hal/mmu_ll.h"
|
||||
|
||||
#define FLASH_IO_MATRIX_DUMMY_40M 0
|
||||
#define FLASH_IO_MATRIX_DUMMY_80M 0
|
||||
|
||||
void bootloader_flash_update_id()
|
||||
{
|
||||
esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
|
||||
chip->device_id = bootloader_read_flash_id();
|
||||
}
|
||||
|
||||
void IRAM_ATTR bootloader_flash_cs_timing_config()
|
||||
{
|
||||
SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
|
||||
SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
|
||||
}
|
||||
|
||||
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
|
||||
{
|
||||
uint32_t spi_clk_div = 0;
|
||||
switch (pfhdr->spi_speed) {
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_1:
|
||||
spi_clk_div = 1;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_2:
|
||||
spi_clk_div = 2;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_3:
|
||||
spi_clk_div = 3;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_4:
|
||||
spi_clk_div = 4;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
esp_rom_spiflash_config_clk(spi_clk_div, 0);
|
||||
}
|
||||
|
||||
void IRAM_ATTR bootloader_flash_set_dummy_out(void)
|
||||
{
|
||||
REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
|
||||
REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
|
||||
}
|
||||
|
||||
void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
|
||||
{
|
||||
bootloader_configure_spi_pins(1);
|
||||
bootloader_flash_set_dummy_out();
|
||||
}
|
||||
|
||||
static const char *TAG = "boot.esp32h4";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
clk_gpio_num = spiconfig & 0x3f;
|
||||
q_gpio_num = (spiconfig >> 6) & 0x3f;
|
||||
d_gpio_num = (spiconfig >> 12) & 0x3f;
|
||||
cs0_gpio_num = (spiconfig >> 18) & 0x3f;
|
||||
hd_gpio_num = (spiconfig >> 24) & 0x3f;
|
||||
wp_gpio_num = wp_pin;
|
||||
}
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
|
||||
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
|
||||
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
|
||||
}
|
||||
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
|
||||
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
|
||||
}
|
||||
}
|
||||
|
||||
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
|
||||
{
|
||||
uint32_t size;
|
||||
switch (bootloader_hdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
size = 1;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
size = 2;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
size = 4;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
size = 8;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
size = 16;
|
||||
break;
|
||||
default:
|
||||
size = 2;
|
||||
}
|
||||
cache_hal_disable(CACHE_TYPE_ALL);
|
||||
// Set flash chip size
|
||||
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
|
||||
cache_hal_enable(CACHE_TYPE_ALL);
|
||||
}
|
||||
|
||||
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
|
||||
{
|
||||
ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
|
||||
ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
|
||||
ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
|
||||
ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
|
||||
ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
|
||||
|
||||
const char *str;
|
||||
switch (bootloader_hdr->spi_speed) {
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_2:
|
||||
str = "24MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_3:
|
||||
str = "16MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_4:
|
||||
str = "12MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_1:
|
||||
str = "48MHz";
|
||||
break;
|
||||
default:
|
||||
str = "12MHz";
|
||||
break;
|
||||
}
|
||||
ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str);
|
||||
|
||||
/* SPI mode could have been set to QIO during boot already,
|
||||
so test the SPI registers not the flash header */
|
||||
uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
|
||||
if (spi_ctrl & SPI_MEM_FREAD_QIO) {
|
||||
str = "QIO";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
|
||||
str = "QOUT";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
|
||||
str = "DIO";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
|
||||
str = "DOUT";
|
||||
} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
|
||||
str = "FAST READ";
|
||||
} else {
|
||||
str = "SLOW READ";
|
||||
}
|
||||
ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
|
||||
|
||||
switch (bootloader_hdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
str = "1MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
str = "2MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
str = "4MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
str = "8MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
str = "16MB";
|
||||
break;
|
||||
default:
|
||||
str = "2MB";
|
||||
break;
|
||||
}
|
||||
ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
|
||||
}
|
||||
|
||||
static void IRAM_ATTR bootloader_init_flash_configure(void)
|
||||
{
|
||||
bootloader_flash_dummy_config(&bootloader_image_hdr);
|
||||
bootloader_flash_cs_timing_config();
|
||||
}
|
||||
|
||||
static void bootloader_spi_flash_resume(void)
|
||||
{
|
||||
bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
|
||||
esp_rom_spiflash_wait_idle(&g_rom_flashchip);
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init_spi_flash(void)
|
||||
{
|
||||
bootloader_init_flash_configure();
|
||||
#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
|
||||
ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
|
||||
return ESP_FAIL;
|
||||
}
|
||||
#endif
|
||||
|
||||
bootloader_spi_flash_resume();
|
||||
bootloader_flash_unlock();
|
||||
|
||||
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
|
||||
bootloader_enable_qio_mode();
|
||||
#endif
|
||||
|
||||
print_flash_info(&bootloader_image_hdr);
|
||||
update_flash_config(&bootloader_image_hdr);
|
||||
//ensure the flash is write-protected
|
||||
bootloader_enable_wp();
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -18,11 +18,6 @@ typedef enum {
|
||||
ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
|
||||
ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
|
||||
ESP_CHIP_ID_ESP32C2 = 0x000C, /*!< chip ID: ESP32-C2 */
|
||||
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
|
||||
ESP_CHIP_ID_ESP32H4 = 0x000E, /*!< chip ID: ESP32-H4 Beta2*/ // ESP32H4-TODO: IDF-3475
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
|
||||
ESP_CHIP_ID_ESP32H4 = 0x000A, /*!< chip ID: ESP32-H4 Beta1 */
|
||||
#endif
|
||||
ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
|
||||
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
|
||||
} __attribute__((packed)) esp_chip_id_t;
|
||||
|
||||
@@ -17,8 +17,6 @@
|
||||
#include "esp32c3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
|
||||
@@ -27,9 +27,6 @@ int bootloader_clock_get_rated_freq_mhz(void)
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
return 160;
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
return 96;
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
return 160;
|
||||
|
||||
|
||||
@@ -1,24 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/apb_saradc_reg.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "esp_private/regi2c_ctrl.h"
|
||||
|
||||
// ESP32H4-TODO: IDF-3381
|
||||
void bootloader_random_enable(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void bootloader_random_disable(void)
|
||||
{
|
||||
|
||||
}
|
||||
@@ -28,12 +28,6 @@
|
||||
#include "esp32c3/rom/uart.h"
|
||||
#include "esp32c3/rom/gpio.h"
|
||||
#include "esp32c3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/efuse.h"
|
||||
#include "esp32h4/rom/crc.h"
|
||||
#include "esp32h4/rom/uart.h"
|
||||
#include "esp32h4/rom/gpio.h"
|
||||
#include "esp32h4/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/efuse.h"
|
||||
#include "esp32c2/rom/crc.h"
|
||||
|
||||
@@ -1,155 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_image_format.h"
|
||||
#include "flash_qio_mode.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "esp_rom_uart.h"
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp_rom_spiflash.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/assist_debug_reg.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "esp32h4/rom/efuse.h"
|
||||
#include "esp32h4/rom/ets_sys.h"
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader_init.h"
|
||||
#include "bootloader_clock.h"
|
||||
#include "bootloader_flash_config.h"
|
||||
#include "bootloader_mem.h"
|
||||
#include "bootloader_console.h"
|
||||
#include "bootloader_flash_priv.h"
|
||||
#include "bootloader_soc.h"
|
||||
#include "esp_private/bootloader_flash_internal.h"
|
||||
#include "hal/mmu_hal.h"
|
||||
#include "hal/cache_hal.h"
|
||||
|
||||
static const char *TAG = "boot.esp32h4";
|
||||
|
||||
static void wdt_reset_cpu0_info_enable(void)
|
||||
{
|
||||
REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
|
||||
REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
|
||||
REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
|
||||
}
|
||||
|
||||
static void wdt_reset_info_dump(int cpu)
|
||||
{
|
||||
(void) cpu;
|
||||
// saved PC was already printed by the ROM bootloader.
|
||||
// nothing to do here.
|
||||
}
|
||||
|
||||
static void bootloader_check_wdt_reset(void)
|
||||
{
|
||||
int wdt_rst = 0;
|
||||
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
|
||||
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
|
||||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
|
||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
if (wdt_rst) {
|
||||
// if reset by WDT dump info from trace port
|
||||
wdt_reset_info_dump(0);
|
||||
}
|
||||
wdt_reset_cpu0_info_enable();
|
||||
}
|
||||
|
||||
static void bootloader_super_wdt_auto_feed(void)
|
||||
{
|
||||
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
|
||||
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
|
||||
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
|
||||
}
|
||||
|
||||
static inline void bootloader_hardware_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static inline void bootloader_ana_reset_config(void)
|
||||
{
|
||||
//Enable WDT, BOD, and GLITCH reset
|
||||
bootloader_ana_super_wdt_reset_config(true);
|
||||
bootloader_ana_bod_reset_config(true);
|
||||
bootloader_ana_clock_glitch_reset_config(true);
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init(void)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
|
||||
bootloader_hardware_init();
|
||||
bootloader_ana_reset_config();
|
||||
bootloader_super_wdt_auto_feed();
|
||||
|
||||
// In RAM_APP, memory will be initialized in `call_start_cpu0`
|
||||
#if !CONFIG_APP_BUILD_TYPE_RAM
|
||||
// protect memory region
|
||||
bootloader_init_mem();
|
||||
/* check that static RAM is after the stack */
|
||||
assert(&_bss_start <= &_bss_end);
|
||||
assert(&_data_start <= &_data_end);
|
||||
// clear bss section
|
||||
bootloader_clear_bss_section();
|
||||
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
||||
|
||||
// config clock
|
||||
bootloader_clock_configure();
|
||||
// initialize console, from now on, we can use esp_log
|
||||
bootloader_console_init();
|
||||
/* print 2nd bootloader banner */
|
||||
bootloader_print_banner();
|
||||
|
||||
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||
//init cache hal
|
||||
cache_hal_init(); //TODO IDF-4649
|
||||
//init mmu
|
||||
mmu_hal_init();
|
||||
// update flash ID
|
||||
bootloader_flash_update_id();
|
||||
// Check and run XMC startup flow
|
||||
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
|
||||
return ret;
|
||||
}
|
||||
#if !CONFIG_APP_BUILD_TYPE_RAM
|
||||
// read bootloader header
|
||||
if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
// read chip revision and check if it's compatible to bootloader
|
||||
if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
||||
// initialize spi flash
|
||||
if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||
|
||||
// check whether a WDT reset happend
|
||||
bootloader_check_wdt_reset();
|
||||
// config WDT
|
||||
bootloader_config_wdt();
|
||||
// enable RNG early entropy source
|
||||
bootloader_enable_random();
|
||||
return ret;
|
||||
}
|
||||
@@ -1,40 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "bootloader_sha.h"
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <sys/param.h>
|
||||
|
||||
#include "esp32h4/rom/sha.h"
|
||||
|
||||
static SHA_CTX ctx;
|
||||
|
||||
bootloader_sha256_handle_t bootloader_sha256_start()
|
||||
{
|
||||
// Enable SHA hardware
|
||||
ets_sha_enable();
|
||||
ets_sha_init(&ctx, SHA2_256);
|
||||
return &ctx; // Meaningless non-NULL value
|
||||
}
|
||||
|
||||
void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
assert(data_len % 4 == 0);
|
||||
ets_sha_update(&ctx, data, data_len, false);
|
||||
}
|
||||
|
||||
void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
|
||||
if (digest == NULL) {
|
||||
bzero(&ctx, sizeof(ctx));
|
||||
return;
|
||||
}
|
||||
ets_sha_finish(&ctx, digest);
|
||||
}
|
||||
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
|
||||
void bootloader_ana_super_wdt_reset_config(bool enable)
|
||||
{
|
||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
|
||||
|
||||
if (enable) {
|
||||
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
|
||||
} else {
|
||||
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
|
||||
}
|
||||
}
|
||||
|
||||
void bootloader_ana_bod_reset_config(bool enable)
|
||||
{
|
||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
|
||||
|
||||
if (enable) {
|
||||
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
||||
} else {
|
||||
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
||||
}
|
||||
}
|
||||
|
||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||
{
|
||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
|
||||
|
||||
if (enable) {
|
||||
REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
|
||||
} else {
|
||||
REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
|
||||
}
|
||||
}
|
||||
@@ -1,59 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <strings.h>
|
||||
#include "esp_flash_encrypt.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "flash_encrypt";
|
||||
|
||||
esp_err_t esp_flash_encryption_enable_secure_features(void)
|
||||
{
|
||||
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
|
||||
ESP_LOGI(TAG, "Disable UART bootloader encryption...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
|
||||
ESP_LOGI(TAG, "Disable UART bootloader cache...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||
ESP_LOGI(TAG, "Disable JTAG...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||
|
||||
#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
|
||||
// This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
|
||||
// otherwise the Flash Encryption key cannot be read protected
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE
|
||||
// Set write-protection for DIS_ICACHE to prevent bricking chip in case it will be set accidentally.
|
||||
// esp32h4 has DIS_ICACHE. Write-protection bit = 2.
|
||||
// List of eFuses with the same write protection bit:
|
||||
// DIS_ICACHE, DIS_USB_JTAG, POWERGLITCH_EN, DIS_FORCE_DOWNLOAD, SPI_DOWNLOAD_MSPI_DIS,
|
||||
// DIS_TWAI, JTAG_SEL_ENABLE, DIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_ICACHE);
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -1,70 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <strings.h>
|
||||
#include "esp_flash_encrypt.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "secure_boot";
|
||||
|
||||
esp_err_t esp_secure_boot_enable_secure_features(void)
|
||||
{
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||
|
||||
#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Enabling Security download mode...");
|
||||
esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not enable Security download mode...");
|
||||
return err;
|
||||
}
|
||||
#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Disable ROM Download mode...");
|
||||
esp_err_t err = esp_efuse_disable_rom_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not disable ROM Download mode...");
|
||||
return err;
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||
ESP_LOGI(TAG, "Disable hardware & software JTAG...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||
esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
|
||||
#endif
|
||||
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||
bool rd_dis_now = true;
|
||||
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
|
||||
/* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
|
||||
when Flash Encryption is being enabled */
|
||||
rd_dis_now = esp_flash_encryption_enabled();
|
||||
#endif
|
||||
if (rd_dis_now) {
|
||||
ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -29,8 +29,6 @@
|
||||
#include "esp32s3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#include "esp32c3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/rtc.h"
|
||||
#include "esp32c2/rom/secure_boot.h"
|
||||
|
||||
@@ -13,8 +13,6 @@
|
||||
#include "esp32c3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
|
||||
@@ -17,10 +17,6 @@ if(CONFIG_BT_ENABLED)
|
||||
list(APPEND srcs "controller/esp32c3/bt.c")
|
||||
list(APPEND include_dirs include/esp32c3/include)
|
||||
|
||||
elseif(CONFIG_IDF_TARGET_ESP32H4)
|
||||
list(APPEND srcs "controller/esp32h4/bt.c")
|
||||
list(APPEND include_dirs include/esp32h4/include)
|
||||
|
||||
elseif(CONFIG_IDF_TARGET_ESP32C2)
|
||||
list(APPEND srcs "controller/esp32c2/bt.c")
|
||||
list(APPEND include_dirs include/esp32c2/include)
|
||||
@@ -716,15 +712,6 @@ if(CONFIG_BT_ENABLED)
|
||||
target_link_directories(${COMPONENT_LIB} INTERFACE
|
||||
"${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
|
||||
target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
|
||||
elseif(CONFIG_IDF_TARGET_ESP32H4)
|
||||
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1)
|
||||
# TODO: rename esp32h2 to esp32h4 [BT-2875]
|
||||
add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta1/libble_app.a")
|
||||
elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2)
|
||||
# TODO: rename esp32h2 to esp32h4 [BT-2875]
|
||||
add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta2/libble_app.a")
|
||||
endif()
|
||||
target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
|
||||
elseif(CONFIG_IDF_TARGET_ESP32C2)
|
||||
add_prebuilt_library(libble_app "controller/lib_esp32c2/esp32c2-bt-lib/libble_app.a")
|
||||
target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
|
||||
|
||||
@@ -1,392 +0,0 @@
|
||||
|
||||
menu "HCI Config"
|
||||
|
||||
choice BT_LE_HCI_INTERFACE
|
||||
prompt "Select HCI interface"
|
||||
default BT_LE_HCI_INTERFACE_USE_RAM
|
||||
|
||||
config BT_LE_HCI_INTERFACE_USE_RAM
|
||||
bool "ram"
|
||||
help
|
||||
Use RAM as HCI interface
|
||||
config BT_LE_HCI_INTERFACE_USE_UART
|
||||
bool "uart"
|
||||
help
|
||||
Use UART as HCI interface
|
||||
endchoice
|
||||
|
||||
config BT_LE_HCI_UART_PORT
|
||||
int "HCI UART port"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default 1
|
||||
help
|
||||
Set the port number of HCI UART
|
||||
|
||||
config BT_LE_HCI_UART_FLOWCTRL
|
||||
bool "HCI uart Hardware Flow ctrl"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default n
|
||||
|
||||
config BT_LE_HCI_UART_TX_PIN
|
||||
int "HCI uart Tx gpio"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default 19
|
||||
|
||||
config BT_LE_HCI_UART_RX_PIN
|
||||
int "HCI uart Rx gpio"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default 10
|
||||
|
||||
config BT_LE_HCI_UART_RTS_PIN
|
||||
int "HCI uart RTS gpio"
|
||||
depends on BT_LE_HCI_UART_FLOWCTRL
|
||||
default 4
|
||||
|
||||
config BT_LE_HCI_UART_CTS_PIN
|
||||
int "HCI uart CTS gpio"
|
||||
depends on BT_LE_HCI_UART_FLOWCTRL
|
||||
default 5
|
||||
|
||||
config BT_LE_HCI_UART_BAUD
|
||||
int "HCI uart baudrate"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default 921600
|
||||
help
|
||||
HCI uart baud rate 115200 ~ 1000000
|
||||
|
||||
choice BT_LE_HCI_UART_PARITY
|
||||
prompt "select uart parity"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default BT_LE_HCI_UART_UART_PARITY_DISABLE
|
||||
|
||||
config BT_LE_HCI_UART_UART_PARITY_DISABLE
|
||||
bool "PARITY_DISABLE"
|
||||
help
|
||||
UART_PARITY_DISABLE
|
||||
config BT_LE_HCI_UART_UART_PARITY_EVEN
|
||||
bool "PARITY_EVEN"
|
||||
help
|
||||
UART_PARITY_EVEN
|
||||
config BT_LE_HCI_UART_UART_PARITY_ODD
|
||||
bool "PARITY_ODD"
|
||||
help
|
||||
UART_PARITY_ODD
|
||||
endchoice
|
||||
|
||||
config BT_LE_HCI_UART_TASK_STACK_SIZE
|
||||
int "HCI uart task stack size"
|
||||
depends on BT_LE_HCI_INTERFACE_USE_UART
|
||||
default 1000
|
||||
help
|
||||
Set the size of uart task stack
|
||||
endmenu
|
||||
|
||||
config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT
|
||||
bool
|
||||
default y
|
||||
help
|
||||
Enable NPL porting for controller.
|
||||
|
||||
|
||||
menuconfig BT_LE_50_FEATURE_SUPPORT
|
||||
bool "Enable BLE 5 feature"
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
default y
|
||||
help
|
||||
Enable BLE 5 feature
|
||||
|
||||
config BT_LE_LL_CFG_FEAT_LE_2M_PHY
|
||||
bool "Enable 2M Phy"
|
||||
depends on BT_LE_50_FEATURE_SUPPORT
|
||||
default y
|
||||
help
|
||||
Enable 2M-PHY
|
||||
|
||||
config BT_LE_LL_CFG_FEAT_LE_CODED_PHY
|
||||
bool "Enable coded Phy"
|
||||
depends on BT_LE_50_FEATURE_SUPPORT
|
||||
default y
|
||||
help
|
||||
Enable coded-PHY
|
||||
|
||||
config BT_LE_EXT_ADV
|
||||
bool "Enable extended advertising"
|
||||
depends on BT_LE_50_FEATURE_SUPPORT
|
||||
default y
|
||||
help
|
||||
Enable this option to do extended advertising. Extended advertising
|
||||
will be supported from BLE 5.0 onwards.
|
||||
|
||||
if BT_LE_EXT_ADV
|
||||
config BT_LE_MAX_EXT_ADV_INSTANCES
|
||||
int "Maximum number of extended advertising instances."
|
||||
range 0 4
|
||||
default 1
|
||||
depends on BT_LE_EXT_ADV
|
||||
help
|
||||
Change this option to set maximum number of extended advertising
|
||||
instances. Minimum there is always one instance of
|
||||
advertising. Enter how many more advertising instances you
|
||||
want.
|
||||
Each extended advertising instance will take about 0.5k DRAM.
|
||||
|
||||
config BT_LE_EXT_ADV_MAX_SIZE
|
||||
int "Maximum length of the advertising data."
|
||||
range 0 1650
|
||||
default 1650
|
||||
depends on BT_LE_EXT_ADV
|
||||
help
|
||||
Defines the length of the extended adv data. The value should not
|
||||
exceed 1650.
|
||||
|
||||
config BT_LE_ENABLE_PERIODIC_ADV
|
||||
bool "Enable periodic advertisement."
|
||||
default y
|
||||
depends on BT_LE_EXT_ADV
|
||||
help
|
||||
Enable this option to start periodic advertisement.
|
||||
|
||||
config BT_LE_PERIODIC_ADV_SYNC_TRANSFER
|
||||
bool "Enable Transer Sync Events"
|
||||
depends on BT_LE_ENABLE_PERIODIC_ADV
|
||||
default y
|
||||
help
|
||||
This enables controller transfer periodic sync events to host
|
||||
|
||||
endif
|
||||
|
||||
config BT_LE_MAX_PERIODIC_SYNCS
|
||||
int "Maximum number of periodic advertising syncs"
|
||||
depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED
|
||||
|
||||
range 0 8
|
||||
default 1 if BT_LE_ENABLE_PERIODIC_ADV
|
||||
default 0
|
||||
help
|
||||
Set this option to set the upper limit for number of periodic sync
|
||||
connections. This should be less than maximum connections allowed by
|
||||
controller.
|
||||
|
||||
config BT_LE_MAX_PERIODIC_ADVERTISER_LIST
|
||||
int "Maximum number of periodic advertiser list"
|
||||
depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED
|
||||
range 1 5
|
||||
default 5
|
||||
help
|
||||
Set this option to set the upper limit for number of periodic advertiser list.
|
||||
|
||||
menu "Memory Settings"
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
|
||||
config BT_LE_MSYS_1_BLOCK_COUNT
|
||||
int "MSYS_1 Block Count"
|
||||
default 12
|
||||
help
|
||||
MSYS is a system level mbuf registry. For prepare write & prepare
|
||||
responses MBUFs are allocated out of msys_1 pool. For NIMBLE_MESH
|
||||
enabled cases, this block count is increased by 8 than user defined
|
||||
count.
|
||||
|
||||
config BT_LE_MSYS_1_BLOCK_SIZE
|
||||
int "MSYS_1 Block Size"
|
||||
default 256
|
||||
help
|
||||
Dynamic memory size of block 1
|
||||
|
||||
config BT_LE_MSYS_2_BLOCK_COUNT
|
||||
int "MSYS_2 Block Count"
|
||||
default 24
|
||||
help
|
||||
Dynamic memory count
|
||||
|
||||
config BT_LE_MSYS_2_BLOCK_SIZE
|
||||
int "MSYS_2 Block Size"
|
||||
default 320
|
||||
help
|
||||
Dynamic memory size of block 2
|
||||
|
||||
config BT_LE_ACL_BUF_COUNT
|
||||
int "ACL Buffer count"
|
||||
default 10
|
||||
help
|
||||
The number of ACL data buffers.
|
||||
|
||||
config BT_LE_ACL_BUF_SIZE
|
||||
int "ACL Buffer size"
|
||||
default 517
|
||||
help
|
||||
This is the maximum size of the data portion of HCI ACL data packets.
|
||||
It does not include the HCI data header (of 4 bytes)
|
||||
|
||||
config BT_LE_HCI_EVT_BUF_SIZE
|
||||
int "HCI Event Buffer size"
|
||||
default 257 if BT_LE_EXT_ADV
|
||||
default 70
|
||||
help
|
||||
This is the size of each HCI event buffer in bytes. In case of
|
||||
extended advertising, packets can be fragmented. 257 bytes is the
|
||||
maximum size of a packet.
|
||||
|
||||
config BT_LE_HCI_EVT_HI_BUF_COUNT
|
||||
int "High Priority HCI Event Buffer count"
|
||||
default 30
|
||||
help
|
||||
This is the high priority HCI events' buffer size. High-priority
|
||||
event buffers are for everything except advertising reports. If there
|
||||
are no free high-priority event buffers then host will try to allocate a
|
||||
low-priority buffer instead
|
||||
|
||||
config BT_LE_HCI_EVT_LO_BUF_COUNT
|
||||
int "Low Priority HCI Event Buffer count"
|
||||
default 8
|
||||
help
|
||||
This is the low priority HCI events' buffer size. Low-priority event
|
||||
buffers are only used for advertising reports. If there are no free
|
||||
low-priority event buffers, then an incoming advertising report will
|
||||
get dropped
|
||||
endmenu
|
||||
|
||||
config BT_LE_CONTROLLER_TASK_STACK_SIZE
|
||||
int "Controller task stack size"
|
||||
default 5120 if BLE_MESH
|
||||
default 4096
|
||||
help
|
||||
This configures stack size of NimBLE controller task
|
||||
|
||||
config BT_LE_LL_RESOLV_LIST_SIZE
|
||||
int "BLE LL Resolving list size"
|
||||
range 1 5
|
||||
default 4
|
||||
help
|
||||
Configure the size of resolving list used in link layer.
|
||||
|
||||
menuconfig BT_LE_SECURITY_ENABLE
|
||||
bool "Enable BLE SM feature"
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
default y
|
||||
help
|
||||
Enable BLE sm feature
|
||||
|
||||
config BT_LE_SM_LEGACY
|
||||
bool "Security manager legacy pairing"
|
||||
depends on BT_LE_SECURITY_ENABLE
|
||||
default y
|
||||
help
|
||||
Enable security manager legacy pairing
|
||||
|
||||
config BT_LE_SM_SC
|
||||
bool "Security manager secure connections (4.2)"
|
||||
depends on BT_LE_SECURITY_ENABLE
|
||||
default y
|
||||
help
|
||||
Enable security manager secure connections
|
||||
|
||||
config BT_LE_SM_SC_DEBUG_KEYS
|
||||
bool "Use predefined public-private key pair"
|
||||
default n
|
||||
depends on BT_LE_SECURITY_ENABLE && BT_LE_SM_SC
|
||||
help
|
||||
If this option is enabled, SM uses predefined DH key pair as described
|
||||
in Core Specification, Vol. 3, Part H, 2.3.5.6.1. This allows to
|
||||
decrypt air traffic easily and thus should only be used for debugging.
|
||||
|
||||
config BT_LE_LL_CFG_FEAT_LE_ENCRYPTION
|
||||
bool "Enable LE encryption"
|
||||
depends on BT_LE_SECURITY_ENABLE
|
||||
default y
|
||||
help
|
||||
Enable encryption connection
|
||||
|
||||
config BT_LE_CRYPTO_STACK_MBEDTLS
|
||||
bool "Override TinyCrypt with mbedTLS for crypto computations"
|
||||
default y
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
select MBEDTLS_ECP_RESTARTABLE
|
||||
select MBEDTLS_CMAC_C
|
||||
help
|
||||
Enable this option to choose mbedTLS instead of TinyCrypt for crypto
|
||||
computations.
|
||||
|
||||
config BT_LE_WHITELIST_SIZE
|
||||
int "BLE white list size"
|
||||
range 1 15
|
||||
default 12
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
|
||||
help
|
||||
BLE list size
|
||||
|
||||
config BT_LE_LL_DUP_SCAN_LIST_COUNT
|
||||
int "BLE duplicate scan list count"
|
||||
range 1 100
|
||||
default 20
|
||||
help
|
||||
config the max count of duplicate scan list
|
||||
|
||||
config BT_LE_LL_SCA
|
||||
int "BLE Sleep clock accuracy"
|
||||
range 0 500
|
||||
default 60
|
||||
help
|
||||
Sleep clock accuracy of our device (in ppm)
|
||||
|
||||
config BT_LE_MAX_CONNECTIONS
|
||||
int "Maximum number of concurrent connections"
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
range 1 9
|
||||
default 3
|
||||
help
|
||||
Defines maximum number of concurrent BLE connections. For ESP32, user
|
||||
is expected to configure BTDM_CTRL_BLE_MAX_CONN from controller menu
|
||||
along with this option. Similarly for ESP32-C3 or ESP32-S3, user is expected to
|
||||
configure BT_CTRL_BLE_MAX_ACT from controller menu.
|
||||
Each connection will take about 1k DRAM.
|
||||
|
||||
choice BT_LE_COEX_PHY_CODED_TX_RX_TLIM
|
||||
prompt "Coexistence: limit on MAX Tx/Rx time for coded-PHY connection"
|
||||
default BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
help
|
||||
When using PHY-Coded in BLE connection, limitation on max tx/rx time can be applied to
|
||||
better avoid dramatic performance deterioration of Wi-Fi.
|
||||
|
||||
config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN
|
||||
bool "Force Enable"
|
||||
help
|
||||
Always enable the limitation on max tx/rx time for Coded-PHY connection
|
||||
|
||||
config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS
|
||||
bool "Force Disable"
|
||||
help
|
||||
Disable the limitation on max tx/rx time for Coded-PHY connection
|
||||
endchoice
|
||||
|
||||
config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF
|
||||
int
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
default 1 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN
|
||||
default 0 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS
|
||||
|
||||
config BT_LE_SLEEP_ENABLE
|
||||
bool "Enable BLE sleep"
|
||||
default n
|
||||
help
|
||||
Enable BLE sleep
|
||||
|
||||
choice BT_LE_WAKEUP_SOURCE
|
||||
prompt "BLE light sleep wakeup source"
|
||||
depends on BT_LE_SLEEP_ENABLE
|
||||
default BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
|
||||
config BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
|
||||
bool "Use ESP timer to wakeup CPU"
|
||||
help
|
||||
Use esp timer to wakeup CPU
|
||||
endchoice
|
||||
|
||||
config BT_LE_USE_ESP_TIMER
|
||||
bool "Use Esp Timer for callout"
|
||||
depends on !BT_NIMBLE_ENABLED
|
||||
default y
|
||||
help
|
||||
Set this option to use Esp Timer which has higher priority timer
|
||||
instead of FreeRTOS timer
|
||||
File diff suppressed because it is too large
Load Diff
@@ -61,7 +61,7 @@ typedef enum {
|
||||
ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */
|
||||
ADC1_CHANNEL_MAX,
|
||||
} adc1_channel_t;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
|
||||
typedef enum {
|
||||
ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
|
||||
ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */
|
||||
@@ -97,7 +97,7 @@ typedef enum {
|
||||
ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */
|
||||
ADC2_CHANNEL_MAX,
|
||||
} adc2_channel_t;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
|
||||
// ESP32C6 has no ADC2
|
||||
typedef enum {
|
||||
ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */
|
||||
|
||||
@@ -32,7 +32,7 @@
|
||||
#define RW_TEST_LENGTH 129 /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
|
||||
#define DELAY_TIME_BETWEEN_ITEMS_MS 1234 /*!< delay time between different test items */
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H4
|
||||
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
|
||||
#define I2C_SLAVE_SCL_IO 5 /*!<gpio number for i2c slave clock */
|
||||
#define I2C_SLAVE_SDA_IO 6 /*!<gpio number for i2c slave data */
|
||||
#else
|
||||
@@ -44,7 +44,7 @@
|
||||
#define I2C_SLAVE_TX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave tx buffer size */
|
||||
#define I2C_SLAVE_RX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave rx buffer size */
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4
|
||||
#if CONFIG_IDF_TARGET_ESP32C3
|
||||
#define I2C_MASTER_SCL_IO 5 /*!<gpio number for i2c master clock */
|
||||
#define I2C_MASTER_SDA_IO 6 /*!<gpio number for i2c master data */
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
|
||||
@@ -467,7 +467,7 @@ TEST_CASE("LEDC multi fade test", "[ledc]")
|
||||
}
|
||||
#endif // SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
|
||||
|
||||
#if SOC_PCNT_SUPPORTED // Note. C3, C2, H4 do not have PCNT peripheral, the following test cases cannot be tested
|
||||
#if SOC_PCNT_SUPPORTED // Note. C3, C2 do not have PCNT peripheral, the following test cases cannot be tested
|
||||
|
||||
#include "driver/pulse_cnt.h"
|
||||
|
||||
|
||||
@@ -33,7 +33,6 @@
|
||||
|
||||
#endif
|
||||
|
||||
// H4 and C2 will not support external flash.
|
||||
#define TEST_FLASH_FREQ_MHZ 5
|
||||
|
||||
typedef struct {
|
||||
|
||||
@@ -273,7 +273,7 @@ TEST_CASE("test slave send unaligned", "[spi]")
|
||||
/********************************************************************************
|
||||
* Test By Master & Slave (2 boards)
|
||||
*
|
||||
* Master (C3, C2, H4) && Slave (C3, C2, H4):
|
||||
* Master (C3, C2, H2) && Slave (C3, C2, H2):
|
||||
* PIN | Master | Slave |
|
||||
* ----| --------- | --------- |
|
||||
* CS | 10 | 10 |
|
||||
|
||||
@@ -583,7 +583,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
|
||||
/********************************************************************************
|
||||
* Test By Master & Slave (2 boards)
|
||||
*
|
||||
* Master (C3, C2, H4) && Slave (C3, C2, H4):
|
||||
* Master (C3, C2, H2) && Slave (C3, C2, H2):
|
||||
* PIN | Master | Slave |
|
||||
* ----| --------- | --------- |
|
||||
* CS | 10 | 10 |
|
||||
|
||||
@@ -498,7 +498,7 @@ def main():
|
||||
|
||||
parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
|
||||
parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3',
|
||||
'esp32h4', 'esp32c2', 'esp32c6', 'esp32h2'], default='esp32')
|
||||
'esp32c2', 'esp32c6', 'esp32h2'], default='esp32')
|
||||
parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
|
||||
parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false')
|
||||
parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true')
|
||||
|
||||
@@ -1,54 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "stdlib.h"
|
||||
#include "esp_types.h"
|
||||
#include "esp32h4/rom/efuse.h"
|
||||
#include "assert.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "sys/param.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "efuse";
|
||||
|
||||
// Contains functions that provide access to efuse fields which are often used in IDF.
|
||||
|
||||
// Returns chip package from efuse
|
||||
uint32_t esp_efuse_get_pkg_ver(void)
|
||||
{
|
||||
uint32_t pkg_ver = 0;
|
||||
esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
|
||||
return pkg_ver;
|
||||
}
|
||||
|
||||
|
||||
esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
|
||||
{
|
||||
int cur_log_scheme = 0;
|
||||
esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2);
|
||||
if (!cur_log_scheme) { // not burned yet
|
||||
return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2);
|
||||
} else {
|
||||
return ESP_ERR_INVALID_STATE;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_disable_rom_download_mode(void)
|
||||
{
|
||||
return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
|
||||
{
|
||||
if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
|
||||
return ESP_ERR_INVALID_STATE;
|
||||
}
|
||||
return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
|
||||
}
|
||||
@@ -1,94 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp_bit_defs.h>
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
|
||||
int esp_efuse_rtc_calib_get_ver(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3);
|
||||
return result;
|
||||
}
|
||||
|
||||
uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten)
|
||||
{
|
||||
assert(version == 1);
|
||||
const esp_efuse_desc_t** init_code_efuse;
|
||||
assert(atten < 4);
|
||||
if (atten == 0) {
|
||||
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0;
|
||||
} else if (atten == 1) {
|
||||
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1;
|
||||
} else if (atten == 2) {
|
||||
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2;
|
||||
} else {
|
||||
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3;
|
||||
}
|
||||
|
||||
int init_code_size = esp_efuse_get_field_size(init_code_efuse);
|
||||
assert(init_code_size == 10);
|
||||
|
||||
uint32_t init_code = 0;
|
||||
ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
|
||||
return init_code + 1000; // version 1 logic
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
|
||||
{
|
||||
const esp_efuse_desc_t** cal_vol_efuse;
|
||||
uint32_t calib_vol_expected_mv;
|
||||
if (version != 1) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
if (atten >= 4) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
if (atten == 0) {
|
||||
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0;
|
||||
calib_vol_expected_mv = 400;
|
||||
} else if (atten == 1) {
|
||||
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1;
|
||||
calib_vol_expected_mv = 550;
|
||||
} else if (atten == 2) {
|
||||
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2;
|
||||
calib_vol_expected_mv = 750;
|
||||
} else {
|
||||
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3;
|
||||
calib_vol_expected_mv = 1370;
|
||||
}
|
||||
|
||||
assert(cal_vol_efuse[0]->bit_count == 10);
|
||||
|
||||
uint32_t cal_vol = 0;
|
||||
ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count));
|
||||
|
||||
*out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol);
|
||||
*out_vol_mv = calib_vol_expected_mv;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
|
||||
{
|
||||
uint32_t version = esp_efuse_rtc_calib_get_ver();
|
||||
if (version != 1) {
|
||||
*tsens_cal = 0.0;
|
||||
return ESP_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
const esp_efuse_desc_t** cal_temp_efuse;
|
||||
cal_temp_efuse = ESP_EFUSE_TEMP_CALIB;
|
||||
int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
|
||||
assert(cal_temp_size == 9);
|
||||
|
||||
uint32_t cal_temp = 0;
|
||||
esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
|
||||
assert(err == ESP_OK);
|
||||
(void)err;
|
||||
// BIT(8) stands for sign: 1: negtive, 0: positive
|
||||
*tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
|
||||
return ESP_OK;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,156 +0,0 @@
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
|
||||
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
|
||||
# | ... | | | #
|
||||
# | EFUSE_BLK10)| | | #
|
||||
##########################################################################
|
||||
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
|
||||
# !!!!!!!!!!! #
|
||||
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# ESP32H4-TODO: IDF-3390
|
||||
# EFUSE_RD_REPEAT_DATA BLOCK #
|
||||
##############################
|
||||
# EFUSE_RD_WR_DIS_REG #
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
|
||||
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
|
||||
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
|
||||
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
|
||||
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
|
||||
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
|
||||
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
|
||||
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
|
||||
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
|
||||
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
|
||||
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
|
||||
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
|
||||
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
|
||||
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA0_REG #
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
|
||||
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
|
||||
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
|
||||
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
|
||||
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
|
||||
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
|
||||
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
|
||||
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode
|
||||
DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently.
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes.
|
||||
USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
|
||||
USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
|
||||
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio
|
||||
BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio
|
||||
POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function
|
||||
POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA1_REG #
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA2_REG #
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA3_REG #
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Disable download through USB-Serial-JTAG
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
|
||||
BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, Fast verify on wake option in ROM for Secure Boot
|
||||
|
||||
# EFUSE_RD_REPEAT_DATA4_REG #
|
||||
|
||||
|
||||
# MAC_SPI_SYS BLOCK#
|
||||
#######################
|
||||
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
|
||||
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
|
||||
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
|
||||
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
|
||||
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
|
||||
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
|
||||
MAC_EXT, EFUSE_BLK1, 123, 8, Extend MAC addr [0]
|
||||
, EFUSE_BLK1, 131, 8, Extend MAC addr [1]
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
|
||||
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version
|
||||
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H4
|
||||
BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version
|
||||
|
||||
# SYS_DATA_PART1 BLOCK# - System configuration
|
||||
#######################
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
|
||||
BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2
|
||||
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3
|
||||
|
||||
################
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
|
||||
|
||||
################
|
||||
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
|
||||
|
Can't render this file because it contains an unexpected character in line 7 and column 87.
|
@@ -1,201 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "assert.h"
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
static const char *TAG = "efuse";
|
||||
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
/*Range addresses to read blocks*/
|
||||
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
|
||||
{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
|
||||
{EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
|
||||
{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
|
||||
{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
|
||||
{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
|
||||
{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
|
||||
{EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
|
||||
{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
|
||||
{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
|
||||
{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
|
||||
{EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
|
||||
};
|
||||
|
||||
static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
|
||||
|
||||
/*Range addresses to write blocks (it is not real regs, it is buffer) */
|
||||
const esp_efuse_range_addr_t range_write_addr_blocks[] = {
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
|
||||
};
|
||||
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL
|
||||
// Update Efuse timing configuration
|
||||
static esp_err_t esp_efuse_set_timing(void)
|
||||
{
|
||||
// efuse clock is fixed.
|
||||
// An argument (0) is for compatibility and will be ignored.
|
||||
efuse_hal_set_timing(0);
|
||||
return ESP_OK;
|
||||
}
|
||||
#endif // ifndef CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
// Efuse read operation: copies data from physical efuses to efuse read registers.
|
||||
void esp_efuse_utility_clear_program_registers(void)
|
||||
{
|
||||
efuse_hal_read();
|
||||
efuse_hal_clear_program_registers();
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_utility_check_errors(void)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
// Burn values written to the efuse write registers
|
||||
esp_err_t esp_efuse_utility_burn_chip(void)
|
||||
{
|
||||
esp_err_t error = ESP_OK;
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
|
||||
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
int subblock = 0;
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
esp_efuse_utility_write_efuses_to_flash();
|
||||
#endif
|
||||
#else // CONFIG_EFUSE_VIRTUAL
|
||||
if (esp_efuse_set_timing() != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Efuse fields are not burnt");
|
||||
} else {
|
||||
// Permanently update values written to the efuse write registers
|
||||
// It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
|
||||
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
bool need_burn_block = false;
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block) != 0) {
|
||||
need_burn_block = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!need_burn_block) {
|
||||
continue;
|
||||
}
|
||||
if (error) {
|
||||
// It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
|
||||
// in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
|
||||
ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
|
||||
continue;
|
||||
}
|
||||
efuse_hal_clear_program_registers();
|
||||
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
uint8_t block_rs[12];
|
||||
efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
|
||||
hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
|
||||
}
|
||||
unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
|
||||
unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
|
||||
memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
|
||||
|
||||
uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
|
||||
hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
|
||||
int repeat_burn_op = 1;
|
||||
bool correct_written_data;
|
||||
bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
|
||||
if (coding_error_before) {
|
||||
ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
|
||||
}
|
||||
bool coding_error_occurred;
|
||||
|
||||
do {
|
||||
ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
|
||||
efuse_hal_program(num_block); // BURN a block
|
||||
|
||||
bool coding_error_after;
|
||||
for (unsigned i = 0; i < 5; i++) {
|
||||
efuse_hal_read();
|
||||
coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
|
||||
if (coding_error_after == true) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
|
||||
if (coding_error_occurred) {
|
||||
ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
|
||||
}
|
||||
|
||||
correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
|
||||
if (!correct_written_data || coding_error_occurred) {
|
||||
ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
|
||||
hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
|
||||
}
|
||||
|
||||
} while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
|
||||
|
||||
if (coding_error_occurred) {
|
||||
ESP_LOGW(TAG, "Coding error was not fixed");
|
||||
if (num_block == 0) {
|
||||
ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
|
||||
error = ESP_FAIL;
|
||||
}
|
||||
}
|
||||
if (!correct_written_data) {
|
||||
ESP_LOGE(TAG, "Written data are incorrect");
|
||||
error = ESP_FAIL;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
esp_efuse_utility_reset();
|
||||
return error;
|
||||
}
|
||||
|
||||
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
|
||||
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
|
||||
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
|
||||
// They will be filled during the burn operation.
|
||||
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
|
||||
{
|
||||
// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
|
||||
for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block)) {
|
||||
int num_reg = 0;
|
||||
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
|
||||
if (esp_efuse_utility_read_reg(num_block, num_reg)) {
|
||||
ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
|
||||
return ESP_ERR_CODING;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of eFuse blocks ESP32H4
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
/**
|
||||
* @brief Type of coding scheme
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_CODING_SCHEME_NONE = 0, /**< None */
|
||||
EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */
|
||||
} esp_efuse_coding_scheme_t;
|
||||
|
||||
/**
|
||||
* @brief Type of key purpose
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
|
||||
ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */
|
||||
} esp_efuse_purpose_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,55 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp_types.h>
|
||||
#include <esp_err.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get the RTC calibration efuse version
|
||||
*
|
||||
* @return Version of the stored efuse
|
||||
*/
|
||||
int esp_efuse_rtc_calib_get_ver(void);
|
||||
|
||||
/**
|
||||
* @brief Get the init code in the efuse, for the corresponding attenuation.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param atten Attenuation of the init code
|
||||
* @return The init code stored in efuse
|
||||
*/
|
||||
uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten);
|
||||
|
||||
/**
|
||||
* @brief Get the calibration digits stored in the efuse, and the corresponding voltage.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param atten Attenuation to use
|
||||
* @param out_digi Output buffer of the digits
|
||||
* @param out_vol_mv Output of the voltage, in mV
|
||||
* @return
|
||||
* - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid
|
||||
* - ESP_OK: if success
|
||||
*/
|
||||
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv);
|
||||
|
||||
/**
|
||||
* @brief Get the temperature sensor calibration number delta_T stored in the efuse.
|
||||
*
|
||||
* @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse.
|
||||
*
|
||||
* @return ESP_OK if get the calibration value successfully.
|
||||
* ESP_ERR_INVALID_ARG if can't get the calibration value.
|
||||
*/
|
||||
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,136 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 4561606695cfe94477d259619fd723ef
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,21 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
|
||||
|
||||
#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
|
||||
|
||||
#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,4 +0,0 @@
|
||||
set(EFUSE_SOC_SRCS "esp_efuse_table.c"
|
||||
"esp_efuse_fields.c"
|
||||
"esp_efuse_rtc_calib.c"
|
||||
"esp_efuse_utility.c")
|
||||
@@ -1,15 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file adc_cali_schemes.h
|
||||
*
|
||||
* @brief Supported calibration schemes
|
||||
*/
|
||||
|
||||
//Now no scheme supported
|
||||
@@ -8,17 +8,8 @@ if(CONFIG_ESP_COEX_SW_COEXIST_ENABLE OR CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE)
|
||||
set(link_binary_libs 1)
|
||||
set(ldfragments "linker.lf")
|
||||
endif()
|
||||
|
||||
# TODO: need to remove these logic when unsupport esp32h4.
|
||||
if(IDF_TARGET STREQUAL "esp32h4")
|
||||
set(srcs
|
||||
"src/coexist.c"
|
||||
"esp32h2/esp_coex_adapter.c")
|
||||
else()
|
||||
set(srcs
|
||||
"src/coexist.c"
|
||||
"${idf_target}/esp_coex_adapter.c")
|
||||
endif()
|
||||
set(srcs "src/coexist.c"
|
||||
"${idf_target}/esp_coex_adapter.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_ESP_WIFI_ENABLED)
|
||||
@@ -38,14 +29,8 @@ if(CONFIG_ESP_COEX_SW_COEXIST_ENABLE OR CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE)
|
||||
|
||||
if(link_binary_libs)
|
||||
set(blob coexist)
|
||||
# TODO: need to remove these logic when unsupport esp32h4.
|
||||
if(IDF_TARGET STREQUAL "esp32h4")
|
||||
add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h2/lib${blob}.a"
|
||||
add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/lib${blob}.a"
|
||||
REQUIRES ${COMPONENT_NAME})
|
||||
else()
|
||||
add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/lib${blob}.a"
|
||||
REQUIRES ${COMPONENT_NAME})
|
||||
endif()
|
||||
target_link_libraries(${COMPONENT_LIB} PUBLIC ${blob})
|
||||
endif()
|
||||
|
||||
|
||||
@@ -29,9 +29,6 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#include "esp32c3/rom/rtc.h"
|
||||
#include "esp32c3/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#include "esp32h4/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/rtc.h"
|
||||
#include "esp32c2/rtc.h"
|
||||
|
||||
@@ -44,10 +44,6 @@
|
||||
#include "esp32c6/rom/digital_signature.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/digital_signature.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/digital_signature.h"
|
||||
#endif
|
||||
|
||||
@@ -24,7 +24,6 @@ typedef enum {
|
||||
CHIP_ESP32S2 = 2, //!< ESP32-S2
|
||||
CHIP_ESP32S3 = 9, //!< ESP32-S3
|
||||
CHIP_ESP32C3 = 5, //!< ESP32-C3
|
||||
CHIP_ESP32H4 = 6, //!< ESP32-H4
|
||||
CHIP_ESP32C2 = 12, //!< ESP32-C2
|
||||
CHIP_ESP32C6 = 13, //!< ESP32-C6
|
||||
CHIP_ESP32H2 = 16, //!< ESP32-H2
|
||||
|
||||
@@ -40,8 +40,6 @@ typedef enum {
|
||||
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H4_UNIVERSAL_MAC_ADDRESSES
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
|
||||
@@ -1,68 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for HMAC cryptography peripheral
|
||||
*
|
||||
* Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral
|
||||
*/
|
||||
void esp_crypto_hmac_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for HMAC cryptography peripheral
|
||||
*
|
||||
* Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral
|
||||
*/
|
||||
void esp_crypto_hmac_lock_release(void);
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for DS cryptography peripheral
|
||||
*
|
||||
* Internally also locks the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals
|
||||
*/
|
||||
void esp_crypto_ds_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for DS cryptography peripheral
|
||||
*
|
||||
* Internally also releases the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals
|
||||
*/
|
||||
void esp_crypto_ds_lock_release(void);
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for the SHA and AES cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_sha_aes_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for the SHA and AES cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_sha_aes_lock_release(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Acquire lock for the mpi cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_mpi_lock_acquire(void);
|
||||
|
||||
/**
|
||||
* @brief Release lock for the mpi/rsa cryptography peripheral.
|
||||
*
|
||||
*/
|
||||
void esp_crypto_mpi_lock_release(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,32 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @file esp32h4/rtc.h
|
||||
*
|
||||
* This file contains declarations of rtc related functions.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get current value of RTC counter in microseconds
|
||||
*
|
||||
* Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
|
||||
*
|
||||
* @return current value of RTC counter in microseconds
|
||||
*/
|
||||
uint64_t esp_rtc_get_time_us(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,117 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
//////////////////////////////////////////////////////////
|
||||
// ESP32-H4 PMS memory protection types
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Memory types recognized by PMS
|
||||
*/
|
||||
typedef enum {
|
||||
MEMPROT_TYPE_NONE = 0x00000000,
|
||||
MEMPROT_TYPE_ALL = 0x7FFFFFFF,
|
||||
MEMPROT_TYPE_INVALID = 0x80000000
|
||||
} esp_mprot_mem_t;
|
||||
|
||||
/**
|
||||
* @brief Splitting address (line) type
|
||||
*/
|
||||
typedef enum {
|
||||
MEMPROT_SPLIT_ADDR_NONE = 0x00000000,
|
||||
MEMPROT_SPLIT_ADDR_ALL = 0x7FFFFFFF,
|
||||
MEMPROT_SPLIT_ADDR_INVALID = 0x80000000
|
||||
} esp_mprot_split_addr_t;
|
||||
|
||||
/**
|
||||
* @brief PMS area type (memory space between adjacent splitting addresses or above/below the main splt.address)
|
||||
*/
|
||||
typedef enum {
|
||||
MEMPROT_PMS_AREA_NONE = 0x00000000,
|
||||
MEMPROT_PMS_AREA_ALL = 0x7FFFFFFF,
|
||||
MEMPROT_PMS_AREA_INVALID = 0x80000000
|
||||
} esp_mprot_pms_area_t;
|
||||
|
||||
/**
|
||||
* @brief Memory protection configuration
|
||||
*/
|
||||
typedef struct {
|
||||
bool invoke_panic_handler; /*!< Register PMS violation interrupt for panic-handling */
|
||||
bool lock_feature; /*!< Lock all PMS settings */
|
||||
void *split_addr; /*!< Main I/D splitting address */
|
||||
uint32_t mem_type_mask; /*!< Memory types required to protect. See esp_mprot_mem_t enum */
|
||||
} esp_memp_config_t;
|
||||
|
||||
#define ESP_MEMPROT_DEFAULT_CONFIG() { \
|
||||
.invoke_panic_handler = true, \
|
||||
.lock_feature = true, \
|
||||
.split_addr = NULL, \
|
||||
.mem_type_mask = MEMPROT_TYPE_ALL \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts Memory protection type to string
|
||||
*
|
||||
* @param mem_type Memory protection type
|
||||
*/
|
||||
static inline const char *esp_mprot_mem_type_to_str(const esp_mprot_mem_t mem_type)
|
||||
{
|
||||
switch (mem_type) {
|
||||
case MEMPROT_TYPE_NONE:
|
||||
return "MEMPROT_TYPE_NONE";
|
||||
case MEMPROT_TYPE_ALL:
|
||||
return "MEMPROT_TYPE_ALL";
|
||||
default:
|
||||
return "MEMPROT_TYPE_INVALID";
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts Splitting address type to string
|
||||
*
|
||||
* @param line_type Split line type
|
||||
*/
|
||||
static inline const char *esp_mprot_split_addr_to_str(const esp_mprot_split_addr_t line_type)
|
||||
{
|
||||
switch (line_type) {
|
||||
case MEMPROT_SPLIT_ADDR_NONE:
|
||||
return "MEMPROT_SPLIT_ADDR_NONE";
|
||||
case MEMPROT_SPLIT_ADDR_ALL:
|
||||
return "MEMPROT_SPLIT_ADDR_ALL";
|
||||
default:
|
||||
return "MEMPROT_SPLIT_ADDR_INVALID";
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts PMS Area type to string
|
||||
*
|
||||
* @param area_type PMS Area type
|
||||
*/
|
||||
static inline const char *esp_mprot_pms_area_to_str(const esp_mprot_pms_area_t area_type)
|
||||
{
|
||||
switch (area_type) {
|
||||
case MEMPROT_PMS_AREA_NONE:
|
||||
return "MEMPROT_PMS_AREA_NONE";
|
||||
case MEMPROT_PMS_AREA_ALL:
|
||||
return "MEMPROT_PMS_AREA_ALL";
|
||||
default:
|
||||
return "MEMPROT_PMS_AREA_INVALID";
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,23 +0,0 @@
|
||||
set(srcs "rtc_clk_init.c"
|
||||
"rtc_clk.c"
|
||||
"rtc_init.c"
|
||||
"rtc_sleep.c"
|
||||
"rtc_time.c"
|
||||
"chip_info.c"
|
||||
)
|
||||
|
||||
if(NOT BOOTLOADER_BUILD)
|
||||
list(APPEND srcs "esp_crypto_lock.c"
|
||||
"sar_periph_ctrl.c")
|
||||
|
||||
if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
|
||||
list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
|
||||
endif()
|
||||
|
||||
endif()
|
||||
|
||||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
|
||||
target_include_directories(${COMPONENT_LIB} PRIVATE ../hal)
|
||||
@@ -1,41 +0,0 @@
|
||||
choice ESP32H4_REV_MIN
|
||||
prompt "Minimum Supported ESP32-H4 Revision"
|
||||
default ESP32H4_REV_MIN_0
|
||||
help
|
||||
Required minimum chip revision. ESP-IDF will check for it and
|
||||
reject to boot if the chip revision fails the check.
|
||||
This ensures the chip used will have some modifications (features, or bugfixes).
|
||||
|
||||
The complied binary will only support chips above this revision,
|
||||
this will also help to reduce binary size.
|
||||
|
||||
config ESP32H4_REV_MIN_0
|
||||
bool "Rev v0.0 (ECO0)"
|
||||
endchoice
|
||||
|
||||
config ESP32H4_REV_MIN_FULL
|
||||
int
|
||||
default 0 if ESP32H4_REV_MIN_0
|
||||
|
||||
config ESP_REV_MIN_FULL
|
||||
int
|
||||
default ESP32H4_REV_MIN_FULL
|
||||
|
||||
#
|
||||
# MAX Revision
|
||||
#
|
||||
|
||||
comment "Maximum Supported ESP32-H4 Revision (Rev v1.99)"
|
||||
# Maximum revision that IDF supports.
|
||||
# It can not be changed by user.
|
||||
# Only Espressif can change it when a new version will be supported in IDF.
|
||||
# Supports all chips starting from ESP32H4_REV_MIN_FULL to ESP32H4_REV_MAX_FULL
|
||||
|
||||
config ESP32H4_REV_MAX_FULL
|
||||
int
|
||||
default 199
|
||||
# keep in sync the "Maximum Supported Revision" description with this value
|
||||
|
||||
config ESP_REV_MAX_FULL
|
||||
int
|
||||
default ESP32H4_REV_MAX_FULL
|
||||
@@ -1,19 +0,0 @@
|
||||
# ESP32H4-TODO: IDF-3390
|
||||
choice ESP32H4_UNIVERSAL_MAC_ADDRESSES
|
||||
bool "Number of universally administered (by IEEE) MAC address"
|
||||
default ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
help
|
||||
Configure the number of universally administered (by IEEE) MAC addresses.
|
||||
During initialization, MAC addresses for each network interface are generated or derived from a
|
||||
single base MAC address.
|
||||
|
||||
config ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
bool "Two"
|
||||
select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
select ESP_MAC_ADDR_UNIVERSE_IEEE802154
|
||||
select ESP_MAC_ADDR_UNIVERSE_BT
|
||||
endchoice
|
||||
|
||||
config ESP32H4_UNIVERSAL_MAC_ADDRESSES
|
||||
int
|
||||
default 2 if ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
@@ -1,38 +0,0 @@
|
||||
choice RTC_CLK_SRC
|
||||
prompt "RTC clock source"
|
||||
default RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
config RTC_CLK_SRC_INT_RC
|
||||
bool "Internal 136kHz RC oscillator"
|
||||
config RTC_CLK_SRC_EXT_CRYS
|
||||
bool "External 32.768kHz crystal"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
config RTC_CLK_SRC_EXT_OSC
|
||||
bool "External 32kHz oscillator at 32K_XP pin"
|
||||
select ESP_SYSTEM_RTC_EXT_OSC
|
||||
config RTC_CLK_SRC_INT_RC32K
|
||||
bool "Internal 32kHz RC oscillator"
|
||||
endchoice
|
||||
|
||||
config RTC_CLK_CAL_CYCLES
|
||||
int "Number of cycles for RTC_SLOW_CLK calibration"
|
||||
default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K
|
||||
default 576 if RTC_CLK_SRC_INT_RC
|
||||
range 0 125000
|
||||
help
|
||||
When the startup code initializes RTC_SLOW_CLK, it can perform
|
||||
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
|
||||
frequency. This option sets the number of RTC_SLOW_CLK cycles measured
|
||||
by the calibration routine. Higher numbers increase calibration
|
||||
precision, which may be important for applications which spend a lot of
|
||||
time in deep sleep. Lower numbers reduce startup time.
|
||||
|
||||
When this option is set to 0, clock calibration will not be performed at
|
||||
startup, and approximate clock frequencies will be assumed:
|
||||
|
||||
- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
|
||||
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
|
||||
In case more value will help improve the definition of the launch of the crystal.
|
||||
If the crystal could not start, it will be switched to internal RC.
|
||||
@@ -1,18 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include "esp_chip_info.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
void esp_chip_info(esp_chip_info_t *out_info)
|
||||
{
|
||||
memset(out_info, 0, sizeof(*out_info));
|
||||
out_info->model = CHIP_ESP32H4;
|
||||
out_info->revision = efuse_hal_chip_revision();
|
||||
out_info->cores = 1;
|
||||
out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;
|
||||
}
|
||||
@@ -1,62 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "clk_tree.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_check.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "esp_private/clk_tree_common.h"
|
||||
|
||||
static const char *TAG = "clk_tree";
|
||||
|
||||
esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
|
||||
uint32_t *freq_value)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src");
|
||||
ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision");
|
||||
ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer");
|
||||
|
||||
uint32_t clk_src_freq = 0;
|
||||
switch (clk_src) {
|
||||
case SOC_MOD_CLK_CPU:
|
||||
clk_src_freq = clk_hal_cpu_get_freq_hz();
|
||||
break;
|
||||
case SOC_MOD_CLK_AHB:
|
||||
clk_src_freq = clk_hal_ahb_get_freq_hz();
|
||||
break;
|
||||
case SOC_MOD_CLK_APB:
|
||||
clk_src_freq = clk_hal_apb_get_freq_hz();
|
||||
break;
|
||||
case SOC_MOD_CLK_XTAL:
|
||||
clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
|
||||
break;
|
||||
case SOC_MOD_CLK_PLL:
|
||||
clk_src_freq = clk_ll_bbpll_get_freq_mhz() * MHZ;
|
||||
break;
|
||||
case SOC_MOD_CLK_RTC_SLOW:
|
||||
clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
|
||||
break;
|
||||
case SOC_MOD_CLK_RTC_FAST:
|
||||
clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
|
||||
break;
|
||||
case SOC_MOD_CLK_RC_FAST:
|
||||
clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
|
||||
break;
|
||||
case SOC_MOD_CLK_XTAL32K:
|
||||
clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG,
|
||||
"freq shouldn't be 0, calibration failed");
|
||||
*freq_value = clk_src_freq;
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -1,107 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "riscv/csr.h"
|
||||
|
||||
void esp_cpu_configure_region_protection(void)
|
||||
{
|
||||
/* Notes on implementation:
|
||||
*
|
||||
* 1) Note: ESP32-H4 CPU doesn't support overlapping PMP regions
|
||||
*
|
||||
* 2) Therefore, we use TOR (top of range) entries to map the whole address
|
||||
* space, bottom to top.
|
||||
*
|
||||
* 3) There are not enough entries to describe all the memory regions 100% accurately.
|
||||
*
|
||||
* 4) This means some gaps (invalid memory) are accessible. Priority for extending regions
|
||||
* to cover gaps is to extend read-only or read-execute regions or read-only regions only
|
||||
* (executing unmapped addresses should always fault with invalid instruction, read-only means
|
||||
* stores will correctly fault even if reads may return some invalid value.)
|
||||
*
|
||||
* 5) Entries are grouped in order with some static asserts to try and verify everything is
|
||||
* correct.
|
||||
*/
|
||||
const unsigned NONE = PMP_L | PMP_TOR;
|
||||
const unsigned R = PMP_L | PMP_TOR | PMP_R;
|
||||
const unsigned RW = PMP_L | PMP_TOR | PMP_R | PMP_W;
|
||||
const unsigned RX = PMP_L | PMP_TOR | PMP_R | PMP_X;
|
||||
const unsigned RWX = PMP_L | PMP_TOR | PMP_R | PMP_W | PMP_X;
|
||||
|
||||
// 1. Gap at bottom of address space
|
||||
PMP_ENTRY_SET(0, SOC_DEBUG_LOW, NONE);
|
||||
|
||||
// 2. Debug region
|
||||
PMP_ENTRY_SET(1, SOC_DEBUG_HIGH, RWX);
|
||||
_Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region");
|
||||
|
||||
// 3. Gap between debug region & DROM (flash cache)
|
||||
PMP_ENTRY_SET(2, SOC_DROM_LOW, NONE);
|
||||
_Static_assert(SOC_DEBUG_HIGH < SOC_DROM_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 4. DROM (flash cache)
|
||||
// 5. Gap between DROM & DRAM
|
||||
// (Note: To save PMP entries these two are merged into one read-only region)
|
||||
PMP_ENTRY_SET(3, SOC_DRAM_LOW, R);
|
||||
_Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid DROM region");
|
||||
_Static_assert(SOC_DROM_HIGH < SOC_DRAM_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 6. DRAM
|
||||
PMP_ENTRY_SET(4, SOC_DRAM_HIGH, RW);
|
||||
_Static_assert(SOC_DRAM_LOW < SOC_DRAM_HIGH, "Invalid DRAM region");
|
||||
|
||||
// 7. Gap between DRAM and Mask DROM
|
||||
// 8. Mask DROM
|
||||
// (Note: to save PMP entries these two are merged into one read-only region)
|
||||
PMP_ENTRY_SET(5, SOC_DROM_MASK_HIGH, R);
|
||||
_Static_assert(SOC_DRAM_HIGH < SOC_DROM_MASK_LOW, "Invalid PMP entry order");
|
||||
_Static_assert(SOC_DROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid mask DROM region");
|
||||
|
||||
// 9. Gap between mask DROM and mask IROM
|
||||
// 10. Mask IROM
|
||||
// (Note: to save PMP entries these two are merged into one RX region)
|
||||
PMP_ENTRY_SET(6, SOC_IROM_MASK_HIGH, RX);
|
||||
_Static_assert(SOC_DROM_MASK_HIGH < SOC_IROM_MASK_LOW, "Invalid PMP entry order");
|
||||
_Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid mask IROM region");
|
||||
|
||||
// 11. Gap between mask IROM & IRAM
|
||||
PMP_ENTRY_SET(7, SOC_IRAM_LOW, NONE);
|
||||
_Static_assert(SOC_IROM_MASK_HIGH < SOC_IRAM_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 12. IRAM
|
||||
PMP_ENTRY_SET(8, SOC_IRAM_HIGH, RWX);
|
||||
_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid IRAM region");
|
||||
|
||||
// 13. Gap between IRAM and IROM
|
||||
// 14. IROM (flash cache)
|
||||
// (Note: to save PMP entries these two are merged into one RX region)
|
||||
PMP_ENTRY_SET(9, SOC_IROM_HIGH, RX);
|
||||
_Static_assert(SOC_IRAM_HIGH < SOC_IROM_LOW, "Invalid PMP entry order");
|
||||
_Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid IROM region");
|
||||
|
||||
// 15. Gap between IROM & RTC slow memory
|
||||
PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE);
|
||||
_Static_assert(SOC_IROM_HIGH < SOC_RTC_IRAM_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 16. RTC fast memory
|
||||
PMP_ENTRY_SET(11, SOC_RTC_IRAM_HIGH, RWX);
|
||||
_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
|
||||
|
||||
// 17. Gap between RTC fast memory & peripheral addresses
|
||||
PMP_ENTRY_SET(12, SOC_PERIPHERAL_LOW, NONE);
|
||||
_Static_assert(SOC_RTC_IRAM_HIGH < SOC_PERIPHERAL_LOW, "Invalid PMP entry order");
|
||||
|
||||
// 18. Peripheral addresses
|
||||
PMP_ENTRY_SET(13, SOC_PERIPHERAL_HIGH, RW);
|
||||
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
|
||||
|
||||
// 19. End of address space
|
||||
PMP_ENTRY_SET(14, UINT32_MAX, NONE); // all but last 4 bytes
|
||||
PMP_ENTRY_SET(15, UINT32_MAX, PMP_L | PMP_NA4); // last 4 bytes
|
||||
}
|
||||
@@ -1,75 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <sys/lock.h>
|
||||
|
||||
#include "esp_crypto_lock.h"
|
||||
|
||||
/* Lock overview:
|
||||
SHA: peripheral independent, but DMA is shared with AES
|
||||
AES: peripheral independent, but DMA is shared with SHA
|
||||
MPI/RSA: independent
|
||||
HMAC: needs SHA
|
||||
DS: needs HMAC (which needs SHA), AES and MPI
|
||||
*/
|
||||
|
||||
/* Lock for DS peripheral */
|
||||
static _lock_t s_crypto_ds_lock;
|
||||
|
||||
/* Lock for HMAC peripheral */
|
||||
static _lock_t s_crypto_hmac_lock;
|
||||
|
||||
/* Lock for the MPI/RSA peripheral, also used by the DS peripheral */
|
||||
static _lock_t s_crypto_mpi_lock;
|
||||
|
||||
/* Single lock for SHA and AES, sharing a reserved GDMA channel */
|
||||
static _lock_t s_crypto_sha_aes_lock;
|
||||
|
||||
void esp_crypto_hmac_lock_acquire(void)
|
||||
{
|
||||
_lock_acquire(&s_crypto_hmac_lock);
|
||||
esp_crypto_sha_aes_lock_acquire();
|
||||
}
|
||||
|
||||
void esp_crypto_hmac_lock_release(void)
|
||||
{
|
||||
esp_crypto_sha_aes_lock_release();
|
||||
_lock_release(&s_crypto_hmac_lock);
|
||||
}
|
||||
|
||||
void esp_crypto_ds_lock_acquire(void)
|
||||
{
|
||||
_lock_acquire(&s_crypto_ds_lock);
|
||||
esp_crypto_hmac_lock_acquire();
|
||||
esp_crypto_mpi_lock_acquire();
|
||||
}
|
||||
|
||||
void esp_crypto_ds_lock_release(void)
|
||||
{
|
||||
esp_crypto_mpi_lock_release();
|
||||
esp_crypto_hmac_lock_release();
|
||||
_lock_release(&s_crypto_ds_lock);
|
||||
}
|
||||
|
||||
void esp_crypto_sha_aes_lock_acquire(void)
|
||||
{
|
||||
_lock_acquire(&s_crypto_sha_aes_lock);
|
||||
}
|
||||
|
||||
void esp_crypto_sha_aes_lock_release(void)
|
||||
{
|
||||
_lock_release(&s_crypto_sha_aes_lock);
|
||||
}
|
||||
|
||||
void esp_crypto_mpi_lock_acquire(void)
|
||||
{
|
||||
_lock_acquire(&s_crypto_mpi_lock);
|
||||
}
|
||||
|
||||
void esp_crypto_mpi_lock_release(void)
|
||||
{
|
||||
_lock_release(&s_crypto_mpi_lock);
|
||||
}
|
||||
@@ -1,215 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
#include "esp_fault.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_memprot_err.h"
|
||||
#include "hal/memprot_types.h"
|
||||
#include "esp_private/esp_memprot_internal.h"
|
||||
#include "esp_memprot.h"
|
||||
|
||||
esp_err_t esp_mprot_set_split_addr(const esp_mprot_mem_t mem_type, const esp_mprot_split_addr_t line_type, const void *line_addr)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_split_addr(const esp_mprot_mem_t mem_type, const esp_mprot_split_addr_t line_type, void **line_addr)
|
||||
{
|
||||
if (line_addr == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*line_addr = NULL;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_default_main_split_addr(const esp_mprot_mem_t mem_type, void **def_split_addr)
|
||||
{
|
||||
if (def_split_addr == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*def_split_addr = NULL;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_set_split_addr_lock(const esp_mprot_mem_t mem_type)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_split_addr_lock(const esp_mprot_mem_t mem_type, bool *locked)
|
||||
{
|
||||
if (locked == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*locked = false;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_set_pms_lock(const esp_mprot_mem_t mem_type)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_pms_lock(const esp_mprot_mem_t mem_type, bool *locked)
|
||||
{
|
||||
if (locked == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*locked = false;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_set_pms_area(const esp_mprot_pms_area_t area_type, const uint32_t flags)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_pms_area(const esp_mprot_pms_area_t area_type, uint32_t *flags)
|
||||
{
|
||||
if (flags == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*flags = MEMPROT_OP_NONE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_set_monitor_lock(const esp_mprot_mem_t mem_type)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_monitor_lock(const esp_mprot_mem_t mem_type, bool *locked)
|
||||
{
|
||||
if (locked == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*locked = false;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_set_monitor_en(const esp_mprot_mem_t mem_type, const bool enable)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_monitor_en(const esp_mprot_mem_t mem_type, bool *enabled)
|
||||
{
|
||||
if (enabled == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*enabled = false;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_monitor_clear_intr(const esp_mprot_mem_t mem_type, const int core __attribute__((unused)))
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_active_intr(esp_memp_intr_source_t *active_memp_intr)
|
||||
{
|
||||
if (active_memp_intr == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
active_memp_intr->mem_type = MEMPROT_TYPE_NONE;
|
||||
active_memp_intr->core = -1;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_is_conf_locked_any(bool *locked)
|
||||
{
|
||||
if (locked == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*locked = false;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_is_intr_ena_any(bool *enabled)
|
||||
{
|
||||
if (enabled == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*enabled = false;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_violate_addr(const esp_mprot_mem_t mem_type, void **fault_addr, const int core __attribute__((unused)))
|
||||
{
|
||||
if (fault_addr == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*fault_addr = NULL;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_violate_world(const esp_mprot_mem_t mem_type, esp_mprot_pms_world_t *world, const int core __attribute__((unused)))
|
||||
{
|
||||
if (world == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*world = MEMPROT_PMS_WORLD_NONE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_violate_operation(const esp_mprot_mem_t mem_type, uint32_t *oper, const int core __attribute__((unused)))
|
||||
{
|
||||
if (oper == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*oper = MEMPROT_OP_NONE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
bool esp_mprot_has_byte_enables(const esp_mprot_mem_t mem_type)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_get_violate_byte_enables(const esp_mprot_mem_t mem_type, uint32_t *byte_en, const int core __attribute__((unused)))
|
||||
{
|
||||
if (byte_en == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
|
||||
*byte_en = 0;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_mprot_set_prot(const esp_memp_config_t *memp_config)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file i2c_brownout.h
|
||||
* @brief Register definitions for brownout detector
|
||||
*
|
||||
* This file lists register fields of the brownout detector, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in i2c_rtc_clk.h.
|
||||
*/
|
||||
|
||||
#define I2C_BOD 0x61
|
||||
#define I2C_BOD_HOSTID 1
|
||||
|
||||
#define I2C_BOD_THRESHOLD 0x5
|
||||
#define I2C_BOD_THRESHOLD_MSB 2
|
||||
#define I2C_BOD_THRESHOLD_LSB 0
|
||||
@@ -1,13 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "esp_private/io_mux.h"
|
||||
|
||||
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
|
||||
{
|
||||
// IO MUX clock source is not selectable
|
||||
return ESP_OK;
|
||||
}
|
||||
@@ -1,423 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <assert.h>
|
||||
#include <stdlib.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp32h4/rom/ets_sys.h"
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#include "esp32h4/rom/uart.h"
|
||||
#include "esp32h4/rom/gpio.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "esp_private/rtc_clk.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "hal/gpio_ll.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
static const char *TAG = "rtc_clk";
|
||||
|
||||
#define RTC_OSC_FREQ_RC8M 8
|
||||
|
||||
// Current PLL frequency, in 96MHZ. Zero if PLL is not enabled.
|
||||
static int s_cur_pll_freq;
|
||||
|
||||
static uint32_t rtc_clk_ahb_freq_get(void);
|
||||
static void rtc_clk_cpu_freq_to_xtal(int freq, int div);
|
||||
void rtc_clk_cpu_freq_to_8m(void);
|
||||
|
||||
// Unused as unsupported yet
|
||||
static uint32_t __attribute((unused)) s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG
|
||||
|
||||
void rtc_clk_bbpll_add_consumer(void)
|
||||
{
|
||||
s_bbpll_digi_consumers_ref_count += 1;
|
||||
}
|
||||
|
||||
void rtc_clk_bbpll_remove_consumer(void)
|
||||
{
|
||||
s_bbpll_digi_consumers_ref_count -= 1;
|
||||
}
|
||||
|
||||
static void rtc_gpio_hangup(uint32_t gpio_no)
|
||||
{
|
||||
gpio_ll_pulldown_dis(&GPIO, gpio_no);
|
||||
gpio_ll_pullup_dis(&GPIO, gpio_no);
|
||||
gpio_ll_output_disable(&GPIO, gpio_no);
|
||||
gpio_ll_input_disable(&GPIO, gpio_no);
|
||||
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_no], PIN_FUNC_GPIO);
|
||||
}
|
||||
|
||||
void rtc_clk_32k_enable(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
/* need to hangup 32K_P and 32K_N pins before enable xtal_32k */
|
||||
rtc_gpio_hangup(XTAL32K_P_GPIO_NUM);
|
||||
rtc_gpio_hangup(XTAL32K_N_GPIO_NUM);
|
||||
clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL);
|
||||
} else {
|
||||
clk_ll_xtal32k_disable();
|
||||
}
|
||||
}
|
||||
|
||||
void rtc_clk_32k_enable_external(void)
|
||||
{
|
||||
clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL);
|
||||
}
|
||||
|
||||
void rtc_clk_32k_bootstrap(uint32_t cycle)
|
||||
{
|
||||
/* No special bootstrapping needed for ESP32-H4, 'cycle' argument is to keep the signature
|
||||
* same as for the ESP32. Just enable the XTAL here.
|
||||
*/
|
||||
(void)cycle;
|
||||
rtc_clk_32k_enable(true);
|
||||
}
|
||||
|
||||
bool rtc_clk_32k_enabled(void)
|
||||
{
|
||||
return clk_ll_xtal32k_is_enabled();
|
||||
}
|
||||
|
||||
void rtc_clk_rc32k_enable(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
clk_ll_rc32k_enable();
|
||||
} else {
|
||||
clk_ll_rc32k_disable();
|
||||
}
|
||||
}
|
||||
|
||||
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
|
||||
{
|
||||
clk_ll_rtc_slow_set_src(clk_src);
|
||||
rtc_clk_32k_enable((clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? 1 : 0);
|
||||
rtc_clk_rc32k_enable((clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? 1 : 0);
|
||||
esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
|
||||
}
|
||||
|
||||
soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
|
||||
{
|
||||
return clk_ll_rtc_slow_get_src();
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_slow_freq_get_hz(void)
|
||||
{
|
||||
switch (rtc_clk_slow_src_get()) {
|
||||
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
|
||||
case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
|
||||
case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src)
|
||||
{
|
||||
clk_ll_rtc_fast_set_src(clk_src);
|
||||
esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH);
|
||||
}
|
||||
|
||||
soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
|
||||
{
|
||||
return clk_ll_rtc_fast_get_src();
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_disable(void)
|
||||
{
|
||||
clk_ll_bbpll_disable();
|
||||
s_cur_pll_freq = 0;
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_enable(void)
|
||||
{
|
||||
clk_ll_bbpll_enable();
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
if (!((pll_freq == CLK_LL_PLL_96M_FREQ_MHZ) && (xtal_freq == RTC_XTAL_FREQ_32M))) {
|
||||
ESP_HW_LOGE(TAG, "invalid pll or xtal frequency");
|
||||
}
|
||||
|
||||
// No digital part needs to be set, pll_freq can only be 96MHz
|
||||
|
||||
// Configure analog part
|
||||
regi2c_ctrl_ll_bbpll_calibration_start();
|
||||
clk_ll_bbpll_set_config(pll_freq, xtal_freq);
|
||||
// Wait until calibration finishes
|
||||
while (!regi2c_ctrl_ll_bbpll_calibration_is_done());
|
||||
// Prevent BBPLL clock jitter
|
||||
regi2c_ctrl_ll_bbpll_calibration_stop();
|
||||
s_cur_pll_freq = pll_freq;
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_select_root_clk(soc_cpu_clk_src_t cpu_clk_src)
|
||||
{
|
||||
uint32_t root_clk_freq_mhz;
|
||||
switch (cpu_clk_src) {
|
||||
case SOC_CPU_CLK_SRC_XTAL:
|
||||
root_clk_freq_mhz = RTC_XTAL_FREQ_32M;
|
||||
rtc_clk_bbpll_disable();
|
||||
break;
|
||||
case SOC_CPU_CLK_SRC_PLL:
|
||||
// SPLL_ENABLE
|
||||
root_clk_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
|
||||
rtc_clk_bbpll_enable();
|
||||
rtc_clk_bbpll_configure(RTC_XTAL_FREQ_32M, root_clk_freq_mhz);
|
||||
break;
|
||||
case SOC_CPU_CLK_SRC_RC_FAST:
|
||||
root_clk_freq_mhz = RTC_OSC_FREQ_RC8M;
|
||||
rtc_dig_clk8m_enable(); // TODO: Do we need to enable digital gating here?
|
||||
rtc_clk_8m_divider_set(1);
|
||||
rtc_clk_bbpll_disable();
|
||||
break;
|
||||
case SOC_CPU_CLK_SRC_XTAL_D2:
|
||||
root_clk_freq_mhz = RTC_XTAL_FREQ_32M / 2;
|
||||
rtc_clk_bbpll_disable();
|
||||
break;
|
||||
default:
|
||||
ESP_HW_LOGE(TAG, "unsupported source clk configuration");
|
||||
// fallback to XTAL as root clock source
|
||||
root_clk_freq_mhz = RTC_XTAL_FREQ_32M;
|
||||
rtc_clk_bbpll_disable();
|
||||
cpu_clk_src = SOC_CPU_CLK_SRC_XTAL;
|
||||
break;
|
||||
}
|
||||
clk_ll_cpu_set_src(cpu_clk_src);
|
||||
return root_clk_freq_mhz;
|
||||
}
|
||||
|
||||
/**
|
||||
* Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
|
||||
* PLL must already be enabled.
|
||||
* @param cpu_freq new CPU frequency
|
||||
*/
|
||||
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
|
||||
{
|
||||
int div = 1;
|
||||
if (CLK_LL_PLL_96M_FREQ_MHZ % cpu_freq_mhz == 0) {
|
||||
div = CLK_LL_PLL_96M_FREQ_MHZ / cpu_freq_mhz;
|
||||
} else {
|
||||
ESP_HW_LOGE(TAG, "invalid frequency");
|
||||
abort();
|
||||
}
|
||||
rtc_clk_cpu_freq_set(SOC_CPU_CLK_SRC_PLL, div);
|
||||
if (cpu_freq_mhz > RTC_XTAL_FREQ_32M) {
|
||||
clk_ll_ahb_set_divider(2);
|
||||
} else {
|
||||
clk_ll_ahb_set_divider(1);
|
||||
}
|
||||
|
||||
ets_update_cpu_frequency(cpu_freq_mhz);
|
||||
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
|
||||
}
|
||||
|
||||
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
|
||||
{
|
||||
// TODO: This function supposes to only fill a cpu config, but it is writing to registers, needs to check
|
||||
uint32_t source_freq_mhz;
|
||||
soc_cpu_clk_src_t source;
|
||||
uint32_t divider;
|
||||
uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
|
||||
if (freq_mhz > xtal_freq) {
|
||||
source = SOC_CPU_CLK_SRC_PLL;
|
||||
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
|
||||
divider = CLK_LL_PLL_96M_FREQ_MHZ / freq_mhz;
|
||||
clk_ll_ahb_set_divider(2);
|
||||
} else if (freq_mhz != 0) {
|
||||
source = clk_ll_cpu_get_src();
|
||||
source_freq_mhz = rtc_clk_select_root_clk(source);
|
||||
divider = source_freq_mhz / freq_mhz;
|
||||
clk_ll_ahb_set_divider(1);
|
||||
} else {
|
||||
// unsupported frequency
|
||||
return false;
|
||||
}
|
||||
*out_config = (rtc_cpu_freq_config_t) {
|
||||
.source = source,
|
||||
.div = divider,
|
||||
.source_freq_mhz = source_freq_mhz,
|
||||
.freq_mhz = freq_mhz
|
||||
};
|
||||
return true;
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
|
||||
{
|
||||
uint32_t src_freq_mhz = rtc_clk_select_root_clk(config->source);
|
||||
uint32_t div = src_freq_mhz / (config->freq_mhz);
|
||||
rtc_clk_cpu_freq_set(config->source, div);
|
||||
ets_update_cpu_frequency(config->freq_mhz);
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
|
||||
{
|
||||
soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
|
||||
uint32_t source_freq_mhz;
|
||||
uint32_t div;
|
||||
uint32_t freq_mhz;
|
||||
switch (source) {
|
||||
case SOC_CPU_CLK_SRC_XTAL: {
|
||||
div = clk_ll_cpu_get_divider();
|
||||
source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
|
||||
freq_mhz = source_freq_mhz / div;
|
||||
break;
|
||||
}
|
||||
case SOC_CPU_CLK_SRC_PLL: {
|
||||
div = clk_ll_cpu_get_divider();
|
||||
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
|
||||
freq_mhz = source_freq_mhz / div;
|
||||
break;
|
||||
}
|
||||
case SOC_CPU_CLK_SRC_RC_FAST: {
|
||||
source_freq_mhz = RTC_OSC_FREQ_RC8M;
|
||||
div = clk_ll_cpu_get_divider();
|
||||
freq_mhz = source_freq_mhz / div;
|
||||
break;
|
||||
}
|
||||
case SOC_CPU_CLK_SRC_XTAL_D2: {
|
||||
div = clk_ll_cpu_get_divider();
|
||||
source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
|
||||
freq_mhz = source_freq_mhz / div / 2;
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
ESP_HW_LOGE(TAG, "unsupported frequency configuration");
|
||||
abort();
|
||||
}
|
||||
}
|
||||
*out_config = (rtc_cpu_freq_config_t) {
|
||||
.source = source,
|
||||
.source_freq_mhz = source_freq_mhz,
|
||||
.div = div,
|
||||
.freq_mhz = freq_mhz
|
||||
};
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
|
||||
{
|
||||
if (config->source == SOC_CPU_CLK_SRC_XTAL) {
|
||||
rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
|
||||
} else if (config->source == SOC_CPU_CLK_SRC_PLL &&
|
||||
s_cur_pll_freq == config->source_freq_mhz) {
|
||||
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
|
||||
} else {
|
||||
/* fallback */
|
||||
rtc_clk_cpu_freq_set_config(config);
|
||||
}
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_freq_set_xtal(void)
|
||||
{
|
||||
rtc_clk_cpu_set_to_default_config();
|
||||
rtc_clk_bbpll_disable();
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_set_to_default_config(void)
|
||||
{
|
||||
int freq_mhz = (int)rtc_clk_xtal_freq_get();
|
||||
|
||||
rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Switch to use XTAL as the CPU clock source.
|
||||
* Must satisfy: cpu_freq = XTAL_FREQ / div.
|
||||
* Does not disable the PLL.
|
||||
*/
|
||||
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
|
||||
{
|
||||
ets_update_cpu_frequency(cpu_freq);
|
||||
/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
|
||||
rtc_clk_cpu_freq_set(SOC_CPU_CLK_SRC_XTAL, div);
|
||||
/* no need to adjust the REF_TICK */
|
||||
/* switch clock source */
|
||||
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_freq_to_8m(void)
|
||||
{
|
||||
ets_update_cpu_frequency(RTC_OSC_FREQ_RC8M);
|
||||
rtc_clk_select_root_clk(SOC_CPU_CLK_SRC_RC_FAST);
|
||||
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
|
||||
if (xtal_freq_mhz == 0) {
|
||||
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 32MHz");
|
||||
return RTC_XTAL_FREQ_32M;
|
||||
}
|
||||
return (rtc_xtal_freq_t)xtal_freq_mhz;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
||||
void rtc_clk_apb_freq_update(uint32_t apb_freq)
|
||||
{
|
||||
clk_ll_apb_store_freq_hz(apb_freq);
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_apb_freq_get(void)
|
||||
{
|
||||
return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider();
|
||||
}
|
||||
|
||||
static uint32_t rtc_clk_ahb_freq_get(void)
|
||||
{
|
||||
rtc_cpu_freq_config_t cpu_config;
|
||||
rtc_clk_cpu_freq_get_config(&cpu_config);
|
||||
return cpu_config.freq_mhz * MHZ / clk_ll_ahb_get_divider();
|
||||
}
|
||||
|
||||
void rtc_clk_cpu_freq_set(uint32_t source, uint32_t div)
|
||||
{
|
||||
if ((uint32_t)clk_ll_cpu_get_src() != source) {
|
||||
rtc_clk_select_root_clk(source);
|
||||
}
|
||||
clk_ll_cpu_set_divider(div);
|
||||
}
|
||||
|
||||
void rtc_clk_divider_set(uint32_t div)
|
||||
{
|
||||
clk_ll_rc_slow_set_divider(div);
|
||||
}
|
||||
|
||||
void rtc_clk_8m_divider_set(uint32_t div)
|
||||
{
|
||||
clk_ll_rc_fast_set_divider(div);
|
||||
}
|
||||
|
||||
void rtc_dig_clk8m_enable(void)
|
||||
{
|
||||
clk_ll_rc_fast_digi_enable();
|
||||
esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
|
||||
}
|
||||
|
||||
void rtc_dig_clk8m_disable(void)
|
||||
{
|
||||
clk_ll_rc_fast_digi_disable();
|
||||
esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
|
||||
}
|
||||
|
||||
bool rtc_dig_8m_enabled(void)
|
||||
{
|
||||
return clk_ll_rc_fast_digi_is_enabled();
|
||||
}
|
||||
|
||||
/* Name used in libphy.a:phy_chip_v7.o
|
||||
* TODO: update the library to use rtc_clk_xtal_freq_get
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
|
||||
@@ -1,85 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp32h4/rom/ets_sys.h"
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#include "esp32h4/rom/uart.h"
|
||||
#include "esp32h4/rom/gpio.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_periph.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_uart.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
static const char *TAG = "rtc_clk_init";
|
||||
|
||||
void rtc_clk_init(rtc_clk_config_t cfg)
|
||||
{
|
||||
rtc_cpu_freq_config_t old_config, new_config;
|
||||
|
||||
/* Set tuning parameters for 8M and 150k clocks.
|
||||
* Note: this doesn't attempt to set the clocks to precise frequencies.
|
||||
* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
|
||||
* - SCK_DCAP value controls tuning of 150k clock.
|
||||
* The higher the value of DCAP is, the lower is the frequency.
|
||||
* - CK8M_DFREQ value controls tuning of 8M clock.
|
||||
* CLK_8M_DFREQ constant gives the best temperature characteristics.
|
||||
*/
|
||||
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
|
||||
REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
|
||||
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
|
||||
#endif
|
||||
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
|
||||
|
||||
/* enable modem clk */
|
||||
REG_WRITE(SYSTEM_MODEM_CLK_EN_REG, UINT32_MAX);
|
||||
|
||||
/* Configure 150k clock division */
|
||||
rtc_clk_divider_set(cfg.clk_rtc_clk_div);
|
||||
|
||||
/* Configure 8M clock division */
|
||||
rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
|
||||
|
||||
/* Set CPU frequency */
|
||||
rtc_clk_cpu_freq_get_config(&old_config);
|
||||
uint32_t freq_before = old_config.freq_mhz;
|
||||
|
||||
rtc_clk_select_root_clk(cfg.root_clk_slt);
|
||||
bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
|
||||
if (!res) {
|
||||
ESP_HW_LOGE(TAG, "invalid CPU frequency value");
|
||||
abort();
|
||||
}
|
||||
rtc_clk_cpu_freq_set_config(&new_config);
|
||||
|
||||
/* Re-calculate the ccount to make time calculation correct. */
|
||||
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
|
||||
|
||||
/* Slow & fast clocks setup */
|
||||
if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
rtc_clk_32k_enable(true);
|
||||
}
|
||||
if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) {
|
||||
rtc_dig_clk8m_enable();
|
||||
}
|
||||
rtc_clk_fast_src_set(cfg.fast_clk_src);
|
||||
rtc_clk_slow_src_set(cfg.slow_clk_src);
|
||||
}
|
||||
@@ -1,176 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/gpio_reg.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "regi2c_ctrl.h"
|
||||
#include "i2c_pmu.h"
|
||||
#include "soc/clkrst_reg.h"
|
||||
#ifndef BOOTLOADER_BUILD
|
||||
#include "esp_private/sar_periph_ctrl.h"
|
||||
#endif
|
||||
|
||||
void pmu_ctl(void);
|
||||
void dcdc_ctl(uint32_t mode);
|
||||
void regulator_slt(regulator_config_t regula_cfg);
|
||||
|
||||
void rtc_init(rtc_config_t cfg)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
|
||||
|
||||
// set default powerup & wait time
|
||||
rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
|
||||
|
||||
if (cfg.clkctl_init) {
|
||||
//clear CMMU clock force on
|
||||
CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
|
||||
//clear tag clock force on
|
||||
CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
|
||||
//clear register clock force on
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
|
||||
CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
|
||||
}
|
||||
|
||||
if (cfg.pwrctl_init) {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
|
||||
//cancel xtal force pu if no need to force power up
|
||||
//cannot cancel xtal force pu if pll is force power on
|
||||
if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
|
||||
} else {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
|
||||
}
|
||||
// force pd APLL
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
|
||||
|
||||
if (!cfg.bbpll_fpu) {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
|
||||
} else {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_DBOOST_FORCE_PU);
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
|
||||
#endif
|
||||
|
||||
// clear i2c_reset_protect pd force, need tested in low temperature.
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD);
|
||||
|
||||
/* If this mask is enabled, all soc memories cannot enter power down mode */
|
||||
/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
|
||||
CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
|
||||
|
||||
/* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
|
||||
/* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
|
||||
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0);
|
||||
rtc_sleep_pu(pu_cfg);
|
||||
|
||||
//cancel digital PADS force pu
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU); //
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_MEM_FORCE_PU); //
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); //
|
||||
|
||||
//cancel digital PADS force no iso
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); //
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_MEM_FORCE_NOISO); //
|
||||
|
||||
if (cfg.cpu_waiti_clk_gate) {
|
||||
CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
|
||||
} else {
|
||||
SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
|
||||
}
|
||||
/*if SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
|
||||
}
|
||||
|
||||
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
|
||||
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
|
||||
if (cfg.pmu_ctl) {
|
||||
/* pmu init*/
|
||||
pmu_ctl();
|
||||
}
|
||||
/* config dcdc frequency */
|
||||
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL0_REG, RTC_CNTL_FSW_DCDC, RTC_CNTL_DCDC_FREQ_DEFAULT);
|
||||
|
||||
#ifndef BOOTLOADER_BUILD
|
||||
//initialise SAR related peripheral register settings
|
||||
sar_periph_ctrl_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
void pmu_ctl(void)
|
||||
{
|
||||
pmu_config_t pmu_cfg = PMU_CONFIG_DEFAULT();
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_EN_CONT_CAL, pmu_cfg.or_en_cont_cal);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_ENX_RTC_DREG, pmu_cfg.enx_rtc_dreg);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_ENX_DIG_DREG, pmu_cfg.enx_dig_dreg);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, pmu_cfg.en_i2c_rtc_dreg);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, pmu_cfg.en_i2c_dig_dreg);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, pmu_cfg.en_i2c_rtc_dreg_slp);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG_SLP, pmu_cfg.en_i2c_dig_dreg_slp);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_SLAVE_3P3, pmu_cfg.or_xpd_rtc_slave_3p3);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, pmu_cfg.or_xpd_rtc_reg);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DIG_REG, pmu_cfg.or_xpd_dig_reg);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_PD_RTC_REG_SLP, pmu_cfg.or_pd_rtc_reg_slp);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_PD_DIG_REG_SLP, pmu_cfg.or_pd_dig_reg_slp);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DCDC, pmu_cfg.or_xpd_dcdc);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC, pmu_cfg.or_disalbe_deep_sleep_dcdc);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC, pmu_cfg.or_disalbe_light_sleep_dcdc);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENALBE_TRX_MODE_DCDC, pmu_cfg.or_enalbe_trx_mode_dcdc);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENX_REG_DCDC, pmu_cfg.or_enx_reg_dcdc);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_UNLOCK_DCDC, pmu_cfg.or_unlock_dcdc);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_FORCE_LOCK_DCDC, pmu_cfg.or_force_lock_dcdc);
|
||||
// REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENB_SLOW_CLK, pmu_cfg.or_enb_slow_clk);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_TRX, pmu_cfg.or_xpd_trx);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_EN_RESET_CHIP, pmu_cfg.or_en_reset_chip);
|
||||
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_FORCE_XPD_REG_SLAVE, pmu_cfg.or_force_xpd_reg_slave);
|
||||
}
|
||||
|
||||
void dslp_osc_pd(void){
|
||||
REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG,RTC_CNTL_RC32K_XPD, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_PLL8M_REG, RTC_CNTL_XPD_PLL8M, 0);
|
||||
}
|
||||
@@ -1,397 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "soc/i2s_reg.h"
|
||||
#include "soc/bb_reg.h"
|
||||
#include "soc/nrx_reg.h"
|
||||
#include "soc/fe_reg.h"
|
||||
#include "soc/timer_group_reg.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "esp32h4/rom/ets_sys.h"
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#include "regi2c_ctrl.h"
|
||||
#include "soc/regi2c_bias.h"
|
||||
#include "soc/regi2c_ulp.h"
|
||||
#include "i2c_pmu.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "esp_rom_uart.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2
|
||||
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIG_REGULATOR_REG
|
||||
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_DIG_REGULATOR_REG
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
|
||||
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIGULATOR_REG
|
||||
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_REG
|
||||
#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG RTC_CNTL_DIGULATOR1_DBIAS_REG
|
||||
#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG RTC_CNTL_DIGULATOR0_DBIAS_REG
|
||||
#define RTC_CNTL_REGULATOR1_DBIAS_REG RTC_CNTL_RTCULATOR1_DBIAS_REG
|
||||
#define RTC_CNTL_REGULATOR0_DBIAS_REG RTC_CNTL_RTCULATOR0_DBIAS_REG
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Configure whether certain peripherals are powered down in deep sleep
|
||||
* @param cfg power down flags as rtc_sleep_pu_config_t structure
|
||||
*/
|
||||
static const char *TAG = "rtc_sleep";
|
||||
|
||||
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
|
||||
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
|
||||
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
|
||||
REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
|
||||
REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
|
||||
REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
|
||||
REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
|
||||
REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
|
||||
REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
|
||||
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
|
||||
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
|
||||
if (cfg.sram_fpu) {
|
||||
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
|
||||
} else {
|
||||
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
|
||||
}
|
||||
if (cfg.rom_ram_fpu) {
|
||||
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
|
||||
} else {
|
||||
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void dcdc_ctl(uint32_t mode)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_IDLE, RTC_CNTL_DCDC_TRX_MODE);
|
||||
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_MONITOR, RTC_CNTL_DCDC_TRX_MODE);
|
||||
if ((mode & 0x10) == 0x10) {
|
||||
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, mode);
|
||||
} else if (mode == 0) {
|
||||
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_TRX_MODE);
|
||||
} else if (mode == 1) {
|
||||
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_LSLP_MODE);
|
||||
} else if (mode == 2) {
|
||||
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_DSLP_MODE);
|
||||
} else {
|
||||
ESP_HW_LOGE(TAG, "invalid dcdc mode!\n");
|
||||
}
|
||||
}
|
||||
|
||||
void regulator_set(regulator_cfg_t cfg)
|
||||
{
|
||||
// DIG REGULATOR0
|
||||
if (cfg.dig_regul0_en) {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
|
||||
} else {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
|
||||
}
|
||||
// DIG REGULATOR1
|
||||
if (cfg.dig_regul1_en) {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
|
||||
} else {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
|
||||
}
|
||||
// RTC REGULATOR0
|
||||
if (cfg.rtc_regul0_en) {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 0);
|
||||
} else {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 1);
|
||||
}
|
||||
}
|
||||
|
||||
void regulator_slt(regulator_config_t regula_cfg)
|
||||
{
|
||||
// dig regulator
|
||||
if (regula_cfg.dig_source == 1) {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
|
||||
} else {
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
|
||||
}
|
||||
// rtc regulator
|
||||
if (regula_cfg.rtc_source == 1) {
|
||||
REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
|
||||
REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
|
||||
} else {
|
||||
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
|
||||
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
|
||||
}
|
||||
}
|
||||
|
||||
void dbias_switch_set(dbias_swt_cfg_t cfg)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
|
||||
}
|
||||
|
||||
void left_up_trx_fpu(bool fpu)
|
||||
{
|
||||
if (fpu) {
|
||||
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP, 0);
|
||||
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_BIAS_BUF, 0);
|
||||
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 0);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU);
|
||||
}
|
||||
}
|
||||
|
||||
void rtc_sleep_pmu_init(void)
|
||||
{
|
||||
dcdc_ctl(DCDC_SLP_DSLP_MODE);
|
||||
dbias_swt_cfg_t swt_cfg = DBIAS_SWITCH_CONFIG_DEFAULT();
|
||||
dbias_switch_set(swt_cfg);
|
||||
regulator_config_t regula0_cfg = REGULATOR0_CONFIG_DEFAULT();
|
||||
regulator_slt(regula0_cfg);
|
||||
regulator_config_t regula1_cfg = REGULATOR1_CONFIG_DEFAULT();
|
||||
regulator_slt(regula1_cfg);
|
||||
regulator_cfg_t rg_set = REGULATOR_SET_DEFAULT();
|
||||
regulator_set(rg_set);
|
||||
left_up_trx_fpu(0);
|
||||
}
|
||||
|
||||
void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config)
|
||||
{
|
||||
*out_config = (rtc_sleep_config_t) {
|
||||
.lslp_mem_inf_fpu = 0,
|
||||
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0,
|
||||
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0,
|
||||
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0,
|
||||
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0,
|
||||
.dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0,
|
||||
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0,
|
||||
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0,
|
||||
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0,
|
||||
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0,
|
||||
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0,
|
||||
.wdt_flashboot_mod_en = 0,
|
||||
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0,
|
||||
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1,
|
||||
.deep_slp_reject = 1,
|
||||
.light_slp_reject = 1
|
||||
};
|
||||
|
||||
if ((sleep_flags) & RTC_SLEEP_PD_DIG) {
|
||||
out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
|
||||
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP;
|
||||
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
|
||||
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP;
|
||||
|
||||
out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
|
||||
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
|
||||
out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
|
||||
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
|
||||
} else {
|
||||
out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
|
||||
out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP;
|
||||
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
|
||||
out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP;
|
||||
|
||||
out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
|
||||
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
|
||||
out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
|
||||
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
|
||||
}
|
||||
}
|
||||
|
||||
void rtc_sleep_init(rtc_sleep_config_t cfg)
|
||||
{
|
||||
if (cfg.lslp_mem_inf_fpu) {
|
||||
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
|
||||
rtc_sleep_pu(pu_cfg);
|
||||
}
|
||||
if (cfg.bt_pd_en) {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
|
||||
}
|
||||
if (cfg.cpu_pd_en) {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
|
||||
}
|
||||
if (cfg.dig_peri_pd_en) {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
|
||||
}
|
||||
if (cfg.dig_ret_pd_en) {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN);
|
||||
}
|
||||
|
||||
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor);
|
||||
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp);
|
||||
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor);
|
||||
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
|
||||
|
||||
// ESP32-H4 TO-DO: IDF-3693
|
||||
if (cfg.deep_slp) {
|
||||
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
|
||||
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
|
||||
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
|
||||
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
|
||||
} else {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
|
||||
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
|
||||
// SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
|
||||
}
|
||||
|
||||
if (!cfg.int_8m_pd_en) {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
|
||||
}
|
||||
|
||||
/* enable VDDSDIO control by state machine */
|
||||
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
|
||||
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
|
||||
|
||||
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
|
||||
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
|
||||
|
||||
/* gating XTAL clock */
|
||||
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING);
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
|
||||
}
|
||||
|
||||
void rtc_sleep_low_init(uint32_t slowclk_period)
|
||||
{
|
||||
// set 5 PWC state machine times to fit in main state machine time
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
|
||||
}
|
||||
|
||||
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
|
||||
|
||||
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
|
||||
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
|
||||
|
||||
/* Start entry into sleep mode */
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
|
||||
while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
|
||||
RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
|
||||
;
|
||||
}
|
||||
|
||||
return rtc_sleep_finish(lslp_mem_inf_fpu);
|
||||
}
|
||||
|
||||
#define STR2(X) #X
|
||||
#define STR(X) STR2(X)
|
||||
|
||||
uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
|
||||
WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
|
||||
|
||||
/* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep
|
||||
|
||||
Because we may be running from RTC memory as stack, we can't easily call any
|
||||
functions to do this (as registers will spill to stack, corrupting the CRC).
|
||||
|
||||
Instead, load all the values we need into registers then use register ops only to calculate
|
||||
the CRC value, write it to the RTC CRC value register, and immediately go into deep sleep.
|
||||
*/
|
||||
|
||||
/* Values used to set the SYSTEM_RTC_FASTMEM_CONFIG_REG value */
|
||||
const unsigned CRC_START_ADDR = 0;
|
||||
const unsigned CRC_LEN = 0x7ff;
|
||||
|
||||
asm volatile(
|
||||
/* Start CRC calculation */
|
||||
"sw %1, 0(%0)\n" // set RTC_MEM_CRC_ADDR & RTC_MEM_CRC_LEN
|
||||
"or t0, %1, %2\n"
|
||||
"sw t0, 0(%0)\n" // set RTC_MEM_CRC_START
|
||||
|
||||
/* Wait for the CRC calculation to finish */
|
||||
".Lwaitcrc:\n"
|
||||
"fence\n"
|
||||
"lw t0, 0(%0)\n"
|
||||
"li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n"
|
||||
"and t0, t0, t1\n"
|
||||
"beqz t0, .Lwaitcrc\n"
|
||||
"not %2, %2\n" // %2 -> ~DPORT_RTC_MEM_CRC_START
|
||||
"and t0, t0, %2\n"
|
||||
"sw t0, 0(%0)\n" // clear RTC_MEM_CRC_START
|
||||
"fence\n"
|
||||
"not %2, %2\n" // %2 -> DPORT_RTC_MEM_CRC_START, probably unnecessary but gcc assumes inputs unchanged
|
||||
|
||||
/* Store the calculated value in RTC_MEM_CRC_REG */
|
||||
"lw t0, 0(%3)\n"
|
||||
"sw t0, 0(%4)\n"
|
||||
"fence\n"
|
||||
|
||||
/* Set register bit to go into deep sleep */
|
||||
"lw t0, 0(%5)\n"
|
||||
"or t0, t0, %6\n"
|
||||
"sw t0, 0(%5)\n"
|
||||
"fence\n"
|
||||
|
||||
/* Wait for sleep reject interrupt (never finishes if successful) */
|
||||
".Lwaitsleep:"
|
||||
"fence\n"
|
||||
"lw t0, 0(%7)\n"
|
||||
"and t0, t0, %8\n"
|
||||
"beqz t0, .Lwaitsleep\n"
|
||||
|
||||
:
|
||||
:
|
||||
"r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), // %0
|
||||
"r" ( (CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S)
|
||||
| (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), // %1
|
||||
"r" (SYSTEM_RTC_MEM_CRC_START), // %2
|
||||
"r" (SYSTEM_RTC_FASTMEM_CRC_REG), // %3
|
||||
"r" (RTC_MEMORY_CRC_REG), // %4
|
||||
"r" (RTC_CNTL_STATE0_REG), // %5
|
||||
"r" (RTC_CNTL_SLEEP_EN), // %6
|
||||
"r" (RTC_CNTL_INT_RAW_REG), // %7
|
||||
"r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
|
||||
: "t0", "t1" // working registers
|
||||
);
|
||||
|
||||
return rtc_sleep_finish(0);
|
||||
}
|
||||
|
||||
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
|
||||
{
|
||||
/* In deep sleep mode, we never get here */
|
||||
uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
|
||||
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
|
||||
|
||||
/* restore config if it is a light sleep */
|
||||
if (lslp_mem_inf_fpu) {
|
||||
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
|
||||
rtc_sleep_pu(pu_cfg);
|
||||
}
|
||||
return reject;
|
||||
}
|
||||
@@ -1,184 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp32h4/rom/ets_sys.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "hal/rtc_cntl_ll.h"
|
||||
#include "soc/timer_group_reg.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
|
||||
* This feature counts the number of XTAL clock cycles within a given number of
|
||||
* RTC_SLOW_CLK cycles.
|
||||
*
|
||||
* Slow clock calibration feature has two modes of operation: one-off and cycling.
|
||||
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
|
||||
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
|
||||
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
|
||||
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
|
||||
* enabled using TIMG_RTC_CALI_START bit.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
|
||||
* @param cal_clk which clock to calibrate
|
||||
* @param slowclk_cycles number of slow clock cycles to count
|
||||
* @return number of XTAL clock cycles within the given number of slow clock cycles
|
||||
*/
|
||||
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
/* On ESP32H4, choosing RTC_CAL_RTC_MUX results in calibration of
|
||||
* the 150k RTC clock regardless of the currenlty selected SLOW_CLK.
|
||||
* On the ESP32, it used the currently selected SLOW_CLK.
|
||||
* The following code emulates ESP32 behavior:
|
||||
*/
|
||||
if (cal_clk == RTC_CAL_RTC_MUX) {
|
||||
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
|
||||
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
cal_clk = RTC_CAL_32K_XTAL;
|
||||
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
|
||||
cal_clk = RTC_CAL_RC32K;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable requested clock (150k clock is always on) */
|
||||
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
|
||||
clk_ll_xtal32k_digi_enable();
|
||||
}
|
||||
bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
|
||||
if (cal_clk == RTC_CAL_RC32K && !dig_rc32k_enabled) {
|
||||
clk_ll_rc32k_digi_enable();
|
||||
}
|
||||
/* There may be another calibration process already running during we call this function,
|
||||
* so we should wait the last process is done.
|
||||
*/
|
||||
if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
|
||||
/**
|
||||
* Set a small timeout threshold to accelerate the generation of timeout.
|
||||
* The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
|
||||
*/
|
||||
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
|
||||
while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
|
||||
&& !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
|
||||
}
|
||||
|
||||
/* Prepare calibration */
|
||||
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
|
||||
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
|
||||
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
|
||||
/* Figure out how long to wait for calibration to finish */
|
||||
|
||||
/* Set timeout reg and expect time delay*/
|
||||
uint32_t expected_freq;
|
||||
if (cal_clk == RTC_CAL_32K_XTAL) {
|
||||
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
|
||||
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
|
||||
} else if (cal_clk == RTC_CAL_RC32K) {
|
||||
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(slowclk_cycles));
|
||||
expected_freq = SOC_CLK_RC32K_FREQ_APPROX;
|
||||
} else {
|
||||
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
|
||||
expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
|
||||
}
|
||||
uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
|
||||
/* Start calibration */
|
||||
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
|
||||
SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
|
||||
|
||||
/* Wait for calibration to finish up to another us_time_estimate */
|
||||
esp_rom_delay_us(us_time_estimate * 3);
|
||||
uint32_t cal_val;
|
||||
while (true) {
|
||||
if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
|
||||
cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
|
||||
break;
|
||||
}
|
||||
if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
|
||||
cal_val = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
|
||||
|
||||
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
|
||||
clk_ll_xtal32k_digi_disable();
|
||||
}
|
||||
/* if dig_rc32k was originally off and enabled due to calibration, then set back to off state */
|
||||
if (cal_clk == RTC_CAL_RC32K && !dig_rc32k_enabled) {
|
||||
clk_ll_rc32k_digi_disable();
|
||||
}
|
||||
|
||||
return cal_val;
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
|
||||
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
|
||||
return ratio;
|
||||
}
|
||||
|
||||
static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
|
||||
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
|
||||
uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
|
||||
uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
|
||||
return period;
|
||||
}
|
||||
|
||||
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
|
||||
{
|
||||
/* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
|
||||
* TODO: fix overflow.
|
||||
*/
|
||||
return (time_in_us << RTC_CLK_CAL_FRACT) / period;
|
||||
}
|
||||
|
||||
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
|
||||
{
|
||||
return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
|
||||
}
|
||||
|
||||
uint64_t rtc_time_get(void)
|
||||
{
|
||||
return rtc_cntl_ll_get_rtc_time();
|
||||
}
|
||||
|
||||
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
|
||||
while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
|
||||
esp_rom_delay_us(1);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
|
||||
{
|
||||
if (cal_val == 0) {
|
||||
return 0; // cal_val will be denominator, return 0 as the symbol of failure.
|
||||
}
|
||||
return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
|
||||
}
|
||||
@@ -1,110 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* SAR related peripherals are interdependent. This file
|
||||
* provides a united control to these registers, as multiple
|
||||
* components require these controls.
|
||||
*
|
||||
* Related peripherals are:
|
||||
* - ADC
|
||||
* - PWDET
|
||||
*/
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "esp_private/sar_periph_ctrl.h"
|
||||
#include "hal/sar_ctrl_ll.h"
|
||||
|
||||
static const char *TAG = "sar_periph_ctrl";
|
||||
extern portMUX_TYPE rtc_spinlock;
|
||||
|
||||
|
||||
void sar_periph_ctrl_init(void)
|
||||
{
|
||||
//TODO: IDF-6123
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_power_enable(void)
|
||||
{
|
||||
//TODO: IDF-6123
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_power_disable(void)
|
||||
{
|
||||
//TODO: IDF-6123
|
||||
}
|
||||
|
||||
/**
|
||||
* This gets incremented when s_sar_power_acquire() is called,
|
||||
* and decremented when s_sar_power_release() is called.
|
||||
* PWDET is powered down when the value reaches zero.
|
||||
* Should be modified within critical section.
|
||||
*/
|
||||
static int s_pwdet_power_on_cnt;
|
||||
|
||||
static void s_sar_power_acquire(void)
|
||||
{
|
||||
portENTER_CRITICAL_SAFE(&rtc_spinlock);
|
||||
s_pwdet_power_on_cnt++;
|
||||
if (s_pwdet_power_on_cnt == 1) {
|
||||
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
|
||||
}
|
||||
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
}
|
||||
|
||||
static void s_sar_power_release(void)
|
||||
{
|
||||
portENTER_CRITICAL_SAFE(&rtc_spinlock);
|
||||
s_pwdet_power_on_cnt--;
|
||||
if (s_pwdet_power_on_cnt < 0) {
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
|
||||
abort();
|
||||
} else if (s_pwdet_power_on_cnt == 0) {
|
||||
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
|
||||
}
|
||||
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* PWDET Power
|
||||
*----------------------------------------------------------------------------*/
|
||||
void sar_periph_ctrl_pwdet_power_acquire(void)
|
||||
{
|
||||
s_sar_power_acquire();
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_pwdet_power_release(void)
|
||||
{
|
||||
s_sar_power_release();
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* ADC Power
|
||||
*----------------------------------------------------------------------------*/
|
||||
void sar_periph_ctrl_adc_oneshot_power_acquire(void)
|
||||
{
|
||||
s_sar_power_acquire();
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_adc_oneshot_power_release(void)
|
||||
{
|
||||
s_sar_power_release();
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_adc_continuous_power_acquire(void)
|
||||
{
|
||||
s_sar_power_acquire();
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_adc_continuous_power_release(void)
|
||||
{
|
||||
s_sar_power_release();
|
||||
}
|
||||
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "esp_private/systimer.h"
|
||||
|
||||
/**
|
||||
* @brief systimer's clock source is fixed to XTAL (32MHz), and has a fixed fractional divider (2.0).
|
||||
* So the resolution of the systimer is 32MHz/2.0 = 16MHz.
|
||||
*/
|
||||
|
||||
uint64_t systimer_ticks_to_us(uint64_t ticks)
|
||||
{
|
||||
return ticks / 16;
|
||||
}
|
||||
|
||||
uint64_t systimer_us_to_ticks(uint64_t us)
|
||||
{
|
||||
return us * 16;
|
||||
}
|
||||
@@ -76,8 +76,6 @@
|
||||
#include "esp_private/mspi_timing_tuning.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#include "esp32c3/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
@@ -115,9 +113,6 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (105)
|
||||
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37)
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (105)
|
||||
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37)
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)
|
||||
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
|
||||
|
||||
@@ -41,8 +41,6 @@
|
||||
#include "esp32s3/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#include "esp32c3/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
|
||||
@@ -40,9 +40,6 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#include "esp32c3/rtc.h"
|
||||
#include "esp32c3/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rtc.h"
|
||||
#include "esp32h4/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rtc.h"
|
||||
#include "esp32c2/rom/rtc.h"
|
||||
|
||||
@@ -1,25 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "../ext_mem_layout.h"
|
||||
|
||||
/**
|
||||
* The start addresses in this list should always be sorted from low to high, as MMU driver will need to
|
||||
* coalesce adjacent regions
|
||||
*/
|
||||
const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
|
||||
[0] = {
|
||||
.start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
|
||||
.end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
|
||||
.size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
|
||||
.bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
|
||||
.targets = MMU_TARGET_FLASH0,
|
||||
.caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
|
||||
},
|
||||
};
|
||||
@@ -47,16 +47,7 @@ idf_component_register(SRCS "${srcs}"
|
||||
)
|
||||
|
||||
set(target_name "${idf_target}")
|
||||
if(IDF_TARGET STREQUAL "esp32h4")
|
||||
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2)
|
||||
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h4/rev2")
|
||||
endif()
|
||||
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1)
|
||||
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h4/rev1")
|
||||
endif()
|
||||
else()
|
||||
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}")
|
||||
endif()
|
||||
target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}")
|
||||
|
||||
# Override functions in PHY lib with the functions in 'phy_override.c'
|
||||
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u include_esp_phy_override")
|
||||
|
||||
@@ -54,10 +54,10 @@ void esp_phy_enable(void)
|
||||
s_phy_access_ref++;
|
||||
|
||||
_lock_release(&s_phy_access_lock);
|
||||
// ESP32H4-TODO: enable common clk.
|
||||
// ESP32H2-TODO: enable common clk.
|
||||
}
|
||||
|
||||
void esp_phy_disable(void)
|
||||
{
|
||||
// ESP32H4-TODO: close rf and disable clk for modem sleep and light sleep
|
||||
// ESP32H2-TODO: close rf and disable clk for modem sleep and light sleep
|
||||
}
|
||||
|
||||
@@ -1,13 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#pragma once
|
||||
|
||||
#warning "esp_pm_config_esp32h4_t is deprecated, please include esp_pm.h and use esp_pm_config_t instead"
|
||||
|
||||
/* backward compatibility */
|
||||
#include "esp_pm.h"
|
||||
@@ -33,7 +33,6 @@ typedef esp_pm_config_t esp_pm_config_esp32_t __attribute__((deprecated("pleas
|
||||
typedef esp_pm_config_t esp_pm_config_esp32s2_t __attribute__((deprecated("please use esp_pm_config_t instead")));
|
||||
typedef esp_pm_config_t esp_pm_config_esp32s3_t __attribute__((deprecated("please use esp_pm_config_t instead")));
|
||||
typedef esp_pm_config_t esp_pm_config_esp32c3_t __attribute__((deprecated("please use esp_pm_config_t instead")));
|
||||
typedef esp_pm_config_t esp_pm_config_esp32h4_t __attribute__((deprecated("please use esp_pm_config_t instead")));
|
||||
typedef esp_pm_config_t esp_pm_config_esp32c2_t __attribute__((deprecated("please use esp_pm_config_t instead")));
|
||||
typedef esp_pm_config_t esp_pm_config_esp32c6_t __attribute__((deprecated("please use esp_pm_config_t instead")));
|
||||
|
||||
|
||||
@@ -73,8 +73,6 @@
|
||||
#define REF_CLK_DIV_MIN 2 // TODO: IDF-5660
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
* Feel free to change when debugging.
|
||||
*/
|
||||
static const int DRAM_ATTR s_trace_io[] = {
|
||||
#if !defined(CONFIG_IDF_TARGET_ESP32C3) && !defined(CONFIG_IDF_TARGET_ESP32H4) && !defined(CONFIG_IDF_TARGET_ESP32C2)
|
||||
#if !defined(CONFIG_IDF_TARGET_ESP32C3) && !defined(CONFIG_IDF_TARGET_ESP32C2)
|
||||
BIT(4), BIT(5), // ESP_PM_TRACE_IDLE
|
||||
BIT(16), BIT(17), // ESP_PM_TRACE_TICK
|
||||
BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH
|
||||
|
||||
@@ -67,8 +67,6 @@ static const int test_freqs[] = {40, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, 40, 80
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
static const int test_freqs[] = {CONFIG_XTAL_FREQ, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, CONFIG_XTAL_FREQ, 80,
|
||||
CONFIG_XTAL_FREQ / 2, CONFIG_XTAL_FREQ}; // C2 xtal has 40/26MHz option
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
static const int test_freqs[] = {32, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 32} // TODO: IDF-3786
|
||||
#else
|
||||
static const int test_freqs[] = {240, 40, 160, 240, 80, 40, 240, 40, 80, 10, 80, 20, 40};
|
||||
#endif
|
||||
|
||||
@@ -51,15 +51,7 @@ idf_component_register(SRCS ${sources}
|
||||
PRIV_REQUIRES ${private_required_comp}
|
||||
LDFRAGMENTS linker.lf)
|
||||
|
||||
if(target STREQUAL "esp32h4")
|
||||
if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1)
|
||||
set(ld_folder "ld/rev1")
|
||||
elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2)
|
||||
set(ld_folder "ld/rev2")
|
||||
endif()
|
||||
else()
|
||||
set(ld_folder "ld")
|
||||
endif()
|
||||
set(ld_folder "ld")
|
||||
|
||||
# Append a target linker script at the target-specific path,
|
||||
# only the 'name' part is different for each script
|
||||
@@ -108,9 +100,6 @@ if(BOOTLOADER_BUILD)
|
||||
elseif(target STREQUAL "esp32c3")
|
||||
rom_linker_script("newlib")
|
||||
|
||||
elseif(target STREQUAL "esp32h4")
|
||||
rom_linker_script("newlib")
|
||||
|
||||
elseif(target STREQUAL "esp32c2")
|
||||
rom_linker_script("newlib")
|
||||
rom_linker_script("mbedtls")
|
||||
@@ -215,16 +204,6 @@ else() # Regular app build
|
||||
rom_linker_script("eco3")
|
||||
endif()
|
||||
|
||||
elseif(target STREQUAL "esp32h4")
|
||||
rom_linker_script("newlib")
|
||||
rom_linker_script("version")
|
||||
|
||||
if(CONFIG_NEWLIB_NANO_FORMAT AND time_t_size EQUAL 4)
|
||||
# nano formatting functions in ROM are built for 32-bit time_t,
|
||||
# only link them if the toolchain is also using 32-bit time_t and nano formatting was requested.
|
||||
rom_linker_script("newlib-nano")
|
||||
endif()
|
||||
|
||||
elseif(target STREQUAL "esp32c2")
|
||||
rom_linker_script("newlib")
|
||||
rom_linker_script("version")
|
||||
|
||||
@@ -17,8 +17,6 @@ When using ROM functions in esp-idf, the including convention is `<target>/rom/<
|
||||
#include "esp32c3/rom/uart.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/uart.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#include "esp32h4/rom/uart.h"
|
||||
...
|
||||
```
|
||||
|
||||
|
||||
@@ -1,60 +0,0 @@
|
||||
#####################################################
|
||||
# This file is auto-generated from SoC caps
|
||||
# using gen_soc_caps_kconfig.py, do not edit manually
|
||||
#####################################################
|
||||
|
||||
config ESP_ROM_HAS_CRC_LE
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_CRC_BE
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_MZ_CRC32
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_JPEG_DECODE
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_UART_CLK_IS_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_USB_SERIAL_DEVICE_NUM
|
||||
int
|
||||
default 3
|
||||
|
||||
config ESP_ROM_HAS_RETARGETABLE_LOCKING
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_ERASE_0_REGION_BUG
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_GET_CLK_FREQ
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_LAYOUT_TABLE
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_ETS_PRINTF_BUG
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
|
||||
bool
|
||||
default y
|
||||
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian
|
||||
#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian
|
||||
#define ESP_ROM_HAS_MZ_CRC32 (1) // ROM has mz_crc32 function
|
||||
#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library
|
||||
#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM
|
||||
#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM.
|
||||
#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking
|
||||
#define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug
|
||||
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
|
||||
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
|
||||
#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
|
||||
#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions
|
||||
#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
|
||||
#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
|
||||
@@ -1,62 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** ROM APIs
|
||||
*/
|
||||
PROVIDE ( esp_rom_crc32_le = crc32_le );
|
||||
PROVIDE ( esp_rom_crc16_le = crc16_le );
|
||||
PROVIDE ( esp_rom_crc8_le = crc8_le );
|
||||
PROVIDE ( esp_rom_crc32_be = crc32_be );
|
||||
PROVIDE ( esp_rom_crc16_be = crc16_be );
|
||||
PROVIDE ( esp_rom_crc8_be = crc8_be );
|
||||
|
||||
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
|
||||
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
|
||||
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
|
||||
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
|
||||
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
|
||||
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
|
||||
|
||||
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
|
||||
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
|
||||
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
|
||||
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
|
||||
|
||||
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
|
||||
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
|
||||
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
|
||||
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
|
||||
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
|
||||
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
|
||||
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
|
||||
|
||||
PROVIDE ( esp_rom_md5_init = MD5Init );
|
||||
PROVIDE ( esp_rom_md5_update = MD5Update );
|
||||
PROVIDE ( esp_rom_md5_final = MD5Final );
|
||||
|
||||
PROVIDE ( esp_rom_software_reset_system = software_reset );
|
||||
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
|
||||
|
||||
PROVIDE ( esp_rom_printf = ets_printf );
|
||||
PROVIDE ( esp_rom_delay_us = ets_delay_us );
|
||||
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
|
||||
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
|
||||
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
|
||||
|
||||
PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
|
||||
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
|
||||
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
|
||||
PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
|
||||
|
||||
PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
|
||||
PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
|
||||
PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
|
||||
PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );
|
||||
|
||||
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
|
||||
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
|
||||
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
|
||||
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );
|
||||
@@ -1,723 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* ROM function interface esp32b1z.rom.ld for esp32b1z
|
||||
*
|
||||
*
|
||||
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group common
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
rtc_get_reset_reason = 0x40000018;
|
||||
analog_super_wdt_reset_happened = 0x4000001c;
|
||||
jtag_cpu_reset_happened = 0x40000020;
|
||||
rtc_get_wakeup_cause = 0x40000024;
|
||||
rtc_select_apb_bridge = 0x40000028;
|
||||
rtc_unhold_all_pads = 0x4000002c;
|
||||
ets_is_print_boot = 0x40000030;
|
||||
ets_printf = 0x40000034;
|
||||
ets_install_putc1 = 0x40000038;
|
||||
ets_install_uart_printf = 0x4000003c;
|
||||
ets_install_putc2 = 0x40000040;
|
||||
PROVIDE( ets_delay_us = 0x40000044 );
|
||||
ets_get_stack_info = 0x40000048;
|
||||
ets_install_lock = 0x4000004c;
|
||||
ets_backup_dma_copy = 0x40000050;
|
||||
ets_apb_backup_init_lock_func = 0x40000054;
|
||||
UartRxString = 0x40000058;
|
||||
uart_tx_one_char = 0x4000005c;
|
||||
uart_tx_one_char2 = 0x40000060;
|
||||
uart_rx_one_char = 0x40000064;
|
||||
uart_rx_one_char_block = 0x40000068;
|
||||
uart_rx_readbuff = 0x4000006c;
|
||||
uartAttach = 0x40000070;
|
||||
uart_tx_flush = 0x40000074;
|
||||
uart_tx_wait_idle = 0x40000078;
|
||||
uart_div_modify = 0x4000007c;
|
||||
multofup = 0x40000080;
|
||||
software_reset = 0x40000084;
|
||||
software_reset_cpu = 0x40000088;
|
||||
assist_debug_clock_enable = 0x4000008c;
|
||||
assist_debug_record_enable = 0x40000090;
|
||||
clear_super_wdt_reset_flag = 0x40000094;
|
||||
disable_default_watchdog = 0x40000098;
|
||||
esp_rom_set_rtc_wake_addr = 0x4000009c;
|
||||
esp_rom_get_rtc_wake_addr = 0x400000a0;
|
||||
send_packet = 0x400000a4;
|
||||
recv_packet = 0x400000a8;
|
||||
GetUartDevice = 0x400000ac;
|
||||
UartDwnLdProc = 0x400000b0;
|
||||
Uart_Init = 0x400000b4;
|
||||
ets_set_user_start = 0x400000b8;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
ets_rom_layout_p = 0x3ff1fffc;
|
||||
ets_ops_table_ptr = 0x3fcdfffc;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group miniz
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
mz_adler32 = 0x400000bc;
|
||||
mz_crc32 = 0x400000c0;
|
||||
mz_free = 0x400000c4;
|
||||
tdefl_compress = 0x400000c8;
|
||||
tdefl_compress_buffer = 0x400000cc;
|
||||
tdefl_compress_mem_to_heap = 0x400000d0;
|
||||
tdefl_compress_mem_to_mem = 0x400000d4;
|
||||
tdefl_compress_mem_to_output = 0x400000d8;
|
||||
tdefl_get_adler32 = 0x400000dc;
|
||||
tdefl_get_prev_return_status = 0x400000e0;
|
||||
tdefl_init = 0x400000e4;
|
||||
tdefl_write_image_to_png_file_in_memory = 0x400000e8;
|
||||
tdefl_write_image_to_png_file_in_memory_ex = 0x400000ec;
|
||||
tinfl_decompress = 0x400000f0;
|
||||
tinfl_decompress_mem_to_callback = 0x400000f4;
|
||||
tinfl_decompress_mem_to_heap = 0x400000f8;
|
||||
tinfl_decompress_mem_to_mem = 0x400000fc;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group tjpgd
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( jd_prepare = 0x40000100 );
|
||||
PROVIDE( jd_decomp = 0x40000104 );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group esp-dsp
|
||||
***************************************/
|
||||
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
dsps_fft2r_w_table_fc32_1024 = 0x3fcdfff8;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group spiflash_legacy
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( esp_rom_spiflash_wait_idle = 0x40000108 );
|
||||
PROVIDE( esp_rom_spiflash_write_encrypted = 0x4000010c );
|
||||
PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000110 );
|
||||
PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000114 );
|
||||
PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000118 );
|
||||
PROVIDE( esp_rom_spiflash_erase_chip = 0x4000011c );
|
||||
PROVIDE( esp_rom_spiflash_erase_block = 0x40000120 );
|
||||
PROVIDE( esp_rom_spiflash_erase_sector = 0x40000124 );
|
||||
PROVIDE( esp_rom_spiflash_write = 0x40000128 );
|
||||
PROVIDE( esp_rom_spiflash_read = 0x4000012c );
|
||||
PROVIDE( esp_rom_spiflash_config_param = 0x40000130 );
|
||||
PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000134 );
|
||||
PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000138 );
|
||||
PROVIDE( esp_rom_spiflash_unlock = 0x4000013c );
|
||||
PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000140 );
|
||||
PROVIDE( esp_rom_spi_flash_send_resume = 0x40000144 );
|
||||
PROVIDE( esp_rom_spi_flash_update_id = 0x40000148 );
|
||||
PROVIDE( esp_rom_spiflash_config_clk = 0x4000014c );
|
||||
PROVIDE( esp_rom_spiflash_config_readmode = 0x40000150 );
|
||||
PROVIDE( esp_rom_spiflash_read_status = 0x40000154 );
|
||||
PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000158 );
|
||||
PROVIDE( esp_rom_spiflash_write_status = 0x4000015c );
|
||||
PROVIDE( spi_flash_attach = 0x40000160 );
|
||||
PROVIDE( spi_flash_get_chip_size = 0x40000164 );
|
||||
PROVIDE( spi_flash_guard_set = 0x40000168 );
|
||||
PROVIDE( spi_flash_guard_get = 0x4000016c );
|
||||
PROVIDE( spi_flash_write_config_set = 0x40000170 );
|
||||
PROVIDE( spi_flash_write_config_get = 0x40000174 );
|
||||
PROVIDE( spi_flash_safe_write_address_func_set = 0x40000178 );
|
||||
PROVIDE( spi_flash_unlock = 0x4000017c );
|
||||
PROVIDE( spi_flash_erase_range = 0x40000180 );
|
||||
PROVIDE( spi_flash_erase_sector = 0x40000184 );
|
||||
PROVIDE( spi_flash_write = 0x40000188 );
|
||||
PROVIDE( spi_flash_read = 0x4000018c );
|
||||
PROVIDE( spi_flash_write_encrypted = 0x40000190 );
|
||||
PROVIDE( spi_flash_read_encrypted = 0x40000194 );
|
||||
PROVIDE( spi_flash_mmap_os_func_set = 0x40000198 );
|
||||
PROVIDE( spi_flash_mmap_page_num_init = 0x4000019c );
|
||||
PROVIDE( spi_flash_mmap = 0x400001a0 );
|
||||
PROVIDE( spi_flash_mmap_pages = 0x400001a4 );
|
||||
PROVIDE( spi_flash_munmap = 0x400001a8 );
|
||||
PROVIDE( spi_flash_mmap_dump = 0x400001ac );
|
||||
PROVIDE( spi_flash_check_and_flush_cache = 0x400001b0 );
|
||||
PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b4 );
|
||||
PROVIDE( spi_flash_cache2phys = 0x400001b8 );
|
||||
PROVIDE( spi_flash_phys2cache = 0x400001bc );
|
||||
PROVIDE( spi_flash_disable_cache = 0x400001c0 );
|
||||
PROVIDE( spi_flash_restore_cache = 0x400001c4 );
|
||||
PROVIDE( spi_flash_cache_enabled = 0x400001c8 );
|
||||
PROVIDE( spi_flash_enable_cache = 0x400001cc );
|
||||
PROVIDE( spi_cache_mode_switch = 0x400001d0 );
|
||||
PROVIDE( spi_common_set_dummy_output = 0x400001d4 );
|
||||
PROVIDE( spi_common_set_flash_cs_timing = 0x400001d8 );
|
||||
PROVIDE( esp_enable_cache_flash_wrap = 0x400001dc );
|
||||
PROVIDE( SPIEraseArea = 0x400001e0 );
|
||||
PROVIDE( SPILock = 0x400001e4 );
|
||||
PROVIDE( SPIMasterReadModeCnfig = 0x400001e8 );
|
||||
PROVIDE( SPI_Common_Command = 0x400001ec );
|
||||
PROVIDE( SPI_WakeUp = 0x400001f0 );
|
||||
PROVIDE( SPI_block_erase = 0x400001f4 );
|
||||
PROVIDE( SPI_chip_erase = 0x400001f8 );
|
||||
PROVIDE( SPI_init = 0x400001fc );
|
||||
PROVIDE( SPI_page_program = 0x40000200 );
|
||||
PROVIDE( SPI_read_data = 0x40000204 );
|
||||
PROVIDE( SPI_sector_erase = 0x40000208 );
|
||||
PROVIDE( SPI_write_enable = 0x4000020c );
|
||||
PROVIDE( SelectSpiFunction = 0x40000210 );
|
||||
PROVIDE( SetSpiDrvs = 0x40000214 );
|
||||
PROVIDE( Wait_SPI_Idle = 0x40000218 );
|
||||
PROVIDE( spi_dummy_len_fix = 0x4000021c );
|
||||
PROVIDE( Disable_QMode = 0x40000220 );
|
||||
PROVIDE( Enable_QMode = 0x40000224 );
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 );
|
||||
PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec );
|
||||
PROVIDE( g_flash_guard_ops = 0x3fcdfff4 );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group hal_soc
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 );
|
||||
PROVIDE( spi_flash_hal_device_config = 0x4000022c );
|
||||
PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 );
|
||||
PROVIDE( spi_flash_hal_common_command = 0x40000234 );
|
||||
PROVIDE( spi_flash_hal_read = 0x40000238 );
|
||||
PROVIDE( spi_flash_hal_erase_chip = 0x4000023c );
|
||||
PROVIDE( spi_flash_hal_erase_sector = 0x40000240 );
|
||||
PROVIDE( spi_flash_hal_erase_block = 0x40000244 );
|
||||
PROVIDE( spi_flash_hal_program_page = 0x40000248 );
|
||||
PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c );
|
||||
PROVIDE( spi_flash_hal_host_idle = 0x40000250 );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group spi_flash_chips
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( spi_flash_chip_generic_probe = 0x40000254 );
|
||||
PROVIDE( spi_flash_chip_generic_detect_size = 0x40000258 );
|
||||
PROVIDE( spi_flash_chip_generic_write = 0x4000025c );
|
||||
PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000260 );
|
||||
PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000264 );
|
||||
PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000268 );
|
||||
PROVIDE( spi_flash_chip_generic_reset = 0x4000026c );
|
||||
PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000270 );
|
||||
PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000274 );
|
||||
PROVIDE( spi_flash_chip_generic_erase_block = 0x40000278 );
|
||||
PROVIDE( spi_flash_chip_generic_page_program = 0x4000027c );
|
||||
PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000280 );
|
||||
PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000284 );
|
||||
PROVIDE( spi_flash_chip_generic_read_reg = 0x40000288 );
|
||||
PROVIDE( spi_flash_chip_generic_yield = 0x4000028c );
|
||||
PROVIDE( spi_flash_generic_wait_host_idle = 0x40000290 );
|
||||
PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000294 );
|
||||
PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x40000298 );
|
||||
PROVIDE( spi_flash_chip_generic_read = 0x4000029c );
|
||||
PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a0 );
|
||||
PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a4 );
|
||||
PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002a8 );
|
||||
PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002ac );
|
||||
PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b0 );
|
||||
PROVIDE( spi_flash_common_set_io_mode = 0x400002b4 );
|
||||
PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002b8 );
|
||||
PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002bc );
|
||||
PROVIDE( spi_flash_chip_gd_probe = 0x400002c0 );
|
||||
PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c4 );
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group memspi_host
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( memspi_host_read_id_hs = 0x400002c8 );
|
||||
PROVIDE( memspi_host_read_status_hs = 0x400002cc );
|
||||
PROVIDE( memspi_host_flush_cache = 0x400002d0 );
|
||||
PROVIDE( memspi_host_erase_chip = 0x400002d4 );
|
||||
PROVIDE( memspi_host_erase_sector = 0x400002d8 );
|
||||
PROVIDE( memspi_host_erase_block = 0x400002dc );
|
||||
PROVIDE( memspi_host_program_page = 0x400002e0 );
|
||||
PROVIDE( memspi_host_read = 0x400002e4 );
|
||||
PROVIDE( memspi_host_set_write_protect = 0x400002e8 );
|
||||
PROVIDE( memspi_host_set_max_read_len = 0x400002ec );
|
||||
PROVIDE( memspi_host_read_data_slicer = 0x400002f0 );
|
||||
PROVIDE( memspi_host_write_data_slicer = 0x400002f4 );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group esp_flash
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( esp_flash_chip_driver_initialized = 0x400002f8 );
|
||||
PROVIDE( esp_flash_read_id = 0x400002fc );
|
||||
PROVIDE( esp_flash_get_size = 0x40000300 );
|
||||
PROVIDE( esp_flash_erase_chip = 0x40000304 );
|
||||
PROVIDE( rom_esp_flash_erase_region = 0x40000308 );
|
||||
PROVIDE( esp_flash_get_chip_write_protect = 0x4000030c );
|
||||
PROVIDE( esp_flash_set_chip_write_protect = 0x40000310 );
|
||||
PROVIDE( esp_flash_get_protectable_regions = 0x40000314 );
|
||||
PROVIDE( esp_flash_get_protected_region = 0x40000318 );
|
||||
PROVIDE( esp_flash_set_protected_region = 0x4000031c );
|
||||
PROVIDE( esp_flash_read = 0x40000320 );
|
||||
PROVIDE( esp_flash_write = 0x40000324 );
|
||||
PROVIDE( esp_flash_write_encrypted = 0x40000328 );
|
||||
PROVIDE( esp_flash_read_encrypted = 0x4000032c );
|
||||
PROVIDE( esp_flash_get_io_mode = 0x40000330 );
|
||||
PROVIDE( esp_flash_set_io_mode = 0x40000334 );
|
||||
PROVIDE( spi_flash_boot_attach = 0x40000338 );
|
||||
PROVIDE( spi_flash_dump_counters = 0x4000033c );
|
||||
PROVIDE( spi_flash_get_counters = 0x40000340 );
|
||||
PROVIDE( spi_flash_op_counters_config = 0x40000344 );
|
||||
PROVIDE( spi_flash_reset_counters = 0x40000348 );
|
||||
PROVIDE( esp_flash_read_chip_id = 0x4000034c );
|
||||
PROVIDE( detect_spi_flash_chip = 0x40000350 );
|
||||
PROVIDE( esp_rom_spiflash_write_disable = 0x40000354 );
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
PROVIDE( esp_flash_default_chip = 0x3fcdffe4 );
|
||||
PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group cache
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( Cache_Get_ICache_Line_Size = 0x400004b8 );
|
||||
PROVIDE( Cache_Get_Mode = 0x400004bc );
|
||||
PROVIDE( Cache_Address_Through_IBus = 0x400004c0 );
|
||||
PROVIDE( Cache_Address_Through_DBus = 0x400004c4 );
|
||||
PROVIDE( Cache_Set_Default_Mode = 0x400004c8 );
|
||||
PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004cc );
|
||||
PROVIDE( ROM_Boot_Cache_Init = 0x400004d0 );
|
||||
PROVIDE( Cache_Invalidate_ICache_Items = 0x400004d4 );
|
||||
PROVIDE( Cache_Op_Addr = 0x400004d8 );
|
||||
PROVIDE( Cache_Invalidate_Addr = 0x400004dc );
|
||||
PROVIDE( Cache_Invalidate_ICache_All = 0x400004e0 );
|
||||
PROVIDE( Cache_Mask_All = 0x400004e4 );
|
||||
PROVIDE( Cache_UnMask_Dram0 = 0x400004e8 );
|
||||
PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004ec );
|
||||
PROVIDE( Cache_Resume_ICache_Autoload = 0x400004f0 );
|
||||
PROVIDE( Cache_Start_ICache_Preload = 0x400004f4 );
|
||||
PROVIDE( Cache_ICache_Preload_Done = 0x400004f8 );
|
||||
PROVIDE( Cache_End_ICache_Preload = 0x400004fc );
|
||||
PROVIDE( Cache_Config_ICache_Autoload = 0x40000500 );
|
||||
PROVIDE( Cache_Enable_ICache_Autoload = 0x40000504 );
|
||||
PROVIDE( Cache_Disable_ICache_Autoload = 0x40000508 );
|
||||
PROVIDE( Cache_Enable_ICache_PreLock = 0x4000050c );
|
||||
PROVIDE( Cache_Disable_ICache_PreLock = 0x40000510 );
|
||||
PROVIDE( Cache_Lock_ICache_Items = 0x40000514 );
|
||||
PROVIDE( Cache_Unlock_ICache_Items = 0x40000518 );
|
||||
PROVIDE( Cache_Lock_Addr = 0x4000051c );
|
||||
PROVIDE( Cache_Unlock_Addr = 0x40000520 );
|
||||
PROVIDE( Cache_Disable_ICache = 0x40000524 );
|
||||
PROVIDE( Cache_Enable_ICache = 0x40000528 );
|
||||
PROVIDE( Cache_Suspend_ICache = 0x4000052c );
|
||||
PROVIDE( Cache_Resume_ICache = 0x40000530 );
|
||||
PROVIDE( Cache_Freeze_ICache_Enable = 0x40000534 );
|
||||
PROVIDE( Cache_Freeze_ICache_Disable = 0x40000538 );
|
||||
PROVIDE( Cache_Pms_Lock = 0x4000053c );
|
||||
PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000540 );
|
||||
PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x40000544 );
|
||||
PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000548 );
|
||||
PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x4000054c );
|
||||
PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000550 );
|
||||
PROVIDE( Cache_Get_IROM_MMU_End = 0x40000554 );
|
||||
PROVIDE( Cache_Get_DROM_MMU_End = 0x40000558 );
|
||||
PROVIDE( Cache_Owner_Init = 0x4000055c );
|
||||
PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000560 );
|
||||
PROVIDE( Cache_MMU_Init = 0x40000564 );
|
||||
PROVIDE( Cache_Ibus_MMU_Set = 0x40000568 );
|
||||
PROVIDE( Cache_Dbus_MMU_Set = 0x4000056c );
|
||||
PROVIDE( Cache_Count_Flash_Pages = 0x40000570 );
|
||||
PROVIDE( Cache_Travel_Tag_Memory = 0x40000574 );
|
||||
PROVIDE( Cache_Get_Virtual_Addr = 0x40000578 );
|
||||
PROVIDE( Cache_Get_Memory_BaseAddr = 0x4000057c );
|
||||
PROVIDE( Cache_Get_Memory_Addr = 0x40000580 );
|
||||
PROVIDE( Cache_Get_Memory_value = 0x40000584 );
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
PROVIDE( rom_cache_op_cb = 0x3fcdffd4 );
|
||||
PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group clock
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ets_get_apb_freq = 0x40000588;
|
||||
ets_get_cpu_frequency = 0x4000058c;
|
||||
ets_update_cpu_frequency = 0x40000590;
|
||||
ets_get_printf_channel = 0x40000594;
|
||||
ets_get_xtal_div = 0x40000598;
|
||||
ets_set_xtal_div = 0x4000059c;
|
||||
ets_get_xtal_freq = 0x400005a0;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group gpio
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
gpio_input_get = 0x400005a4;
|
||||
gpio_matrix_in = 0x400005a8;
|
||||
gpio_matrix_out = 0x400005ac;
|
||||
gpio_output_disable = 0x400005b0;
|
||||
gpio_output_enable = 0x400005b4;
|
||||
gpio_output_set = 0x400005b8;
|
||||
gpio_pad_hold = 0x400005bc;
|
||||
gpio_pad_input_disable = 0x400005c0;
|
||||
gpio_pad_input_enable = 0x400005c4;
|
||||
gpio_pad_pulldown = 0x400005c8;
|
||||
gpio_pad_pullup = 0x400005cc;
|
||||
gpio_pad_select_gpio = 0x400005d0;
|
||||
gpio_pad_set_drv = 0x400005d4;
|
||||
gpio_pad_unhold = 0x400005d8;
|
||||
gpio_pin_wakeup_disable = 0x400005dc;
|
||||
gpio_pin_wakeup_enable = 0x400005e0;
|
||||
gpio_bypass_matrix_in = 0x400005e4;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group interrupts
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esprv_intc_int_set_priority = 0x400005e8;
|
||||
esprv_intc_int_set_threshold = 0x400005ec;
|
||||
esprv_intc_int_enable = 0x400005f0;
|
||||
esprv_intc_int_disable = 0x400005f4;
|
||||
esprv_intc_int_set_type = 0x400005f8;
|
||||
intr_matrix_set = 0x400005fc;
|
||||
ets_intr_lock = 0x40000600;
|
||||
ets_intr_unlock = 0x40000604;
|
||||
PROVIDE( intr_handler_set = 0x40000608 );
|
||||
ets_isr_attach = 0x4000060c;
|
||||
ets_isr_mask = 0x40000610;
|
||||
ets_isr_unmask = 0x40000614;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group crypto
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
md5_vector = 0x40000618;
|
||||
MD5Init = 0x4000061c;
|
||||
MD5Update = 0x40000620;
|
||||
MD5Final = 0x40000624;
|
||||
hmac_md5_vector = 0x40000628;
|
||||
hmac_md5 = 0x4000062c;
|
||||
crc32_le = 0x40000630;
|
||||
crc32_be = 0x40000634;
|
||||
crc16_le = 0x40000638;
|
||||
crc16_be = 0x4000063c;
|
||||
crc8_le = 0x40000640;
|
||||
crc8_be = 0x40000644;
|
||||
esp_crc8 = 0x40000648;
|
||||
ets_sha_enable = 0x4000064c;
|
||||
ets_sha_disable = 0x40000650;
|
||||
ets_sha_get_state = 0x40000654;
|
||||
ets_sha_init = 0x40000658;
|
||||
ets_sha_process = 0x4000065c;
|
||||
ets_sha_starts = 0x40000660;
|
||||
ets_sha_update = 0x40000664;
|
||||
ets_sha_finish = 0x40000668;
|
||||
ets_sha_clone = 0x4000066c;
|
||||
ets_hmac_enable = 0x40000670;
|
||||
ets_hmac_disable = 0x40000674;
|
||||
ets_hmac_calculate_message = 0x40000678;
|
||||
ets_hmac_calculate_downstream = 0x4000067c;
|
||||
ets_hmac_invalidate_downstream = 0x40000680;
|
||||
ets_jtag_enable_temporarily = 0x40000684;
|
||||
ets_aes_enable = 0x40000688;
|
||||
ets_aes_disable = 0x4000068c;
|
||||
ets_aes_setkey = 0x40000690;
|
||||
ets_aes_block = 0x40000694;
|
||||
ets_bigint_enable = 0x40000698;
|
||||
ets_bigint_disable = 0x4000069c;
|
||||
ets_bigint_multiply = 0x400006a0;
|
||||
ets_bigint_modmult = 0x400006a4;
|
||||
ets_bigint_modexp = 0x400006a8;
|
||||
ets_bigint_wait_finish = 0x400006ac;
|
||||
ets_bigint_getz = 0x400006b0;
|
||||
ets_ds_enable = 0x400006b4;
|
||||
ets_ds_disable = 0x400006b8;
|
||||
ets_ds_start_sign = 0x400006bc;
|
||||
ets_ds_is_busy = 0x400006c0;
|
||||
ets_ds_finish_sign = 0x400006c4;
|
||||
ets_ds_encrypt_params = 0x400006c8;
|
||||
ets_aes_setkey_dec = 0x400006cc;
|
||||
ets_aes_setkey_enc = 0x400006d0;
|
||||
ets_mgf1_sha256 = 0x400006d4;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group efuse
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ets_efuse_read = 0x400006d8;
|
||||
ets_efuse_program = 0x400006dc;
|
||||
ets_efuse_clear_program_registers = 0x400006e0;
|
||||
ets_efuse_write_key = 0x400006e4;
|
||||
ets_efuse_get_read_register_address = 0x400006e8;
|
||||
ets_efuse_get_key_purpose = 0x400006ec;
|
||||
ets_efuse_key_block_unused = 0x400006f0;
|
||||
ets_efuse_find_unused_key_block = 0x400006f4;
|
||||
ets_efuse_rs_calculate = 0x400006f8;
|
||||
ets_efuse_count_unused_key_blocks = 0x400006fc;
|
||||
ets_efuse_secure_boot_enabled = 0x40000700;
|
||||
ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000704;
|
||||
ets_efuse_cache_encryption_enabled = 0x40000708;
|
||||
ets_efuse_download_modes_disabled = 0x4000070c;
|
||||
ets_efuse_find_purpose = 0x40000710;
|
||||
ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x40000714;
|
||||
ets_efuse_force_send_resume = 0x40000718;
|
||||
ets_efuse_get_flash_delay_us = 0x4000071c;
|
||||
ets_efuse_get_mac = 0x40000720;
|
||||
ets_efuse_get_spiconfig = 0x40000724;
|
||||
ets_efuse_usb_print_is_disabled = 0x40000728;
|
||||
/*ets_efuse_get_uart_print_channel = 0x4000072c;*/
|
||||
ets_efuse_usb_serial_jtag_print_is_disabled = 0x4000072c;
|
||||
ets_efuse_get_uart_print_control = 0x40000730;
|
||||
ets_efuse_get_wp_pad = 0x40000734;
|
||||
ets_efuse_direct_boot_mode_disabled = 0x40000738;
|
||||
ets_efuse_security_download_modes_enabled = 0x4000073c;
|
||||
ets_efuse_set_timing = 0x40000740;
|
||||
ets_efuse_jtag_disabled = 0x40000744;
|
||||
ets_efuse_usb_download_mode_disabled = 0x40000748;
|
||||
ets_efuse_usb_module_disabled = 0x4000074c;
|
||||
ets_efuse_usb_device_disabled = 0x40000750;
|
||||
ets_efuse_secure_boot_fast_wake_enabled = 0x40000754;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group secureboot
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ets_emsa_pss_verify = 0x40000758;
|
||||
ets_rsa_pss_verify = 0x4000075c;
|
||||
ets_secure_boot_verify_bootloader_with_keys = 0x40000760;
|
||||
ets_secure_boot_verify_signature = 0x40000764;
|
||||
ets_secure_boot_read_key_digests = 0x40000768;
|
||||
ets_secure_boot_revoke_public_key_digest = 0x4000076c;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group usb_uart
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
PROVIDE( usb_uart_device_rx_one_char = 0x400008d8 );
|
||||
PROVIDE( usb_uart_device_rx_one_char_block = 0x400008dc );
|
||||
PROVIDE( usb_uart_device_tx_flush = 0x400008e0 );
|
||||
PROVIDE( usb_uart_device_tx_one_char = 0x400008e4 );
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
PROVIDE( g_uart_print = 0x3fcdffcd );
|
||||
PROVIDE( g_usb_print = 0x3fcdffcc );
|
||||
|
||||
|
||||
/***************************************
|
||||
Group rom_phy
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
phy_get_romfuncs = 0x400008e8;
|
||||
rom_abs_temp = 0x400008ec;
|
||||
rom_bb_bss_cbw40_dig = 0x400008f0;
|
||||
rom_bb_wdg_test_en = 0x400008f4;
|
||||
rom_bb_wdt_get_status = 0x400008f8;
|
||||
rom_bb_wdt_int_enable = 0x400008fc;
|
||||
rom_bb_wdt_rst_enable = 0x40000900;
|
||||
rom_bb_wdt_timeout_clear = 0x40000904;
|
||||
rom_cbw2040_cfg = 0x40000908;
|
||||
rom_check_noise_floor = 0x4000090c;
|
||||
rom_chip_i2c_readReg = 0x40000910;
|
||||
rom_chip_i2c_writeReg = 0x40000914;
|
||||
rom_correct_rf_ana_gain = 0x40000918;
|
||||
rom_dc_iq_est = 0x4000091c;
|
||||
rom_disable_agc = 0x40000920;
|
||||
rom_en_pwdet = 0x40000924;
|
||||
rom_enable_agc = 0x40000928;
|
||||
rom_get_bbgain_db = 0x4000092c;
|
||||
rom_get_data_sat = 0x40000930;
|
||||
rom_get_i2c_read_mask = 0x40000934;
|
||||
rom_get_pwctrl_correct = 0x40000938;
|
||||
rom_get_rf_gain_qdb = 0x4000093c;
|
||||
rom_i2c_readReg = 0x40000940;
|
||||
rom_i2c_readReg_Mask = 0x40000944;
|
||||
rom_i2c_writeReg = 0x40000948;
|
||||
rom_i2c_writeReg_Mask = 0x4000094c;
|
||||
rom_index_to_txbbgain = 0x40000950;
|
||||
rom_iq_est_disable = 0x40000954;
|
||||
rom_iq_est_enable = 0x40000958;
|
||||
rom_linear_to_db = 0x4000095c;
|
||||
rom_loopback_mode_en = 0x40000960;
|
||||
rom_mhz2ieee = 0x40000964;
|
||||
rom_noise_floor_auto_set = 0x40000968;
|
||||
rom_pbus_debugmode = 0x4000096c;
|
||||
rom_pbus_force_mode = 0x40000970;
|
||||
rom_pbus_force_test = 0x40000974;
|
||||
rom_pbus_rd = 0x40000978;
|
||||
rom_pbus_rd_addr = 0x4000097c;
|
||||
rom_pbus_rd_shift = 0x40000980;
|
||||
rom_pbus_set_dco = 0x40000984;
|
||||
rom_pbus_set_rxgain = 0x40000988;
|
||||
rom_pbus_workmode = 0x4000098c;
|
||||
rom_pbus_xpd_rx_off = 0x40000990;
|
||||
rom_pbus_xpd_rx_on = 0x40000994;
|
||||
rom_pbus_xpd_tx_off = 0x40000998;
|
||||
rom_pbus_xpd_tx_on = 0x4000099c;
|
||||
rom_phy_byte_to_word = 0x400009a0;
|
||||
rom_phy_disable_cca = 0x400009a4;
|
||||
rom_phy_enable_cca = 0x400009a8;
|
||||
rom_phy_get_noisefloor = 0x400009ac;
|
||||
rom_phy_get_rx_freq = 0x400009b0;
|
||||
rom_phy_set_bbfreq_init = 0x400009b4;
|
||||
rom_pow_usr = 0x400009b8;
|
||||
rom_pwdet_sar2_init = 0x400009bc;
|
||||
rom_read_hw_noisefloor = 0x400009c0;
|
||||
rom_read_sar_dout = 0x400009c4;
|
||||
rom_set_cal_rxdc = 0x400009c8;
|
||||
rom_set_chan_cal_interp = 0x400009cc;
|
||||
rom_set_loopback_gain = 0x400009d0;
|
||||
rom_set_noise_floor = 0x400009d4;
|
||||
rom_set_rxclk_en = 0x400009d8;
|
||||
rom_set_tx_dig_gain = 0x400009dc;
|
||||
rom_set_txcap_reg = 0x400009e0;
|
||||
rom_set_txclk_en = 0x400009e4;
|
||||
rom_spur_cal = 0x400009e8;
|
||||
rom_spur_reg_write_one_tone = 0x400009ec;
|
||||
rom_target_power_add_backoff = 0x400009f0;
|
||||
rom_tx_pwctrl_bg_init = 0x400009f4;
|
||||
rom_txbbgain_to_index = 0x400009f8;
|
||||
rom_wifi_11g_rate_chg = 0x400009fc;
|
||||
rom_write_gain_mem = 0x40000a00;
|
||||
chip726_phyrom_version = 0x40000a04;
|
||||
rom_disable_wifi_agc = 0x40000a08;
|
||||
rom_enable_wifi_agc = 0x40000a0c;
|
||||
rom_set_tx_gain_table = 0x40000a10;
|
||||
rom_bt_index_to_bb = 0x40000a14;
|
||||
rom_bt_bb_to_index = 0x40000a18;
|
||||
rom_wr_bt_tx_atten = 0x40000a1c;
|
||||
rom_wr_bt_tx_gain_mem = 0x40000a20;
|
||||
rom_spur_coef_cfg = 0x40000a24;
|
||||
rom_bb_bss_cbw40 = 0x40000a28;
|
||||
rom_set_cca = 0x40000a2c;
|
||||
rom_tx_paon_set = 0x40000a30;
|
||||
rom_i2cmst_reg_init = 0x40000a34;
|
||||
rom_iq_corr_enable = 0x40000a38;
|
||||
rom_fe_reg_init = 0x40000a3c;
|
||||
rom_agc_reg_init = 0x40000a40;
|
||||
rom_bb_reg_init = 0x40000a44;
|
||||
rom_mac_enable_bb = 0x40000a48;
|
||||
rom_bb_wdg_cfg = 0x40000a4c;
|
||||
rom_force_txon = 0x40000a50;
|
||||
rom_fe_txrx_reset = 0x40000a54;
|
||||
rom_set_rx_comp = 0x40000a58;
|
||||
rom_set_pbus_reg = 0x40000a5c;
|
||||
rom_write_chan_freq = 0x40000a60;
|
||||
rom_phy_xpd_rf = 0x40000a64;
|
||||
rom_set_xpd_sar = 0x40000a68;
|
||||
rom_write_dac_gain2 = 0x40000a6c;
|
||||
rom_rtc_sar2_init = 0x40000a70;
|
||||
rom_get_target_power_offset = 0x40000a74;
|
||||
rom_write_txrate_power_offset = 0x40000a78;
|
||||
rom_get_rate_fcc_index = 0x40000a7c;
|
||||
rom_get_rate_target_power = 0x40000a80;
|
||||
rom_write_wifi_dig_gain = 0x40000a84;
|
||||
rom_bt_correct_rf_ana_gain = 0x40000a88;
|
||||
rom_pkdet_vol_start = 0x40000a8c;
|
||||
rom_read_sar2_code = 0x40000a90;
|
||||
rom_get_sar2_vol = 0x40000a94;
|
||||
rom_get_pll_vol = 0x40000a98;
|
||||
rom_get_phy_target_power = 0x40000a9c;
|
||||
rom_temp_to_power = 0x40000aa0;
|
||||
rom_phy_track_pll_cap = 0x40000aa4;
|
||||
rom_phy_pwdet_always_en = 0x40000aa8;
|
||||
rom_phy_pwdet_onetime_en = 0x40000aac;
|
||||
rom_get_i2c_mst0_mask = 0x40000ab0;
|
||||
rom_get_i2c_hostid = 0x40000ab4;
|
||||
rom_enter_critical_phy = 0x40000ab8;
|
||||
rom_exit_critical_phy = 0x40000abc;
|
||||
rom_chip_i2c_readReg_org = 0x40000ac0;
|
||||
rom_i2c_paral_set_mst0 = 0x40000ac4;
|
||||
rom_i2c_paral_set_read = 0x40000ac8;
|
||||
rom_i2c_paral_read = 0x40000acc;
|
||||
rom_i2c_paral_write = 0x40000ad0;
|
||||
rom_i2c_paral_write_num = 0x40000ad4;
|
||||
rom_i2c_paral_write_mask = 0x40000ad8;
|
||||
rom_bb_bss_cbw40_ana = 0x40000adc;
|
||||
rom_chan_to_freq = 0x40000ae0;
|
||||
rom_open_i2c_xpd = 0x40000ae4;
|
||||
rom_dac_rate_set = 0x40000ae8;
|
||||
rom_tsens_read_init = 0x40000aec;
|
||||
rom_tsens_code_read = 0x40000af0;
|
||||
rom_tsens_index_to_dac = 0x40000af4;
|
||||
rom_tsens_index_to_offset = 0x40000af8;
|
||||
rom_tsens_dac_cal = 0x40000afc;
|
||||
rom_code_to_temp = 0x40000b00;
|
||||
rom_write_pll_cap_mem = 0x40000b04;
|
||||
rom_pll_correct_dcap = 0x40000b08;
|
||||
rom_phy_en_hw_set_freq = 0x40000b0c;
|
||||
rom_phy_dis_hw_set_freq = 0x40000b10;
|
||||
rom_pll_vol_cal = 0x40000b14;
|
||||
rom_wrtie_pll_cap = 0x40000b18;
|
||||
rom_set_tx_gain_mem = 0x40000b1c;
|
||||
rom_bt_tx_dig_gain = 0x40000b20;
|
||||
rom_bt_get_tx_gain = 0x40000b24;
|
||||
rom_get_chan_target_power = 0x40000b28;
|
||||
rom_get_tx_gain_value = 0x40000b2c;
|
||||
rom_wifi_tx_dig_gain = 0x40000b30;
|
||||
rom_wifi_get_tx_gain = 0x40000b34;
|
||||
rom_fe_i2c_reg_renew = 0x40000b38;
|
||||
rom_wifi_agc_sat_gain = 0x40000b3c;
|
||||
rom_i2c_master_reset = 0x40000b40;
|
||||
rom_bt_filter_reg = 0x40000b44;
|
||||
rom_phy_bbpll_cal = 0x40000b48;
|
||||
rom_i2c_sar2_init_code = 0x40000b4c;
|
||||
rom_phy_param_addr = 0x40000b50;
|
||||
rom_phy_reg_init = 0x40000b54;
|
||||
rom_set_chan_reg = 0x40000b58;
|
||||
rom_phy_wakeup_init = 0x40000b5c;
|
||||
rom_phy_i2c_init1 = 0x40000b60;
|
||||
rom_tsens_temp_read = 0x40000b64;
|
||||
rom_bt_track_pll_cap = 0x40000b68;
|
||||
rom_wifi_track_pll_cap = 0x40000b6c;
|
||||
rom_wifi_set_tx_gain = 0x40000b70;
|
||||
rom_txpwr_cal_track = 0x40000b74;
|
||||
rom_tx_pwctrl_background = 0x40000b78;
|
||||
rom_bt_set_tx_gain = 0x40000b7c;
|
||||
rom_noise_check_loop = 0x40000b80;
|
||||
rom_phy_close_rf = 0x40000b84;
|
||||
rom_phy_xpd_tsens = 0x40000b88;
|
||||
rom_phy_freq_mem_backup = 0x40000b8c;
|
||||
rom_phy_ant_init = 0x40000b90;
|
||||
rom_bt_track_tx_power = 0x40000b94;
|
||||
rom_wifi_track_tx_power = 0x40000b98;
|
||||
rom_phy_dig_reg_backup = 0x40000b9c;
|
||||
chip726_phyrom_version_num = 0x40000ba0;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
phy_param_rom = 0x3fcdffc8;
|
||||
@@ -1,111 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z
|
||||
*
|
||||
*
|
||||
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group libgcc
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
__absvdi2 = 0x40000770;
|
||||
__absvsi2 = 0x40000774;
|
||||
__adddf3 = 0x40000778;
|
||||
__addsf3 = 0x4000077c;
|
||||
__addvdi3 = 0x40000780;
|
||||
__addvsi3 = 0x40000784;
|
||||
__ashldi3 = 0x40000788;
|
||||
__ashrdi3 = 0x4000078c;
|
||||
__bswapdi2 = 0x40000790;
|
||||
__bswapsi2 = 0x40000794;
|
||||
__clear_cache = 0x40000798;
|
||||
__clrsbdi2 = 0x4000079c;
|
||||
__clrsbsi2 = 0x400007a0;
|
||||
__clzdi2 = 0x400007a4;
|
||||
__clzsi2 = 0x400007a8;
|
||||
__cmpdi2 = 0x400007ac;
|
||||
__ctzdi2 = 0x400007b0;
|
||||
__ctzsi2 = 0x400007b4;
|
||||
__divdc3 = 0x400007b8;
|
||||
__divdf3 = 0x400007bc;
|
||||
__divdi3 = 0x400007c0;
|
||||
__divsc3 = 0x400007c4;
|
||||
__divsf3 = 0x400007c8;
|
||||
__divsi3 = 0x400007cc;
|
||||
__eqdf2 = 0x400007d0;
|
||||
__eqsf2 = 0x400007d4;
|
||||
__extendsfdf2 = 0x400007d8;
|
||||
__ffsdi2 = 0x400007dc;
|
||||
__ffssi2 = 0x400007e0;
|
||||
__fixdfdi = 0x400007e4;
|
||||
__fixdfsi = 0x400007e8;
|
||||
__fixsfdi = 0x400007ec;
|
||||
__fixsfsi = 0x400007f0;
|
||||
__fixunsdfsi = 0x400007f4;
|
||||
__fixunssfdi = 0x400007f8;
|
||||
__fixunssfsi = 0x400007fc;
|
||||
__floatdidf = 0x40000800;
|
||||
__floatdisf = 0x40000804;
|
||||
__floatsidf = 0x40000808;
|
||||
__floatsisf = 0x4000080c;
|
||||
__floatundidf = 0x40000810;
|
||||
__floatundisf = 0x40000814;
|
||||
__floatunsidf = 0x40000818;
|
||||
__floatunsisf = 0x4000081c;
|
||||
__gcc_bcmp = 0x40000820;
|
||||
__gedf2 = 0x40000824;
|
||||
__gesf2 = 0x40000828;
|
||||
__gtdf2 = 0x4000082c;
|
||||
__gtsf2 = 0x40000830;
|
||||
__ledf2 = 0x40000834;
|
||||
__lesf2 = 0x40000838;
|
||||
__lshrdi3 = 0x4000083c;
|
||||
__ltdf2 = 0x40000840;
|
||||
__ltsf2 = 0x40000844;
|
||||
__moddi3 = 0x40000848;
|
||||
__modsi3 = 0x4000084c;
|
||||
__muldc3 = 0x40000850;
|
||||
__muldf3 = 0x40000854;
|
||||
__muldi3 = 0x40000858;
|
||||
__mulsc3 = 0x4000085c;
|
||||
__mulsf3 = 0x40000860;
|
||||
__mulsi3 = 0x40000864;
|
||||
__mulvdi3 = 0x40000868;
|
||||
__mulvsi3 = 0x4000086c;
|
||||
__nedf2 = 0x40000870;
|
||||
__negdf2 = 0x40000874;
|
||||
__negdi2 = 0x40000878;
|
||||
__negsf2 = 0x4000087c;
|
||||
__negvdi2 = 0x40000880;
|
||||
__negvsi2 = 0x40000884;
|
||||
__nesf2 = 0x40000888;
|
||||
__paritysi2 = 0x4000088c;
|
||||
__popcountdi2 = 0x40000890;
|
||||
__popcountsi2 = 0x40000894;
|
||||
__powidf2 = 0x40000898;
|
||||
__powisf2 = 0x4000089c;
|
||||
__subdf3 = 0x400008a0;
|
||||
__subsf3 = 0x400008a4;
|
||||
__subvdi3 = 0x400008a8;
|
||||
__subvsi3 = 0x400008ac;
|
||||
__truncdfsf2 = 0x400008b0;
|
||||
__ucmpdi2 = 0x400008b4;
|
||||
__udivdi3 = 0x400008b8;
|
||||
__udivmoddi4 = 0x400008bc;
|
||||
__udivsi3 = 0x400008c0;
|
||||
__udiv_w_sdiv = 0x400008c4;
|
||||
__umoddi3 = 0x400008c8;
|
||||
__umodsi3 = 0x400008cc;
|
||||
__unorddf2 = 0x400008d0;
|
||||
__unordsf2 = 0x400008d4;
|
||||
@@ -1,33 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z
|
||||
*
|
||||
*
|
||||
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group newlib_nano_format
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
__sprint_r = 0x40000488;
|
||||
_fiprintf_r = 0x4000048c;
|
||||
_fprintf_r = 0x40000490;
|
||||
_printf_common = 0x40000494;
|
||||
_printf_i = 0x40000498;
|
||||
_vfiprintf_r = 0x4000049c;
|
||||
_vfprintf_r = 0x400004a0;
|
||||
fiprintf = 0x400004a4;
|
||||
fprintf = 0x400004a8;
|
||||
printf = 0x400004ac;
|
||||
vfiprintf = 0x400004b0;
|
||||
vfprintf = 0x400004b4;
|
||||
@@ -1,96 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z
|
||||
*
|
||||
*
|
||||
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group newlib
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esp_rom_newlib_init_common_mutexes = 0x40000358;
|
||||
memset = 0x4000035c;
|
||||
memcpy = 0x40000360;
|
||||
memmove = 0x40000364;
|
||||
memcmp = 0x40000368;
|
||||
strcpy = 0x4000036c;
|
||||
strncpy = 0x40000370;
|
||||
strcmp = 0x40000374;
|
||||
strncmp = 0x40000378;
|
||||
strlen = 0x4000037c;
|
||||
strstr = 0x40000380;
|
||||
bzero = 0x40000384;
|
||||
sbrk = 0x4000038c;
|
||||
isalnum = 0x40000390;
|
||||
isalpha = 0x40000394;
|
||||
isascii = 0x40000398;
|
||||
isblank = 0x4000039c;
|
||||
iscntrl = 0x400003a0;
|
||||
isdigit = 0x400003a4;
|
||||
islower = 0x400003a8;
|
||||
isgraph = 0x400003ac;
|
||||
isprint = 0x400003b0;
|
||||
ispunct = 0x400003b4;
|
||||
isspace = 0x400003b8;
|
||||
isupper = 0x400003bc;
|
||||
toupper = 0x400003c0;
|
||||
tolower = 0x400003c4;
|
||||
toascii = 0x400003c8;
|
||||
memccpy = 0x400003cc;
|
||||
memchr = 0x400003d0;
|
||||
memrchr = 0x400003d4;
|
||||
strcasecmp = 0x400003d8;
|
||||
strcasestr = 0x400003dc;
|
||||
strcat = 0x400003e0;
|
||||
strdup = 0x400003e4;
|
||||
strchr = 0x400003e8;
|
||||
strcspn = 0x400003ec;
|
||||
strcoll = 0x400003f0;
|
||||
strlcat = 0x400003f4;
|
||||
strlcpy = 0x400003f8;
|
||||
strlwr = 0x400003fc;
|
||||
strncasecmp = 0x40000400;
|
||||
strncat = 0x40000404;
|
||||
strndup = 0x40000408;
|
||||
strnlen = 0x4000040c;
|
||||
strrchr = 0x40000410;
|
||||
strsep = 0x40000414;
|
||||
strspn = 0x40000418;
|
||||
strtok_r = 0x4000041c;
|
||||
strupr = 0x40000420;
|
||||
longjmp = 0x40000424;
|
||||
setjmp = 0x40000428;
|
||||
abs = 0x4000042c;
|
||||
div = 0x40000430;
|
||||
labs = 0x40000434;
|
||||
ldiv = 0x40000438;
|
||||
qsort = 0x4000043c;
|
||||
rand_r = 0x40000440;
|
||||
rand = 0x40000444;
|
||||
srand = 0x40000448;
|
||||
utoa = 0x4000044c;
|
||||
itoa = 0x40000450;
|
||||
atoi = 0x40000454;
|
||||
atol = 0x40000458;
|
||||
strtol = 0x4000045c;
|
||||
strtoul = 0x40000460;
|
||||
PROVIDE( fflush = 0x40000464 );
|
||||
PROVIDE( _fflush_r = 0x40000468 );
|
||||
PROVIDE( _fwalk = 0x4000046c );
|
||||
PROVIDE( _fwalk_reent = 0x40000470 );
|
||||
PROVIDE( __swbuf_r = 0x4000047c );
|
||||
__swbuf = 0x40000480;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
syscall_table_ptr = 0x3fcdffdc;
|
||||
_global_impure_ptr = 0x3fcdffd8;
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* ROM version variables for esp32b1z
|
||||
*
|
||||
* These addresses should be compatible with any ROM version for this chip.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
_rom_chip_id = 0x40000010;
|
||||
_rom_eco_version = 0x40000014;
|
||||
@@ -1,61 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** ROM APIs
|
||||
*/
|
||||
PROVIDE ( esp_rom_crc32_le = crc32_le );
|
||||
PROVIDE ( esp_rom_crc16_le = crc16_le );
|
||||
PROVIDE ( esp_rom_crc8_le = crc8_le );
|
||||
PROVIDE ( esp_rom_crc32_be = crc32_be );
|
||||
PROVIDE ( esp_rom_crc16_be = crc16_be );
|
||||
PROVIDE ( esp_rom_crc8_be = crc8_be );
|
||||
|
||||
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
|
||||
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
|
||||
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
|
||||
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
|
||||
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
|
||||
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
|
||||
|
||||
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
|
||||
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
|
||||
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
|
||||
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
|
||||
|
||||
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
|
||||
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
|
||||
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
|
||||
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
|
||||
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
|
||||
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
|
||||
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
|
||||
|
||||
PROVIDE ( esp_rom_md5_init = MD5Init );
|
||||
PROVIDE ( esp_rom_md5_update = MD5Update );
|
||||
PROVIDE ( esp_rom_md5_final = MD5Final );
|
||||
|
||||
PROVIDE ( esp_rom_software_reset_system = software_reset );
|
||||
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
|
||||
|
||||
PROVIDE ( esp_rom_printf = ets_printf );
|
||||
PROVIDE ( esp_rom_delay_us = ets_delay_us );
|
||||
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
|
||||
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
|
||||
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
|
||||
|
||||
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
|
||||
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
|
||||
PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
|
||||
|
||||
PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
|
||||
PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
|
||||
PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
|
||||
PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );
|
||||
|
||||
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
|
||||
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
|
||||
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
|
||||
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,112 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group libgcc
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
__absvdi2 = 0x40000998;
|
||||
__absvsi2 = 0x4000099c;
|
||||
__adddf3 = 0x400009a0;
|
||||
__addsf3 = 0x400009a4;
|
||||
__addvdi3 = 0x400009a8;
|
||||
__addvsi3 = 0x400009ac;
|
||||
__ashldi3 = 0x400009b0;
|
||||
__ashrdi3 = 0x400009b4;
|
||||
__bswapdi2 = 0x400009b8;
|
||||
__bswapsi2 = 0x400009bc;
|
||||
__clear_cache = 0x400009c0;
|
||||
__clrsbdi2 = 0x400009c4;
|
||||
__clrsbsi2 = 0x400009c8;
|
||||
__clzdi2 = 0x400009cc;
|
||||
__clzsi2 = 0x400009d0;
|
||||
__cmpdi2 = 0x400009d4;
|
||||
__ctzdi2 = 0x400009d8;
|
||||
__ctzsi2 = 0x400009dc;
|
||||
__divdc3 = 0x400009e0;
|
||||
__divdf3 = 0x400009e4;
|
||||
__divdi3 = 0x400009e8;
|
||||
__divsc3 = 0x400009ec;
|
||||
__divsf3 = 0x400009f0;
|
||||
__divsi3 = 0x400009f4;
|
||||
__eqdf2 = 0x400009f8;
|
||||
__eqsf2 = 0x400009fc;
|
||||
__extendsfdf2 = 0x40000a00;
|
||||
__ffsdi2 = 0x40000a04;
|
||||
__ffssi2 = 0x40000a08;
|
||||
__fixdfdi = 0x40000a0c;
|
||||
__fixdfsi = 0x40000a10;
|
||||
__fixsfdi = 0x40000a14;
|
||||
__fixsfsi = 0x40000a18;
|
||||
__fixunsdfsi = 0x40000a1c;
|
||||
__fixunssfdi = 0x40000a20;
|
||||
__fixunssfsi = 0x40000a24;
|
||||
__floatdidf = 0x40000a28;
|
||||
__floatdisf = 0x40000a2c;
|
||||
__floatsidf = 0x40000a30;
|
||||
__floatsisf = 0x40000a34;
|
||||
__floatundidf = 0x40000a38;
|
||||
__floatundisf = 0x40000a3c;
|
||||
__floatunsidf = 0x40000a40;
|
||||
__floatunsisf = 0x40000a44;
|
||||
__gcc_bcmp = 0x40000a48;
|
||||
__gedf2 = 0x40000a4c;
|
||||
__gesf2 = 0x40000a50;
|
||||
__gtdf2 = 0x40000a54;
|
||||
__gtsf2 = 0x40000a58;
|
||||
__ledf2 = 0x40000a5c;
|
||||
__lesf2 = 0x40000a60;
|
||||
__lshrdi3 = 0x40000a64;
|
||||
__ltdf2 = 0x40000a68;
|
||||
__ltsf2 = 0x40000a6c;
|
||||
__moddi3 = 0x40000a70;
|
||||
__modsi3 = 0x40000a74;
|
||||
__muldc3 = 0x40000a78;
|
||||
__muldf3 = 0x40000a7c;
|
||||
__muldi3 = 0x40000a80;
|
||||
__mulsc3 = 0x40000a84;
|
||||
__mulsf3 = 0x40000a88;
|
||||
__mulsi3 = 0x40000a8c;
|
||||
__mulvdi3 = 0x40000a90;
|
||||
__mulvsi3 = 0x40000a94;
|
||||
__nedf2 = 0x40000a98;
|
||||
__negdf2 = 0x40000a9c;
|
||||
__negdi2 = 0x40000aa0;
|
||||
__negsf2 = 0x40000aa4;
|
||||
__negvdi2 = 0x40000aa8;
|
||||
__negvsi2 = 0x40000aac;
|
||||
__nesf2 = 0x40000ab0;
|
||||
__paritysi2 = 0x40000ab4;
|
||||
__popcountdi2 = 0x40000ab8;
|
||||
__popcountsi2 = 0x40000abc;
|
||||
__powidf2 = 0x40000ac0;
|
||||
__powisf2 = 0x40000ac4;
|
||||
__subdf3 = 0x40000ac8;
|
||||
__subsf3 = 0x40000acc;
|
||||
__subvdi3 = 0x40000ad0;
|
||||
__subvsi3 = 0x40000ad4;
|
||||
__truncdfsf2 = 0x40000ad8;
|
||||
__ucmpdi2 = 0x40000adc;
|
||||
__udivdi3 = 0x40000ae0;
|
||||
__udivmoddi4 = 0x40000ae4;
|
||||
__udivsi3 = 0x40000ae8;
|
||||
__udiv_w_sdiv = 0x40000aec;
|
||||
__umoddi3 = 0x40000af0;
|
||||
__umodsi3 = 0x40000af4;
|
||||
__unorddf2 = 0x40000af8;
|
||||
__unordsf2 = 0x40000afc;
|
||||
__extenddftf2 = 0x40000b00;
|
||||
__trunctfdf2 = 0x40000b04;
|
||||
@@ -1,47 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32h4.rom.newlib-nano.ld for esp32h4
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group newlib_nano_format
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
__sprint_r = 0x40000684;
|
||||
_fiprintf_r = 0x40000688;
|
||||
_fprintf_r = 0x4000068c;
|
||||
_printf_common = 0x40000690;
|
||||
_printf_i = 0x40000694;
|
||||
_vfiprintf_r = 0x40000698;
|
||||
_vfprintf_r = 0x4000069c;
|
||||
fiprintf = 0x400006a0;
|
||||
fprintf = 0x400006a4;
|
||||
printf = 0x400006a8;
|
||||
vfiprintf = 0x400006ac;
|
||||
vfprintf = 0x400006b0;
|
||||
asprintf = 0x400006b4;
|
||||
sprintf = 0x400006b8;
|
||||
snprintf = 0x400006bc;
|
||||
siprintf = 0x400006c0;
|
||||
sniprintf = 0x400006c4;
|
||||
vprintf = 0x400006c8;
|
||||
viprintf = 0x400006cc;
|
||||
vsnprintf = 0x400006d0;
|
||||
vsniprintf = 0x400006d4;
|
||||
_printf_float = 0x400006d8;
|
||||
_scanf_float = 0x400006dc;
|
||||
_scanf_i = 0x400006e0;
|
||||
_scanf_chars = 0x400006e4;
|
||||
sscanf = 0x400006e8;
|
||||
siscanf = 0x400006ec;
|
||||
@@ -1,143 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32h4.rom.newlib.ld for esp32h4
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group newlib
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esp_rom_newlib_init_common_mutexes = 0x40000494;
|
||||
memset = 0x40000498;
|
||||
memcpy = 0x4000049c;
|
||||
memmove = 0x400004a0;
|
||||
memcmp = 0x400004a4;
|
||||
strcpy = 0x400004a8;
|
||||
strncpy = 0x400004ac;
|
||||
strcmp = 0x400004b0;
|
||||
strncmp = 0x400004b4;
|
||||
strlen = 0x400004b8;
|
||||
strstr = 0x400004bc;
|
||||
bzero = 0x400004c0;
|
||||
sbrk = 0x400004c8;
|
||||
isalnum = 0x400004cc;
|
||||
isalpha = 0x400004d0;
|
||||
isascii = 0x400004d4;
|
||||
isblank = 0x400004d8;
|
||||
iscntrl = 0x400004dc;
|
||||
isdigit = 0x400004e0;
|
||||
islower = 0x400004e4;
|
||||
isgraph = 0x400004e8;
|
||||
isprint = 0x400004ec;
|
||||
ispunct = 0x400004f0;
|
||||
isspace = 0x400004f4;
|
||||
isupper = 0x400004f8;
|
||||
toupper = 0x400004fc;
|
||||
tolower = 0x40000500;
|
||||
toascii = 0x40000504;
|
||||
memccpy = 0x40000508;
|
||||
memchr = 0x4000050c;
|
||||
memrchr = 0x40000510;
|
||||
strcasecmp = 0x40000514;
|
||||
strcasestr = 0x40000518;
|
||||
strcat = 0x4000051c;
|
||||
strdup = 0x40000520;
|
||||
strchr = 0x40000524;
|
||||
strcspn = 0x40000528;
|
||||
strcoll = 0x4000052c;
|
||||
strlcat = 0x40000530;
|
||||
strlcpy = 0x40000534;
|
||||
strlwr = 0x40000538;
|
||||
strncasecmp = 0x4000053c;
|
||||
strncat = 0x40000540;
|
||||
strndup = 0x40000544;
|
||||
strnlen = 0x40000548;
|
||||
strrchr = 0x4000054c;
|
||||
strsep = 0x40000550;
|
||||
strspn = 0x40000554;
|
||||
strtok_r = 0x40000558;
|
||||
strupr = 0x4000055c;
|
||||
longjmp = 0x40000560;
|
||||
setjmp = 0x40000564;
|
||||
abs = 0x40000568;
|
||||
div = 0x4000056c;
|
||||
labs = 0x40000570;
|
||||
ldiv = 0x40000574;
|
||||
qsort = 0x40000578;
|
||||
rand_r = 0x4000057c;
|
||||
rand = 0x40000580;
|
||||
srand = 0x40000584;
|
||||
utoa = 0x40000588;
|
||||
itoa = 0x4000058c;
|
||||
atoi = 0x40000590;
|
||||
atol = 0x40000594;
|
||||
strtol = 0x40000598;
|
||||
strtoul = 0x4000059c;
|
||||
fflush = 0x400005a0;
|
||||
_fflush_r = 0x400005a4;
|
||||
_fwalk = 0x400005a8;
|
||||
_fwalk_reent = 0x400005ac;
|
||||
__swbuf_r = 0x400005b8;
|
||||
__swbuf = 0x400005bc;
|
||||
_strtod_l = 0x400005c4;
|
||||
_strtod_r = 0x400005c8;
|
||||
strtod_l = 0x400005cc;
|
||||
strtod = 0x400005d0;
|
||||
strtof_l = 0x400005d4;
|
||||
strtof = 0x400005d8;
|
||||
_strtol_r = 0x400005dc;
|
||||
strtol_l = 0x400005e0;
|
||||
_strtoul_r = 0x400005e4;
|
||||
strtoul_l = 0x400005e8;
|
||||
__match = 0x400005ec;
|
||||
__hexnan = 0x400005f0;
|
||||
__hexdig_fun = 0x400005f4;
|
||||
__gethex = 0x400005f8;
|
||||
_Balloc = 0x400005fc;
|
||||
_Bfree = 0x40000600;
|
||||
__multadd = 0x40000604;
|
||||
__s2b = 0x40000608;
|
||||
__hi0bits = 0x4000060c;
|
||||
__lo0bits = 0x40000610;
|
||||
__i2b = 0x40000614;
|
||||
__multiply = 0x40000618;
|
||||
__pow5mult = 0x4000061c;
|
||||
__lshift = 0x40000620;
|
||||
__mcmp = 0x40000624;
|
||||
__mdiff = 0x40000628;
|
||||
__ulp = 0x4000062c;
|
||||
__b2d = 0x40000630;
|
||||
__d2b = 0x40000634;
|
||||
__ratio = 0x40000638;
|
||||
_mprec_log10 = 0x4000063c;
|
||||
__copybits = 0x40000640;
|
||||
__any_on = 0x40000644;
|
||||
asctime = 0x40000648;
|
||||
asctime_r = 0x4000064c;
|
||||
atof = 0x40000650;
|
||||
atoff = 0x40000654;
|
||||
_dtoa_r = 0x40000658;
|
||||
_wctomb_r = 0x4000065c;
|
||||
__ascii_wctomb = 0x40000660;
|
||||
_mbtowc_r = 0x40000664;
|
||||
__ascii_mbtowc = 0x40000668;
|
||||
puts = 0x4000066c;
|
||||
putc = 0x40000670;
|
||||
putchar = 0x40000674;
|
||||
nan = 0x40000678;
|
||||
nanf = 0x4000067c;
|
||||
__errno = 0x40000680;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
syscall_table_ptr = 0x3fcdffd4;
|
||||
_global_impure_ptr = 0x3fcdffd0;
|
||||
@@ -1,13 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM version variables for esp32h4
|
||||
*
|
||||
* These addresses should be compatible with any ROM version for this chip.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
_rom_chip_id = 0x40000010;
|
||||
_rom_eco_version = 0x40000014;
|
||||
@@ -1,46 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_AES_H_
|
||||
#define _ROM_AES_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AES_BLOCK_SIZE 16
|
||||
|
||||
enum AES_TYPE {
|
||||
AES_ENC,
|
||||
AES_DEC,
|
||||
};
|
||||
|
||||
enum AES_BITS {
|
||||
AES128,
|
||||
AES192,
|
||||
AES256
|
||||
};
|
||||
|
||||
void ets_aes_enable(void);
|
||||
|
||||
void ets_aes_disable(void);
|
||||
|
||||
int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits);
|
||||
|
||||
int ets_aes_setkey_enc(const void *key, enum AES_BITS bits);
|
||||
|
||||
int ets_aes_setkey_dec(const void *key, enum AES_BITS bits);
|
||||
|
||||
void ets_aes_block(const void *input, void *output);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_AES_H_ */
|
||||
@@ -1,17 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void));
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_BIGINT_H_
|
||||
#define _ROM_BIGINT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void ets_bigint_enable(void);
|
||||
|
||||
void ets_bigint_disable(void);
|
||||
|
||||
int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words);
|
||||
|
||||
int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words);
|
||||
|
||||
int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words);
|
||||
|
||||
void ets_bigint_wait_finish(void);
|
||||
|
||||
int ets_bigint_getz(uint32_t *z, uint32_t len_words);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_BIGINT_H_ */
|
||||
@@ -1,750 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_CACHE_H_
|
||||
#define _ROM_CACHE_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup cache_apis, cache operation related apis
|
||||
* @brief cache apis
|
||||
*/
|
||||
|
||||
/** @addtogroup cache_apis
|
||||
* @{
|
||||
*/
|
||||
#define MIN_ICACHE_SIZE 16384
|
||||
#define MAX_ICACHE_SIZE 16384
|
||||
#define MIN_ICACHE_WAYS 8
|
||||
#define MAX_ICACHE_WAYS 8
|
||||
#define MAX_CACHE_WAYS 8
|
||||
#define MIN_CACHE_LINE_SIZE 32
|
||||
#define TAG_SIZE 4
|
||||
#define MIN_ICACHE_BANK_NUM 1
|
||||
#define MAX_ICACHE_BANK_NUM 1
|
||||
#define CACHE_MEMORY_BANK_NUM 1
|
||||
#define CACHE_MEMORY_IBANK_SIZE 0x4000
|
||||
|
||||
#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE)
|
||||
#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE)
|
||||
#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE)
|
||||
#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE)
|
||||
|
||||
typedef enum {
|
||||
CACHE_DCACHE = 0,
|
||||
CACHE_ICACHE0 = 1,
|
||||
CACHE_ICACHE1 = 2,
|
||||
} cache_t;
|
||||
|
||||
typedef enum {
|
||||
CACHE_MEMORY_INVALID = 0,
|
||||
CACHE_MEMORY_IBANK0 = BIT(0),
|
||||
CACHE_MEMORY_IBANK1 = BIT(1),
|
||||
CACHE_MEMORY_IBANK2 = BIT(2),
|
||||
CACHE_MEMORY_IBANK3 = BIT(3),
|
||||
CACHE_MEMORY_DBANK0 = BIT(0),
|
||||
CACHE_MEMORY_DBANK1 = BIT(1),
|
||||
CACHE_MEMORY_DBANK2 = BIT(2),
|
||||
CACHE_MEMORY_DBANK3 = BIT(3),
|
||||
} cache_array_t;
|
||||
|
||||
#define ICACHE_SIZE_16KB CACHE_SIZE_HALF
|
||||
#define ICACHE_SIZE_32KB CACHE_SIZE_FULL
|
||||
#define DCACHE_SIZE_32KB CACHE_SIZE_HALF
|
||||
#define DCACHE_SIZE_64KB CACHE_SIZE_FULL
|
||||
|
||||
typedef enum {
|
||||
CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */
|
||||
CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */
|
||||
} cache_size_t;
|
||||
|
||||
typedef enum {
|
||||
CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */
|
||||
CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */
|
||||
} cache_ways_t;
|
||||
|
||||
typedef enum {
|
||||
CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */
|
||||
CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */
|
||||
CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */
|
||||
} cache_line_size_t;
|
||||
|
||||
typedef enum {
|
||||
CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */
|
||||
CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */
|
||||
} cache_autoload_order_t;
|
||||
|
||||
#define CACHE_AUTOLOAD_STEP(i) ((i) - 1)
|
||||
|
||||
typedef enum {
|
||||
CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */
|
||||
CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */
|
||||
CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */
|
||||
} cache_autoload_trigger_t;
|
||||
|
||||
typedef enum {
|
||||
CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/
|
||||
CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
|
||||
} cache_freeze_mode_t;
|
||||
|
||||
struct cache_mode {
|
||||
uint32_t cache_size; /*!< cache size in byte */
|
||||
uint16_t cache_line_size; /*!< cache line size in byte */
|
||||
uint8_t cache_ways; /*!< cache ways, always 4 */
|
||||
uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */
|
||||
};
|
||||
|
||||
struct icache_tag_item {
|
||||
uint32_t valid:1; /*!< the tag item is valid or not */
|
||||
uint32_t lock:1; /*!< the cache line is locked or not */
|
||||
uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */
|
||||
uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */
|
||||
uint32_t reserved:14;
|
||||
};
|
||||
|
||||
struct autoload_config {
|
||||
uint8_t order; /*!< autoload step is positive or negative */
|
||||
uint8_t trigger; /*!< autoload trigger */
|
||||
uint8_t ena0; /*!< autoload region0 enable */
|
||||
uint8_t ena1; /*!< autoload region1 enable */
|
||||
uint32_t addr0; /*!< autoload region0 start address */
|
||||
uint32_t size0; /*!< autoload region0 size */
|
||||
uint32_t addr1; /*!< autoload region1 start address */
|
||||
uint32_t size1; /*!< autoload region1 size */
|
||||
};
|
||||
|
||||
struct tag_group_info {
|
||||
struct cache_mode mode; /*!< cache and cache mode */
|
||||
uint32_t filter_addr; /*!< the address that used to generate the struct */
|
||||
uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */
|
||||
uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */
|
||||
uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */
|
||||
};
|
||||
|
||||
struct lock_config {
|
||||
uint32_t addr; /*!< manual lock address*/
|
||||
uint16_t size; /*!< manual lock size*/
|
||||
uint16_t group; /*!< manual lock group, 0 or 1*/
|
||||
};
|
||||
|
||||
struct cache_internal_stub_table {
|
||||
uint32_t (* icache_line_size)(void);
|
||||
uint32_t (* icache_addr)(uint32_t addr);
|
||||
uint32_t (* dcache_addr)(uint32_t addr);
|
||||
void (* invalidate_icache_items)(uint32_t addr, uint32_t items);
|
||||
void (* lock_icache_items)(uint32_t addr, uint32_t items);
|
||||
void (* unlock_icache_items)(uint32_t addr, uint32_t items);
|
||||
uint32_t (* suspend_icache_autoload)(void);
|
||||
void (* resume_icache_autoload)(uint32_t autoload);
|
||||
void (* freeze_icache_enable)(cache_freeze_mode_t mode);
|
||||
void (* freeze_icache_disable)(void);
|
||||
int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t));
|
||||
};
|
||||
|
||||
/* Defined in the interface file, default value is rom_default_cache_internal_table */
|
||||
extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
|
||||
|
||||
typedef void (* cache_op_start)(void);
|
||||
typedef void (* cache_op_end)(void);
|
||||
|
||||
typedef struct {
|
||||
cache_op_start start;
|
||||
cache_op_end end;
|
||||
} cache_op_cb_t;
|
||||
|
||||
/* Defined in the interface file, default value is NULL */
|
||||
extern const cache_op_cb_t* rom_cache_op_cb;
|
||||
|
||||
#define ESP_ROM_ERR_INVALID_ARG 1
|
||||
#define MMU_SET_ADDR_ALIGNED_ERROR 2
|
||||
#define MMU_SET_PASE_SIZE_ERROR 3
|
||||
#define MMU_SET_VADDR_OUT_RANGE 4
|
||||
|
||||
#define CACHE_OP_ICACHE_Y 1
|
||||
#define CACHE_OP_ICACHE_N 0
|
||||
|
||||
/**
|
||||
* @brief Initialise cache mmu, mark all entries as invalid.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_MMU_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Set ICache mmu mapping.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
|
||||
* esp32h4, external memory is always flash
|
||||
*
|
||||
* @param uint32_t vaddr : virtual address in CPU address space.
|
||||
* Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t paddr : physical address in external memory.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here.
|
||||
*
|
||||
* @param uint32_t num : pages to be set.
|
||||
*
|
||||
* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
|
||||
*
|
||||
* @return uint32_t: error status
|
||||
* 0 : mmu set success
|
||||
* 2 : vaddr or paddr is not aligned
|
||||
* 3 : psize error
|
||||
* 4 : vaddr is out of range
|
||||
*/
|
||||
int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
|
||||
/**
|
||||
* @brief Set DCache mmu mapping.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
|
||||
* esp32h4, external memory is always flash
|
||||
*
|
||||
* @param uint32_t vaddr : virtual address in CPU address space.
|
||||
* Can be DRam0, DRam1, DRom0, DPort and AHB buses address.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t paddr : physical address in external memory.
|
||||
* Should be aligned by psize.
|
||||
*
|
||||
* @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here.
|
||||
*
|
||||
* @param uint32_t num : pages to be set.
|
||||
|
||||
* @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
|
||||
*
|
||||
* @return uint32_t: error status
|
||||
* 0 : mmu set success
|
||||
* 2 : vaddr or paddr is not aligned
|
||||
* 3 : psize error
|
||||
* 4 : vaddr is out of range
|
||||
*/
|
||||
int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
|
||||
/**
|
||||
* @brief Count the pages in the bus room address which map to Flash.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t bus : the bus to count with.
|
||||
*
|
||||
* @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count.
|
||||
*
|
||||
* return uint32_t : the number of pages which map to Flash.
|
||||
*/
|
||||
uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
|
||||
|
||||
/**
|
||||
* @brief allocate memory to used by ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0
|
||||
*
|
||||
* return none
|
||||
*/
|
||||
void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low);
|
||||
|
||||
/**
|
||||
* @brief Get cache mode of ICache or DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
|
||||
*
|
||||
* return none
|
||||
*/
|
||||
void Cache_Get_Mode(struct cache_mode * mode);
|
||||
|
||||
/**
|
||||
* @brief Init Cache for ROM boot, including resetting the Icache, initializing Owner, MMU, setting ICache mode, Enabling ICache, unmasking bus.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ROM_Boot_Cache_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Init mmu owner register to make i/d cache use half mmu entries.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Owner_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Invalidate the cache items for ICache.
|
||||
* Operation will be done CACHE_LINE_SIZE aligned.
|
||||
* If the region is not in ICache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr: start address to invalidate
|
||||
*
|
||||
* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items);
|
||||
|
||||
/**
|
||||
* @brief Invalidate the Cache items in the region from ICache or DCache.
|
||||
* If the region is not in Cache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : invalidated region start address.
|
||||
*
|
||||
* @param uint32_t size : invalidated region size.
|
||||
*
|
||||
* @return 0 for success
|
||||
* 1 for invalid argument
|
||||
*/
|
||||
int Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
|
||||
|
||||
/**
|
||||
* @brief Invalidate all cache items in ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Invalidate_ICache_All(void);
|
||||
|
||||
/**
|
||||
* @brief Mask all buses through ICache and DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Mask_All(void);
|
||||
|
||||
/**
|
||||
* @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : 0 for ICache not auto preload before suspend.
|
||||
*/
|
||||
uint32_t Cache_Suspend_ICache_Autoload(void);
|
||||
|
||||
/**
|
||||
* @brief Resume ICache auto preload operation after some ICache operations.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : 0 for ICache not auto preload before suspend.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void Cache_Resume_ICache_Autoload(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Start an ICache manual preload, will suspend auto preload of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : start address of the preload region.
|
||||
*
|
||||
* @param uint32_t size : size of the preload region, should not exceed the size of ICache.
|
||||
*
|
||||
* @param uint32_t order : the preload order, 0 for positive, other for negative
|
||||
*
|
||||
* @return uint32_t : 0 for ICache not auto preload before manual preload.
|
||||
*/
|
||||
uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order);
|
||||
|
||||
/**
|
||||
* @brief Return if the ICache manual preload done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : 0 for ICache manual preload not done.
|
||||
*/
|
||||
uint32_t Cache_ICache_Preload_Done(void);
|
||||
|
||||
/**
|
||||
* @brief End the ICache manual preload to resume auto preload of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : 0 for ICache not auto preload before manual preload.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_End_ICache_Preload(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Config autoload parameters of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct autoload_config * config : autoload parameters.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Config_ICache_Autoload(const struct autoload_config * config);
|
||||
|
||||
/**
|
||||
* @brief Enable auto preload for ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Enable_ICache_Autoload(void);
|
||||
|
||||
/**
|
||||
* @brief Disable auto preload for ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Disable_ICache_Autoload(void);
|
||||
|
||||
/**
|
||||
* @brief Config a group of prelock parameters of ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct lock_config * config : a group of lock parameters.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
|
||||
void Cache_Enable_ICache_PreLock(const struct lock_config *config);
|
||||
|
||||
/**
|
||||
* @brief Disable a group of prelock parameters for ICache.
|
||||
* However, the locked data will not be released.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint16_t group : 0 for group0, 1 for group1.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Disable_ICache_PreLock(uint16_t group);
|
||||
|
||||
/**
|
||||
* @brief Lock the cache items for ICache.
|
||||
* Operation will be done CACHE_LINE_SIZE aligned.
|
||||
* If the region is not in ICache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr: start address to lock
|
||||
*
|
||||
* @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items);
|
||||
|
||||
/**
|
||||
* @brief Unlock the cache items for ICache.
|
||||
* Operation will be done CACHE_LINE_SIZE aligned.
|
||||
* If the region is not in ICache addr room, nothing will be done.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr: start address to unlock
|
||||
*
|
||||
* @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items);
|
||||
|
||||
/**
|
||||
* @brief Lock the cache items in tag memory for ICache or DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : start address of lock region.
|
||||
*
|
||||
* @param uint32_t size : size of lock region.
|
||||
*
|
||||
* @return 0 for success
|
||||
* 1 for invalid argument
|
||||
*/
|
||||
int Cache_Lock_Addr(uint32_t addr, uint32_t size);
|
||||
|
||||
/**
|
||||
* @brief Unlock the cache items in tag memory for ICache or DCache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t addr : start address of unlock region.
|
||||
*
|
||||
* @param uint32_t size : size of unlock region.
|
||||
*
|
||||
* @return 0 for success
|
||||
* 1 for invalid argument
|
||||
*/
|
||||
int Cache_Unlock_Addr(uint32_t addr, uint32_t size);
|
||||
|
||||
/**
|
||||
* @brief Disable ICache access for the cpu.
|
||||
* This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @return uint32_t : auto preload enabled before
|
||||
*/
|
||||
uint32_t Cache_Disable_ICache(void);
|
||||
|
||||
/**
|
||||
* @brief Enable ICache access for the cpu.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : ICache will preload then.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Enable_ICache(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Suspend ICache access for the cpu.
|
||||
* The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle.
|
||||
* Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case).
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : auto preload enabled before
|
||||
*/
|
||||
uint32_t Cache_Suspend_ICache(void);
|
||||
|
||||
/**
|
||||
* @brief Resume ICache access for the cpu.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t autoload : ICache will preload then.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Resume_ICache(uint32_t autoload);
|
||||
|
||||
/**
|
||||
* @brief Get ICache cache line size
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t: 16, 32, 64 Byte
|
||||
*/
|
||||
uint32_t Cache_Get_ICache_Line_Size(void);
|
||||
|
||||
/**
|
||||
* @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Set_Default_Mode(void);
|
||||
|
||||
/**
|
||||
* @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Enable_Defalut_ICache_Mode(void);
|
||||
|
||||
/**
|
||||
* @brief Enable freeze for ICache.
|
||||
* Any miss request will be rejected, including cpu miss and preload/autoload miss.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Disable freeze for ICache.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Freeze_ICache_Disable(void);
|
||||
|
||||
/**
|
||||
* @brief Travel tag memory to run a call back function.
|
||||
* ICache and DCache are suspend when doing this.
|
||||
* The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the cache to check and the cache mode.
|
||||
*
|
||||
* @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function.
|
||||
* 0 for do not filter, all cache lines will be returned.
|
||||
*
|
||||
* @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *));
|
||||
|
||||
/**
|
||||
* @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
|
||||
*
|
||||
* @param uint32_t tag : the tag part fo a tag item, 12-14 bits.
|
||||
*
|
||||
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
|
||||
*
|
||||
* @return uint32_t : the virtual address.
|
||||
*/
|
||||
uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset);
|
||||
|
||||
/**
|
||||
* @brief Get cache memory block base address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t icache : 0 for dcache, other for icache.
|
||||
*
|
||||
* @param uint32_t bank_no : 0 ~ 3 bank.
|
||||
*
|
||||
* @return uint32_t : the cache memory block base address, 0 if the block not used.
|
||||
*/
|
||||
uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no);
|
||||
|
||||
/**
|
||||
* @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
|
||||
*
|
||||
* @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line.
|
||||
*
|
||||
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
|
||||
*
|
||||
* @return uint32_t : the virtual address.
|
||||
*/
|
||||
uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset);
|
||||
|
||||
/**
|
||||
* @brief Get the cache memory value by DRAM address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address.
|
||||
*
|
||||
* @return uint32_t : the word value of the address.
|
||||
*/
|
||||
uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the cache MMU IROM end address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return uint32_t : the word value of the address.
|
||||
*/
|
||||
uint32_t Cache_Get_IROM_MMU_End(void);
|
||||
|
||||
/**
|
||||
* @brief Get the cache MMU DROM end address.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return uint32_t : the word value of the address.
|
||||
*/
|
||||
uint32_t Cache_Get_DROM_MMU_End(void);
|
||||
|
||||
/**
|
||||
* @brief Configure cache MMU page size according to instruction and rodata size
|
||||
*
|
||||
* @param irom_size The instruction cache MMU page size
|
||||
* @param drom_size The rodata data cache MMU page size
|
||||
*/
|
||||
void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
|
||||
|
||||
/**
|
||||
* @brief Lock the permission control section configuration. After lock, any
|
||||
* configuration modification will be bypass. Digital reset will clear the lock!
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Pms_Lock(int ibus);
|
||||
|
||||
/**
|
||||
* @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ibus_boundary0_addr : vaddress for split line0
|
||||
*
|
||||
* @param uint32_t ibus_boundary1_addr : vaddress for split line1
|
||||
*
|
||||
* @param uint32_t ibus_boundary2_addr : vaddress for split line2
|
||||
*
|
||||
* @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
|
||||
*/
|
||||
int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr);
|
||||
|
||||
/**
|
||||
* @brief Set three ibus pms attribute, which will determine pms in different section and world.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t ibus_pms_sct2_attr : attr for section2
|
||||
*
|
||||
* @param uint32_t ibus_pms_sct1_attr : attr for section1
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr);
|
||||
|
||||
/**
|
||||
* @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t dbus_boundary0_addr : vaddress for split line0
|
||||
*
|
||||
* @param uint32_t dbus_boundary1_addr : vaddress for split line1
|
||||
*
|
||||
* @param uint32_t dbus_boundary2_addr : vaddress for split line2
|
||||
*
|
||||
* @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
|
||||
*/
|
||||
int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr);
|
||||
|
||||
/**
|
||||
* @brief Set three dbus pms attribute, which will determine pms in different section and world.
|
||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param uint32_t dbus_pms_sct2_attr : attr for section2
|
||||
*
|
||||
* @param uint32_t dbus_pms_sct1_attr : attr for section1
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_CACHE_H_ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user