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Merge branch 'bugfix/cleanup_aes_192_references_for_unsupported_chips' into 'master'

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fix(esp_rom): Remove AES - 192 references for unsupported chips

See merge request espressif/esp-idf!37506
This commit is contained in:
Mahavir Jain
2025-03-10 14:06:25 +08:00
parent 54cfdce964 49e1e22f72
commit 87024c3da1
11 changed files with 13 additions and 19 deletions
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3
components/esp_rom/esp32c3/include/esp32c3/rom/aes.h
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@@ -23,8 +23,7 @@ enum AES_TYPE {
enum AES_BITS { enum AES_BITS {
AES128, AES128,
AES192, AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
AES256
}; };
void ets_aes_enable(void); void ets_aes_enable(void);

3
components/esp_rom/esp32c5/include/esp32c5/rom/aes.h
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@@ -23,8 +23,7 @@ enum AES_TYPE {
enum AES_BITS { enum AES_BITS {
AES128, AES128,
AES192, AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
AES256
}; };
void ets_aes_enable(void); void ets_aes_enable(void);

3
components/esp_rom/esp32c6/include/esp32c6/rom/aes.h
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@@ -23,8 +23,7 @@ enum AES_TYPE {
enum AES_BITS { enum AES_BITS {
AES128, AES128,
AES192, AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
AES256
}; };
void ets_aes_enable(void); void ets_aes_enable(void);

3
components/esp_rom/esp32h2/include/esp32h2/rom/aes.h
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@@ -23,8 +23,7 @@ enum AES_TYPE {
enum AES_BITS { enum AES_BITS {
AES128, AES128,
AES192, AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
AES256
}; };
void ets_aes_enable(void); void ets_aes_enable(void);

3
components/esp_rom/esp32p4/include/esp32p4/rom/aes.h
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@@ -23,8 +23,7 @@ enum AES_TYPE {
enum AES_BITS { enum AES_BITS {
AES128, AES128,
AES192, AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
AES256
}; };
void ets_aes_enable(void); void ets_aes_enable(void);

3
components/esp_rom/esp32s3/include/esp32s3/rom/aes.h
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@@ -20,8 +20,7 @@ enum AES_TYPE {
enum AES_BITS { enum AES_BITS {
AES128, AES128,
AES192, AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */
AES256
}; };
void ets_aes_enable(void); void ets_aes_enable(void);

4
components/soc/esp32c5/register/soc/aes_reg.h
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@@ -210,11 +210,11 @@ extern "C" {
/** AES_MODE : R/W; bitpos: [2:0]; default: 0; /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.\\ * Configures the key length and encryption / decryption of the AES accelerator.\\
* 0: AES-128 encryption\\ * 0: AES-128 encryption\\
* 1: AES-192 encryption\\ * 1: Reserved\\
* 2: AES-256 encryption\\ * 2: AES-256 encryption\\
* 3: Reserved\\ * 3: Reserved\\
* 4: AES-128 decryption\\ * 4: AES-128 decryption\\
* 5: AES-192 decryption\\ * 5: Reserved\\
* 6: AES-256 decryption\\ * 6: AES-256 decryption\\
* 7: Reserved\\ * 7: Reserved\\
*/ */

2
components/soc/esp32c6/register/soc/aes_reg.h
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@@ -209,7 +209,7 @@ extern "C" {
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) #define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0; /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. * Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
*/ */
#define AES_MODE 0x00000007U #define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S) #define AES_MODE_M (AES_MODE_V << AES_MODE_S)

2
components/soc/esp32h2/register/soc/aes_reg.h
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@@ -209,7 +209,7 @@ extern "C" {
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) #define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0; /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. * Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
*/ */
#define AES_MODE 0x00000007U #define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S) #define AES_MODE_M (AES_MODE_V << AES_MODE_S)

4
components/soc/esp32h4/register/soc/aes_reg.h
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@@ -210,11 +210,11 @@ extern "C" {
/** AES_MODE : R/W; bitpos: [2:0]; default: 0; /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator. * Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption * 0: AES-128 encryption
* 1: AES-192 encryption * 1: Reserved
* 2: AES-256 encryption * 2: AES-256 encryption
* 3: Reserved * 3: Reserved
* 4: AES-128 decryption * 4: AES-128 decryption
* 5: AES-192 decryption * 5: Reserved
* 6: AES-256 decryption * 6: AES-256 decryption
* 7: Reserved * 7: Reserved
*/ */

2
components/soc/esp32p4/register/soc/aes_reg.h
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@@ -209,7 +209,7 @@ extern "C" {
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) #define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0; /** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. * Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
*/ */
#define AES_MODE 0x00000007U #define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S) #define AES_MODE_M (AES_MODE_V << AES_MODE_S)