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fix(usb_serial_jtag): Fix issue that use u32_reg read/write cannot be used to modify fifo regs

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This commit is contained in:
C.S.M
2024-07-03 14:49:02 +08:00
parent 15c4d0e076
commit 8b2350ce1c
11 changed files with 28 additions and 33 deletions
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4
components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
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@@ -117,7 +117,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
int i; int i;
for (i = 0; i < (int)rd_len; i++) { for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
} }
return i; return i;
} }
@@ -136,7 +136,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
int i; int i;
for (i = 0; i < (int)wr_len; i++) { for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
} }
return i; return i;
} }

4
components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h
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@@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
int i; int i;
for (i = 0; i < (int)rd_len; i++) { for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
} }
return i; return i;
} }
@@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
int i; int i;
for (i = 0; i < (int)wr_len; i++) { for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
} }
return i; return i;
} }

4
components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h
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@@ -117,7 +117,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
int i; int i;
for (i = 0; i < (int)rd_len; i++) { for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
} }
return i; return i;
} }
@@ -136,7 +136,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
int i; int i;
for (i = 0; i < (int)wr_len; i++) { for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
} }
return i; return i;
} }

4
components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
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@@ -117,7 +117,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
int i; int i;
for (i = 0; i < (int)rd_len; i++) { for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
} }
return i; return i;
} }
@@ -136,7 +136,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
int i; int i;
for (i = 0; i < (int)wr_len; i++) { for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
} }
return i; return i;
} }

4
components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h
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@@ -120,7 +120,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
int i; int i;
for (i = 0; i < (int)rd_len; i++) { for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
} }
return i; return i;
} }
@@ -139,7 +139,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
int i; int i;
for (i = 0; i < (int)wr_len; i++) { for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
} }
return i; return i;
} }

4
components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
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@@ -119,7 +119,7 @@ static inline uint32_t usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_
uint32_t i; uint32_t i;
for (i = 0; i < rd_len; i++) { for (i = 0; i < rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
} }
return i; return i;
} }
@@ -138,7 +138,7 @@ static inline uint32_t usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint3
uint32_t i; uint32_t i;
for (i = 0; i < wr_len; i++) { for (i = 0; i < wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
} }
return i; return i;
} }

3
components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
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@@ -23,8 +23,7 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO. * how many data is received, then read data from UART Rx FIFO.
*/ */
uint32_t rdwr_byte:8; uint32_t rdwr_byte:32;
uint32_t reserved_8:24;
}; };
uint32_t val; uint32_t val;
} usb_serial_jtag_ep1_reg_t; } usb_serial_jtag_ep1_reg_t;

9
components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h
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@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -23,8 +23,7 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO. * how many data is received, then read data from UART Rx FIFO.
*/ */
uint32_t rdwr_byte:8; uint32_t rdwr_byte:32;
uint32_t reserved_8:24;
}; };
uint32_t val; uint32_t val;
} usb_serial_jtag_ep1_reg_t; } usb_serial_jtag_ep1_reg_t;
@@ -131,7 +130,7 @@ typedef union {
*/ */
uint32_t test_enable:1; uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0; /** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test * USB pad output enable in test
*/ */
uint32_t test_usb_oe:1; uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0; /** test_tx_dp : R/W; bitpos: [2]; default: 0;
@@ -290,7 +289,7 @@ typedef union {
*/ */
uint32_t serial_out_afifo_reset_rd:1; uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain. * CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/ */
uint32_t serial_out_afifo_rempty:1; uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;

7
components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h
View File

@@ -23,8 +23,7 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO. * how many data is received, then read data from UART Rx FIFO.
*/ */
uint32_t rdwr_byte:8; uint32_t rdwr_byte:32;
uint32_t reserved_8:24;
}; };
uint32_t val; uint32_t val;
} usb_serial_jtag_ep1_reg_t; } usb_serial_jtag_ep1_reg_t;
@@ -131,7 +130,7 @@ typedef union {
*/ */
uint32_t test_enable:1; uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0; /** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test * USB pad output enable in test
*/ */
uint32_t test_usb_oe:1; uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0; /** test_tx_dp : R/W; bitpos: [2]; default: 0;
@@ -290,7 +289,7 @@ typedef union {
*/ */
uint32_t serial_out_afifo_reset_rd:1; uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain. * CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/ */
uint32_t serial_out_afifo_rempty:1; uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;

9
components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
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@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -23,8 +23,7 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO. * how many data is received, then read data from UART Rx FIFO.
*/ */
uint32_t rdwr_byte:8; uint32_t rdwr_byte:32;
uint32_t reserved_8:24;
}; };
uint32_t val; uint32_t val;
} usb_serial_jtag_ep1_reg_t; } usb_serial_jtag_ep1_reg_t;
@@ -131,7 +130,7 @@ typedef union {
*/ */
uint32_t test_enable:1; uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0; /** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test * USB pad output enable in test
*/ */
uint32_t test_usb_oe:1; uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0; /** test_tx_dp : R/W; bitpos: [2]; default: 0;
@@ -290,7 +289,7 @@ typedef union {
*/ */
uint32_t serial_out_afifo_reset_rd:1; uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain. * CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/ */
uint32_t serial_out_afifo_rempty:1; uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;

9
components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h
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@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -23,8 +23,7 @@ typedef union {
* USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
* received, then read data from UART Rx FIFO. * received, then read data from UART Rx FIFO.
*/ */
uint32_t rdwr_byte:8; uint32_t rdwr_byte:32;
uint32_t reserved_8:24;
}; };
uint32_t val; uint32_t val;
} usb_serial_jtag_ep1_reg_t; } usb_serial_jtag_ep1_reg_t;
@@ -131,7 +130,7 @@ typedef union {
*/ */
uint32_t test_enable:1; uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0; /** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test * USB pad output enable in test
*/ */
uint32_t test_usb_oe:1; uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0; /** test_tx_dp : R/W; bitpos: [2]; default: 0;
@@ -290,7 +289,7 @@ typedef union {
*/ */
uint32_t serial_out_afifo_reset_rd:1; uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain. * CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/ */
uint32_t serial_out_afifo_rempty:1; uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;