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refactor(sd): updated sd host api to make 0 value as no change to configurations

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use value 0 for `sd_host_slot_cfg_t` members, means no change to previous configurations,
instead of using `override/valid` flag
This commit is contained in:
armando
2025-05-15 15:16:23 +08:00
parent c2b8ea07d0
commit 8f6a2370d2
4 changed files with 38 additions and 56 deletions
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32
components/esp_driver_sd_intf/include/driver/sd_types.h
View File

@@ -29,35 +29,21 @@ typedef struct sd_slot_driver_t *sd_host_slot_handle_t;
* @brief SD Host slot configuration
*/
typedef struct {
struct {
int freq_hz; ///< Frequency in Hz
bool override; ///< If set to true, frequency will be set to freq_hz; If set to false, frequency is unchanged. By default it's false
} freq; ///< Frequency settings
struct {
bool override; ///< If set to true, width will be set to width configured in `sd_host_sdmmc_slot_io_cfg_t`; If set to false, width is unchanged. By default it's false
} width; ///< Bus width settings
struct {
sd_sampling_mode_t mode; ///< Sampling mode, see `sd_sampling_mode_t`
bool override; ///< If set to true, sampling mode will be set to sampling_mode; If set to false, sampling mode is unchanged. By default it's false
} sampling_mode; ///< Sampling mode settings
struct {
sdmmc_delay_phase_t delayphase; ///< Delay phase, see `sdmmc_delay_phase_t`
bool override; ///< If set to true, delay phase will be set to delay_phase; If set to false, delay phase is unchanged. By default it's false
} delay_phase; ///< Delay phase settings
struct {
sdmmc_delay_line_t delayline; ///< Delay line, see `sdmmc_delay_line_t`
bool override; ///< If set to true, delay line will be set to delay_line; If set to false, delay line is unchanged. By default it's false
} delay_line; ///< Delay line settings
int freq_hz; ///< Frequency in Hz
sd_bus_width_t width; ///< Bus width
sd_sampling_mode_t sampling_mode; ///< Sampling mode, see `sd_sampling_mode_t`
sdmmc_delay_phase_t delayphase; ///< Delay phase, see `sdmmc_delay_phase_t`
sdmmc_delay_line_t delayline; ///< Delay line, see `sdmmc_delay_line_t`
} sd_host_slot_cfg_t;
/**
* @brief Slot info
*/
typedef struct {
int freq_hz; ///< Frequency in Hz
uint8_t width; ///< Bus width
sd_mode_t sd_mode; ///< SD mode, see `sd_mode_t`
sd_sampling_mode_t sampling_mode; ///< Sampling mode, see `sd_sampling_mode_t`
int freq_hz; ///< Frequency in Hz
sd_bus_width_t width; ///< Bus width
sd_mode_t sd_mode; ///< SD mode, see `sd_mode_t`
sd_sampling_mode_t sampling_mode; ///< Sampling mode, see `sd_sampling_mode_t`
} sd_host_slot_info_t;
/*---------------------------------------------

14
components/esp_driver_sdmmc/legacy/src/sdmmc_host.c
View File

@@ -33,8 +33,7 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz)
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
sd_host_slot_cfg_t cfg = {
.freq.freq_hz = freq_khz * 1000,
.freq.override = true,
.freq_hz = freq_khz * 1000,
};
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot freq");
@@ -57,8 +56,7 @@ esp_err_t sdmmc_host_set_input_delay(int slot, sdmmc_delay_phase_t delay_phase)
SLOT_CHECK(slot);
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
sd_host_slot_cfg_t cfg = {
.delay_phase.delayphase = delay_phase,
.delay_phase.override = true,
.delayphase = delay_phase,
};
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot delay phase");
@@ -70,8 +68,7 @@ esp_err_t sdmmc_host_set_input_delayline(int slot, sdmmc_delay_line_t delay_line
SLOT_CHECK(slot);
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
sd_host_slot_cfg_t cfg = {
.delay_line.delayline = delay_line,
.delay_line.override = true,
.delayline = delay_line,
};
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot delay line");
@@ -181,7 +178,7 @@ esp_err_t sdmmc_host_set_bus_width(int slot, size_t width)
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
sd_host_slot_cfg_t cfg = {
.width.override = true,
.width = width,
};
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot bus width");
@@ -204,8 +201,7 @@ esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled)
{
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
sd_host_slot_cfg_t cfg = {
.sampling_mode.mode = ddr_enabled ? SD_SAMPLING_MODE_DDR : SD_SAMPLING_MODE_SDR,
.sampling_mode.override = true,
.sampling_mode = ddr_enabled ? SD_SAMPLING_MODE_DDR : SD_SAMPLING_MODE_SDR,
};
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot ddr mode");

24
components/esp_driver_sdmmc/src/sd_host_sdmmc.c
View File

@@ -201,20 +201,20 @@ static esp_err_t sd_host_slot_sdmmc_configure(sd_host_slot_handle_t slot, const
{
ESP_RETURN_ON_FALSE(slot && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
#if SDMMC_LL_DELAY_PHASE_SUPPORTED
ESP_RETURN_ON_FALSE(config->delay_phase.delayphase < SOC_SDMMC_DELAY_PHASE_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid delay phase");
ESP_RETURN_ON_FALSE(config->delayphase < (SOC_SDMMC_DELAY_PHASE_NUM + 1), ESP_ERR_INVALID_ARG, TAG, "invalid delay phase");
#else
//DIG-217
ESP_LOGW(TAG, "esp32 doesn't support input phase delay, fallback to 0 delay");
#endif
#if SOC_SDMMC_UHS_I_SUPPORTED
ESP_RETURN_ON_FALSE(config->delay_line.delayline < SOC_SDMMC_DELAY_PHASE_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid delay line");
ESP_RETURN_ON_FALSE(config->delayline < (SOC_SDMMC_DELAY_PHASE_NUM + 1), ESP_ERR_INVALID_ARG, TAG, "invalid delay line");
#else
ESP_LOGW(TAG, "input line delay not supported, fallback to 0 delay");
#endif
#if CONFIG_IDF_TARGET_ESP32P4
if (config->freq.freq_hz == SDMMC_FREQ_SDR104 * 1000) {
if (config->freq_hz == SDMMC_FREQ_SDR104 * 1000) {
unsigned chip_version = efuse_hal_chip_revision();
ESP_LOGD(TAG, "chip_version: %d", chip_version);
if (!ESP_CHIP_REV_ABOVE(chip_version, 200)) {
@@ -225,28 +225,28 @@ static esp_err_t sd_host_slot_sdmmc_configure(sd_host_slot_handle_t slot, const
sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv);
portENTER_CRITICAL(&slot_ctx->ctlr->spinlock);
if (config->freq.override) {
slot_ctx->freq.freq_hz = config->freq.freq_hz;
if (config->freq_hz != 0) {
slot_ctx->freq.freq_hz = config->freq_hz;
slot_ctx->freq.freq_state = SD_HOST_SLOT_STATE_READY;
}
if (config->width.override) {
if (config->width != 0) {
slot_ctx->width.width_state = SD_HOST_SLOT_STATE_READY;
}
if (config->sampling_mode.override) {
slot_ctx->sampling_mode.mode = config->sampling_mode.mode;
if (config->sampling_mode != 0) {
slot_ctx->sampling_mode.mode = config->sampling_mode;
slot_ctx->sampling_mode.sampling_mode_state = SD_HOST_SLOT_STATE_READY;
}
if (config->delay_phase.override) {
if (config->delayphase != 0) {
#if SDMMC_LL_DELAY_PHASE_SUPPORTED
slot_ctx->delay_phase.delayphase = config->delay_phase.delayphase;
slot_ctx->delay_phase.delayphase = config->delayphase;
#else
slot_ctx->delay_phase.delayphase = SDMMC_DELAY_PHASE_0;
#endif
slot_ctx->delay_phase.delay_phase_state = SD_HOST_SLOT_STATE_READY;
}
if (config->delay_line.override) {
if (config->delayline != 0) {
#if SOC_SDMMC_UHS_I_SUPPORTED
slot_ctx->delay_line.delayline = config->delay_line.delayline;
slot_ctx->delay_line.delayline = config->delayline;
#else
slot_ctx->delay_line.delayline = SDMMC_DELAY_LINE_0;
#endif

24
components/hal/include/hal/sd_types.h
View File

@@ -33,8 +33,8 @@ typedef enum {
* @brief SD sampling mode
*/
typedef enum {
SD_SAMPLING_MODE_SDR, ///< Single data rate mode
SD_SAMPLING_MODE_DDR, ///< Double data rate mode
SD_SAMPLING_MODE_SDR = 1, ///< Single data rate mode
SD_SAMPLING_MODE_DDR, ///< Double data rate mode
} sd_sampling_mode_t;
/**
@@ -49,7 +49,7 @@ typedef enum {
* Driver will print out how long the delay is, in picosecond (ps).
*/
typedef enum {
SDMMC_DELAY_PHASE_0, /*!< Delay phase 0 */
SDMMC_DELAY_PHASE_0 = 1, /*!< Delay phase 0 */
SDMMC_DELAY_PHASE_1, /*!< Delay phase 1 */
SDMMC_DELAY_PHASE_2, /*!< Delay phase 2 */
SDMMC_DELAY_PHASE_3, /*!< Delay phase 3 */
@@ -64,15 +64,15 @@ typedef enum {
* @brief SD/MMC Host clock timing delay lines
*/
typedef enum {
SDMMC_DELAY_LINE_0, /*!< Delay line 0 */
SDMMC_DELAY_LINE_1, /*!< Delay line 1 */
SDMMC_DELAY_LINE_2, /*!< Delay line 2 */
SDMMC_DELAY_LINE_3, /*!< Delay line 3 */
SDMMC_DELAY_LINE_4, /*!< Delay line 4 */
SDMMC_DELAY_LINE_5, /*!< Delay line 5 */
SDMMC_DELAY_LINE_6, /*!< Delay line 6 */
SDMMC_DELAY_LINE_7, /*!< Delay line 7 */
SDMMC_DELAY_LINE_AUTO, /*!< Auto detect line */
SDMMC_DELAY_LINE_0 = 1, /*!< Delay line 0 */
SDMMC_DELAY_LINE_1, /*!< Delay line 1 */
SDMMC_DELAY_LINE_2, /*!< Delay line 2 */
SDMMC_DELAY_LINE_3, /*!< Delay line 3 */
SDMMC_DELAY_LINE_4, /*!< Delay line 4 */
SDMMC_DELAY_LINE_5, /*!< Delay line 5 */
SDMMC_DELAY_LINE_6, /*!< Delay line 6 */
SDMMC_DELAY_LINE_7, /*!< Delay line 7 */
SDMMC_DELAY_LINE_AUTO, /*!< Auto detect line */
} sdmmc_delay_line_t;
#if SOC_SDMMC_DATA_WIDTH_MAX