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refactor(clk): deprecate SOC_RTC_FAST_CLK_SRC_XTAL_DIV

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This commit is contained in:
Song Ruo Jing
2024-08-06 21:55:21 +08:00
parent ce6085349f
commit 92ed77933b
38 changed files with 115 additions and 37 deletions
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2
components/bootloader_support/src/bootloader_clock_init.c
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@@ -64,7 +64,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
// RTC_FAST clock source will be switched to RC_FAST at application startup
clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_DEFAULT;
}
#if CONFIG_IDF_TARGET_ESP32C6

2
components/esp_hw_support/port/esp32/include/soc/rtc.h
View File

@@ -726,7 +726,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 4
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4 //!< Main XTAL, divided by 4
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
/**

2
components/esp_hw_support/port/esp32c2/include/soc/rtc.h
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@@ -715,7 +715,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
/**

2
components/esp_hw_support/port/esp32c3/include/soc/rtc.h
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@@ -784,7 +784,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
/**

2
components/esp_hw_support/port/esp32c6/include/soc/rtc.h
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@@ -465,7 +465,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
/**

2
components/esp_hw_support/port/esp32h2/include/soc/rtc.h
View File

@@ -462,7 +462,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
/**

2
components/esp_hw_support/port/esp32s2/include/soc/rtc.h
View File

@@ -864,7 +864,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 4
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4 //!< Main XTAL, divided by 4
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
/**

2
components/esp_hw_support/port/esp32s3/include/soc/rtc.h
View File

@@ -842,7 +842,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
/**

20
components/esp_hw_support/port/esp_clk_tree_common.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -177,23 +177,23 @@ uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
{
switch (clk_ll_rtc_fast_get_src()) {
case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 //SOC_RTC_FAST_CLK_SRC_XTAL_D4
return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
#elif CONFIG_IDF_TARGET_ESP32P4 //SOC_RTC_FAST_CLK_SRC_XTAL
return clk_hal_xtal_get_freq_mhz() * MHZ;
#else //SOC_RTC_FAST_CLK_SRC_XTAL_D2
return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
#endif
case SOC_RTC_FAST_CLK_SRC_RC_FAST:
return esp_clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
#if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
case SOC_RTC_FAST_CLK_SRC_LP_PLL:
return clk_ll_lp_pll_get_freq_mhz() * MHZ;
#endif
#if SOC_CLK_LP_FAST_SUPPORT_XTAL && !CONFIG_IDF_TARGET_ESP32P4 // On P4 SOC_RTC_FAST_CLK_SRC_XTAL is an alias for SOC_RTC_FAST_CLK_SRC_XTAL_DIV
#if SOC_CLK_LP_FAST_SUPPORT_XTAL
case SOC_RTC_FAST_CLK_SRC_XTAL:
return clk_hal_xtal_get_freq_mhz() * MHZ;
#endif
#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
#endif
#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
case SOC_RTC_FAST_CLK_SRC_XTAL_D4:
return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
#endif
default:
// Invalid clock source

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@@ -899,6 +899,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
bool
default y
config SOC_SDMMC_USE_IOMUX
bool
default y

7
components/soc/esp32/include/soc/clk_tree_defs.h
View File

@@ -21,7 +21,7 @@ extern "C" {
*
* 2) External 2~40MHz Crystal Clock: XTAL
*
* 3) Internal 150kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
* 3) Internal 150kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
*
* This RC oscillator generates a ~150kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
@@ -86,9 +86,12 @@ typedef enum {
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0, /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< XTAL_D4_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32/include/soc/soc_caps.h
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@@ -426,6 +426,8 @@
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D4 (1) /*!< Support XTAL_D4 clock as the LP_FAST clock source */
/*-------------------------- SDMMC CAPS -----------------------------------------*/
/* On ESP32, clock/cmd/data pins use IO MUX.

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@@ -755,6 +755,10 @@ config SOC_CLK_OSC_SLOW_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_WIFI_HW_TSF
bool
default y

7
components/soc/esp32c2/include/soc/clk_tree_defs.h
View File

@@ -21,7 +21,7 @@ extern "C" {
*
* 2) External 26/40MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
@@ -82,9 +82,12 @@ typedef enum {
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32c2/include/soc/soc_caps.h
View File

@@ -336,6 +336,8 @@
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< ESP32C2 only supports to connect an external oscillator, not a crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
/*------------------------------------ WI-FI CAPS ------------------------------------*/
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@@ -1075,6 +1075,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
bool
default y

7
components/soc/esp32c3/include/soc/clk_tree_defs.h
View File

@@ -21,7 +21,7 @@ extern "C" {
*
* 2) External 40MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
@@ -83,9 +83,12 @@ typedef enum {
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32c3/include/soc/soc_caps.h
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@@ -450,6 +450,8 @@
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -1419,6 +1419,10 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_RCC_IS_INDEPENDENT
bool
default y

3
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@@ -92,9 +92,10 @@ typedef enum {
typedef enum {
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_XTAL = 2, /*!< Select XTAL_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -593,6 +593,8 @@
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@@ -1463,6 +1463,10 @@ config SOC_CLK_RC32K_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_RCC_IS_INDEPENDENT
bool
default y

5
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@@ -96,8 +96,11 @@ typedef enum {
typedef enum {
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32c6/include/soc/soc_caps.h
View File

@@ -573,6 +573,8 @@
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -1031,6 +1031,10 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_RCC_IS_INDEPENDENT
bool
default y

3
components/soc/esp32c61/include/soc/clk_tree_defs.h
View File

@@ -89,9 +89,10 @@ typedef enum {
typedef enum {
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_XTAL = 2, /*!< Select XTAL_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -463,6 +463,8 @@
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -1423,6 +1423,10 @@ config SOC_CLK_LP_FAST_SUPPORT_LP_PLL
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y

5
components/soc/esp32h2/include/soc/clk_tree_defs.h
View File

@@ -97,9 +97,12 @@ typedef enum {
typedef enum {
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)*/
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
} soc_rtc_fast_clk_src_t;
/**

3
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -555,7 +555,8 @@
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */
#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */

9
components/soc/esp32p4/include/soc/clk_tree_defs.h
View File

@@ -103,9 +103,12 @@ typedef enum {
typedef enum {
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL = 1, /*!< Select XTAL_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */
SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K) */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< XTAL_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */
} soc_rtc_fast_clk_src_t;
/**
@@ -159,8 +162,8 @@ typedef enum {
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
SOC_MOD_CLK_LP_PLL, /*!< LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz */
SOC_MOD_CLK_LP_DYN_FAST, /*!< LP_DYN_FAST can be derived from RTC_SLOW_CLK or RTC_FAST_CLK depending on the chip’s power mode:
in active mode, select RTC_FAST_CLK as the clock source;
in light/deep sleep mode, select RTC_SLOW_CLK as the clock source */
Only in LP_SLEEP mode, select RTC_SLOW_CLK as the clock source;
In other non-LP_SLEEP mode, select RTC_FAST_CLK as the clock source; */
SOC_MOD_CLK_LP_PERI, /*!< LP_PERI_CLK is derived from LP_DYN_FAST (configurable divider) */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;

1
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -738,7 +738,6 @@
#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */
#define SOC_PERIPH_CLK_CTRL_SHARED (1) /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
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@@ -1151,6 +1151,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
bool
default y
config SOC_COEX_HW_PTI
bool
default y

7
components/soc/esp32s2/include/soc/clk_tree_defs.h
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@@ -21,7 +21,7 @@ extern "C" {
*
* 2) External 40MHz Crystal Clock: XTAL
*
* 3) Internal 90kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
* 3) Internal 90kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
*
* This RC oscillator generates a ~90kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
@@ -84,9 +84,12 @@ typedef enum {
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0, /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< XTAL_D4_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32s2/include/soc/soc_caps.h
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@@ -482,6 +482,8 @@
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D4 (1) /*!< Support XTAL_D4 clock as the LP_FAST clock source */
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/* ---------------------------- Compatibility ------------------------------- */

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@@ -1243,6 +1243,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default y

7
components/soc/esp32s3/include/soc/clk_tree_defs.h
View File

@@ -21,7 +21,7 @@ extern "C" {
*
* 2) External 40MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
@@ -83,9 +83,12 @@ typedef enum {
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
} soc_rtc_fast_clk_src_t;
/**

2
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -484,6 +484,8 @@
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1