feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

Merge branch 'esp32/run_panic_debug_v5.3' into 'release/v5.3'

Browse Source 
fix(esp32): Fixed qa program may fail issue when cpu 240m (v5.3)

See merge request espressif/esp-idf!37233
This commit is contained in:
Jiang Jiang Jian
2025-04-22 10:20:30 +08:00
parent 8b725deb56 bb0dac0a72
commit 9312c3595e
2 changed files with 3 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
components/esp_hw_support/port/esp32/include/soc/rtc.h
View File

@@ -66,16 +66,13 @@ extern "C" {
/* Core voltage needs to be increased in two cases:
* 1. running at 240 MHz
* 2. running with 80MHz Flash frequency
*
* There is a record in efuse which indicates the proper voltage for these two cases.
*/
#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - efuse_ll_get_vol_level_hp_inv())
#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25
#else
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
#endif
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00

1
components/esp_hw_support/port/esp32/rtc_clk.c
View File

@@ -400,6 +400,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
rtc_clk_apb_freq_update(80 * MHZ);
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
rtc_clk_wait_for_slow_cycle();
esp_rom_delay_us(30);
}
void rtc_clk_cpu_freq_set_xtal(void)