forked from espressif/esp-idf
fix(i2s): return error when mclk_div is smaller than 2
This commit is contained in:
@@ -44,8 +44,8 @@ static esp_err_t i2s_pdm_tx_calculate_clock(i2s_chan_handle_t handle, const i2s_
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clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
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clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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/* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
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ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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/* Set up sampling configuration */
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i2s_ll_tx_set_pdm_fpfs(handle->controller->hal.dev, pdm_tx_clk->up_sample_fp, pdm_tx_clk->up_sample_fs);
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i2s_ll_tx_set_pdm_over_sample_ratio(handle->controller->hal.dev, over_sample_ratio);
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@@ -342,8 +342,8 @@ static esp_err_t i2s_pdm_rx_calculate_clock(i2s_chan_handle_t handle, const i2s_
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clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
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clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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/* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
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ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
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/* Set down-sampling configuration */
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i2s_ll_rx_set_pdm_dsr(handle->controller->hal.dev, pdm_rx_clk->dn_sample_mode);
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return ESP_OK;
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@@ -51,13 +51,15 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std
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#if SOC_I2S_HW_VERSION_2
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clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ?
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clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
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float min_mclk_div = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? 0.99 : 1.99;
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#else
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clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
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float min_mclk_div = 1.99;
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#endif
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clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large for the current clock source");
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/* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
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ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > min_mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate or mclk_multiple is too large for the current clock source");
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return ESP_OK;
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}
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@@ -61,10 +61,11 @@ static esp_err_t i2s_tdm_calculate_clock(i2s_chan_handle_t handle, const i2s_tdm
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}
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clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ?
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clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk);
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float min_mclk_div = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? 0.99 : 1.99;
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clk_info->mclk_div = clk_info->sclk / clk_info->mclk;
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/* Check if the configuration is correct */
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ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large for the current clock source");
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/* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */
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ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > min_mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate or mclk_multiple is too large for the current clock source");
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return ESP_OK;
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}
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@@ -904,7 +904,11 @@ TEST_CASE("I2S_package_lost_test", "[i2s]")
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TEST_ESP_OK(i2s_channel_register_event_callback(rx_handle, &cbs, &count));
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uint32_t test_freq[] = {16000, 32000, 48000, 64000, 96000, 128000, 144000};
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#if CONFIG_IDF_TARGET_ESP32P4
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uint32_t test_num = 4;
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#else
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uint32_t test_num = sizeof(test_freq) / sizeof(uint32_t);
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#endif // CONFIG_IDF_TARGET_ESP32P4
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uint8_t *data = (uint8_t *)calloc(TEST_RECV_BUF_LEN, sizeof(uint8_t));
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size_t bytes_read = 0;
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int i;
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@@ -330,6 +330,13 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external)
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std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL;
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std_cfg.clk_cfg.ext_clk_freq_hz = 22579200;
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}
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#if CONFIG_IDF_TARGET_ESP32P4
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else {
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// Use APLL instead.
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// Because the default clock source is not sufficient for 22.58M MCLK
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std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_APLL;
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}
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#endif
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TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
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TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
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