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Merge branch 'bugfix/multiple_adc_bugfix_v4.4' into 'release/v4.4'

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adc: fix multiple bugs (v4.4)

See merge request espressif/esp-idf!19142
This commit is contained in:
Jiang Jiang Jian
2022-08-04 14:42:53 +08:00
parent bfb88338bb cb62457f6d
commit 9f9021a221
13 changed files with 48 additions and 22 deletions
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2
components/driver/adc.c
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@@ -280,7 +280,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
#endif
.desc_max_num = INTERNAL_BUF_NUM,
.dma_chan = dma_chan,
.eof_num = init_config->conv_num_each_intr / ADC_HAL_DATA_LEN_PER_CONV
.eof_num = init_config->conv_num_each_intr / SOC_ADC_DIGI_DATA_BYTES_PER_CONV
};
adc_hal_context_config(&s_adc_digi_ctx->hal, &config);

24
components/hal/adc_hal.c
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@@ -14,6 +14,7 @@
#if CONFIG_IDF_TARGET_ESP32
//ADC utilises I2S0 DMA on ESP32
#include "hal/i2s_hal.h"
#include "hal/i2s_ll.h"
#include "hal/i2s_types.h"
#include "soc/i2s_struct.h"
@@ -232,14 +233,21 @@ static void adc_hal_digi_sample_freq_config(adc_hal_context_t *hal, uint32_t fre
adc_ll_digi_clk_sel(0); //use APB
#else
i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_D2CLK); /*!< Clock from PLL_D2_CLK(160M)*/
uint32_t bck = I2S_BASE_CLK / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_B_DEFAULT / ADC_LL_CLKM_DIV_A_DEFAULT) / 2 / freq;
i2s_ll_mclk_div_t clk = {
.mclk_div = ADC_LL_CLKM_DIV_NUM_DEFAULT,
.a = ADC_LL_CLKM_DIV_A_DEFAULT,
.b = ADC_LL_CLKM_DIV_B_DEFAULT,
uint32_t bclk_div = 16;
uint32_t bclk = freq * 2;
uint32_t mclk = bclk * bclk_div;
uint32_t mclk_div = I2S_BASE_CLK / mclk;
i2s_hal_clock_cfg_t i2s_hal_clk_cfg = {
.sclk = I2S_BASE_CLK,
.bclk = bclk,
.bclk_div = bclk_div,
.mclk = mclk ,
.mclk_div = mclk_div,
};
i2s_ll_rx_set_clk(hal->dev, &clk);
i2s_ll_rx_set_bck_div_num(hal->dev, bck);
i2s_ll_mclk_div_t mclk_set = {};
i2s_hal_mclk_div_decimal_cal(&i2s_hal_clk_cfg, &mclk_set);
i2s_ll_rx_set_clk(hal->dev, &mclk_set);
i2s_ll_rx_set_bck_div_num(hal->dev, i2s_hal_clk_cfg.bclk_div);
#endif
}
@@ -350,7 +358,7 @@ void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf)
//reset the current descriptor address
hal->cur_desc_ptr = &hal->desc_dummy_head;
adc_hal_digi_dma_link_descriptors(hal->rx_desc, data_buf, hal->eof_num * ADC_HAL_DATA_LEN_PER_CONV, hal->desc_max_num);
adc_hal_digi_dma_link_descriptors(hal->rx_desc, data_buf, hal->eof_num * SOC_ADC_DIGI_DATA_BYTES_PER_CONV, hal->desc_max_num);
//start DMA
adc_dma_ll_rx_start(hal->dev, hal->dma_chan, (lldesc_t *)hal->rx_desc);

2
components/hal/i2s_hal.c
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@@ -19,7 +19,7 @@
* @param clk_cfg I2S clock configuration(input)
* @param cal Point to `i2s_ll_mclk_div_t` structure(output).
*/
static void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mclk_div_t *cal)
void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mclk_div_t *cal)
{
int ma = 0;
int mb = 0;

3
components/hal/include/hal/adc_hal.h
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@@ -36,9 +36,6 @@
#define ADC_HAL_DMA_INTR_MASK BIT(9)
#endif
//For ADC module, each conversion contains 4 bytes
#define ADC_HAL_DATA_LEN_PER_CONV 4
typedef enum adc_hal_work_mode_t {
ADC_HAL_ULP_MODE,
ADC_HAL_SINGLE_READ_MODE,

3
components/hal/include/hal/adc_types.h
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@@ -161,7 +161,8 @@ typedef struct {
typedef struct {
union {
struct {
uint32_t data: 13; /*!<ADC real output data info. Resolution: 13 bit. */
uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint32_t reserved12: 1; /*!<Reserved12. */
uint32_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */

10
components/hal/include/hal/i2s_hal.h
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@@ -125,6 +125,16 @@ void i2s_hal_init(i2s_hal_context_t *hal, int i2s_num);
*/
void i2s_hal_set_clock_src(i2s_hal_context_t *hal, i2s_clock_src_t sel);
/**
* @brief Calculate the closest sample rate clock configuration.
* clock relationship:
* Fmclk = bck_div*fbck = fsclk/(mclk_div+b/a)
*
* @param clk_cfg I2S clock configuration(input)
* @param cal Point to `i2s_ll_mclk_div_t` structure(output).
*/
void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mclk_div_t *cal);
/**
* @brief Set Tx channel style
*

4
components/soc/esp32/include/soc/soc_caps.h
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@@ -89,9 +89,11 @@
#define SOC_ADC_PATT_LEN_MAX (16) //Two pattern table, each contains 16 items. Each item takes 1 byte. But only support ADC1 using DMA mode
#define SOC_ADC_DIGI_MIN_BITWIDTH (9)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (2)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (2*1000*1000)
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW (2000)
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW (20*1000)
/*!< RTC */
#define SOC_ADC_MAX_BITWIDTH (12)

10
components/soc/esp32c3/include/soc/adc_channel.h
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@@ -15,19 +15,19 @@
#ifndef _SOC_ADC_CHANNEL_H
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_GPIO0_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_4
#define ADC1_CHANNEL_4_GPIO_NUM 4
#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0

2
components/soc/esp32c3/include/soc/soc_caps.h
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@@ -56,6 +56,8 @@
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
#define SOC_ADC_DIGI_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */

2
components/soc/esp32h2/include/soc/soc_caps.h
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@@ -45,6 +45,8 @@
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
#define SOC_ADC_DIGI_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */

2
components/soc/esp32s2/include/soc/soc_caps.h
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@@ -69,6 +69,8 @@
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (32) /*!< Two pattern table, each contains 16 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (2)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (2)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611

4
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -58,7 +58,9 @@
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (24) //Two pattern table, each contains 12 items. Each item takes 1 byte
#define SOC_ADC_DIGI_MAX_BITWIDTH (13)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611

2
examples/peripherals/adc/dma_read/main/adc_dma_example_main.c
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@@ -69,7 +69,7 @@ static void continuous_adc_init(uint16_t adc1_chan_mask, uint16_t adc2_chan_mask
adc_digi_configuration_t dig_cfg = {
.conv_limit_en = ADC_CONV_LIMIT_EN,
.conv_limit_num = 250,
.sample_freq_hz = 10 * 1000,
.sample_freq_hz = 20 * 1000,
.conv_mode = ADC_CONV_MODE,
.format = ADC_OUTPUT_TYPE,
};