feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

Merge branch 'refactor/split_esp32s3_soc_include_folder' into 'master'

Browse Source 
refactor(soc): sort esp32s3 soc headers

See merge request espressif/esp-idf!33313
This commit is contained in:
Kevin (Lao Kaiyao)
2024-10-11 18:03:38 +08:00
parent a97a7b0962 c3e0dd610a
commit a0477f3bb4
84 changed files with 415 additions and 823 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
components/soc/esp32s3/include/soc/dport_reg.h
View File

@@ -5,20 +5,19 @@
*/
#pragma once
#include "soc.h"
#include "soc/interrupt_reg.h"
#include "soc/system_reg.h"
#include "soc/sensitive_reg.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "interrupt_reg.h"
#include "system_reg.h"
#include "sensitive_reg.h"
#include "soc.h"
#define DPORT_DATE_REG SYSTEM_DATE_REG
#ifndef __ASSEMBLER__
#include "dport_access.h"
#include "soc/dport_access.h"
#endif
#ifdef __cplusplus

2
components/soc/esp32s3/include/soc/soc.h
View File

@@ -12,7 +12,7 @@
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#include "soc/reg_base.h"
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)

2
components/soc/esp32s3/include/soc/usb_dwc_struct.h
View File

@@ -33,7 +33,7 @@ typedef union {
uint32_t hnpreq: 1;
uint32_t hstsethnpen: 1;
uint32_t devhnpen: 1;
uint32_t ehen: 1;
uint32_t ehen: 1; // codespell:ignore ehen
uint32_t reserved_13: 2;
uint32_t dbncefltrbypass: 1;
uint32_t conidsts: 1;

0
components/soc/esp32s3/register/soc/.gitkeep
View File

2
components/soc/esp32s3/include/soc/apb_ctrl_reg.h → components/soc/esp32s3/register/soc/apb_ctrl_reg.h
View File

@@ -8,7 +8,7 @@
#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

0
components/soc/esp32s3/include/soc/apb_ctrl_struct.h → components/soc/esp32s3/register/soc/apb_ctrl_struct.h
View File

20
components/soc/esp32s3/include/soc/apb_saradc_reg.h → components/soc/esp32s3/register/soc/apb_saradc_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_APB_SARADC_REG_H_
#define _SOC_APB_SARADC_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

0
components/soc/esp32s3/include/soc/apb_saradc_struct.h → components/soc/esp32s3/register/soc/apb_saradc_struct.h
View File

20
components/soc/esp32s3/include/soc/assist_debug_reg.h → components/soc/esp32s3/register/soc/assist_debug_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ASSIST_DEBUG_REG_H_
#define _SOC_ASSIST_DEBUG_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

18
components/soc/esp32s3/include/soc/assist_debug_struct.h → components/soc/esp32s3/register/soc/assist_debug_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
#define _SOC_ASSIST_DEBUG_STRUCT_H_

6
components/soc/esp32s3/include/soc/efuse_reg.h → components/soc/esp32s3/register/soc/efuse_reg.h
View File

@@ -7,7 +7,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "efuse_defs.h"
#include "soc/efuse_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -553,7 +553,7 @@ extern "C" {
#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U
#define EFUSE_DIS_DIRECT_BOOT_S 1
/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
* Selectes the default UART print channel. 0: UART0. 1: UART1.
* Selects the default UART print channel. 0: UART0. 1: UART1.
*/
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2))
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
@@ -2638,7 +2638,7 @@ extern "C" {
#define EFUSE_CLK_EN_S 16
/** EFUSE_CONF_REG register
* eFuse operation mode configuraiton register
* eFuse operation mode configuration register
*/
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;

4
components/soc/esp32s3/include/soc/efuse_struct.h → components/soc/esp32s3/register/soc/efuse_struct.h
View File

@@ -423,7 +423,7 @@ typedef union {
*/
uint32_t dis_direct_boot:1;
/** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
* Selectes the default UART print channel. 0: UART0. 1: UART1.
* Selects the default UART print channel. 0: UART0. 1: UART1.
*/
uint32_t dis_usb_serial_jtag_rom_print:1;
/** flash_ecc_mode : RO; bitpos: [3]; default: 0;
@@ -2163,7 +2163,7 @@ typedef union {
} efuse_clk_reg_t;
/** Type of conf register
* eFuse operation mode configuraiton register
* eFuse operation mode configuration register
*/
typedef union {
struct {

58
components/soc/esp32s3/include/soc/extmem_reg.h → components/soc/esp32s3/register/soc/extmem_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EXTMEM_REG_H_
#define _SOC_EXTMEM_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -112,15 +104,15 @@ which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG.*/
#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18)
/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: The bits are used to configure the first length of data locking, which is combin
ed with DCACHE_PRELOCK_SCT0_ADDR_REG.*/
/*description: The bits are used to configure the first length of data locking, which is
combined with DCACHE_PRELOCK_SCT0_ADDR_REG.*/
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S))
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0xFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16
/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: The bits are used to configure the second length of data locking, which is combi
ned with DCACHE_PRELOCK_SCT1_ADDR_REG.*/
/*description: The bits are used to configure the second length of data locking, which is
combined with DCACHE_PRELOCK_SCT1_ADDR_REG.*/
#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000FFFF
#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S))
#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0xFFFF
@@ -189,7 +181,7 @@ ter writeback operation done..*/
#define EXTMEM_DCACHE_WRITEBACK_ENA_S 1
/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
fter invalidate operation done..*/
after invalidate operation done..*/
#define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0))
#define EXTMEM_DCACHE_INVALIDATE_ENA_M (BIT(0))
#define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x1
@@ -342,8 +334,8 @@ ache_autoload_done. 1: enable, 0: disable. .*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x50)
/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The bits are used to configure the start virtual address of the first section fo
r autoload operation. It should be combined with dcache_autoload_sct0_ena..*/
/*description: The bits are used to configure the start virtual address of the first section
for autoload operation. It should be combined with dcache_autoload_sct0_ena..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S))
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF
@@ -472,15 +464,15 @@ which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG.*/
#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x78)
/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: The bits are used to configure the first length of data locking, which is combin
ed with ICACHE_PRELOCK_SCT0_ADDR_REG.*/
/*description: The bits are used to configure the first length of data locking, which is
combined with ICACHE_PRELOCK_SCT0_ADDR_REG.*/
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16
/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: The bits are used to configure the second length of data locking, which is combi
ned with ICACHE_PRELOCK_SCT1_ADDR_REG.*/
/*description: The bits are used to configure the second length of data locking, which is
combined with ICACHE_PRELOCK_SCT1_ADDR_REG.*/
#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF
#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S))
#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF
@@ -535,7 +527,7 @@ counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG..*/
#define EXTMEM_ICACHE_SYNC_DONE_S 1
/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
fter invalidate operation done..*/
after invalidate operation done..*/
#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0))
#define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0))
#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1
@@ -655,8 +647,8 @@ ache_autoload_done. 1: enable, 0: disable. .*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA4)
/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The bits are used to configure the start virtual address of the first section fo
r autoload operation. It should be combined with icache_autoload_sct0_ena..*/
/*description: The bits are used to configure the start virtual address of the first section
for autoload operation. It should be combined with icache_autoload_sct0_ena..*/
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S))
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF
@@ -855,7 +847,7 @@ cks all have been occupied by occupy-mode..*/
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7
/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by dcache trying to replace a line whose bloc
/*description: The bit is used to clear interrupt by dcache trying to replace a line whose block
ks all have been occupied by occupy-mode..*/
#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6))
#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (BIT(6))
@@ -914,7 +906,7 @@ w..*/
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10
/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl
/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overflow
ow..*/
#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9))
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9))
@@ -928,7 +920,7 @@ verflow..*/
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8
/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl
/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overflow
ow..*/
#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7))
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7))
@@ -1642,8 +1634,8 @@ the others fields inside this register..*/
#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x188)
/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */
/*description: Those bits stores the virtual address which will decide where inside the specifi
ed tag memory object will be accessed..*/
/*description: Those bits stores the virtual address which will decide where inside the
specified tag memory object will be accessed..*/
#define EXTMEM_CACHE_VADDR 0xFFFFFFFF
#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S))
#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF

18
components/soc/esp32s3/include/soc/extmem_struct.h → components/soc/esp32s3/register/soc/extmem_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EXTMEM_STRUCT_H_
#define _SOC_EXTMEM_STRUCT_H_

2
components/soc/esp32s3/include/soc/gdma_reg.h → components/soc/esp32s3/register/soc/gdma_reg.h
View File

@@ -7,7 +7,7 @@
#define _SOC_GDMA_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

0
components/soc/esp32s3/include/soc/gdma_struct.h → components/soc/esp32s3/register/soc/gdma_struct.h
View File

22
components/soc/esp32s3/include/soc/gpio_reg.h → components/soc/esp32s3/register/soc/gpio_reg.h
View File

@@ -1,26 +1,18 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_REG_H_
#define _SOC_GPIO_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#include "soc/soc.h"
#define GPIO_PIN_CONFIG_MSB 12
#define GPIO_PIN_CONFIG_LSB 11

2
components/soc/esp32s3/include/soc/gpio_sd_reg.h → components/soc/esp32s3/register/soc/gpio_sd_reg.h
View File

@@ -6,7 +6,7 @@
#pragma once
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {

0
components/soc/esp32s3/include/soc/gpio_sd_struct.h → components/soc/esp32s3/register/soc/gpio_sd_struct.h
View File

0
components/soc/esp32s3/include/soc/gpio_struct.h → components/soc/esp32s3/register/soc/gpio_struct.h
View File

20
components/soc/esp32s3/include/soc/hinf_reg.h → components/soc/esp32s3/register/soc/hinf_reg.h
View File

@@ -1,19 +1,11 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
#include "soc/soc.h"
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */

18
components/soc/esp32s3/include/soc/hinf_struct.h → components/soc/esp32s3/register/soc/hinf_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>

20
components/soc/esp32s3/include/soc/host_reg.h → components/soc/esp32s3/register/soc/host_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_HOST_REG_H_
#define _SOC_HOST_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

20
components/soc/esp32s3/include/soc/host_struct.h → components/soc/esp32s3/register/soc/host_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_HOST_STRUCT_H_
#define _SOC_HOST_STRUCT_H_
@@ -459,7 +451,7 @@ typedef volatile struct host_dev_s {
uint32_t reserved_f0;
union {
struct {
uint32_t infor : 20;
uint32_t infor : 20; // codespell:ignore infor
uint32_t reserved20 : 12;
};
uint32_t val;

15
components/soc/esp32s3/include/soc/i2c_reg.h → components/soc/esp32s3/register/soc/i2c_reg.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

15
components/soc/esp32s3/include/soc/i2c_struct.h → components/soc/esp32s3/register/soc/i2c_struct.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) CO LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

34
components/soc/esp32s3/include/soc/i2s_reg.h → components/soc/esp32s3/register/soc/i2s_reg.h
View File

@@ -7,7 +7,7 @@
#define _SOC_I2S_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -151,7 +151,7 @@ MSB is received first..*/
#define I2S_RX_BIT_ORDER_S 18
/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
1: WS should be 1 when receiving left channel data, and WS is 0in right channe
1: WS should be 1 when receiving left channel data, and WS is 0in right channel
l. .*/
#define I2S_RX_WS_IDLE_POL (BIT(17))
#define I2S_RX_WS_IDLE_POL_M (BIT(17))
@@ -330,7 +330,7 @@ his bit will be cleared by hardware after update register done..*/
#define I2S_TX_UPDATE_S 8
/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr v
alue..*/
value..*/
#define I2S_TX_BIG_ENDIAN (BIT(7))
#define I2S_TX_BIG_ENDIAN_M (BIT(7))
#define I2S_TX_BIG_ENDIAN_V 0x1
@@ -530,7 +530,7 @@ I2S_RX_CLKM_DIV_YN1 is 1. .*/
#define I2S_RX_CLKM_DIV_YN1_V 0x1
#define I2S_RX_CLKM_DIV_YN1_S 27
/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu
/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
e of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. .*/
#define I2S_RX_CLKM_DIV_X 0x000001FF
#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S))
@@ -560,7 +560,7 @@ I2S_TX_CLKM_DIV_YN1 is 1. .*/
#define I2S_TX_CLKM_DIV_YN1_V 0x1
#define I2S_TX_CLKM_DIV_YN1_S 27
/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu
/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
e of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. .*/
#define I2S_TX_CLKM_DIV_X 0x000001FF
#define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S))
@@ -747,56 +747,56 @@ T12_5[2:0]).*/
#define I2S_RX_TDM_CHAN8_EN_V 0x1
#define I2S_RX_TDM_CHAN8_EN_S 8
/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7))
#define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7))
#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1
#define I2S_RX_TDM_PDM_CHAN7_EN_S 7
/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6))
#define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6))
#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1
#define I2S_RX_TDM_PDM_CHAN6_EN_S 6
/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5))
#define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5))
#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1
#define I2S_RX_TDM_PDM_CHAN5_EN_S 5
/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4))
#define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4))
#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1
#define I2S_RX_TDM_PDM_CHAN4_EN_S 4
/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3))
#define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3))
#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1
#define I2S_RX_TDM_PDM_CHAN3_EN_S 3
/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2))
#define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2))
#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1
#define I2S_RX_TDM_PDM_CHAN2_EN_S 2
/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1))
#define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1))
#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1
#define I2S_RX_TDM_PDM_CHAN1_EN_S 1
/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
t input 0 in this channel..*/
#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0))
#define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0))
@@ -805,8 +805,8 @@ t input 0 in this channel..*/
#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, a
nd only the data of the enabled channels is sent, then this bit should be set. C
/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels,
and only the data of the enabled channels is sent, then this bit should be set. C
lear it when all the data stored in DMA TX buffer is for enabled channels..*/
#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20))
#define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20))
@@ -1041,8 +1041,8 @@ delay by neg edge. 3: not used..*/
#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1
#define I2S_LC_FIFO_TIMEOUT_ENA_S 11
/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
/*description: The bits are used to scale tick counter threshold. The tick counter is reset whe
n counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/
/*description: The bits are used to scale tick counter threshold. The tick counter is reset
when counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/
#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7

2
components/soc/esp32s3/include/soc/i2s_struct.h → components/soc/esp32s3/register/soc/i2s_struct.h
View File

@@ -97,7 +97,7 @@ typedef volatile struct i2s_dev_s {
uint32_t tx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
uint32_t tx_pcm_conf : 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
uint32_t tx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty*/
uint32_t reserved14 : 1; /* Reserved*/
uint32_t tx_left_align : 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
uint32_t tx_24_fill_en : 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/

20
components/soc/esp32s3/include/soc/interrupt_core0_reg.h → components/soc/esp32s3/register/soc/interrupt_core0_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

18
components/soc/esp32s3/include/soc/interrupt_core0_struct.h → components/soc/esp32s3/register/soc/interrupt_core0_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE0_STRUCT_H_
#define _SOC_INTERRUPT_CORE0_STRUCT_H_
#include <stdint.h>

20
components/soc/esp32s3/include/soc/interrupt_core1_reg.h → components/soc/esp32s3/register/soc/interrupt_core1_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE1_REG_H_
#define _SOC_INTERRUPT_CORE1_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

18
components/soc/esp32s3/include/soc/interrupt_core1_struct.h → components/soc/esp32s3/register/soc/interrupt_core1_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE1_STRUCT_H_
#define _SOC_INTERRUPT_CORE1_STRUCT_H_
#include <stdint.h>

2
components/soc/esp32s3/include/soc/io_mux_reg.h → components/soc/esp32s3/register/soc/io_mux_reg.h
View File

@@ -5,7 +5,7 @@
*/
#pragma once
#include "soc.h"
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */

0
components/soc/esp32s3/include/soc/lcd_cam_reg.h → components/soc/esp32s3/register/soc/lcd_cam_reg.h
View File

0
components/soc/esp32s3/include/soc/lcd_cam_struct.h → components/soc/esp32s3/register/soc/lcd_cam_struct.h
View File

22
components/soc/esp32s3/include/soc/ledc_reg.h → components/soc/esp32s3/register/soc/ledc_reg.h
View File

@@ -1,24 +1,16 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#include "soc/soc.h"
#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)
/* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */

18
components/soc/esp32s3/include/soc/ledc_struct.h → components/soc/esp32s3/register/soc/ledc_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>

14
components/soc/esp32s3/include/soc/mcpwm_reg.h → components/soc/esp32s3/register/soc/mcpwm_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -921,7 +921,7 @@ extern "C" {
#define MCPWM_DT0_RED_S 0
/** MCPWM_CARRIER0_CFG_REG register
* PWM generator 0 carrier enable and configuratoin
* PWM generator 0 carrier enable and configuration
*/
#define MCPWM_CARRIER0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x64)
/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0;
@@ -1625,7 +1625,7 @@ extern "C" {
#define MCPWM_DT1_RED_S 0
/** MCPWM_CARRIER1_CFG_REG register
* PWM generator 1 carrier enable and configuratoin
* PWM generator 1 carrier enable and configuration
*/
#define MCPWM_CARRIER1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x9c)
/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0;
@@ -2328,7 +2328,7 @@ extern "C" {
#define MCPWM_DT2_RED_S 0
/** MCPWM_CARRIER2_CFG_REG register
* PWM generator 2 carrier enable and configuratoin
* PWM generator 2 carrier enable and configuration
*/
#define MCPWM_CARRIER2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd4)
/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0;
@@ -2693,7 +2693,7 @@ extern "C" {
#define MCPWM_CAP0_MODE_V 0x00000003U
#define MCPWM_CAP0_MODE_S 1
/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
* Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
* 1
*/
#define MCPWM_CAP0_PRESCALE 0x000000FFU
@@ -2736,7 +2736,7 @@ extern "C" {
#define MCPWM_CAP1_MODE_V 0x00000003U
#define MCPWM_CAP1_MODE_S 1
/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
* Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
* 1
*/
#define MCPWM_CAP1_PRESCALE 0x000000FFU
@@ -2779,7 +2779,7 @@ extern "C" {
#define MCPWM_CAP2_MODE_V 0x00000003U
#define MCPWM_CAP2_MODE_S 1
/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
* Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
* 1
*/
#define MCPWM_CAP2_PRESCALE 0x000000FFU

4
components/soc/esp32s3/include/soc/mcpwm_struct.h → components/soc/esp32s3/register/soc/mcpwm_struct.h
View File

@@ -474,7 +474,7 @@ typedef union {
} mcpwm_dt_red_cfg_reg_t;
/** Type of carrier_cfg register
* PWM generator carrier enable and configuratoin
* PWM generator carrier enable and configuration
*/
typedef union {
struct {
@@ -746,7 +746,7 @@ typedef union {
*/
uint32_t capn_mode: 2;
/** capn_prescale : R/W; bitpos: [10:3]; default: 0;
* Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE +
* Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE +
* 1
*/
uint32_t capn_prescale: 8;

0
components/soc/esp32s3/include/soc/pcnt_reg.h → components/soc/esp32s3/register/soc/pcnt_reg.h
View File

0
components/soc/esp32s3/include/soc/pcnt_struct.h → components/soc/esp32s3/register/soc/pcnt_struct.h
View File

20
components/soc/esp32s3/include/soc/peri_backup_reg.h → components/soc/esp32s3/register/soc/peri_backup_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_PERI_BACKUP_REG_H_
#define _SOC_PERI_BACKUP_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

18
components/soc/esp32s3/include/soc/peri_backup_struct.h → components/soc/esp32s3/register/soc/peri_backup_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_PERI_BACKUP_STRUCT_H_
#define _SOC_PERI_BACKUP_STRUCT_H_

0
components/soc/esp32s3/include/soc/reg_base.h → components/soc/esp32s3/register/soc/reg_base.h
View File

0
components/soc/esp32s3/include/soc/rmt_reg.h → components/soc/esp32s3/register/soc/rmt_reg.h
View File

0
components/soc/esp32s3/include/soc/rmt_struct.h → components/soc/esp32s3/register/soc/rmt_struct.h
View File

2
components/soc/esp32s3/include/soc/rtc_cntl_reg.h → components/soc/esp32s3/register/soc/rtc_cntl_reg.h
View File

@@ -8,7 +8,7 @@
#define _SOC_RTC_CNTL_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

10
components/soc/esp32s3/include/soc/rtc_cntl_struct.h → components/soc/esp32s3/register/soc/rtc_cntl_struct.h
View File

@@ -207,7 +207,7 @@ typedef volatile struct rtc_cntl_dev_s {
uint32_t rtc_xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/
uint32_t rtc_cocpu_trap : 1; /*enable cocpu trap interrupt*/
uint32_t rtc_touch_timeout : 1; /*enable touch timeout interrupt*/
uint32_t rtc_glitch_det : 1; /*enbale gitch det interrupt*/
uint32_t rtc_glitch_det : 1; /*enable gitch det interrupt*/
uint32_t rtc_touch_approach_loop_done : 1;
uint32_t reserved21 : 11;
};
@@ -565,7 +565,7 @@ typedef volatile struct rtc_cntl_dev_s {
uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/
uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/
uint32_t swd_feed : 1; /*Sw feed swd*/
uint32_t swd_disable : 1; /*disabel SWD*/
uint32_t swd_disable : 1; /*disable SWD*/
uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/
};
uint32_t val;
@@ -689,7 +689,7 @@ typedef volatile struct rtc_cntl_dev_s {
uint32_t xtal32k_clk_factor;
union {
struct {
uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/
uint32_t xtal32k_return_wait : 4; /*cycles to wait to return normal xtal 32k*/
uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/
uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time*/
uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this*/
@@ -894,7 +894,7 @@ typedef volatile struct rtc_cntl_dev_s {
uint32_t rtc_xtal32k_dead_w1ts : 1; /*enable xtal32k_dead interrupt*/
uint32_t rtc_cocpu_trap_w1ts : 1; /*enable cocpu trap interrupt*/
uint32_t rtc_touch_timeout_w1ts : 1; /*enable touch timeout interrupt*/
uint32_t rtc_glitch_det_w1ts : 1; /*enbale gitch det interrupt*/
uint32_t rtc_glitch_det_w1ts : 1; /*enable gitch det interrupt*/
uint32_t rtc_touch_approach_loop_done_w1ts: 1;
uint32_t reserved21 : 11;
};
@@ -921,7 +921,7 @@ typedef volatile struct rtc_cntl_dev_s {
uint32_t rtc_xtal32k_dead_w1tc : 1; /*enable xtal32k_dead interrupt*/
uint32_t rtc_cocpu_trap_w1tc : 1; /*enable cocpu trap interrupt*/
uint32_t rtc_touch_timeout_w1tc : 1; /*enable touch timeout interrupt*/
uint32_t rtc_glitch_det_w1tc : 1; /*enbale gitch det interrupt*/
uint32_t rtc_glitch_det_w1tc : 1; /*enable gitch det interrupt*/
uint32_t rtc_touch_approach_loop_done_w1tc: 1;
uint32_t reserved21 : 11;
};

15
components/soc/esp32s3/include/soc/rtc_i2c_reg.h → components/soc/esp32s3/register/soc/rtc_i2c_reg.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

15
components/soc/esp32s3/include/soc/rtc_i2c_struct.h → components/soc/esp32s3/register/soc/rtc_i2c_struct.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

108
components/soc/esp32s3/include/soc/rtc_io_reg.h → components/soc/esp32s3/register/soc/rtc_io_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_IO_REG_H_
#define _SOC_RTC_IO_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -109,8 +101,8 @@ extern "C" {
#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN0_INT_TYPE 0x00000007
#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
#define RTC_GPIO_PIN0_INT_TYPE_V 0x7
@@ -131,8 +123,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN1_INT_TYPE 0x00000007
#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
#define RTC_GPIO_PIN1_INT_TYPE_V 0x7
@@ -153,8 +145,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN2_INT_TYPE 0x00000007
#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
#define RTC_GPIO_PIN2_INT_TYPE_V 0x7
@@ -175,8 +167,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN3_INT_TYPE 0x00000007
#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
#define RTC_GPIO_PIN3_INT_TYPE_V 0x7
@@ -197,8 +189,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN4_INT_TYPE 0x00000007
#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
#define RTC_GPIO_PIN4_INT_TYPE_V 0x7
@@ -219,8 +211,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN5_INT_TYPE 0x00000007
#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
#define RTC_GPIO_PIN5_INT_TYPE_V 0x7
@@ -241,8 +233,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN6_INT_TYPE 0x00000007
#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
#define RTC_GPIO_PIN6_INT_TYPE_V 0x7
@@ -263,8 +255,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN7_INT_TYPE 0x00000007
#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
#define RTC_GPIO_PIN7_INT_TYPE_V 0x7
@@ -285,8 +277,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN8_INT_TYPE 0x00000007
#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
#define RTC_GPIO_PIN8_INT_TYPE_V 0x7
@@ -307,8 +299,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN9_INT_TYPE 0x00000007
#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
#define RTC_GPIO_PIN9_INT_TYPE_V 0x7
@@ -329,8 +321,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN10_INT_TYPE 0x00000007
#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
#define RTC_GPIO_PIN10_INT_TYPE_V 0x7
@@ -351,8 +343,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN11_INT_TYPE 0x00000007
#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
#define RTC_GPIO_PIN11_INT_TYPE_V 0x7
@@ -373,8 +365,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN12_INT_TYPE 0x00000007
#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
#define RTC_GPIO_PIN12_INT_TYPE_V 0x7
@@ -395,8 +387,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN13_INT_TYPE 0x00000007
#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
#define RTC_GPIO_PIN13_INT_TYPE_V 0x7
@@ -417,8 +409,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN14_INT_TYPE 0x00000007
#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
#define RTC_GPIO_PIN14_INT_TYPE_V 0x7
@@ -439,8 +431,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN15_INT_TYPE 0x00000007
#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
#define RTC_GPIO_PIN15_INT_TYPE_V 0x7
@@ -461,8 +453,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN16_INT_TYPE 0x00000007
#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
#define RTC_GPIO_PIN16_INT_TYPE_V 0x7
@@ -483,8 +475,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN17_INT_TYPE 0x00000007
#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
#define RTC_GPIO_PIN17_INT_TYPE_V 0x7
@@ -505,8 +497,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN18_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN18_INT_TYPE 0x00000007
#define RTC_GPIO_PIN18_INT_TYPE_M ((RTC_GPIO_PIN18_INT_TYPE_V)<<(RTC_GPIO_PIN18_INT_TYPE_S))
#define RTC_GPIO_PIN18_INT_TYPE_V 0x7
@@ -527,8 +519,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN19_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN19_INT_TYPE 0x00000007
#define RTC_GPIO_PIN19_INT_TYPE_M ((RTC_GPIO_PIN19_INT_TYPE_V)<<(RTC_GPIO_PIN19_INT_TYPE_S))
#define RTC_GPIO_PIN19_INT_TYPE_V 0x7
@@ -549,8 +541,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN20_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN20_INT_TYPE 0x00000007
#define RTC_GPIO_PIN20_INT_TYPE_M ((RTC_GPIO_PIN20_INT_TYPE_V)<<(RTC_GPIO_PIN20_INT_TYPE_S))
#define RTC_GPIO_PIN20_INT_TYPE_V 0x7
@@ -571,8 +563,8 @@ l trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN21_WAKEUP_ENABLE_S 10
/* RTC_GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
l trigger, if set to 5: high level trigger.*/
to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
level trigger, if set to 5: high level trigger.*/
#define RTC_GPIO_PIN21_INT_TYPE 0x00000007
#define RTC_GPIO_PIN21_INT_TYPE_M ((RTC_GPIO_PIN21_INT_TYPE_V)<<(RTC_GPIO_PIN21_INT_TYPE_S))
#define RTC_GPIO_PIN21_INT_TYPE_V 0x7

18
components/soc/esp32s3/include/soc/rtc_io_struct.h → components/soc/esp32s3/register/soc/rtc_io_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_IO_STRUCT_H_
#define _SOC_RTC_IO_STRUCT_H_

20
components/soc/esp32s3/include/soc/sdmmc_reg.h → components/soc/esp32s3/register/soc/sdmmc_reg.h
View File

@@ -1,19 +1,11 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
#include "soc/soc.h"
#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)

0
components/soc/esp32s3/include/soc/sdmmc_struct.h → components/soc/esp32s3/register/soc/sdmmc_struct.h
View File

2
components/soc/esp32s3/include/soc/sens_reg.h → components/soc/esp32s3/register/soc/sens_reg.h
View File

@@ -7,7 +7,7 @@
#define _SOC_SENS_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

0
components/soc/esp32s3/include/soc/sens_struct.h → components/soc/esp32s3/register/soc/sens_struct.h
View File

20
components/soc/esp32s3/include/soc/sensitive_reg.h → components/soc/esp32s3/register/soc/sensitive_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENSITIVE_REG_H_
#define _SOC_SENSITIVE_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

18
components/soc/esp32s3/include/soc/sensitive_struct.h → components/soc/esp32s3/register/soc/sensitive_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENSITIVE_STRUCT_H_
#define _SOC_SENSITIVE_STRUCT_H_

64
components/soc/esp32s3/include/soc/spi_mem_reg.h → components/soc/esp32s3/register/soc/spi_mem_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_MEM_REG_H_
#define _SOC_SPI_MEM_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -209,14 +201,14 @@ QUAD or SPI_MEM_FREAD_DUAL is set..*/
#define SPI_MEM_FASTRD_MODE_V 0x1
#define SPI_MEM_FASTRD_MODE_S 13
/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
e.*/
#define SPI_MEM_TX_CRC_EN (BIT(11))
#define SPI_MEM_TX_CRC_EN_M (BIT(11))
#define SPI_MEM_TX_CRC_EN_V 0x1
#define SPI_MEM_TX_CRC_EN_S 11
/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ
/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Active
e low..*/
#define SPI_MEM_FCS_CRC_EN (BIT(10))
#define SPI_MEM_FCS_CRC_EN_M (BIT(10))
@@ -826,8 +818,8 @@ tive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two
#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48)
/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register val
ue shall be (bit_num-1)..*/
/*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register
value shall be (bit_num-1)..*/
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF
@@ -1072,8 +1064,8 @@ ES command is sent..*/
#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1
#define SPI_MEM_FLASH_PER_WAIT_EN_S 2
/* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */
/*description: program erase suspend bit, program erase suspend operation will be triggered whe
n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
/*description: program erase suspend bit, program erase suspend operation will be triggered
when the bit is set. The bit will be cleared once the operation done.1: enable 0: d
isable. .*/
#define SPI_MEM_FLASH_PES (BIT(1))
#define SPI_MEM_FLASH_PES_M (BIT(1))
@@ -1166,7 +1158,7 @@ PI_MEM_TIMING_CALI bit is set..*/
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2
/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio
/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operation
ns..*/
#define SPI_MEM_TIMING_CALI (BIT(1))
#define SPI_MEM_TIMING_CALI_M (BIT(1))
@@ -1174,7 +1166,7 @@ ns..*/
#define SPI_MEM_TIMING_CALI_S 1
/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
also to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
#define SPI_MEM_TIMING_CLK_ENA (BIT(0))
#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0))
#define SPI_MEM_TIMING_CLK_ENA_V 0x1
@@ -1245,8 +1237,8 @@ cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
/*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg
ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
nagetive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_DIN3_MODE 0x00000007
@@ -1257,8 +1249,8 @@ les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
/*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg
ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
nagetive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_DIN2_MODE 0x00000007
@@ -1420,7 +1412,7 @@ esses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set..*/
#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7
#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2
/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio
/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operation
ns..*/
#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1))
#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1))
@@ -1428,7 +1420,7 @@ ns..*/
#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1
/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
also to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0))
#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0))
#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1
@@ -1524,8 +1516,8 @@ and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a
nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007
#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S))
@@ -1536,8 +1528,8 @@ nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a
nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007
#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S))
@@ -1708,8 +1700,8 @@ INT_CLR bit..*/
#define SPI_MEM_ECC_BYTE_ERR_V 0x1
#define SPI_MEM_ECC_BYTE_ERR_S 16
/* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */
/*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC by
te..*/
/*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC
byte..*/
#define SPI_MEM_ECC_CHK_ERR_BIT 0x00000007
#define SPI_MEM_ECC_CHK_ERR_BIT_M ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S))
#define SPI_MEM_ECC_CHK_ERR_BIT_V 0x7
@@ -2126,7 +2118,7 @@ or times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_
NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is s
et, this bit is triggered when the error times of SPI0/1 ECC read external RAM a
re equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN
and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total erro
and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error
r times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_C
TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN
are cleared, this bit will not be triggered..*/
@@ -2136,7 +2128,7 @@ TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN
#define SPI_MEM_ECC_ERR_INT_RAW_S 4
/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
chip is loosing power and RTC module sends out brown out close flash request to
chip is losing power and RTC module sends out brown out close flash request to
SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
and MSPI returns to idle state. 0: Others..*/
#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(3))

20
components/soc/esp32s3/include/soc/spi_mem_struct.h → components/soc/esp32s3/register/soc/spi_mem_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_MEM_STRUCT_H_
#define _SOC_SPI_MEM_STRUCT_H_
@@ -551,7 +543,7 @@ typedef volatile struct spi_mem_dev_s {
uint32_t per_end_int_raw : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
uint32_t pes_end_int_raw : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
uint32_t total_trans_end_int_raw : 1; /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.*/
uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
uint32_t ecc_err_int_raw : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
uint32_t reserved5 : 27; /*reserved*/
};

36
components/soc/esp32s3/include/soc/spi_reg.h → components/soc/esp32s3/register/soc/spi_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -167,7 +159,7 @@ e, the FSPI bus signals are output. Can be configured in CONF state..*/
#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC)
/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst
/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst
em clock. Can be configured in CONF state..*/
#define SPI_CLK_EQU_SYSCLK (BIT(31))
#define SPI_CLK_EQU_SYSCLK_M (BIT(31))
@@ -204,15 +196,15 @@ e 0. Can be configured in CONF state..*/
#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
/*description: This bit enable the command phase of an operation. Can be configured in CONF sta
te..*/
/*description: This bit enable the command phase of an operation. Can be configured in CONF
state..*/
#define SPI_USR_COMMAND (BIT(31))
#define SPI_USR_COMMAND_M (BIT(31))
#define SPI_USR_COMMAND_V 0x1
#define SPI_USR_COMMAND_S 31
/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: This bit enable the address phase of an operation. Can be configured in CONF sta
te..*/
/*description: This bit enable the address phase of an operation. Can be configured in CONF
state..*/
#define SPI_USR_ADDR (BIT(30))
#define SPI_USR_ADDR_M (BIT(30))
#define SPI_USR_ADDR_V 0x1
@@ -400,7 +392,7 @@ n be configured in CONF state..*/
#define SPI_USR_COMMAND_BITLEN_S 28
/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro
aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
r is valid in GP-SPI master FD/HD-mode..*/
#define SPI_MST_REMPTY_ERR_END_EN (BIT(27))
#define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27))
@@ -1121,7 +1113,7 @@ AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1
#define SPI_SLV_CMD_ERR_INT_RAW_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres
/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
is bigger than 63. 0: Others..*/
#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15))
@@ -1692,7 +1684,7 @@ dge 0: output data at tsck posedge .*/
/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
ve 3: SPI clock is always on. Can be configured in CONF state..*/
#define SPI_CLK_MODE 0x00000003
#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
#define SPI_CLK_MODE_V 0x3

22
components/soc/esp32s3/include/soc/spi_struct.h → components/soc/esp32s3/register/soc/spi_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
@@ -66,7 +58,7 @@ typedef volatile struct spi_dev_s {
uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
uint32_t reserved22 : 9; /*reserved*/
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
};
uint32_t val;
} clock;
@@ -374,7 +366,7 @@ typedef volatile struct spi_dev_s {
uint32_t reserved_dc;
union {
struct {
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */
uint32_t reserved4 : 4; /*reserved*/

4
components/soc/esp32s3/include/soc/syscon_reg.h → components/soc/esp32s3/register/soc/syscon_reg.h
View File

@@ -7,7 +7,7 @@
#define _SOC_SYSCON_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -210,7 +210,7 @@ extern "C" {
#define SYSTEM_MACPWR_RST BIT(8)
#define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */
#define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */
#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */
#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Registers */
#define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */
#define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */

18
components/soc/esp32s3/include/soc/syscon_struct.h → components/soc/esp32s3/register/soc/syscon_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_

20
components/soc/esp32s3/include/soc/system_reg.h → components/soc/esp32s3/register/soc/system_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSTEM_REG_H_
#define _SOC_SYSTEM_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

18
components/soc/esp32s3/include/soc/system_struct.h → components/soc/esp32s3/register/soc/system_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSTEM_STRUCT_H_
#define _SOC_SYSTEM_STRUCT_H_

15
components/soc/esp32s3/include/soc/systimer_reg.h → components/soc/esp32s3/register/soc/systimer_reg.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

15
components/soc/esp32s3/include/soc/systimer_struct.h → components/soc/esp32s3/register/soc/systimer_struct.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

15
components/soc/esp32s3/include/soc/timer_group_reg.h → components/soc/esp32s3/register/soc/timer_group_reg.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

0
components/soc/esp32s3/include/soc/timer_group_struct.h → components/soc/esp32s3/register/soc/timer_group_struct.h
View File

0
components/soc/esp32s3/include/soc/twai_struct.h → components/soc/esp32s3/register/soc/twai_struct.h
View File

25
components/soc/esp32s3/include/soc/uart_reg.h → components/soc/esp32s3/register/soc/uart_reg.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -109,7 +100,7 @@ extern "C" {
#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U
#define UART_RXFIFO_TOUT_INT_RAW_S 8
/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
* This interrupt raw bit turns to high level when receiver recevies Xon char when
* This interrupt raw bit turns to high level when receiver receives Xon char when
* uart_sw_flow_con_en is set to 1.
*/
#define UART_SW_XON_INT_RAW (BIT(9))
@@ -294,7 +285,7 @@ extern "C" {
#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U
#define UART_TX_BRK_DONE_INT_ST_S 12
/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
* This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
* This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
* is set to 1.
*/
#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))
@@ -785,7 +776,7 @@ extern "C" {
#define UART_SW_DTR_V 0x00000001U
#define UART_SW_DTR_S 7
/** UART_TXD_BRK : R/W; bitpos: [8]; default: 0;
* Set this bit to enbale transmitter to send NULL when the process of sending data
* Set this bit to enable transmitter to send NULL when the process of sending data
* is done.
*/
#define UART_TXD_BRK (BIT(8))
@@ -978,7 +969,7 @@ extern "C" {
#define UART_RX_FLOW_EN_V 0x00000001U
#define UART_RX_FLOW_EN_S 22
/** UART_RX_TOUT_EN : R/W; bitpos: [23]; default: 0;
* This is the enble bit for uart receiver's timeout function.
* This is the enable bit for uart receiver's timeout function.
*/
#define UART_RX_TOUT_EN (BIT(23))
#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
@@ -1003,7 +994,7 @@ extern "C" {
*/
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c)
/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the maxinum duration time for the high level
* This register stores the value of the maximum duration time for the high level
* pulse. It is used in baud rate-detect process.
*/
#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU

25
components/soc/esp32s3/include/soc/uart_struct.h → components/soc/esp32s3/register/soc/uart_struct.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -129,7 +120,7 @@ typedef union {
*/
uint32_t rxfifo_tout_int_raw:1;
/** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* This interrupt raw bit turns to high level when receiver recevies Xon char when
* This interrupt raw bit turns to high level when receiver receives Xon char when
* uart_sw_flow_con_en is set to 1.
*/
uint32_t sw_xon_int_raw:1;
@@ -247,7 +238,7 @@ typedef union {
*/
uint32_t tx_brk_done_int_st:1;
/** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
* This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
* This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
* is set to 1.
*/
uint32_t tx_brk_idle_done_int_st:1;
@@ -534,7 +525,7 @@ typedef union {
*/
uint32_t sw_dtr:1;
/** txd_brk : R/W; bitpos: [8]; default: 0;
* Set this bit to enbale transmitter to send NULL when the process of sending data
* Set this bit to enable transmitter to send NULL when the process of sending data
* is done.
*/
uint32_t txd_brk:1;
@@ -654,7 +645,7 @@ typedef union {
*/
uint32_t rx_flow_en:1;
/** rx_tout_en : R/W; bitpos: [23]; default: 0;
* This is the enble bit for uart receiver's timeout function.
* This is the enable bit for uart receiver's timeout function.
*/
uint32_t rx_tout_en:1;
uint32_t reserved_24:8;
@@ -1001,7 +992,7 @@ typedef union {
typedef union {
struct {
/** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the maxinum duration time for the high level
* This register stores the value of the maximum duration time for the high level
* pulse. It is used in baud rate-detect process.
*/
uint32_t highpulse_min_cnt:12;

20
components/soc/esp32s3/include/soc/uhci_reg.h → components/soc/esp32s3/register/soc/uhci_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UHCI_REG_H_
#define _SOC_UHCI_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

0
components/soc/esp32s3/include/soc/uhci_struct.h → components/soc/esp32s3/register/soc/uhci_struct.h
View File

62
components/soc/esp32s3/include/soc/usb_reg.h → components/soc/esp32s3/register/soc/usb_reg.h
View File

@@ -8,7 +8,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -608,7 +608,7 @@ extern "C" {
#define USB_H_LSPDDEV0_V 0x00000001
#define USB_H_LSPDDEV0_S 17
/** USB_H_EPTYPE0 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -647,7 +647,7 @@ extern "C" {
#define USB_H_ODDFRM0_S 29
/** USB_H_CHDIS0 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS0 (BIT(30))
@@ -720,7 +720,7 @@ extern "C" {
#define USB_H_LSPDDEV1_V 0x00000001
#define USB_H_LSPDDEV1_S 17
/** USB_H_EPTYPE1 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -759,7 +759,7 @@ extern "C" {
#define USB_H_ODDFRM1_S 29
/** USB_H_CHDIS1 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS1 (BIT(30))
@@ -832,7 +832,7 @@ extern "C" {
#define USB_H_LSPDDEV2_V 0x00000001
#define USB_H_LSPDDEV2_S 17
/** USB_H_EPTYPE2 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -871,7 +871,7 @@ extern "C" {
#define USB_H_ODDFRM2_S 29
/** USB_H_CHDIS2 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS2 (BIT(30))
@@ -944,7 +944,7 @@ extern "C" {
#define USB_H_LSPDDEV3_V 0x00000001
#define USB_H_LSPDDEV3_S 17
/** USB_H_EPTYPE3 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -983,7 +983,7 @@ extern "C" {
#define USB_H_ODDFRM3_S 29
/** USB_H_CHDIS3 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS3 (BIT(30))
@@ -1056,7 +1056,7 @@ extern "C" {
#define USB_H_LSPDDEV4_V 0x00000001
#define USB_H_LSPDDEV4_S 17
/** USB_H_EPTYPE4 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -1095,7 +1095,7 @@ extern "C" {
#define USB_H_ODDFRM4_S 29
/** USB_H_CHDIS4 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS4 (BIT(30))
@@ -1168,7 +1168,7 @@ extern "C" {
#define USB_H_LSPDDEV5_V 0x00000001
#define USB_H_LSPDDEV5_S 17
/** USB_H_EPTYPE5 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -1207,7 +1207,7 @@ extern "C" {
#define USB_H_ODDFRM5_S 29
/** USB_H_CHDIS5 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS5 (BIT(30))
@@ -1280,7 +1280,7 @@ extern "C" {
#define USB_H_LSPDDEV6_V 0x00000001
#define USB_H_LSPDDEV6_S 17
/** USB_H_EPTYPE6 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -1319,7 +1319,7 @@ extern "C" {
#define USB_H_ODDFRM6_S 29
/** USB_H_CHDIS6 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS6 (BIT(30))
@@ -1392,7 +1392,7 @@ extern "C" {
#define USB_H_LSPDDEV7_V 0x00000001
#define USB_H_LSPDDEV7_S 17
/** USB_H_EPTYPE7 : R/W; bitpos: [20:18]; default: 0;
* 0x0 (CTRL): Contro
* 0x0 (CTRL): Control
* 0x1 (ISOC): Isochronous
* 0x2 (BULK): Bulk
* 0x3 (INTERR): Interrupt
@@ -1431,7 +1431,7 @@ extern "C" {
#define USB_H_ODDFRM7_S 29
/** USB_H_CHDIS7 : R/W; bitpos: [30]; default: 0;
* Channel Disable
* 0x0 : Transmit/Recieve norma
* 0x0 : Transmit/Receive norma
* 0x1 : Stop transmitting/receiving data on channel
*/
#define USB_H_CHDIS7 (BIT(30))
@@ -1476,7 +1476,7 @@ extern "C" {
/** USB_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0;
* 1'b0: Send the received OUT packet to the application (zero-length or non-zero
* length) and send a handshake based on NAK and STALL bits for the endpoint in the
* Devce Endpoint Control Register
* Device Endpoint Control Register
* 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not
* send the received OUT packet to the application
*/
@@ -1488,7 +1488,7 @@ extern "C" {
* This bit can be set only if FS PHY interface is selected.
* Otherwise, this bit needs to be set to zero.
* 1'b0: USB 1.1 Full-Speed Serial transiver not selected
* 1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend
* 1'b1: If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend
* must be switched from 48 MHz to 32 KHz
*/
#define USB_ENA32KHZSUSP (BIT(3))
@@ -1580,7 +1580,7 @@ extern "C" {
#define USB_DCTL_REG (SOC_DPORT_USB_BASE + 0x804)
/** USB_RMTWKUPSIG : R/W; bitpos: [0]; default: 0;
* 0x0 : Core does not send Remote Wakeup Signaling
* 0x1 : Core sends Remote Wakeup Signalin
* 0x1 : Core sends Remote Wakeup Signaling
*/
#define USB_RMTWKUPSIG (BIT(0))
#define USB_RMTWKUPSIG_M (USB_RMTWKUPSIG_V << USB_RMTWKUPSIG_S)
@@ -4729,7 +4729,7 @@ extern "C" {
#define USB_H_NACK0_S 4
/** USB_H_ACK0 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK0 (BIT(5))
#define USB_H_ACK0_M (USB_H_ACK0_V << USB_H_ACK0_S)
@@ -4965,7 +4965,7 @@ extern "C" {
#define USB_H_NACK1_S 4
/** USB_H_ACK1 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK1 (BIT(5))
#define USB_H_ACK1_M (USB_H_ACK1_V << USB_H_ACK1_S)
@@ -5201,7 +5201,7 @@ extern "C" {
#define USB_H_NACK2_S 4
/** USB_H_ACK2 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK2 (BIT(5))
#define USB_H_ACK2_M (USB_H_ACK2_V << USB_H_ACK2_S)
@@ -5437,7 +5437,7 @@ extern "C" {
#define USB_H_NACK3_S 4
/** USB_H_ACK3 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK3 (BIT(5))
#define USB_H_ACK3_M (USB_H_ACK3_V << USB_H_ACK3_S)
@@ -5673,7 +5673,7 @@ extern "C" {
#define USB_H_NACK4_S 4
/** USB_H_ACK4 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK4 (BIT(5))
#define USB_H_ACK4_M (USB_H_ACK4_V << USB_H_ACK4_S)
@@ -5909,7 +5909,7 @@ extern "C" {
#define USB_H_NACK5_S 4
/** USB_H_ACK5 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK5 (BIT(5))
#define USB_H_ACK5_M (USB_H_ACK5_V << USB_H_ACK5_S)
@@ -6145,7 +6145,7 @@ extern "C" {
#define USB_H_NACK6_S 4
/** USB_H_ACK6 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK6 (BIT(5))
#define USB_H_ACK6_M (USB_H_ACK6_V << USB_H_ACK6_S)
@@ -6381,7 +6381,7 @@ extern "C" {
#define USB_H_NACK7_S 4
/** USB_H_ACK7 : R/W1C; bitpos: [5]; default: 0;
* 1'b0: No ACK Response Received or Transmitted Interrupt
* 1'b1: ACK Response Received or Transmitted Interrup
* 1'b1: ACK Response Received or Transmitted Interrupt
*/
#define USB_H_ACK7 (BIT(5))
#define USB_H_ACK7_M (USB_H_ACK7_V << USB_H_ACK7_S)
@@ -8915,9 +8915,9 @@ extern "C" {
#define USB_AHBSINGLE_V 0x00000001
#define USB_AHBSINGLE_S 23
/** USB_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0;
* Invert Descriptor Endianess
* Invert Descriptor Endianness
* 1'b0: Descriptor Endianness is same as AHB Master Endianness
* 1'b1:Invert Descriptor Endianess according to AHB Master endianness
* 1'b1:Invert Descriptor Endianness according to AHB Master endianness
*/
#define USB_INVDESCENDIANESS (BIT(24))
#define USB_INVDESCENDIANESS_M (USB_INVDESCENDIANESS_V << USB_INVDESCENDIANESS_S)
@@ -9678,7 +9678,7 @@ extern "C" {
/** USB_GSNPSID_REG register
* Synopsys ID Register
* ID Register
*/
#define USB_GSNPSID_REG (SOC_DPORT_USB_BASE + 0x40)
/** USB_SYNOPSYSID : RO; bitpos: [32:0]; default: 1330921482;

14
components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h → components/soc/esp32s3/register/soc/usb_serial_jtag_reg.h
View File

@@ -9,7 +9,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#include "soc/soc.h"
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
/* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
@@ -31,8 +31,8 @@ ived, then read data from UART Rx FIFO..*/
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x1
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin
g USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After
writing USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
USB Host..*/
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (BIT(1))
@@ -117,8 +117,8 @@ eived..*/
#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x1
#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp
oint 2 of JTAG..*/
/*description: The raw interrupt bit turns to high level when flush cmd is received for IN
endpoint 2 of JTAG..*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x1
@@ -146,7 +146,7 @@ pt..*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x1
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrup
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt
t..*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8))
@@ -183,7 +183,7 @@ t..*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x1
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrup
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt
t..*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2))

20
components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h → components/soc/esp32s3/register/soc/usb_serial_jtag_struct.h
View File

@@ -1,16 +1,8 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
@@ -18,7 +10,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#include "soc/soc.h"
typedef volatile struct usb_serial_jtag_dev_s {
union {

2
components/soc/esp32s3/include/soc/usb_struct.h → components/soc/esp32s3/register/soc/usb_struct.h
View File

@@ -50,7 +50,7 @@ typedef struct usb_reg {
volatile uint32_t gnptxfsiz; // 0x0028 Non-periodic Transmit FIFO Size Register
volatile uint32_t gnptxsts; // 0x002c Non-periodic Transmit FIFO/Queue Status Register
uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040
volatile uint32_t gsnpsid; // 0x0040 Synopsys ID Register
volatile uint32_t gsnpsid; // 0x0040 ID Register
volatile uint32_t ghwcfg1; // 0x0044 User Hardware Configuration 1 Register
volatile uint32_t ghwcfg2; // 0x0048 User Hardware Configuration 2 Register
volatile uint32_t ghwcfg3; // 0x004c User Hardware Configuration 3 Register

20
components/soc/esp32s3/include/soc/usb_wrap_reg.h → components/soc/esp32s3/register/soc/usb_wrap_reg.h
View File

@@ -1,21 +1,13 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_USB_WRAP_REG_H_
#define _SOC_USB_WRAP_REG_H_
#include "soc.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

15
components/soc/esp32s3/include/soc/usb_wrap_struct.h → components/soc/esp32s3/register/soc/usb_wrap_struct.h
View File

@@ -1,16 +1,7 @@
/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

0
components/soc/esp32s3/include/soc/world_controller_reg.h → components/soc/esp32s3/register/soc/world_controller_reg.h
View File

0
components/soc/esp32s3/include/soc/world_controller_struct.h → components/soc/esp32s3/register/soc/world_controller_struct.h
View File

53
tools/ci/check_copyright_ignore.txt
View File

@@ -565,60 +565,7 @@ components/soc/esp32s2/include/soc/touch_sensor_pins.h
components/soc/esp32s2/include/soc/uart_pins.h
components/soc/esp32s2/include/soc/wdev_reg.h
components/soc/esp32s2/ledc_periph.c
components/soc/esp32s3/include/soc/apb_saradc_reg.h
components/soc/esp32s3/include/soc/assist_debug_reg.h
components/soc/esp32s3/include/soc/assist_debug_struct.h
components/soc/esp32s3/include/soc/bb_reg.h
components/soc/esp32s3/include/soc/boot_mode.h
components/soc/esp32s3/include/soc/extmem_reg.h
components/soc/esp32s3/include/soc/extmem_struct.h
components/soc/esp32s3/include/soc/fe_reg.h
components/soc/esp32s3/include/soc/gpio_reg.h
components/soc/esp32s3/include/soc/hinf_reg.h
components/soc/esp32s3/include/soc/hinf_struct.h
components/soc/esp32s3/include/soc/host_reg.h
components/soc/esp32s3/include/soc/host_struct.h
components/soc/esp32s3/include/soc/i2c_reg.h
components/soc/esp32s3/include/soc/i2c_struct.h
components/soc/esp32s3/include/soc/interrupt_core0_reg.h
components/soc/esp32s3/include/soc/interrupt_core0_struct.h
components/soc/esp32s3/include/soc/interrupt_core1_reg.h
components/soc/esp32s3/include/soc/interrupt_core1_struct.h
components/soc/esp32s3/include/soc/interrupt_struct.h
components/soc/esp32s3/include/soc/ledc_reg.h
components/soc/esp32s3/include/soc/ledc_struct.h
components/soc/esp32s3/include/soc/mpu_caps.h
components/soc/esp32s3/include/soc/nrx_reg.h
components/soc/esp32s3/include/soc/peri_backup_reg.h
components/soc/esp32s3/include/soc/peri_backup_struct.h
components/soc/esp32s3/include/soc/reset_reasons.h
components/soc/esp32s3/include/soc/rtc_i2c_reg.h
components/soc/esp32s3/include/soc/rtc_i2c_struct.h
components/soc/esp32s3/include/soc/rtc_io_reg.h
components/soc/esp32s3/include/soc/rtc_io_struct.h
components/soc/esp32s3/include/soc/sdmmc_pins.h
components/soc/esp32s3/include/soc/sdmmc_reg.h
components/soc/esp32s3/include/soc/sensitive_reg.h
components/soc/esp32s3/include/soc/sensitive_struct.h
components/soc/esp32s3/include/soc/soc_ulp.h
components/soc/esp32s3/include/soc/spi_mem_reg.h
components/soc/esp32s3/include/soc/spi_mem_struct.h
components/soc/esp32s3/include/soc/spi_reg.h
components/soc/esp32s3/include/soc/spi_struct.h
components/soc/esp32s3/include/soc/syscon_struct.h
components/soc/esp32s3/include/soc/system_reg.h
components/soc/esp32s3/include/soc/system_struct.h
components/soc/esp32s3/include/soc/systimer_reg.h
components/soc/esp32s3/include/soc/systimer_struct.h
components/soc/esp32s3/include/soc/touch_channel.h
components/soc/esp32s3/include/soc/uart_pins.h
components/soc/esp32s3/include/soc/uart_reg.h
components/soc/esp32s3/include/soc/uart_struct.h
components/soc/esp32s3/include/soc/uhci_reg.h
components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
components/soc/esp32s3/include/soc/usb_wrap_reg.h
components/soc/esp32s3/include/soc/usb_wrap_struct.h
components/soc/esp32s3/include/soc/wdev_reg.h
components/soc/esp32s3/ledc_periph.c
components/soc/include/soc/gpio_periph.h
components/soc/include/soc/ledc_periph.h