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Merge branch 'feature/esp32c5_eco2_gpio_update' into 'master'

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feat(gpio): esp32c5 eco2 gpio update

Closes IDF-12653, IDF-12710, and IO22-24

See merge request espressif/esp-idf!38358
This commit is contained in:
morris
2025-04-21 14:29:51 +08:00
parent 186f2a8929 6994be3acd
commit a4d32bb460
24 changed files with 4834 additions and 6575 deletions
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4
components/esp_driver_gpio/src/gpio.c
View File

@@ -75,7 +75,7 @@ static gpio_context_t gpio_context = {
esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
{
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PU)", ESP_ERR_INVALID_ARG);
if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@@ -113,7 +113,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
{
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PD)", ESP_ERR_INVALID_ARG);
if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
portENTER_CRITICAL(&gpio_context.gpio_spinlock);

4
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
View File

@@ -96,7 +96,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_21, //GPIO21
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
#elif CONFIG_IDF_TARGET_ESP32C6
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 8
@@ -146,7 +146,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
};
#elif CONFIG_IDF_TARGET_ESP32C61
#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 7

8
components/hal/esp32c5/include/hal/i2c_ll.h
View File

@@ -82,11 +82,11 @@ typedef enum {
// Record for Pins usage logs
#define LP_I2C_SCL_PIN_ERR_LOG "SCL pin can only be configured as GPIO#7"
#define LP_I2C_SDA_PIN_ERR_LOG "SDA pin can only be configured as GPIO#6"
#define LP_I2C_SCL_PIN_ERR_LOG "SCL pin can only be configured as GPIO#3"
#define LP_I2C_SDA_PIN_ERR_LOG "SDA pin can only be configured as GPIO#2"
#define LP_I2C_SDA_IOMUX_PAD 6
#define LP_I2C_SCL_IOMUX_PAD 7
#define LP_I2C_SDA_IOMUX_PAD 2
#define LP_I2C_SCL_IOMUX_PAD 3
/**
* @brief Calculate I2C bus frequency

14
components/hal/esp32c5/include/hal/rtc_io_ll.h
View File

@@ -101,7 +101,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
*/
static inline void rtcio_ll_output_enable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, out_enable_w1ts, BIT(rtcio_num));
LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num);
}
/**
@@ -111,7 +111,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
*/
static inline void rtcio_ll_output_disable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, out_enable_w1tc, BIT(rtcio_num));
LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num);
}
/**
@@ -123,9 +123,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{
if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_data_w1ts, BIT(rtcio_num));
LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num);
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_data_w1tc, BIT(rtcio_num));
LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num);
}
}
@@ -157,7 +157,7 @@ static inline void rtcio_ll_input_disable(int rtcio_num)
*/
static inline uint32_t rtcio_ll_get_level(int rtcio_num)
{
return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.in, in_data_next) >> rtcio_num) & 0x1;
return (LP_GPIO.in.in_data_next >> rtcio_num) & 0x1;
}
/**
@@ -428,7 +428,7 @@ static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num)
*/
static inline uint32_t rtcio_ll_get_interrupt_status(void)
{
return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.status, status_interrupt);
return LP_GPIO.status.status_interrupt;
}
/**
@@ -436,7 +436,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
*/
static inline void rtcio_ll_clear_interrupt_status(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_intr_w1tc, 0xff);
LP_GPIO.status_w1tc.status_w1tc = 0x7F;
}
#ifdef __cplusplus

15
components/soc/esp32c5/i2c_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,15 +7,7 @@
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
typedef enum {
LP_I2C_MUX_FUNC = 0,
LP_GPIO_MUX_FUNC = 1,
LP_IO_MUX_FUNC_NUM = 2,
LP_MUX_FUNC_NOT_USED = 0xFF,
} lp_io_mux_func_t;
#define LP_I2C_MUX_FUNC (3)
static_assert(SOC_I2C_NUM == (SOC_HP_I2C_NUM + SOC_LP_I2C_NUM));
@@ -26,7 +18,6 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.iomux_func = (uint8_t)LP_MUX_FUNC_NOT_USED,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
/* LP_I2C_NUM_0*/
@@ -35,7 +26,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
.sda_in_sig = 0,
.scl_out_sig = 0,
.scl_in_sig = 0,
.iomux_func = (uint8_t)LP_I2C_MUX_FUNC,
.iomux_func = LP_I2C_MUX_FUNC,
.irq = ETS_LP_I2C_INTR_SOURCE,
},
};

6
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -541,11 +541,11 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 8
default 7
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0000000001FFFF00
default 0x0000000001FFFF80
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
@@ -565,7 +565,7 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
config SOC_RTCIO_PIN_COUNT
int
default 8
default 7
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool

3
components/soc/esp32c5/include/soc/rtc_io_channel.h
View File

@@ -26,6 +26,3 @@
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 6
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 7

10
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -223,11 +223,11 @@
#define SOC_GPIO_IN_RANGE_MAX 28
#define SOC_GPIO_OUT_RANGE_MAX 28
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
@@ -241,7 +241,7 @@
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 8
#define SOC_RTCIO_PIN_COUNT 7
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
* so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
* when the pins are switched to RTC function.

1629
components/soc/esp32c5/register/soc/gpio_ext_reg.h
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File diff suppressed because it is too large Load Diff

299
components/soc/esp32c5/register/soc/gpio_ext_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,21 +10,6 @@
extern "C" {
#endif
/** Group: Clock gate Register */
/** Type of clock_gate register
* Clock Gating Configure Register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Clock enable bit of configuration registers for sigma delta modulation.
*/
uint32_t clk_en: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} gpio_ext_clock_gate_reg_t;
/** Group: SDM Configure Registers */
/** Type of sigmadelta_misc register
* MISC Register
@@ -32,9 +17,10 @@ typedef union {
typedef union {
struct {
/** sigmadelta_clk_en : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the clock for sigma delta modulation.\\
* 0: Not enable\\
* 1: Enable\\%\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved.
* Configures whether or not to enable the clock for sigma delta modulation.
* 0: Not enable
* 1: Enable
* %\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved.
*/
uint32_t sigmadelta_clk_en: 1;
uint32_t reserved_1: 31;
@@ -48,11 +34,11 @@ typedef union {
typedef union {
struct {
/** sdn_in : R/W; bitpos: [7:0]; default: 0;
* Configures the duty cycle of sigma delta modulation output. \\
* Configures the duty cycle of sigma delta modulation output.
*/
uint32_t sdn_in: 8;
/** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
* Configures the divider value to divide IO MUX operating clock. \\
* Configures the divider value to divide IO MUX operating clock.
*/
uint32_t sdn_prescale: 8;
uint32_t reserved_16: 16;
@@ -67,28 +53,28 @@ typedef union {
typedef union {
struct {
/** xpd_comp_0 : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the function of analog PAD voltage comparator.\\
* 0: Disable\\
* 1: Enable\\
* Configures whether to enable the function of analog PAD voltage comparator.
* 0: Disable
* 1: Enable
*/
uint32_t xpd_comp_0: 1;
uint32_t xpd_comp_0:1;
/** mode_comp_0 : R/W; bitpos: [1]; default: 0;
* Configures the reference voltage for analog PAD voltage comparator.. \\
* 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
* used as a regular GPIO\\
* 1: Reference voltage is the voltage on the GPIO8 PAD\\
* Configures the reference voltage for analog PAD voltage comparator..
* 0: Reference voltage is the internal reference voltage, meanwhile GPIO8(GPIO8: need
* be reviewd) PAD can be used as a regular GPIO
* 1: Reference voltage is the voltage on the GPIO8 PAD
*/
uint32_t mode_comp_0: 1;
uint32_t mode_comp_0:1;
/** dref_comp_0 : R/W; bitpos: [4:2]; default: 0;
* Configures the internal reference voltage for analog PAD voltage coparator. \\
* 0: Internal reference voltage is 0 * VDDPST1\\
* 1: Internal reference voltage is 0.1 * VDDPST1\\
* …...\\
* 6: Internal reference voltage is 0.6 * VDDPST1\\
* 7: Internal reference voltage is 0.7 * VDDPST1\\
* Configures the internal reference voltage for analog PAD voltage coparator.
* 0: Internal reference voltage is 0 * VDDPST1(VDDPST1: need be reviewed)
* 1: Internal reference voltage is 0.1 * VDDPST1
* ......
* 6: Internal reference voltage is 0.6 * VDDPST1
* 7: Internal reference voltage is 0.7 * VDDPST1
*/
uint32_t dref_comp_0: 3;
uint32_t reserved_5: 27;
uint32_t dref_comp_0:3;
uint32_t reserved_5:27;
};
uint32_t val;
} gpio_ext_pad_comp_config_0_reg_t;
@@ -100,8 +86,8 @@ typedef union {
struct {
/** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0;
* Configures the period of masking new interrupt source foe analog PAD voltage
* comparator.\\
* Measurement unit: IO MUX operating clock cycle\\
* comparator.
* Measurement unit: IO MUX operating clock cycle
*/
uint32_t zero_det_filter_cnt_0: 32;
};
@@ -116,19 +102,22 @@ typedef union {
/** clk_out1 : R/W; bitpos: [4:0]; default: 0;
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
* CLK_OUT_out1 can be found in peripheral output signals.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t clk_out1: 5;
uint32_t clk_out1:5;
/** clk_out2 : R/W; bitpos: [9:5]; default: 0;
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
* CLK_OUT_out2 can be found in peripheral output signals.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t clk_out2: 5;
uint32_t clk_out2:5;
/** clk_out3 : R/W; bitpos: [14:10]; default: 0;
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
* CLK_OUT_out3 can be found in peripheral output signals.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t clk_out3: 5;
uint32_t reserved_15: 17;
uint32_t clk_out3:5;
uint32_t reserved_15:17;
};
uint32_t val;
} gpio_ext_pin_ctrl_reg_t;
@@ -140,32 +129,33 @@ typedef union {
typedef union {
struct {
/** filter_chn_en : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable channel n of Glitch Filter.\\
* 0: Not enable\\
* 1: Enable\\
* Configures whether or not to enable channel n of Glitch Filter.
* 0: Not enable
* 1: Enable
*/
uint32_t filter_chn_en: 1;
/** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Configures to select the input GPIO for Glitch Filter. \\
* 0: Select GPIO0\\
* 1: Select GPIO1\\
* ......\\
* 27: Select GPIO27\\
* 28: Select GPIO28\\
* 29 ~ 63: Reserved\\
* Configures to select the input GPIO for Glitch Filter.
* 0: Select GPIO0
* 1: Select GPIO1
* ......
* 27: Select GPIO27
* 28: Select GPIO28
* 29 ~ 63: Reserved
*/
uint32_t filter_chn_input_io_num: 6;
uint32_t reserved_7: 1;
/** filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0;
* Configures the window threshold for Glitch Filter. The window threshold should be
* less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.\\ %see DOC-4768\\
* Measurement unit: IO MUX operating clock cycle\\
* less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.
* %see DOC-4768
* Measurement unit: IO MUX operating clock cycle
*/
uint32_t filter_chn_window_thres: 6;
/** filter_chn_window_width : R/W; bitpos: [19:14]; default: 0;
* Configures the window width for Glitch Filter. The effective value of window width
* is 0 ~ 63. \\
* Measurement unit: IO MUX operating clock cycle\\
* is 0 ~ 63.
* Measurement unit: IO MUX operating clock cycle
*/
uint32_t filter_chn_window_width: 6;
uint32_t reserved_20: 12;
@@ -179,24 +169,24 @@ typedef union {
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
* Configures to select GPIO for ETM event channel.\\
* 0: Select GPIO0\\
* 1: Select GPIO1\\
* ......\\
* 27: Select GPIO27\\
* 28: Select GPIO28\\
* 29 ~ 63: Reserved\\
/** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
* Configures to select GPIO for ETM event channel.
* 0: Select GPIO0
* 1: Select GPIO1
* ......
* 27: Select GPIO27
* 28: Select GPIO28
* 29 ~ 63: Reserved
*/
uint32_t etm_chn_event_sel: 6;
uint32_t reserved_6: 1;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable ETM event send.\\
* 0: Not enable\\
* 1: Enable\\
uint32_t etm_chn_event_sel:6;
uint32_t reserved_6:1;
/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable ETM event send.
* 0: Not enable
* 1: Enable
*/
uint32_t etm_chn_event_en: 1;
uint32_t reserved_8: 24;
uint32_t etm_chn_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_ext_etm_event_chn_cfg_reg_t;
@@ -207,126 +197,81 @@ typedef union {
typedef union {
struct {
/** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
* Configures to select an ETM task channel for GPIO0.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t etm_task_gpio0_sel: 3;
uint32_t reserved_3: 2;
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Configures whether or not to enable GPIO0 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t etm_task_gpio0_en: 1;
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
* Configures to select an ETM task channel for GPIO1.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t etm_task_gpio1_sel: 3;
uint32_t reserved_9: 2;
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Configures whether or not to enable GPIO1 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t etm_task_gpio1_en: 1;
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
* Configures to select an ETM task channel for GPIO2.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t etm_task_gpio2_sel: 3;
uint32_t reserved_15: 2;
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Configures whether or not to enable GPIO2 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t etm_task_gpio2_en: 1;
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
* Configures to select an ETM task channel for GPIO3.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t etm_task_gpio3_sel: 3;
uint32_t reserved_21: 2;
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Configures whether or not to enable GPIO3 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t etm_task_gpio3_en: 1;
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
* Configures to select an ETM task channel for GPIO4.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t etm_task_gpio4_sel: 3;
uint32_t reserved_27: 2;
uint32_t etm_task_gpio4_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
* Configures whether or not to enable GPIO4 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t etm_task_gpio4_en: 1;
uint32_t reserved_30: 2;
uint32_t etm_task_gpio4_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_pn_cfg_reg_t;
@@ -426,7 +371,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774208;
/** date : R/W; bitpos: [27:0]; default: 37815040;
* Version control register.
*/
uint32_t date: 28;
@@ -436,7 +381,7 @@ typedef union {
} gpio_ext_version_reg_t;
typedef struct gpio_sd_dev_t {
volatile gpio_ext_clock_gate_reg_t clock_gate;
volatile uint32_t reserved;
volatile gpio_ext_sigmadelta_misc_reg_t misc;
volatile gpio_ext_sigmadeltan_reg_t channel[4];
} gpio_sd_dev_t;

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components/soc/esp32c5/register/soc/gpio_reg.h
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components/soc/esp32c5/register/soc/gpio_struct.h
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31
components/soc/esp32c5/register/soc/io_mux_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -143,7 +143,7 @@ extern "C" {
#define EXT_OSC_SLOW_GPIO_NUM 0
#define MAX_RTC_GPIO_NUM 7
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 28
#define MAX_GPIO_NUM 32
#define DIG_IO_HOLD_BIT_SHIFT 32
@@ -160,11 +160,13 @@ extern "C" {
#define FUNC_XTAL_32K_N_GPIO1 1
#define FUNC_XTAL_32K_N_GPIO1_0 0
// Strapping: Boot Mode select
#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x8)
#define FUNC_MTMS_FSPIQ 2
#define FUNC_MTMS_GPIO2 1
#define FUNC_MTMS_MTMS 0
// Strapping: Boot Mode select/sdio_out_strap
#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0xC)
#define FUNC_MTDI_GPIO3 1
#define FUNC_MTDI_MTDI 0
@@ -187,7 +189,7 @@ extern "C" {
#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C)
#define FUNC_GPIO7_FSPID 2
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define FUNC_GPIO7_SDIO_DATA1 0
#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO8_GPIO8 1
@@ -200,7 +202,7 @@ extern "C" {
#define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO10_FSPICS0 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GPIO10_0 0
#define FUNC_GPIO10_SDIO_CMD 0
#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C)
#define FUNC_U0TXD_GPIO11 1
@@ -212,11 +214,11 @@ extern "C" {
#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define FUNC_GPIO13_SDIO_DATA3 0
#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x38)
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define FUNC_GPIO14_SDIO_DATA2 0
#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x3C)
#define FUNC_SPICS1_GPIO15 1
@@ -258,22 +260,39 @@ extern "C" {
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
// Strapping: sdio_in_strap
#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x64)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0
// Strapping: Boot Mode select (analog mode)
#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x68)
#define FUNC_GPIO26_GPIO26 1
#define FUNC_GPIO26_GPIO26_0 0
// Strapping: Boot Mode select
#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x6C)
#define FUNC_GPIO27_GPIO27 1
#define FUNC_GPIO27_GPIO27_0 0
// Strapping: Boot Mode select
#define PERIPHS_IO_MUX_U_PAD_GPIO28 (REG_IO_MUX_BASE + 0x70)
#define FUNC_GPIO28_GPIO28 1
#define FUNC_GPIO28_GPIO28_0 0
/**
* Strapping Info:
*
* GPIO28,GPIO27,GPIO3,GPIO2,GPIO26:
* 1XXXX: SPI Boot mode
* 01XXX: Download mode by UART0/USB
* 00XX0: Download mode by UART0/SDIO
* 00101: Diag mode0
* 00111: Test mode (GPIO25,should be 1 in mbist mode)
* 00001: analog mode
* 00011: Diag mode1
*/
/** IO_MUX_DATE_REG register
* Version control register
*/

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components/soc/esp32c5/register/soc/lp_gpio_reg.h
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components/soc/esp32c5/register/soc/lp_gpio_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,266 +12,191 @@ extern "C" {
/** Group: configuration register */
/** Type of out register
* LP GPIO output register
* GPIO output register for GPIO0-6
*/
typedef union {
struct {
/** out_data_orig : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures the output of GPIO0 ~ GPIO7.\\
* 0: Low level\\
* 1: High level\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
/** out_data_orig : R/W/WTC; bitpos: [6:0]; default: 0;
* GPIO output register for GPIO0-6
*/
uint32_t out_data_orig:8;
uint32_t reserved_8:24;
uint32_t out_data_orig:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_out_reg_t;
/** Type of out_w1ts register
* LP GPIO output set register
* GPIO output set register for GPIO0-6
*/
typedef union {
struct {
/** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
* will be set to 1.
* - Recommended operation: use this register to set LP_IO_OUT_REG.
/** out_w1ts : WT; bitpos: [6:0]; default: 0;
* GPIO output set register for GPIO0-6
*/
uint32_t out_data_w1ts:8;
uint32_t reserved_8:24;
uint32_t out_w1ts:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* LP GPIO output clear register
* GPIO output clear register for GPIO0-6
*/
typedef union {
struct {
/** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
* will be cleared.
* - Recommended operation: use this register to clear LP_IO_OUT_REG.
/** out_w1tc : WT; bitpos: [6:0]; default: 0;
* GPIO output clear register for GPIO0-6
*/
uint32_t out_data_w1tc:8;
uint32_t reserved_8:24;
uint32_t out_w1tc:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_out_w1tc_reg_t;
/** Type of enable register
* LP GPIO output enable register
* GPIO output enable register for GPIO0-6
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures whether or not to enable the output of GPIO0 ~ GPIO7.\\
* 0: Not enable\\
* 1: Enable\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
/** enable_data : R/W/WTC; bitpos: [6:0]; default: 0;
* GPIO output enable register for GPIO0-6
*/
uint32_t enable_data:8;
uint32_t reserved_8:24;
uint32_t enable_data:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_enable_reg_t;
/** Type of enable_w1ts register
* LP GPIO output enable set register
* GPIO output enable set register for GPIO0-6
*/
typedef union {
struct {
/** out_enable_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_ENABLE_REG will be set to 1.
* - Recommended operation: use this register to set LP_IO_ENABLE_REG.
/** enable_w1ts : WT; bitpos: [6:0]; default: 0;
* GPIO output enable set register for GPIO0-6
*/
uint32_t out_enable_w1ts:8;
uint32_t reserved_8:24;
uint32_t enable_w1ts:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* LP GPIO output enable clear register
* GPIO output enable clear register for GPIO0-6
*/
typedef union {
struct {
/** out_enable_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_ENABLE_REG will be cleared.
* - Recommended operation: use this register to clear LP_IO_ENABLE_REG.
/** enable_w1tc : WT; bitpos: [6:0]; default: 0;
* GPIO output enable clear register for GPIO0-6
*/
uint32_t out_enable_w1tc:8;
uint32_t reserved_8:24;
uint32_t enable_w1tc:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_enable_w1tc_reg_t;
/** Type of in register
* LP GPIO input register
* GPIO input register for GPIO0-6
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [7:0]; default: 0;
* Represents the input value of GPIO0 ~ GPIO7.\\
* 0: Low level input\\
* 1: High level input\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
/** in_data_next : RO; bitpos: [6:0]; default: 0;
* GPIO input register for GPIO0-6
*/
uint32_t in_data_next:8;
uint32_t reserved_8:24;
uint32_t in_data_next:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_in_reg_t;
/** Type of status register
* LP GPIO interrupt status register
* GPIO interrupt status register for GPIO0-6
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures the interrupt status of GPIO0 ~ GPIO7.\\
* 0: No interrupt\\
* 1: Interrupt is triggered\\
* Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. This
* register is used together LP_IO_PIN$n_INT_TYPE in register LP_IO_PIN$n_REG.\\
/** status_interrupt : R/W/WTC; bitpos: [6:0]; default: 0;
* GPIO interrupt status register for GPIO0-6
*/
uint32_t status_interrupt:8;
uint32_t reserved_8:24;
uint32_t status_interrupt:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_status_reg_t;
/** Type of status_w1ts register
* LP GPIO interrupt status set register
* GPIO interrupt status set register for GPIO0-6
*/
typedef union {
struct {
/** status_intr_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of
* GPIO0 ~ GPIO7.\\
*
* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_STATUS_INT will be set to 1.
* - Recommended operation: use this register to set LP_IO_STATUS_INT.
/** status_w1ts : WT; bitpos: [6:0]; default: 0;
* GPIO interrupt status set register for GPIO0-6
*/
uint32_t status_intr_w1ts:8;
uint32_t reserved_8:24;
uint32_t status_w1ts:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* LP GPIO interrupt status clear register
* GPIO interrupt status clear register for GPIO0-6
*/
typedef union {
struct {
/** status_intr_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT
* of GPIO0 ~ GPIO7. \\
*
* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_STATUS_INT will be cleared
* - ecommended operation: use this register to clear LP_IO_STATUS_INT.
/** status_w1tc : WT; bitpos: [6:0]; default: 0;
* GPIO interrupt status clear register for GPIO0-6
*/
uint32_t status_intr_w1tc:8;
uint32_t reserved_8:24;
uint32_t status_w1tc:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_status_w1tc_reg_t;
/** Type of status_next register
* LP GPIO interrupt source register
* GPIO interrupt source register for GPIO0-6
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
* Represents the interrupt source status of GPIO0 ~ GPIO7.\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ 7. Each bit represents:\\
* 0: Interrupt source status is invalid.\\
* 1: Interrupt source status is valid.\\
* The interrupt here can be rising-edge triggered, falling-edge triggered, any edge
* triggered, or level triggered.\\
/** status_interrupt_next : RO; bitpos: [6:0]; default: 0;
* GPIO interrupt source register for GPIO0-6
*/
uint32_t status_interrupt_next:8;
uint32_t reserved_8:24;
uint32_t status_interrupt_next:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_gpio_status_next_reg_t;
/** Type of pinn register
* LP GPIO0 configuration register
* GPIO pin configuration register
*/
typedef union {
struct {
/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
* set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t pinn_sync2_bypass:2;
/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIOn.\\
* 0: Normal output\\
* 1: Open drain output\\
* set this bit to select pad driver. 1:open-drain. 0:normal.
*/
uint32_t pinn_pad_driver:1;
/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
* set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t pinn_sync1_bypass:2;
/** pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
* GPIO wakeup clear register.
*/
uint32_t pinn_edge_wakeup_clr:1;
uint32_t reserved_6:1;
/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIOn interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
* set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
* posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
* at high level
*/
uint32_t pinn_int_type:3;
/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIOn wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
* set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
*/
uint32_t pinn_wakeup_enable:1;
uint32_t reserved_11:21;
@@ -280,21 +205,17 @@ typedef union {
} lp_gpio_pinn_reg_t;
/** Type of funcn_out_sel_cfg register
* Configuration register for GPIO0 output
* GPIO output function select register
*/
typedef union {
struct {
/** funcn_out_inv_sel : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
* set this bit to invert output signal.1:invert.0:not invert.
*/
uint32_t funcn_out_inv_sel:1;
uint32_t reserved_1:1;
/** funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
* set this bit to invert output enable signal.1:invert.0:not invert.
*/
uint32_t funcn_oe_inv_sel:1;
uint32_t reserved_3:29;
@@ -308,7 +229,7 @@ typedef union {
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* set this bit to enable GPIO clock gate.\\
* set this bit to enable GPIO clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
@@ -321,8 +242,8 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36773904;
* version register.\\
/** date : R/W; bitpos: [27:0]; default: 37814832;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
@@ -344,10 +265,10 @@ typedef struct {
volatile lp_gpio_status_w1ts_reg_t status_w1ts;
volatile lp_gpio_status_w1tc_reg_t status_w1tc;
volatile lp_gpio_status_next_reg_t status_next;
volatile lp_gpio_pinn_reg_t pinn[8];
uint32_t reserved_050[152];
volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[8];
uint32_t reserved_2d0[74];
volatile lp_gpio_pinn_reg_t pinn[7];
uint32_t reserved_04c[153];
volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[7];
uint32_t reserved_2cc[75];
volatile lp_gpio_clock_gate_reg_t clock_gate;
volatile lp_gpio_date_reg_t date;
} lp_gpio_dev_t;

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components/soc/esp32c5/register/soc/lp_iomux_reg.h
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components/soc/esp32c5/register/soc/lp_iomux_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,102 +12,71 @@ extern "C" {
/** Group: Configure Registers */
/** Type of gpion register
* LP_IO_MUX Configure Register for pad GPIO0
* LP_IO_MUX Configure Register for pad GPIOn
*/
typedef union {
struct {
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of GPIOn during sleep mode.\\
* 0: Not enable\\
* 1: Enable\\
* Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.
*/
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enable the sleep mode for GPIOn.\\
* 0: Not enable\\
* 1: Enable\\
* Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
*/
uint32_t gpion_slp_sel:1;
/** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable the pull-down resistor of GPIOn during sleep
* mode. \\
* 0: Not enable\\
* 1: Enable\\
* Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0:
* internal pull-down disabled.
*/
uint32_t gpion_mcu_wpd:1;
/** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable the pull-up resistor of GPIOn during sleep
* mode.\\
* 0: Not enable\\
* 1: Enable\\
* Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0:
* internal pull-up disabled.
*/
uint32_t gpion_mcu_wpu:1;
/** gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of GPIOn during sleep mode.\\
* 0: Not enable\\
* 1: Enable\\
* Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_mcu_ie:1;
/** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of GPIOn during sleep mode. \\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
* Select the drive strength of the pad during sleep mode.
*/
uint32_t gpion_mcu_drv:2;
/** gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable the pull-down resistor of GPIOn in normal
* execution mode.\\
* 0: Not enable\\
* 1: Enable\\
* Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down
* disabled.
*/
uint32_t gpion_fun_wpd:1;
/** gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable the pull-up resistor of GPIOn in normal
* execution mode.\\
* 0: Not enable\\
* 1: Enable\\
* Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up
* disabled.
*/
uint32_t gpion_fun_wpu:1;
/** gpion_fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable the input of GPIOn in normal execution mode.\\
* 0: Not enable\\
* 1: Enable\\
* Input enable of the pad. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_fun_ie:1;
/** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of GPIOn in normal execution mode.\\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
* Select the drive strength of the pad.
*/
uint32_t gpion_fun_drv:2;
/** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select the LP IO MUX function for GPIOn in normal execution mode.\\
* 0: Select Function 0\\
* 1: Select Function 1\\
* ......\\
* Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2.
* etc.
*/
uint32_t gpion_mcu_sel:3;
/** gpion_filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.\\
* 0: Disable\\
* 1: Enable\\
* Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.
*/
uint32_t gpion_filter_en:1;
/** gpion_hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_GPIOn_HYS_SEL is set to 1.\\
* 0: Disable\\
* 1: Enable\\
* Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0:
* Hysteresis disabled.
*/
uint32_t gpion_hys_en:1;
/** gpion_hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for GPIOn. \\
* 0: Choose the output enable signal of eFuse\\
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN\\
* Select enabling signals of the pad from software and efuse hardware. 1: Select
* enabling signal from slftware. 0: Select enabling signal from efuse hardware.
*/
uint32_t gpion_hys_sel:1;
uint32_t reserved_18:14;
@@ -121,7 +90,7 @@ typedef union {
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 35721840;
* Version control register. \\
* Version control register
*/
uint32_t reg_date:28;
uint32_t reserved_28:4;
@@ -131,8 +100,8 @@ typedef union {
typedef struct {
volatile lp_io_mux_gpion_reg_t gpion[8];
uint32_t reserved_020[119];
volatile lp_io_mux_gpion_reg_t gpion[7];
uint32_t reserved_01c[120];
volatile lp_io_mux_date_reg_t date;
} lp_io_mux_dev_t;

2
components/soc/esp32c5/rtc_io_periph.c
View File

@@ -14,7 +14,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO4_CHANNEL, //GPIO4
RTCIO_GPIO5_CHANNEL, //GPIO5
RTCIO_GPIO6_CHANNEL, //GPIO6
RTCIO_GPIO7_CHANNEL, //GPIO7
-1,//GPIO7
-1,//GPIO8
-1,//GPIO9
-1,//GPIO10

10
components/soc/esp32c5/system_retention_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -49,17 +49,17 @@ const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
/* IO MUX Registers Context */
#define N_REGS_IOMUX_0() (((PERIPHS_IO_MUX_U_PAD_GPIO28 - REG_IO_MUX_BASE) / 4) + 1)
#define N_REGS_IOMUX_1() (((GPIO_FUNC32_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_0() (SOC_GPIO_PIN_COUNT)
#define N_REGS_IOMUX_1() (SOC_GPIO_PIN_COUNT)
#define N_REGS_IOMUX_2() (((GPIO_FUNC116_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_3() (((GPIO_PIN32_REG - GPIO_PIN0_REG) / 4) + 1)
#define N_REGS_IOMUX_3() (SOC_GPIO_PIN_COUNT)
#define GPIO_RETENTION_REGS_CNT 6
#define GPIO_RETENTION_MAP_BASE GPIO_OUT_REG
static const uint32_t gpio_regs_map[4] = {0x90009009, 0, 0, 0};
const regdma_entries_config_t iomux_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), IO_MUX_GPIO0_REG, IO_MUX_GPIO0_REG, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },

10
components/soc/esp32c61/system_retention_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -45,16 +45,16 @@ const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
/* IO MUX Registers Context */
#define N_REGS_IOMUX_0() (((PERIPHS_IO_MUX_U_PAD_SPID - REG_IO_MUX_BASE) / 4) + 1)
#define N_REGS_IOMUX_1() (((GPIO_FUNC21_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_0() (SOC_GPIO_PIN_COUNT)
#define N_REGS_IOMUX_1() (SOC_GPIO_PIN_COUNT)
#define N_REGS_IOMUX_2() (((GPIO_FUNC121_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_3() (((GPIO_PIN21_REG - GPIO_PIN0_REG) / 4) + 1)
#define N_REGS_IOMUX_3() (SOC_GPIO_PIN_COUNT)
#define N_REGS_IOMUX_4() (1)
#define N_REGS_IOMUX_5() (1)
#define N_REGS_IOMUX_6() (1)
const regdma_entries_config_t iomux_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), IO_MUX_GPIO0_REG, IO_MUX_GPIO0_REG, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },

12
components/ulp/lp_core/lp_core_i2c.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,8 +7,8 @@
#include "lp_core_i2c.h"
#include "esp_check.h"
#include "hal/i2c_hal.h"
#include "hal/i2c_ll.h"
#include "driver/rtc_io.h"
#include "soc/rtc_io_channel.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/periph_ctrl.h"
@@ -32,13 +32,13 @@ static esp_err_t lp_i2c_gpio_is_cfg_valid(gpio_num_t sda_io_num, gpio_num_t scl_
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
/* Verify that the SDA and SCL line belong to the LP IO Mux I2C function group */
if (sda_io_num != RTCIO_GPIO6_CHANNEL) {
ESP_LOGE(LPI2C_TAG, "SDA pin can only be configured as GPIO#6");
if (sda_io_num != LP_I2C_SDA_IOMUX_PAD) {
ESP_LOGE(LPI2C_TAG, LP_I2C_SDA_PIN_ERR_LOG);
return ESP_ERR_INVALID_ARG;
}
if (scl_io_num != RTCIO_GPIO7_CHANNEL) {
ESP_LOGE(LPI2C_TAG, "SCL pin can only be configured as GPIO#7");
if (scl_io_num != LP_I2C_SCL_IOMUX_PAD) {
ESP_LOGE(LPI2C_TAG, LP_I2C_SCL_PIN_ERR_LOG);
return ESP_ERR_INVALID_ARG;
}
#endif /* !SOC_LP_GPIO_MATRIX_SUPPORTED */

6
docs/en/api-reference/peripherals/gpio/esp32c5.inc
View File

@@ -59,7 +59,7 @@ The table below provides more information on pin usage, and please note the comm
* - GPIO7
-
- LP_GPIO7
-
- Strapping pin
* - GPIO8
@@ -150,7 +150,7 @@ The table below provides more information on pin usage, and please note the comm
* - GPIO25
-
-
-
- Strapping pin
* - GPIO26
-
@@ -169,7 +169,7 @@ The table below provides more information on pin usage, and please note the comm
.. note::
- Strapping pin: GPIO2, GPIO7, GPIO27, and GPIO28 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
- Strapping pin: GPIO2, GPIO7, GPIO25, GPIO27, and GPIO28 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
- SPI0/1: GPIO16 ~ GPIO22 are usually used for SPI flash and PSRAM, they're not recommended for other uses.
- USB-JTAG: GPIO13 and GPIO14 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled.

6
docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc
View File

@@ -59,7 +59,7 @@
* - GPIO7
-
- LP_GPIO7
-
- Strapping 管脚
* - GPIO8
@@ -150,7 +150,7 @@
* - GPIO25
-
-
-
- Strapping 管脚
* - GPIO26
-
@@ -169,7 +169,7 @@
.. note::
- Strapping 管脚：GPIO2、GPIO7、GPIO27 和 GPIO28 是 Strapping 管脚。更多信息请参考 `ESP32-C5 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
- Strapping 管脚：GPIO2、GPIO7、GPIO25、GPIO27 和 GPIO28 是 Strapping 管脚。更多信息请参考 `ESP32-C5 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
- SPI0/1：GPIO16 ~ GPIO22 通常用于 SPI flash 和 PSRAM，不推荐用于其他用途。
- USB-JTAG：GPIO13 和 GPIO14 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。

14
examples/system/deep_sleep/main/Kconfig.projbuild
View File

@@ -41,8 +41,8 @@ menu "Example Configuration"
depends on !IDF_TARGET_ESP32
default 2 if !IDF_TARGET_ESP32H2
default 10 if IDF_TARGET_ESP32H2
range 0 7 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5
range 0 6 if IDF_TARGET_ESP32C61
range 0 7 if IDF_TARGET_ESP32C6
range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5
range 7 14 if IDF_TARGET_ESP32H2
range 0 21 if IDF_TARGET_ESP32S2
range 0 21 if IDF_TARGET_ESP32S3
@@ -117,8 +117,8 @@ menu "Example Configuration"
depends on !IDF_TARGET_ESP32
default 4 if !IDF_TARGET_ESP32H2
default 11 if IDF_TARGET_ESP32H2
range 0 7 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5
range 0 6 if IDF_TARGET_ESP32C61
range 0 7 if IDF_TARGET_ESP32C6
range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5
range 7 14 if IDF_TARGET_ESP32H2
range 0 21 if IDF_TARGET_ESP32S2
range 0 21 if IDF_TARGET_ESP32S3
@@ -272,10 +272,10 @@ menu "Example Configuration"
config EXAMPLE_GPIO_WAKEUP_PIN
int "Enable wakeup from GPIO"
default 0
range 0 7 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5
range 0 6 if IDF_TARGET_ESP32C61
range 0 7 if IDF_TARGET_ESP32C6
range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5
range 0 15 if IDF_TARGET_ESP32P4
range 0 5 if !IDF_TARGET_ESP32C6 && !IDF_TARGET_ESP32C5
range 0 5
config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL
bool "Enable GPIO high-level wakeup"