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fix(esp_driver_gpio): esp32c61 gpio number update 22 -> 25

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This commit is contained in:
wanckl
2024-11-07 17:48:21 +08:00
parent 5e056de1e7
commit a50c095df1
14 changed files with 483 additions and 56 deletions
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6
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
View File

@@ -83,16 +83,16 @@ TEST_CASE("GPIO_config_parameters_test", "[gpio]")
TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
// test a non-exist pin
io_config.pin_bit_mask = ((uint64_t)1 << GPIO_NUM_MAX);
io_config.pin_bit_mask = BIT64(GPIO_NUM_MAX);
TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
// test an available pin
io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_EXT_OUT_IO);
io_config.pin_bit_mask = BIT64(TEST_GPIO_EXT_OUT_IO);
TEST_ESP_OK(gpio_config(&io_config));
//This IO is just used for input, C3 and S3 doesn't have input only pin.
#if SOC_HAS_INPUT_ONLY_PIN
io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
io_config.pin_bit_mask = BIT64(TEST_GPIO_INPUT_ONLY_PIN);
io_config.mode = GPIO_MODE_INPUT;
TEST_ESP_OK(gpio_config(&io_config));
io_config.mode = GPIO_MODE_OUTPUT;

33
components/esp_rom/esp32c5/include/esp32c5/rom/gpio.h
View File

@@ -44,7 +44,7 @@ typedef enum {
/**
* @brief Change GPIO(0-30) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* @brief Change GPIO(0-28) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
@@ -61,7 +61,7 @@ typedef enum {
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-30) and returns a bitmask.
* @brief Sample the value of GPIO input pins(0-28) and returns a bitmask.
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
@@ -69,7 +69,7 @@ void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mas
uint32_t gpio_input_get(void);
/**
* @brief Set GPIO to wakeup the ESP32.
* @brief Set GPIO to wakeup.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
@@ -81,7 +81,7 @@ uint32_t gpio_input_get(void);
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* @brief disable GPIOs to wakeup.
* Please do not call this function in SDK.
*
* @param None
@@ -93,10 +93,9 @@ void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~30
* gpio == 0x3C, input 0 to signal
* gpio == 0x3A, input nothing to signal
* gpio == 0x38, input 1 to signal
* @param uint32_t gpio : gpio number, 0~28
* gpio == 0x60, input 0 to signal
* gpio == 0x40, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
@@ -109,7 +108,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~30
* @param uint32_t gpio : gpio number, 0~28
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x80, cancel output put to the gpio
@@ -125,7 +124,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @return None
*/
@@ -134,7 +133,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @param uint32_t drv : 0-3
*
@@ -145,7 +144,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @return None
*/
@@ -154,7 +153,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @return None
*/
@@ -163,7 +162,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @return None
*/
@@ -172,7 +171,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @return None
*/
@@ -181,7 +180,7 @@ void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @return None
*/
@@ -190,7 +189,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~28
*
* @return None
*/

33
components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h
View File

@@ -44,7 +44,7 @@ typedef enum {
/**
* @brief Change GPIO(0-30) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* @brief Change GPIO(0-24) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
@@ -61,7 +61,7 @@ typedef enum {
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-30) and returns a bitmask.
* @brief Sample the value of GPIO input pins(0-24) and returns a bitmask.
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
@@ -69,7 +69,7 @@ void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mas
uint32_t gpio_input_get(void);
/**
* @brief Set GPIO to wakeup the ESP32.
* @brief Set GPIO to wakeup.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
@@ -81,7 +81,7 @@ uint32_t gpio_input_get(void);
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* @brief disable GPIOs to wakeup.
* Please do not call this function in SDK.
*
* @param None
@@ -93,10 +93,9 @@ void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~30
* gpio == 0x3C, input 0 to signal
* gpio == 0x3A, input nothing to signal
* gpio == 0x38, input 1 to signal
* @param uint32_t gpio : gpio number, 0~24
* gpio == 0x30, input 0 to signal
* gpio == 0x20, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
@@ -109,7 +108,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~30
* @param uint32_t gpio : gpio number, 0~24
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x80, cancel output put to the gpio
@@ -125,7 +124,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @return None
*/
@@ -134,7 +133,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @param uint32_t drv : 0-3
*
@@ -145,7 +144,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @return None
*/
@@ -154,7 +153,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @return None
*/
@@ -163,7 +162,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @return None
*/
@@ -172,7 +171,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @return None
*/
@@ -181,7 +180,7 @@ void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @return None
*/
@@ -190,7 +189,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~30
* @param uint32_t gpio_num : gpio number, 0~24
*
* @return None
*/

3
components/soc/esp32c61/gpio_periph.c
View File

@@ -29,6 +29,9 @@ const uint32_t GPIO_HOLD_MASK[] = {
BIT(19), //GPIO19
BIT(20), //GPIO20
BIT(21), //GPIO21
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

8
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -301,7 +301,7 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 22
default 25
config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
@@ -325,11 +325,11 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
config SOC_GPIO_IN_RANGE_MAX
int
default 21
default 24
config SOC_GPIO_OUT_RANGE_MAX
int
default 21
default 24
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
@@ -345,7 +345,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00000000003FFF80
default 0x1FFFF80
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool

3
components/soc/esp32c61/include/soc/gpio_num.h
View File

@@ -37,6 +37,9 @@ typedef enum {
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_MAX,
} gpio_num_t;

12
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -159,7 +159,7 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C61 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 22
#define SOC_GPIO_PIN_COUNT 25
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
@@ -173,19 +173,19 @@
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_GPIO_MASK ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_IN_RANGE_MAX 24
#define SOC_GPIO_OUT_RANGE_MAX 24
// GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFF80ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_24)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x1FFFF80ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)

375
components/soc/esp32c61/register/soc/gpio_reg.h
View File

@@ -1844,6 +1844,225 @@ extern "C" {
#define GPIO_PIN21_INT_ENA_V 0x0000001FU
#define GPIO_PIN21_INT_ENA_S 13
/** GPIO_PIN22_REG register
* GPIO22 configuration register
*/
#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c)
/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_S 0
/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN22_PAD_DRIVER (BIT(2))
#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN22_PAD_DRIVER_S 2
/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_S 3
/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN22_INT_TYPE 0x00000007U
#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
#define GPIO_PIN22_INT_TYPE_V 0x00000007U
#define GPIO_PIN22_INT_TYPE_S 7
/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN22_WAKEUP_ENABLE_S 10
/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN22_INT_ENA 0x0000001FU
#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
#define GPIO_PIN22_INT_ENA_V 0x0000001FU
#define GPIO_PIN22_INT_ENA_S 13
/** GPIO_PIN23_REG register
* GPIO23 configuration register
*/
#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120)
/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_S 0
/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN23_PAD_DRIVER (BIT(2))
#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN23_PAD_DRIVER_S 2
/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_S 3
/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN23_INT_TYPE 0x00000007U
#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
#define GPIO_PIN23_INT_TYPE_V 0x00000007U
#define GPIO_PIN23_INT_TYPE_S 7
/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN23_WAKEUP_ENABLE_S 10
/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN23_INT_ENA 0x0000001FU
#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
#define GPIO_PIN23_INT_ENA_V 0x0000001FU
#define GPIO_PIN23_INT_ENA_S 13
/** GPIO_PIN24_REG register
* GPIO24 configuration register
*/
#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124)
/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_S 0
/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN24_PAD_DRIVER (BIT(2))
#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN24_PAD_DRIVER_S 2
/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_S 3
/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN24_INT_TYPE 0x00000007U
#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
#define GPIO_PIN24_INT_TYPE_V 0x00000007U
#define GPIO_PIN24_INT_TYPE_S 7
/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN24_WAKEUP_ENABLE_S 10
/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN24_INT_ENA 0x0000001FU
#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
#define GPIO_PIN24_INT_ENA_V 0x0000001FU
#define GPIO_PIN24_INT_ENA_S 13
/** GPIO_FUNC0_IN_SEL_CFG_REG register
* Configuration register for input signal 0
*/
@@ -4782,6 +5001,162 @@ extern "C" {
#define GPIO_FUNC21_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC21_OE_INV_SEL_S 11
/** GPIO_FUNC22_OUT_SEL_CFG_REG register
* Configuration register for GPIO22 output
*/
#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c)
/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO22.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC22_OUT_SEL 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
#define GPIO_FUNC22_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_S 0
/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OUT_INV_SEL_S 9
/** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC22_OE_SEL (BIT(10))
#define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S)
#define GPIO_FUNC22_OE_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_SEL_S 10
/** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OE_INV_SEL (BIT(11))
#define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S)
#define GPIO_FUNC22_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_INV_SEL_S 11
/** GPIO_FUNC23_OUT_SEL_CFG_REG register
* Configuration register for GPIO23 output
*/
#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20)
/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO23.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC23_OUT_SEL 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
#define GPIO_FUNC23_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_S 0
/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OUT_INV_SEL_S 9
/** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC23_OE_SEL (BIT(10))
#define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S)
#define GPIO_FUNC23_OE_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_SEL_S 10
/** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OE_INV_SEL (BIT(11))
#define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S)
#define GPIO_FUNC23_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_INV_SEL_S 11
/** GPIO_FUNC24_OUT_SEL_CFG_REG register
* Configuration register for GPIO24 output
*/
#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24)
/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO24.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC24_OUT_SEL 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
#define GPIO_FUNC24_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_S 0
/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OUT_INV_SEL_S 9
/** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC24_OE_SEL (BIT(10))
#define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S)
#define GPIO_FUNC24_OE_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_SEL_S 10
/** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OE_INV_SEL (BIT(11))
#define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S)
#define GPIO_FUNC24_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_INV_SEL_S 11
/** GPIO_CLOCK_GATE_REG register
* GPIO clock gate register
*/

8
components/soc/esp32c61/register/soc/gpio_struct.h
View File

@@ -468,12 +468,12 @@ typedef struct {
uint32_t reserved_0a8[3];
volatile gpio_status_next_reg_t status_next;
uint32_t reserved_0b8[3];
volatile gpio_pinn_reg_t pinn[22]; // 0-21 are fanned out, 22-24 are not fanned out but padded out, 25-28 are not padded out. Only 0-21 are available.
uint32_t reserved_11c[106];
volatile gpio_pinn_reg_t pinn[25]; // 0-24 are fanned out, 25-28 are not padded out. Only 0-24 are available.
uint32_t reserved_128[103];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
uint32_t reserved_4ac[256];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[22];
uint32_t reserved_b1c[183];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25];
uint32_t reserved_b28[180];
volatile gpio_clock_gate_reg_t clock_gate;
volatile gpio_date_reg_t date;
} gpio_dev_t;

17
components/soc/esp32c61/register/soc/io_mux_reg.h
View File

@@ -117,6 +117,9 @@ extern "C" {
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24
#define PIN_FUNC_GPIO 1
@@ -130,7 +133,7 @@ extern "C" {
#define EXT_OSC_SLOW_GPIO_NUM 0
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 24
#define MAX_GPIO_NUM 28
#define HIGH_IO_HOLD_BIT_SHIFT 32
@@ -232,6 +235,18 @@ extern "C" {
#define FUNC_SPID_GPIO21 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
/** IO_MUX_DATE_REG register
* Version control register
*/

4
components/soc/esp32c61/register/soc/io_mux_struct.h
View File

@@ -129,8 +129,8 @@ typedef union {
typedef struct {
volatile io_mux_gpion_reg_t gpion[22];
uint32_t reserved_058[105];
volatile io_mux_gpion_reg_t gpion[25];
uint32_t reserved_064[102];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;

3
components/soc/esp32c61/rtc_io_periph.c
View File

@@ -29,4 +29,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-1,//GPIO19
-1,//GPIO20
-1,//GPIO21
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
};

17
docs/en/api-reference/peripherals/gpio/esp32c61.inc
View File

@@ -9,7 +9,7 @@
.. gpio-summary
The {IDF_TARGET_NAME} chip features 22 physical GPIO pins (GPIO0 ~ GPIO21). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The {IDF_TARGET_NAME} chip features 25 physical GPIO pins (GPIO0 ~ GPIO24). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
@@ -132,6 +132,21 @@ The table below provides more information on pin usage, and please note the comm
-
- SPI0/1
* - GPIO22
-
-
-
* - GPIO23
-
-
-
* - GPIO24
-
-
-
.. note::
- Some pins are used as strapping pins, which can be used to select in which boot mode to load the chip, etc.. The details can be found in `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`_ > ``Strapping Pins``.

17
docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
View File

@@ -9,7 +9,7 @@
.. gpio-summary
{IDF_TARGET_NAME} 芯片具有 22 个物理 GPIO 管脚（GPIO0 ~ GPIO21）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
{IDF_TARGET_NAME} 芯片具有 25 个物理 GPIO 管脚（GPIO0 ~ GPIO24）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
@@ -132,6 +132,21 @@
-
- SPI0/1
* - GPIO22
-
-
-
* - GPIO23
-
-
-
* - GPIO24
-
-
-
.. note::
- 其中一些管脚被用作 Strapping 管脚，可用于选择加载芯片的启动模式等。详细信息请见 `ESP32-C61 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_ > ``Strapping 管脚``。