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Merge branch 'feat/h21_introduce_step2_soc' into 'master'

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feat(esp32h21): add soc register header files (stage 2/8, part 1/3)

See merge request espressif/esp-idf!34602
This commit is contained in:
Gao Xu
2024-12-05 15:34:23 +08:00
parent 3029a4b97b 6731d75174
commit ab1d025abb
84 changed files with 103755 additions and 0 deletions
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components/soc/esp32h21/include/soc/spi_mem_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/spi_mem_c_reg.h"
#include "soc/spi1_mem_reg.h"

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components/soc/esp32h21/include/soc/spi_mem_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/spi_mem_c_struct.h"
#include "soc/spi1_mem_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct spi1_mem_dev_s spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM1;
extern spi_mem_c_dev_t SPIMEM0;
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/aes_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* AES key data register 0
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* AES key data register 1
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_2_REG register
* AES key data register 2
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_3_REG register
* AES key data register 3
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_4_REG register
* AES key data register 4
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_5_REG register
* AES key data register 5
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_6_REG register
* AES key data register 6
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_7_REG register
* AES key data register 7
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_TEXT_IN_0_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* Source text data register 1
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_2_REG register
* Source text data register 2
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_3_REG register
* Source text data register 3
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_OUT_0_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* Result text data register 1
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_2_REG register
* Result text data register 2
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_3_REG register
* Result text data register 3
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_MODE_REG register
* Defines key length and encryption / decryption
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_TRIGGER_REG register
* Operation start controlling register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* Operation status register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* Selects the working mode of the AES accelerator
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* Defines the block cipher mode
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* Block number configuration register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_INT_CLEAR_REG register
* DMA-AES interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* DMA-AES interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [27:0]; default: 2360593;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x0FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x0FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* Operation exit controlling register
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
/** AES_RX_RESET_REG register
* AES-DMA reset rx-fifo register
*/
#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
#define AES_RX_RESET (BIT(0))
#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
#define AES_RX_RESET_V 0x00000001U
#define AES_RX_RESET_S 0
/** AES_TX_RESET_REG register
* AES-DMA reset tx-fifo register
*/
#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
#define AES_TX_RESET (BIT(0))
#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
#define AES_TX_RESET_V 0x00000001U
#define AES_TX_RESET_S 0
/** AES_PSEUDO_REG register
* AES PSEUDO function configure register
*/
#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
#define AES_PSEUDO_EN (BIT(0))
#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
#define AES_PSEUDO_EN_V 0x00000001U
#define AES_PSEUDO_EN_S 0
/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
#define AES_PSEUDO_BASE 0x0000000FU
#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
#define AES_PSEUDO_BASE_V 0x0000000FU
#define AES_PSEUDO_BASE_S 1
/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
#define AES_PSEUDO_INC 0x00000003U
#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
#define AES_PSEUDO_INC_V 0x00000003U
#define AES_PSEUDO_INC_S 5
/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
#define AES_PSEUDO_RNG_CNT 0x00000007U
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
#define AES_PSEUDO_RNG_CNT_S 7
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Key Registers */
/** Type of key_n register
* AES key data register n
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_n_reg_t;
/** Group: TEXT_IN Registers */
/** Type of text_in_n register
* Source text data register n
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_n_reg_t;
/** Group: TEXT_OUT Registers */
/** Type of text_out_n register
* Result text data register n
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_n_reg_t;
/** Group: Control / Configuration Registers */
/** Type of mode register
* Defines key length and encryption / decryption
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of trigger register
* Operation start controlling register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of dma_enable register
* Selects the working mode of the AES accelerator
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of block_mode register
* Defines the block cipher mode
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* Block number configuration register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Type of dma_exit register
* Operation exit controlling register
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Type of rx_reset register
* AES-DMA reset rx-fifo register
*/
typedef union {
struct {
/** rx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
uint32_t rx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_rx_reset_reg_t;
/** Type of tx_reset register
* AES-DMA reset tx-fifo register
*/
typedef union {
struct {
/** tx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
uint32_t tx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_tx_reset_reg_t;
/** Group: Configuration register */
/** Type of pseudo register
* AES PSEUDO function configure register
*/
typedef union {
struct {
/** pseudo_en : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
uint32_t pseudo_en:1;
/** pseudo_base : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
uint32_t pseudo_base:4;
/** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
uint32_t pseudo_inc:2;
/** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
uint32_t pseudo_rng_cnt:3;
uint32_t reserved_10:22;
};
uint32_t val;
} aes_pseudo_reg_t;
/** Group: Status Register */
/** Type of state register
* Operation status register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Group: memory type */
/** Group: Interrupt Registers */
/** Type of int_clear register
* DMA-AES interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* DMA-AES interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 2360593;
* This bits stores the version information of AES.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} aes_date_reg_t;
typedef struct {
volatile aes_key_n_reg_t key_n[8];
volatile aes_text_in_n_reg_t text_in_n[4];
volatile aes_text_out_n_reg_t text_out_n[4];
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
uint32_t reserved_0bc;
volatile aes_rx_reset_reg_t rx_reset;
volatile aes_tx_reset_reg_t tx_reset;
uint32_t reserved_0c8[2];
volatile aes_pseudo_reg_t pseudo;
} aes_dev_t;
extern aes_dev_t AES;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/apb_saradc_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** APB_SARADC_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0)
/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
#define APB_SARADC_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U
#define APB_SARADC_SARADC_START_FORCE_S 0
/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
#define APB_SARADC_SARADC_START (BIT(1))
#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
#define APB_SARADC_SARADC_START_V 0x00000001U
#define APB_SARADC_SARADC_START_S 1
/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U
#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6
/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7
/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15
/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23
/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27
/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29))
#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U
#define APB_SARADC_SARADC2_PWDET_DRV_S 29
/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30
/** APB_SARADC_CTRL2_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4)
/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0
/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1
/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR1_INV_S 9
/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR2_INV_S 10
/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_S 12
/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define APB_SARADC_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U
#define APB_SARADC_SARADC_TIMER_EN_S 24
/** APB_SARADC_FILTER_CTRL1_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8)
/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26
/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29
/** APB_SARADC_SAR_PATT_TAB1_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18)
/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0
/** APB_SARADC_SAR_PATT_TAB2_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c)
/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0
/** APB_SARADC_ONETIME_SAMPLE_REG register
* digital saradc configure register
*/
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20)
/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23
/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25
/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
#define APB_SARADC_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U
#define APB_SARADC_SARADC_ONETIME_START_S 29
/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30
/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31
/** APB_SARADC_ARB_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24)
/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/** APB_SARADC_FILTER_CTRL0_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28)
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22
/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U
#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31
/** APB_SARADC_SAR1DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c)
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_S 0
/** APB_SARADC_SAR2DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30)
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_S 0
/** APB_SARADC_THRES0_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34)
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18
/** APB_SARADC_THRES1_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38)
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18
/** APB_SARADC_THRES_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c)
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27
/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_EN_S 30
/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_EN_S 31
/** APB_SARADC_INT_ENA_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40)
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31
/** APB_SARADC_INT_RAW_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44)
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31
/** APB_SARADC_INT_ST_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48)
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31
/** APB_SARADC_INT_CLR_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c)
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31
/** APB_SARADC_DMA_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50)
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U
#define APB_SARADC_APB_ADC_TRANS_S 31
/** APB_SARADC_CLKM_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54)
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_S 0
/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
#define APB_SARADC_CLKM_DIV_B 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_S 8
/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
#define APB_SARADC_CLKM_DIV_A 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_S 14
/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
#define APB_SARADC_CLK_EN_V 0x00000001U
#define APB_SARADC_CLK_EN_S 20
/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
#define APB_SARADC_CLK_SEL 0x00000003U
#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
#define APB_SARADC_CLK_SEL_V 0x00000003U
#define APB_SARADC_CLK_SEL_S 21
/** APB_SARADC_APB_TSENS_CTRL_REG register
* digital tsens configure register
*/
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58)
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
#define APB_SARADC_TSENS_OUT 0x000000FFU
#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
#define APB_SARADC_TSENS_OUT_V 0x000000FFU
#define APB_SARADC_TSENS_OUT_S 0
/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
#define APB_SARADC_TSENS_IN_INV_V 0x00000001U
#define APB_SARADC_TSENS_IN_INV_S 13
/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_S 14
/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
#define APB_SARADC_TSENS_PU_V 0x00000001U
#define APB_SARADC_TSENS_PU_S 22
/** APB_SARADC_TSENS_CTRL2_REG register
* digital tsens configure register
*/
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c)
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U
#define APB_SARADC_TSENS_CLK_SEL_S 15
/** APB_SARADC_CALI_REG register
* digital saradc configure register
*/
#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60)
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_S 0
/** APB_TSENS_WAKE_REG register
* digital tsens configure register
*/
#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64)
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_S 0
/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_S 8
/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16
/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
#define APB_SARADC_WAKEUP_MODE (BIT(17))
#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
#define APB_SARADC_WAKEUP_MODE_V 0x00000001U
#define APB_SARADC_WAKEUP_MODE_S 17
/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
#define APB_SARADC_WAKEUP_EN (BIT(18))
#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
#define APB_SARADC_WAKEUP_EN_V 0x00000001U
#define APB_SARADC_WAKEUP_EN_S 18
/** APB_TSENS_SAMPLE_REG register
* digital tsens configure register
*/
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68)
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_S 0
/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16))
#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U
#define APB_SARADC_TSENS_SAMPLE_EN_S 16
/** APB_SARADC_CTRL_DATE_REG register
* version
*/
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc)
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
#define APB_SARADC_DATE 0xFFFFFFFFU
#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
#define APB_SARADC_DATE_V 0xFFFFFFFFU
#define APB_SARADC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of saradc_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
uint32_t saradc_saradc_start_force:1;
/** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
uint32_t saradc_saradc_start:1;
uint32_t reserved_2:4;
/** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
uint32_t saradc_saradc_sar_clk_gated:1;
/** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
uint32_t saradc_saradc_sar_clk_div:8;
/** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t saradc_saradc_sar_patt_len:3;
uint32_t reserved_18:5;
/** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t saradc_saradc_sar_patt_p_clear:1;
uint32_t reserved_24:3;
/** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
uint32_t saradc_saradc_xpd_sar_force:2;
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
uint32_t saradc_saradc2_pwdet_drv:1;
/** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t saradc_saradc_wait_arb_cycle:2;
};
uint32_t val;
} apb_saradc_ctrl_reg_t;
/** Type of saradc_ctrl2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
uint32_t saradc_saradc_meas_num_limit:1;
/** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t saradc_saradc_max_meas_num:8;
/** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar1_inv:1;
/** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar2_inv:1;
uint32_t reserved_11:1;
/** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t saradc_saradc_timer_target:12;
/** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t saradc_saradc_timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} apb_saradc_ctrl2_reg_t;
/** Type of saradc_filter_ctrl1 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
uint32_t saradc_apb_saradc_filter_factor1:3;
/** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
uint32_t saradc_apb_saradc_filter_factor0:3;
};
uint32_t val;
} apb_saradc_filter_ctrl1_reg_t;
/** Type of saradc_sar_patt_tab1 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab1_reg_t;
/** Type of saradc_sar_patt_tab2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab2_reg_t;
/** Type of saradc_onetime_sample register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
uint32_t saradc_saradc_onetime_atten:2;
/** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
uint32_t saradc_saradc_onetime_channel:4;
/** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
uint32_t saradc_saradc_onetime_start:1;
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
uint32_t saradc_saradc2_onetime_sample:1;
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
uint32_t saradc_saradc1_onetime_sample:1;
};
uint32_t val;
} apb_saradc_onetime_sample_reg_t;
/** Type of saradc_arb_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t saradc_adc_arb_apb_force:1;
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t saradc_adc_arb_rtc_force:1;
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t saradc_adc_arb_wifi_force:1;
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t saradc_adc_arb_grant_force:1;
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t saradc_adc_arb_apb_priority:2;
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t saradc_adc_arb_rtc_priority:2;
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t saradc_adc_arb_wifi_priority:2;
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t saradc_adc_arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} apb_saradc_arb_ctrl_reg_t;
/** Type of saradc_filter_ctrl0 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:18;
/** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel1:4;
/** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel0:4;
uint32_t reserved_26:5;
/** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t saradc_apb_saradc_filter_reset:1;
};
uint32_t val;
} apb_saradc_filter_ctrl0_reg_t;
/** Type of saradc_sar1data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
uint32_t saradc_apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar1data_status_reg_t;
/** Type of saradc_sar2data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
uint32_t saradc_apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar2data_status_reg_t;
/** Type of saradc_thres0_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
uint32_t saradc_apb_saradc_thres0_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_high:13;
/** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres0_ctrl_reg_t;
/** Type of saradc_thres1_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
uint32_t saradc_apb_saradc_thres1_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_high:13;
/** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres1_ctrl_reg_t;
/** Type of saradc_thres_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
uint32_t saradc_apb_saradc_thres_all_en:1;
uint32_t reserved_28:2;
/** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
uint32_t saradc_apb_saradc_thres1_en:1;
/** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
uint32_t saradc_apb_saradc_thres0_en:1;
};
uint32_t val;
} apb_saradc_thres_ctrl_reg_t;
/** Type of saradc_int_ena register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
uint32_t saradc_apb_saradc_tsens_int_ena:1;
/** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
/** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
/** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
/** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
/** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
uint32_t saradc_apb_saradc2_done_int_ena:1;
/** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
uint32_t saradc_apb_saradc1_done_int_ena:1;
};
uint32_t val;
} apb_saradc_int_ena_reg_t;
/** Type of saradc_int_raw register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
uint32_t saradc_apb_saradc_tsens_int_raw:1;
/** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
/** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
/** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
/** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
/** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
uint32_t saradc_apb_saradc2_done_int_raw:1;
/** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
uint32_t saradc_apb_saradc1_done_int_raw:1;
};
uint32_t val;
} apb_saradc_int_raw_reg_t;
/** Type of saradc_int_st register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
uint32_t saradc_apb_saradc_tsens_int_st:1;
/** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
uint32_t saradc_apb_saradc_thres1_low_int_st:1;
/** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
uint32_t saradc_apb_saradc_thres0_low_int_st:1;
/** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
uint32_t saradc_apb_saradc_thres1_high_int_st:1;
/** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
uint32_t saradc_apb_saradc_thres0_high_int_st:1;
/** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
uint32_t saradc_apb_saradc2_done_int_st:1;
/** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
uint32_t saradc_apb_saradc1_done_int_st:1;
};
uint32_t val;
} apb_saradc_int_st_reg_t;
/** Type of saradc_int_clr register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
uint32_t saradc_apb_saradc_tsens_int_clr:1;
/** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
/** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
/** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
/** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
/** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
uint32_t saradc_apb_saradc2_done_int_clr:1;
/** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
uint32_t saradc_apb_saradc1_done_int_clr:1;
};
uint32_t val;
} apb_saradc_int_clr_reg_t;
/** Type of saradc_dma_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t saradc_apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t saradc_apb_adc_reset_fsm:1;
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t saradc_apb_adc_trans:1;
};
uint32_t val;
} apb_saradc_dma_conf_reg_t;
/** Type of saradc_clkm_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t saradc_clkm_div_b:6;
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t saradc_clkm_div_a:6;
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
uint32_t saradc_clk_en:1;
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
uint32_t saradc_clk_sel:2;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_clkm_conf_reg_t;
/** Type of saradc_apb_tsens_ctrl register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
uint32_t saradc_tsens_out:8;
uint32_t reserved_8:5;
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
uint32_t saradc_tsens_in_inv:1;
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
uint32_t saradc_tsens_clk_div:8;
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
uint32_t saradc_tsens_pu:1;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_apb_tsens_ctrl_reg_t;
/** Type of saradc_tsens_ctrl2 register
* digital tsens configure register
*/
typedef union {
struct {
uint32_t reserved_0:15;
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
uint32_t saradc_tsens_clk_sel:1;
uint32_t reserved_16:16;
};
uint32_t val;
} apb_saradc_tsens_ctrl2_reg_t;
/** Type of saradc_cali register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
uint32_t saradc_apb_saradc_cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_cali_reg_t;
/** Type of tsens_wake register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
uint32_t saradc_wakeup_th_low:8;
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
uint32_t saradc_wakeup_th_high:8;
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
uint32_t saradc_wakeup_over_upper_th:1;
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
uint32_t saradc_wakeup_mode:1;
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
uint32_t saradc_wakeup_en:1;
uint32_t reserved_19:13;
};
uint32_t val;
} apb_tsens_wake_reg_t;
/** Type of tsens_sample register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
uint32_t saradc_tsens_sample_rate:16;
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
uint32_t saradc_tsens_sample_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_tsens_sample_reg_t;
/** Type of saradc_ctrl_date register
* version
*/
typedef union {
struct {
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
uint32_t saradc_date:32;
};
uint32_t val;
} apb_saradc_ctrl_date_reg_t;
typedef struct {
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
uint32_t reserved_00c[3];
volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
volatile apb_saradc_int_ena_reg_t saradc_int_ena;
volatile apb_saradc_int_raw_reg_t saradc_int_raw;
volatile apb_saradc_int_st_reg_t saradc_int_st;
volatile apb_saradc_int_clr_reg_t saradc_int_clr;
volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
volatile apb_saradc_cali_reg_t saradc_cali;
volatile apb_tsens_wake_reg_t tsens_wake;
volatile apb_tsens_sample_reg_t tsens_sample;
uint32_t reserved_06c[228];
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
} apb_dev_t;
extern apb_dev_t APB_SARADC;
#ifndef __cplusplus
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/assist_debug_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
* core0 monitor interrupt enable register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clr register
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region0 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region0 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region1 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region1 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region0 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region0 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region1 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region1 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
* core0 area pc status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_BASE + 0x30)
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* the stackpointer when first touch region monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
* core0 area sp status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_BASE + 0x34)
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* the PC when first touch region monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* stack min value
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_BASE + 0x38)
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration register
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* stack max value
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_BASE + 0x3c)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* stack monitor pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_BASE + 0x40)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* This register stores the PC when trigger stack monitor.
*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* record enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_BASE + 0x44)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* record status register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_BASE + 0x48)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* record status register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_BASE + 0x4c)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_BASE + 0x50)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_BASE + 0x54)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register2
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_BASE + 0x58)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register3
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_BASE + 0x5c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
* exception monitor status register4
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_BASE + 0x60)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
* exception monitor status register5
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_BASE + 0x64)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register6
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_BASE + 0x68)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register7
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_BASE + 0x6c)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_BASE + 0x70)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_BASE + 0x74)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* cpu debug_module active status
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** ASSIST_DEBUG_CLOCK_GATE_REG register
* clock register
*/
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_BASE + 0x78)
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 force on the clock gate
*/
#define ASSIST_DEBUG_CLK_EN (BIT(0))
#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
#define ASSIST_DEBUG_CLK_EN_S 0
/** ASSIST_DEBUG_DATE_REG register
* version register
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_BASE + 0x3fc)
/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 35660096;
* version register
*/
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE 0x0FFFFFFFU
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/assist_debug_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: monitor configuration registers */
/** Type of debug_core_0_intr_ena register
* core0 monitor enable configuration register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor enable
*/
uint32_t debug_core_0_area_dram0_0_rd_ena:1;
/** debug_core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor enable
*/
uint32_t debug_core_0_area_dram0_0_wr_ena:1;
/** debug_core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor enable
*/
uint32_t debug_core_0_area_dram0_1_rd_ena:1;
/** debug_core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor enable
*/
uint32_t debug_core_0_area_dram0_1_wr_ena:1;
/** debug_core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor enable
*/
uint32_t debug_core_0_area_pif_0_rd_ena:1;
/** debug_core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor enable
*/
uint32_t debug_core_0_area_pif_0_wr_ena:1;
/** debug_core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor enable
*/
uint32_t debug_core_0_area_pif_1_rd_ena:1;
/** debug_core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor enable
*/
uint32_t debug_core_0_area_pif_1_wr_ena:1;
/** debug_core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor enable
*/
uint32_t debug_core_0_sp_spill_min_ena:1;
/** debug_core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor enable
*/
uint32_t debug_core_0_sp_spill_max_ena:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_ena_reg_t;
/** Type of debug_core_0_area_dram0_0_min register
* core0 dram0 region0 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region0 start addr
*/
uint32_t debug_core_0_area_dram0_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_min_reg_t;
/** Type of debug_core_0_area_dram0_0_max register
* core0 dram0 region0 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region0 end addr
*/
uint32_t debug_core_0_area_dram0_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_max_reg_t;
/** Type of debug_core_0_area_dram0_1_min register
* core0 dram0 region1 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region1 start addr
*/
uint32_t debug_core_0_area_dram0_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_min_reg_t;
/** Type of debug_core_0_area_dram0_1_max register
* core0 dram0 region1 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region1 end addr
*/
uint32_t debug_core_0_area_dram0_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_max_reg_t;
/** Type of debug_core_0_area_pif_0_min register
* core0 PIF region0 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region0 start addr
*/
uint32_t debug_core_0_area_pif_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_min_reg_t;
/** Type of debug_core_0_area_pif_0_max register
* core0 PIF region0 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region0 end addr
*/
uint32_t debug_core_0_area_pif_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_max_reg_t;
/** Type of debug_core_0_area_pif_1_min register
* core0 PIF region1 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region1 start addr
*/
uint32_t debug_core_0_area_pif_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_min_reg_t;
/** Type of debug_core_0_area_pif_1_max register
* core0 PIF region1 addr configuration register
*/
typedef union {
struct {
/** debug_core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region1 end addr
*/
uint32_t debug_core_0_area_pif_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_max_reg_t;
/** Type of debug_core_0_area_pc register
* core0 area pc status register
*/
typedef union {
struct {
/** debug_core_0_area_pc : RO; bitpos: [31:0]; default: 0;
* the stackpointer when first touch region monitor interrupt
*/
uint32_t debug_core_0_area_pc:32;
};
uint32_t val;
} assist_debug_core_0_area_pc_reg_t;
/** Type of debug_core_0_area_sp register
* core0 area sp status register
*/
typedef union {
struct {
/** debug_core_0_area_sp : RO; bitpos: [31:0]; default: 0;
* the PC when first touch region monitor interrupt
*/
uint32_t debug_core_0_area_sp:32;
};
uint32_t val;
} assist_debug_core_0_area_sp_reg_t;
/** Type of debug_core_0_sp_min register
* stack min value
*/
typedef union {
struct {
/** debug_core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration register
*/
uint32_t debug_core_0_sp_min:32;
};
uint32_t val;
} assist_debug_core_0_sp_min_reg_t;
/** Type of debug_core_0_sp_max register
* stack max value
*/
typedef union {
struct {
/** debug_core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
uint32_t debug_core_0_sp_max:32;
};
uint32_t val;
} assist_debug_core_0_sp_max_reg_t;
/** Type of debug_core_0_sp_pc register
* stack monitor pc status register
*/
typedef union {
struct {
/** debug_core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
* This register stores the PC when trigger stack monitor.
*/
uint32_t debug_core_0_sp_pc:32;
};
uint32_t val;
} assist_debug_core_0_sp_pc_reg_t;
/** Group: interrupt configuration register */
/** Type of debug_core_0_intr_raw register
* core0 monitor interrupt status register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt status
*/
uint32_t debug_core_0_area_dram0_0_rd_raw:1;
/** debug_core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt status
*/
uint32_t debug_core_0_area_dram0_0_wr_raw:1;
/** debug_core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt status
*/
uint32_t debug_core_0_area_dram0_1_rd_raw:1;
/** debug_core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt status
*/
uint32_t debug_core_0_area_dram0_1_wr_raw:1;
/** debug_core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt status
*/
uint32_t debug_core_0_area_pif_0_rd_raw:1;
/** debug_core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt status
*/
uint32_t debug_core_0_area_pif_0_wr_raw:1;
/** debug_core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt status
*/
uint32_t debug_core_0_area_pif_1_rd_raw:1;
/** debug_core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt status
*/
uint32_t debug_core_0_area_pif_1_wr_raw:1;
/** debug_core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt status
*/
uint32_t debug_core_0_sp_spill_min_raw:1;
/** debug_core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt status
*/
uint32_t debug_core_0_sp_spill_max_raw:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_raw_reg_t;
/** Type of debug_core_0_intr_rls register
* core0 monitor interrupt enable register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
uint32_t debug_core_0_area_dram0_0_rd_rls:1;
/** debug_core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
uint32_t debug_core_0_area_dram0_0_wr_rls:1;
/** debug_core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
uint32_t debug_core_0_area_dram0_1_rd_rls:1;
/** debug_core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
uint32_t debug_core_0_area_dram0_1_wr_rls:1;
/** debug_core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
uint32_t debug_core_0_area_pif_0_rd_rls:1;
/** debug_core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
uint32_t debug_core_0_area_pif_0_wr_rls:1;
/** debug_core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
uint32_t debug_core_0_area_pif_1_rd_rls:1;
/** debug_core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
uint32_t debug_core_0_area_pif_1_wr_rls:1;
/** debug_core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
uint32_t debug_core_0_sp_spill_min_rls:1;
/** debug_core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
uint32_t debug_core_0_sp_spill_max_rls:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_rls_reg_t;
/** Type of debug_core_0_intr_clr register
* core0 monitor interrupt clr register
*/
typedef union {
struct {
/** debug_core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt clr
*/
uint32_t debug_core_0_area_dram0_0_rd_clr:1;
/** debug_core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt clr
*/
uint32_t debug_core_0_area_dram0_0_wr_clr:1;
/** debug_core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt clr
*/
uint32_t debug_core_0_area_dram0_1_rd_clr:1;
/** debug_core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt clr
*/
uint32_t debug_core_0_area_dram0_1_wr_clr:1;
/** debug_core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt clr
*/
uint32_t debug_core_0_area_pif_0_rd_clr:1;
/** debug_core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt clr
*/
uint32_t debug_core_0_area_pif_0_wr_clr:1;
/** debug_core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt clr
*/
uint32_t debug_core_0_area_pif_1_rd_clr:1;
/** debug_core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt clr
*/
uint32_t debug_core_0_area_pif_1_wr_clr:1;
/** debug_core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt clr
*/
uint32_t debug_core_0_sp_spill_min_clr:1;
/** debug_core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt clr
*/
uint32_t debug_core_0_sp_spill_max_clr:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_clr_reg_t;
/** Group: pc recording configuration register */
/** Type of debug_core_0_rcd_en register
* record enable configuration register
*/
typedef union {
struct {
/** debug_core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
uint32_t debug_core_0_rcd_recorden:1;
/** debug_core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
*/
uint32_t debug_core_0_rcd_pdebugen:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_rcd_en_reg_t;
/** Group: pc recording status register */
/** Type of debug_core_0_rcd_pdebugpc register
* record status register
*/
typedef union {
struct {
/** debug_core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
uint32_t debug_core_0_rcd_pdebugpc:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugpc_reg_t;
/** Type of debug_core_0_rcd_pdebugsp register
* record status register
*/
typedef union {
struct {
/** debug_core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
uint32_t debug_core_0_rcd_pdebugsp:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugsp_reg_t;
/** Group: exception monitor register */
/** Type of debug_core_0_iram0_exception_monitor_0 register
* exception monitor status register0
*/
typedef union {
struct {
/** debug_core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
uint32_t debug_core_0_iram0_recording_addr_0:24;
/** debug_core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
uint32_t debug_core_0_iram0_recording_wr_0:1;
/** debug_core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
uint32_t debug_core_0_iram0_recording_loadstore_0:1;
uint32_t reserved_26:6;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
/** Type of debug_core_0_iram0_exception_monitor_1 register
* exception monitor status register1
*/
typedef union {
struct {
/** debug_core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
uint32_t debug_core_0_iram0_recording_addr_1:24;
/** debug_core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
uint32_t debug_core_0_iram0_recording_wr_1:1;
/** debug_core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
uint32_t debug_core_0_iram0_recording_loadstore_1:1;
uint32_t reserved_26:6;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
/** Type of debug_core_0_dram0_exception_monitor_0 register
* exception monitor status register2
*/
typedef union {
struct {
/** debug_core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
uint32_t debug_core_0_dram0_recording_addr_0:24;
/** debug_core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
uint32_t debug_core_0_dram0_recording_wr_0:1;
/** debug_core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
uint32_t debug_core_0_dram0_recording_byteen_0:4;
uint32_t reserved_29:3;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
/** Type of debug_core_0_dram0_exception_monitor_1 register
* exception monitor status register3
*/
typedef union {
struct {
/** debug_core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
uint32_t debug_core_0_dram0_recording_pc_0:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
/** Type of debug_core_0_dram0_exception_monitor_2 register
* exception monitor status register4
*/
typedef union {
struct {
/** debug_core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
uint32_t debug_core_0_dram0_recording_addr_1:24;
/** debug_core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
uint32_t debug_core_0_dram0_recording_wr_1:1;
/** debug_core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
uint32_t debug_core_0_dram0_recording_byteen_1:4;
uint32_t reserved_29:3;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
/** Type of debug_core_0_dram0_exception_monitor_3 register
* exception monitor status register5
*/
typedef union {
struct {
/** debug_core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
uint32_t debug_core_0_dram0_recording_pc_1:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
/** Type of debug_core_x_iram0_dram0_exception_monitor_0 register
* exception monitor status register6
*/
typedef union {
struct {
/** debug_core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
uint32_t debug_core_x_iram0_dram0_limit_cycle_0:20;
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
/** Type of debug_core_x_iram0_dram0_exception_monitor_1 register
* exception monitor status register7
*/
typedef union {
struct {
/** debug_core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
uint32_t debug_core_x_iram0_dram0_limit_cycle_1:20;
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
/** Group: cpu status registers */
/** Type of debug_core_0_lastpc_before_exception register
* cpu status register
*/
typedef union {
struct {
/** debug_core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
uint32_t debug_core_0_lastpc_before_exc:32;
};
uint32_t val;
} assist_debug_core_0_lastpc_before_exception_reg_t;
/** Type of debug_core_0_debug_mode register
* cpu status register
*/
typedef union {
struct {
/** debug_core_0_debug_mode : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
uint32_t debug_core_0_debug_mode:1;
/** debug_core_0_debug_module_active : RO; bitpos: [1]; default: 0;
* cpu debug_module active status
*/
uint32_t debug_core_0_debug_module_active:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_debug_mode_reg_t;
/** Group: Configuration Registers */
/** Type of debug_clock_gate register
* clock register
*/
typedef union {
struct {
/** debug_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 force on the clock gate
*/
uint32_t debug_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} assist_debug_clock_gate_reg_t;
/** Type of debug_date register
* version register
*/
typedef union {
struct {
/** debug_assist_debug_date : R/W; bitpos: [27:0]; default: 35660096;
* version register
*/
uint32_t debug_assist_debug_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} assist_debug_date_reg_t;
typedef struct {
volatile assist_debug_core_0_intr_ena_reg_t debug_core_0_intr_ena;
volatile assist_debug_core_0_intr_raw_reg_t debug_core_0_intr_raw;
volatile assist_debug_core_0_intr_rls_reg_t debug_core_0_intr_rls;
volatile assist_debug_core_0_intr_clr_reg_t debug_core_0_intr_clr;
volatile assist_debug_core_0_area_dram0_0_min_reg_t debug_core_0_area_dram0_0_min;
volatile assist_debug_core_0_area_dram0_0_max_reg_t debug_core_0_area_dram0_0_max;
volatile assist_debug_core_0_area_dram0_1_min_reg_t debug_core_0_area_dram0_1_min;
volatile assist_debug_core_0_area_dram0_1_max_reg_t debug_core_0_area_dram0_1_max;
volatile assist_debug_core_0_area_pif_0_min_reg_t debug_core_0_area_pif_0_min;
volatile assist_debug_core_0_area_pif_0_max_reg_t debug_core_0_area_pif_0_max;
volatile assist_debug_core_0_area_pif_1_min_reg_t debug_core_0_area_pif_1_min;
volatile assist_debug_core_0_area_pif_1_max_reg_t debug_core_0_area_pif_1_max;
volatile assist_debug_core_0_area_pc_reg_t debug_core_0_area_pc;
volatile assist_debug_core_0_area_sp_reg_t debug_core_0_area_sp;
volatile assist_debug_core_0_sp_min_reg_t debug_core_0_sp_min;
volatile assist_debug_core_0_sp_max_reg_t debug_core_0_sp_max;
volatile assist_debug_core_0_sp_pc_reg_t debug_core_0_sp_pc;
volatile assist_debug_core_0_rcd_en_reg_t debug_core_0_rcd_en;
volatile assist_debug_core_0_rcd_pdebugpc_reg_t debug_core_0_rcd_pdebugpc;
volatile assist_debug_core_0_rcd_pdebugsp_reg_t debug_core_0_rcd_pdebugsp;
volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t debug_core_0_iram0_exception_monitor_0;
volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t debug_core_0_iram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t debug_core_0_dram0_exception_monitor_0;
volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t debug_core_0_dram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t debug_core_0_dram0_exception_monitor_2;
volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t debug_core_0_dram0_exception_monitor_3;
volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t debug_core_x_iram0_dram0_exception_monitor_0;
volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t debug_core_x_iram0_dram0_exception_monitor_1;
volatile assist_debug_core_0_lastpc_before_exception_reg_t debug_core_0_lastpc_before_exception;
volatile assist_debug_core_0_debug_mode_reg_t debug_core_0_debug_mode;
volatile assist_debug_clock_gate_reg_t debug_clock_gate;
uint32_t reserved_07c[224];
volatile assist_debug_date_reg_t debug_date;
} assist_debug_dev_t;
extern assist_debug_dev_t ASSIST_DEBUG;
#ifndef __cplusplus
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* DS start control register
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* DS finish control register
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* DS query busy register
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* DS query key-wrong counter register
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* DS query check result register
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* DS start control register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* DS finish control register
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* DS query busy register
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* DS query key-wrong counter register
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* DS query check result register
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
uint32_t reserved_e18[2];
volatile ds_date_reg_t date;
} ds_dev_t;
extern ds_dev_t DS;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC raw interrupt status register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC masked interrupt status register
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configuration register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
#define ECC_MULT_MOD_BASE (BIT(3))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 3
/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 4
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
#define ECC_MULT_SECURITY_MODE (BIT(8))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 8
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37752928;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 32
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_BASE + 0x120)
#define ECC_MULT_PX_MEM_SIZE_BYTES 32
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_BASE + 0x140)
#define ECC_MULT_PY_MEM_SIZE_BYTES 32
/** ECC_MULT_QX_MEM register
* The memory that stores Qx.
*/
#define ECC_MULT_QX_MEM (DR_REG_ECC_BASE + 0x160)
#define ECC_MULT_QX_MEM_SIZE_BYTES 32
/** ECC_MULT_QY_MEM register
* The memory that stores Qy.
*/
#define ECC_MULT_QY_MEM (DR_REG_ECC_BASE + 0x180)
#define ECC_MULT_QY_MEM_SIZE_BYTES 32
/** ECC_MULT_QZ_MEM register
* The memory that stores Qz.
*/
#define ECC_MULT_QZ_MEM (DR_REG_ECC_BASE + 0x1a0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of mult_int_raw register
* ECC raw interrupt status register
*/
typedef union {
struct {
/** mult_calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of mult_int_st register
* ECC masked interrupt status register
*/
typedef union {
struct {
/** mult_calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of mult_int_ena register
* ECC interrupt enable register
*/
typedef union {
struct {
/** mult_calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of mult_int_clr register
* ECC interrupt clear register
*/
typedef union {
struct {
/** mult_calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of mult_conf register
* ECC configuration register
*/
typedef union {
struct {
/** mult_start : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
uint32_t mult_start:1;
/** mult_reset : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
uint32_t mult_reset:1;
/** mult_key_length : R/W; bitpos: [2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
*/
uint32_t mult_key_length:1;
/** mult_mod_base : R/W; bitpos: [3]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
uint32_t mult_mod_base:1;
/** mult_work_mode : R/W; bitpos: [7:4]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
uint32_t mult_work_mode:4;
/** mult_security_mode : R/W; bitpos: [8]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
uint32_t mult_security_mode:1;
uint32_t reserved_9:20;
/** mult_verification_result : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
uint32_t mult_verification_result:1;
/** mult_clk_en : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t mult_clk_en:1;
/** mult_mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t mult_mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of mult_date register
* Version control register
*/
typedef union {
struct {
/** mult_date : R/W; bitpos: [27:0]; default: 37752928;
* ECC mult version control register
*/
uint32_t mult_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t mult_int_raw;
volatile ecc_mult_int_st_reg_t mult_int_st;
volatile ecc_mult_int_ena_reg_t mult_int_ena;
volatile ecc_mult_int_clr_reg_t mult_int_clr;
volatile ecc_mult_conf_reg_t mult_conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t mult_date;
volatile uint32_t mult_k[8];
volatile uint32_t mult_px[8];
volatile uint32_t mult_py[8];
volatile uint32_t mult_qx[8];
volatile uint32_t mult_qy[8];
volatile uint32_t mult_qz[8];
} ecc_mult_dev_t;
extern ecc_mult_dev_t ECC;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x1c0, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
#define ECDSA_ECC_CURVE (BIT(2))
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000001U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(3))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 3
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(4))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 4
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(5))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 5
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PREP_DONE_INT_RAW_S 0
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PROC_DONE_INT_RAW_S 1
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
#define ECDSA_POST_DONE_INT_RAW_S 2
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 3
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ST_S 0
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ST_S 1
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ST (BIT(2))
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
#define ECDSA_POST_DONE_INT_ST_S 2
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 3
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ENA_S 0
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ENA_S 1
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
#define ECDSA_POST_DONE_INT_ENA_S 2
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 3
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PREP_DONE_INT_CLR_S 0
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PROC_DONE_INT_CLR_S 1
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
#define ECDSA_POST_DONE_INT_CLR_S 2
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 3
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37761312;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
#define ECDSA_SHA_MODE 0x00000007U
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x00000007U
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x340)
#define ECDSA_R_MEM_SIZE_BYTES 32
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x360)
#define ECDSA_S_MEM_SIZE_BYTES 32
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x380)
#define ECDSA_Z_MEM_SIZE_BYTES 32
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x3a0)
#define ECDSA_QAX_MEM_SIZE_BYTES 32
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x3c0)
#define ECDSA_QAY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
uint32_t ecc_curve:1;
/** software_set_k : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
uint32_t reserved_6:26;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
uint32_t sha_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37761312;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
uint32_t reserved_028[53];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[8];
uint32_t reserved_2a0[40];
volatile uint32_t r[8];
volatile uint32_t s[8];
volatile uint32_t z[8];
volatile uint32_t qax[8];
volatile uint32_t qay[8];
} ecdsa_dev_t;
extern ecdsa_dev_t ECDSA;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of ext_sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
/** ext_sigmadelta_clk_en : R/W; bitpos: [0]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t ext_sigmadelta_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_ext_sigmadelta_misc_reg_t;
/** Type of ext_sigmadeltan register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** ext_sdn_in : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t ext_sdn_in:8;
/** ext_sdn_prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t ext_sdn_prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_ext_sigmadeltan_reg_t;
/** Group: Configure Registers */
/** Type of ext_pad_comp_config_0 register
* PAD Compare configure Register
*/
typedef union {
struct {
/** ext_xpd_comp_0 : R/W; bitpos: [0]; default: 0;
* Pad compare enable bit.
*/
uint32_t ext_xpd_comp_0:1;
/** ext_mode_comp_0 : R/W; bitpos: [1]; default: 0;
* 1 to enable external reference from PAD[x]. 0 to enable internal reference,
* meanwhile PAD[x] can be used as a regular GPIO.
*/
uint32_t ext_mode_comp_0:1;
/** ext_dref_comp_0 : R/W; bitpos: [4:2]; default: 0;
* internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
*/
uint32_t ext_dref_comp_0:3;
uint32_t reserved_5:27;
};
uint32_t val;
} gpio_ext_pad_comp_config_0_reg_t;
/** Type of ext_pad_comp_filter_0 register
* Zero Detect filter Register
*/
typedef union {
struct {
/** ext_zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0;
* Zero Detect filter cycle length
*/
uint32_t ext_zero_det_filter_cnt_0:32;
};
uint32_t val;
} gpio_ext_pad_comp_filter_0_reg_t;
/** Type of ext_pin_ctrl register
* Clock Output Configuration Register
*/
typedef union {
struct {
/** ext_clk_out1 : R/W; bitpos: [4:0]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
* CLK_OUT_out1 can be found in peripheral output signals.
*/
uint32_t ext_clk_out1:5;
/** ext_clk_out2 : R/W; bitpos: [9:5]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
* CLK_OUT_out2 can be found in peripheral output signals.
*/
uint32_t ext_clk_out2:5;
/** ext_clk_out3 : R/W; bitpos: [14:10]; default: 7;
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
* CLK_OUT_out3 can be found in peripheral output signals.
*/
uint32_t ext_clk_out3:5;
uint32_t reserved_15:17;
};
uint32_t val;
} gpio_ext_pin_ctrl_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of ext_glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** ext_filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t ext_filter_ch0_en:1;
/** ext_filter_ch0_input_io_num : R/W; bitpos: [5:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t ext_filter_ch0_input_io_num:5;
uint32_t reserved_6:2;
/** ext_filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t ext_filter_ch0_window_thres:6;
/** ext_filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0;
* Glitch Filter window width.
*/
uint32_t ext_filter_ch0_window_width:6;
uint32_t reserved_20:12;
};
uint32_t val;
} gpio_ext_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of ext_etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** ext_etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t ext_etm_ch0_event_sel:5;
uint32_t reserved_5:2;
/** ext_etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t ext_etm_ch0_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_ext_etm_event_chn_cfg_reg_t;
/** Type of ext_etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** ext_etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio0_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio0_en : R/W; bitpos: [5]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio0_en:1;
/** ext_etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio1_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio1_en : R/W; bitpos: [11]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio1_en:1;
/** ext_etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio2_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio2_en : R/W; bitpos: [17]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio2_en:1;
/** ext_etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio3_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio3_en : R/W; bitpos: [23]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio3_en:1;
/** ext_etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio4_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio4_en : R/W; bitpos: [29]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio4_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p0_cfg_reg_t;
/** Type of ext_etm_task_p1_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** ext_etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio5_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio5_en:1;
/** ext_etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio6_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio6_en:1;
/** ext_etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio7_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio7_en:1;
/** ext_etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio8_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio8_en:1;
/** ext_etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio9_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio9_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p1_cfg_reg_t;
/** Type of ext_etm_task_p2_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** ext_etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio10_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio10_en:1;
/** ext_etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio11_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio11_en:1;
/** ext_etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio12_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio12_en:1;
/** ext_etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio13_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio13_en:1;
/** ext_etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio14_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio14_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p2_cfg_reg_t;
/** Type of ext_etm_task_p3_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** ext_etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio15_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio15_en:1;
/** ext_etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio16_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio16_en:1;
/** ext_etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio17_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio17_en:1;
/** ext_etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio18_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio18_en:1;
/** ext_etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio19_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio19_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p3_cfg_reg_t;
/** Type of ext_etm_task_p4_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** ext_etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio20_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio20_en:1;
/** ext_etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio21_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio21_en:1;
/** ext_etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio22_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio22_en:1;
/** ext_etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio23_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio23_en:1;
/** ext_etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio24_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio24_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p4_cfg_reg_t;
/** Type of ext_etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** ext_etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t ext_etm_task_gpio25_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t ext_etm_task_gpio25_en:1;
uint32_t reserved_6:26;
};
uint32_t val;
} gpio_ext_etm_task_p5_cfg_reg_t;
/** Group: Interrupt Registers */
/** Type of ext_int_raw register
* GPIO_EXT interrupt raw register
*/
typedef union {
struct {
/** ext_comp_neg_0_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt raw
*/
uint32_t ext_comp_neg_0_int_raw:1;
/** ext_comp_pos_0_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt raw
*/
uint32_t ext_comp_pos_0_int_raw:1;
/** ext_comp_all_0_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt raw
*/
uint32_t ext_comp_all_0_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_raw_reg_t;
/** Type of ext_int_st register
* GPIO_EXT interrupt masked register
*/
typedef union {
struct {
/** ext_comp_neg_0_int_st : RO; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt status
*/
uint32_t ext_comp_neg_0_int_st:1;
/** ext_comp_pos_0_int_st : RO; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt status
*/
uint32_t ext_comp_pos_0_int_st:1;
/** ext_comp_all_0_int_st : RO; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt status
*/
uint32_t ext_comp_all_0_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_st_reg_t;
/** Type of ext_int_ena register
* GPIO_EXT interrupt enable register
*/
typedef union {
struct {
/** ext_comp_neg_0_int_ena : R/W; bitpos: [0]; default: 1;
* analog comparator pos edge interrupt enable
*/
uint32_t ext_comp_neg_0_int_ena:1;
/** ext_comp_pos_0_int_ena : R/W; bitpos: [1]; default: 1;
* analog comparator neg edge interrupt enable
*/
uint32_t ext_comp_pos_0_int_ena:1;
/** ext_comp_all_0_int_ena : R/W; bitpos: [2]; default: 1;
* analog comparator neg or pos edge interrupt enable
*/
uint32_t ext_comp_all_0_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_ena_reg_t;
/** Type of ext_int_clr register
* GPIO_EXT interrupt clear register
*/
typedef union {
struct {
/** ext_comp_neg_0_int_clr : WT; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt clear
*/
uint32_t ext_comp_neg_0_int_clr:1;
/** ext_comp_pos_0_int_clr : WT; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt clear
*/
uint32_t ext_comp_pos_0_int_clr:1;
/** ext_comp_all_0_int_clr : WT; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt clear
*/
uint32_t ext_comp_all_0_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_clr_reg_t;
/** Group: Version Register */
/** Type of ext_version register
* Version Control Register
*/
typedef union {
struct {
/** ext_date : R/W; bitpos: [27:0]; default: 37781840;
* Version control register.
*/
uint32_t ext_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct {
uint32_t reserved_000;
volatile gpio_ext_sigmadelta_misc_reg_t ext_sigmadelta_misc;
volatile gpio_ext_sigmadeltan_reg_t ext_sigmadeltan[4];
uint32_t reserved_018[16];
volatile gpio_ext_pad_comp_config_0_reg_t ext_pad_comp_config_0;
volatile gpio_ext_pad_comp_filter_0_reg_t ext_pad_comp_filter_0;
uint32_t reserved_060[30];
volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8];
uint32_t reserved_0f8[8];
volatile gpio_ext_etm_event_chn_cfg_reg_t ext_etm_event_chn_cfg[8];
uint32_t reserved_138[8];
volatile gpio_ext_etm_task_p0_cfg_reg_t ext_etm_task_p0_cfg;
volatile gpio_ext_etm_task_p1_cfg_reg_t ext_etm_task_p1_cfg;
volatile gpio_ext_etm_task_p2_cfg_reg_t ext_etm_task_p2_cfg;
volatile gpio_ext_etm_task_p3_cfg_reg_t ext_etm_task_p3_cfg;
volatile gpio_ext_etm_task_p4_cfg_reg_t ext_etm_task_p4_cfg;
volatile gpio_ext_etm_task_p5_cfg_reg_t ext_etm_task_p5_cfg;
uint32_t reserved_170[24];
volatile gpio_ext_int_raw_reg_t ext_int_raw;
volatile gpio_ext_int_st_reg_t ext_int_st;
volatile gpio_ext_int_ena_reg_t ext_int_ena;
volatile gpio_ext_int_clr_reg_t ext_int_clr;
volatile gpio_ext_pin_ctrl_reg_t ext_pin_ctrl;
uint32_t reserved_1e4[6];
volatile gpio_ext_version_reg_t ext_version;
} gpio_ext_dev_t;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* Process control register 0.
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* Configure purpose.
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* Configure key.
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* Finish initial configuration.
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* Process control register 1.
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* Process control register 2.
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* Process control register 3.
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* Process control register 4.
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate register 0.
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate register 1.
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Error register.
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy register.
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Process control register 5.
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* Process control register 6.
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Jtag register 1.
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Date register.
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
* Process control register 0.
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_purpose register
* Configure purpose.
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* Configure key.
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of set_para_finish register
* Finish initial configuration.
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* Process control register 1.
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* Process control register 2.
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* Process control register 3.
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* Process control register 4.
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate register 0.
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate register 1.
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of set_message_pad register
* Process control register 5.
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* Process control register 6.
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Type of wr_jtag register
* Jtag register 1.
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Status Register */
/** Type of query_error register
* Error register.
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Group: Memory Type */
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
extern hmac_dev_t HMAC;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M ( HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : HRO; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M ( HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M ( HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M ( HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
* HP memory usage configuration register
*/
#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [14:10]; default: 0;
* 0: cpu use hp-memory. 1: mac-dump accessing hp-memory.
*/
#define HP_SYSTEM_SRAM_USAGE 0x0000001FU
#define HP_SYSTEM_SRAM_USAGE_M ( HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
#define HP_SYSTEM_SRAM_USAGE_V 0x0000001FU
#define HP_SYSTEM_SRAM_USAGE_S 10
/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [24:20]; default: 0;
* reserved.
*/
#define HP_SYSTEM_MAC_DUMP_ALLOC 0x0000001FU
#define HP_SYSTEM_MAC_DUMP_ALLOC_M ( HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
#define HP_SYSTEM_MAC_DUMP_ALLOC_V 0x0000001FU
#define HP_SYSTEM_MAC_DUMP_ALLOC_S 20
/** HP_SYSTEM_SEC_DPA_CONF_REG register
* HP anti-DPA security configuration register
*/
#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
*/
#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_M ( HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
#define HP_SYSTEM_SEC_DPA_LEVEL_V 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_S 0
/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
*/
#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2))
#define HP_SYSTEM_SEC_DPA_CFG_SEL_M ( HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
#define HP_SYSTEM_SEC_DPA_CFG_SEL_V 0x00000001U
#define HP_SYSTEM_SEC_DPA_CFG_SEL_S 2
/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
* CPU_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M ( HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M ( HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M ( HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
* CPU_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M ( HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
* CPU_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M ( HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
* HP_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M ( HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M ( HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M ( HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
* HP_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M ( HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
* HP_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M ( HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
* Rom-Table lock register
*/
#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* XXXX
*/
#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0))
#define HP_SYSTEM_ROM_TABLE_LOCK_M ( HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U
#define HP_SYSTEM_ROM_TABLE_LOCK_S 0
/** HP_SYSTEM_ROM_TABLE_REG register
* Rom-Table register
*/
#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_M ( HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_S 0
/** HP_SYSTEM_RNG_LOOP_REG register
* configure rng_ring
*/
#define HP_SYSTEM_RNG_LOOP_REG (DR_REG_HP_SYSTEM_BASE + 0x30)
/** HP_SYSTEM_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
* This field get rng ring count
*/
#define HP_SYSTEM_SAMPLE_CNT 0x000000FFU
#define HP_SYSTEM_SAMPLE_CNT_M ( HP_SYSTEM_SAMPLE_CNT_V << HP_SYSTEM_SAMPLE_CNT_S)
#define HP_SYSTEM_SAMPLE_CNT_V 0x000000FFU
#define HP_SYSTEM_SAMPLE_CNT_S 24
/** HP_SYSTEM_DATE_REG register
* Date register.
*/
#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37782128;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
#define HP_SYSTEM_DATE 0x0FFFFFFFU
#define HP_SYSTEM_DATE_M ( HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
#define HP_SYSTEM_DATE_V 0x0FFFFFFFU
#define HP_SYSTEM_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of sys_external_device_encrypt_decrypt_control register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
typedef union {
struct {
/** sys_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
uint32_t sys_enable_spi_manual_encrypt:1;
/** sys_enable_download_db_encrypt : HRO; bitpos: [1]; default: 0;
* reserved
*/
uint32_t sys_enable_download_db_encrypt:1;
/** sys_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
uint32_t sys_enable_download_g0cb_decrypt:1;
/** sys_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
uint32_t sys_enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_sys_external_device_encrypt_decrypt_control_reg_t;
/** Type of sys_sram_usage_conf register
* HP memory usage configuration register
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** sys_sram_usage : R/W; bitpos: [14:10]; default: 0;
* 0: cpu use hp-memory. 1: mac-dump accessing hp-memory.
*/
uint32_t sys_sram_usage:5;
uint32_t reserved_15:5;
/** sys_mac_dump_alloc : R/W; bitpos: [24:20]; default: 0;
* reserved.
*/
uint32_t sys_mac_dump_alloc:5;
uint32_t reserved_25:7;
};
uint32_t val;
} hp_sys_sram_usage_conf_reg_t;
/** Type of sys_sec_dpa_conf register
* HP anti-DPA security configuration register
*/
typedef union {
struct {
/** sys_sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
*/
uint32_t sys_sec_dpa_level:2;
/** sys_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
*/
uint32_t sys_sec_dpa_cfg_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_sys_sec_dpa_conf_reg_t;
/** Type of sys_rom_table_lock register
* Rom-Table lock register
*/
typedef union {
struct {
/** sys_rom_table_lock : R/W; bitpos: [0]; default: 0;
* XXXX
*/
uint32_t sys_rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_sys_rom_table_lock_reg_t;
/** Type of sys_rom_table register
* Rom-Table register
*/
typedef union {
struct {
/** sys_rom_table : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
uint32_t sys_rom_table:32;
};
uint32_t val;
} hp_sys_rom_table_reg_t;
/** Type of sys_rng_loop register
* configure rng_ring
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** sys_sample_cnt : RO; bitpos: [31:24]; default: 0;
* This field get rng ring count
*/
uint32_t sys_sample_cnt:8;
};
uint32_t val;
} hp_sys_rng_loop_reg_t;
/** Group: Timeout Register */
/** Type of sys_cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** sys_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t sys_cpu_peri_timeout_thres:16;
/** sys_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t sys_cpu_peri_timeout_int_clear:1;
/** sys_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
uint32_t sys_cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_conf_reg_t;
/** Type of sys_cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** sys_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t sys_cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_addr_reg_t;
/** Type of sys_cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** sys_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t sys_cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_uid_reg_t;
/** Type of sys_hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** sys_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t sys_hp_peri_timeout_thres:16;
/** sys_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t sys_hp_peri_timeout_int_clear:1;
/** sys_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
uint32_t sys_hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_hp_peri_timeout_conf_reg_t;
/** Type of sys_hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** sys_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t sys_hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_hp_peri_timeout_addr_reg_t;
/** Type of sys_hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** sys_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t sys_hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_hp_peri_timeout_uid_reg_t;
/** Group: Version Register */
/** Type of sys_date register
* Date register.
*/
typedef union {
struct {
/** sys_date : R/W; bitpos: [27:0]; default: 37782128;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
uint32_t sys_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_sys_date_reg_t;
typedef struct {
volatile hp_sys_external_device_encrypt_decrypt_control_reg_t sys_external_device_encrypt_decrypt_control;
volatile hp_sys_sram_usage_conf_reg_t sys_sram_usage_conf;
volatile hp_sys_sec_dpa_conf_reg_t sys_sec_dpa_conf;
volatile hp_sys_cpu_peri_timeout_conf_reg_t sys_cpu_peri_timeout_conf;
volatile hp_sys_cpu_peri_timeout_addr_reg_t sys_cpu_peri_timeout_addr;
volatile hp_sys_cpu_peri_timeout_uid_reg_t sys_cpu_peri_timeout_uid;
volatile hp_sys_hp_peri_timeout_conf_reg_t sys_hp_peri_timeout_conf;
volatile hp_sys_hp_peri_timeout_addr_reg_t sys_hp_peri_timeout_addr;
volatile hp_sys_hp_peri_timeout_uid_reg_t sys_hp_peri_timeout_uid;
volatile hp_sys_rom_table_lock_reg_t sys_rom_table_lock;
volatile hp_sys_rom_table_reg_t sys_rom_table;
uint32_t reserved_02c;
volatile hp_sys_rng_loop_reg_t sys_rng_loop;
uint32_t reserved_034[242];
volatile hp_sys_date_reg_t sys_date;
} hp_system_dev_t;
extern hp_system_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTMTX_CORE0_PMU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0)
/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PMU_INTR mapping register
*/
#define INTMTX_CORE0_PMU_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PMU_INTR_MAP_M (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
#define INTMTX_CORE0_PMU_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PMU_INTR_MAP_S 0
/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4)
/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_EFUSE_INTR mapping register
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_EFUSE_INTR_MAP_M (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
#define INTMTX_CORE0_EFUSE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_EFUSE_INTR_MAP_S 0
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8)
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_RTC_TIMER_INTR mapping register
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc)
/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_BLE_TIMER_INTR mapping register
*/
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10)
/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_WDT_INTR mapping register
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_WDT_INTR_MAP_M (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
#define INTMTX_CORE0_LP_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14)
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_PERI_TIMEOUT_INTR mapping register
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x18)
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_APM_M0_INTR mapping register
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x1c)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_0 mapping register
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x20)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_1 mapping register
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x24)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_2 mapping register
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x28)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_3 mapping register
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c)
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ASSIST_DEBUG_INTR mapping register
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30)
/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TRACE_INTR mapping register
*/
#define INTMTX_CORE0_TRACE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TRACE_INTR_MAP_M (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
#define INTMTX_CORE0_TRACE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TRACE_INTR_MAP_S 0
/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34)
/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CACHE_INTR mapping register
*/
#define INTMTX_CORE0_CACHE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CACHE_INTR_MAP_M (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
#define INTMTX_CORE0_CACHE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CACHE_INTR_MAP_S 0
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38)
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_PERI_TIMEOUT_INTR mapping register
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c)
/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_MAC_INTR mapping register
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BT_MAC_INTR_MAP_M (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
#define INTMTX_CORE0_BT_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40)
/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_BB_INTR mapping register
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BT_BB_INTR_MAP_M (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
#define INTMTX_CORE0_BT_BB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_BB_INTR_MAP_S 0
/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x44)
/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_BB_NMI mapping register
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_BT_BB_NMI_MAP_M (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
#define INTMTX_CORE0_BT_BB_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_BB_NMI_MAP_S 0
/** INTMTX_CORE0_COEX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48)
/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_COEX_INTR mapping register
*/
#define INTMTX_CORE0_COEX_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_COEX_INTR_MAP_M (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
#define INTMTX_CORE0_COEX_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_COEX_INTR_MAP_S 0
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4c)
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BLE_TIMER_INTR mapping register
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x50)
/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BLE_SEC_INTR mapping register
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S 0
/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x54)
/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ZB_MAC_INTR mapping register
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x58)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPIO_INTERRUPT_PRO mapping register
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x5c)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPIO_INTERRUPT_PRO_NMI mapping register
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
/** INTMTX_CORE0_PAU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x60)
/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PAU_INTR mapping register
*/
#define INTMTX_CORE0_PAU_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PAU_INTR_MAP_M (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
#define INTMTX_CORE0_PAU_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PAU_INTR_MAP_S 0
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x64)
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_PERI_TIMEOUT_INTR mapping register
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68)
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M0_INTR mapping register
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x6c)
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M1_INTR mapping register
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x70)
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M2_INTR mapping register
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74)
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M3_INTR mapping register
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S 0
/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x78)
/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_MSPI_INTR mapping register
*/
#define INTMTX_CORE0_MSPI_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_M (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_S 0
/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x7c)
/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2S1_INTR mapping register
*/
#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_S 0
/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80)
/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UHCI0_INTR mapping register
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UHCI0_INTR_MAP_M (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
#define INTMTX_CORE0_UHCI0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UHCI0_INTR_MAP_S 0
/** INTMTX_CORE0_UART0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84)
/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UART0_INTR mapping register
*/
#define INTMTX_CORE0_UART0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UART0_INTR_MAP_M (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
#define INTMTX_CORE0_UART0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UART0_INTR_MAP_S 0
/** INTMTX_CORE0_UART1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88)
/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UART1_INTR mapping register
*/
#define INTMTX_CORE0_UART1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UART1_INTR_MAP_M (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
#define INTMTX_CORE0_UART1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UART1_INTR_MAP_S 0
/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c)
/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LEDC_INTR mapping register
*/
#define INTMTX_CORE0_LEDC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LEDC_INTR_MAP_M (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
#define INTMTX_CORE0_LEDC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LEDC_INTR_MAP_S 0
/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90)
/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CAN0_INTR mapping register
*/
#define INTMTX_CORE0_CAN0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CAN0_INTR_MAP_M (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
#define INTMTX_CORE0_CAN0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CAN0_INTR_MAP_S 0
/** INTMTX_CORE0_USB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94)
/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_USB_INTR mapping register
*/
#define INTMTX_CORE0_USB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_USB_INTR_MAP_M (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
#define INTMTX_CORE0_USB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_USB_INTR_MAP_S 0
/** INTMTX_CORE0_RMT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98)
/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_RMT_INTR mapping register
*/
#define INTMTX_CORE0_RMT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_RMT_INTR_MAP_M (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
#define INTMTX_CORE0_RMT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_RMT_INTR_MAP_S 0
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c)
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2C_EXT0_INTR mapping register
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S 0
/** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0)
/** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2C_EXT1_INTR mapping register
*/
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_M (INTMTX_CORE0_I2C_EXT1_INTR_MAP_V << INTMTX_CORE0_I2C_EXT1_INTR_MAP_S)
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4)
/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG0_T0_INTR mapping register
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_T0_INTR_MAP_M (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
#define INTMTX_CORE0_TG0_T0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_T0_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8)
/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG0_WDT_INTR mapping register
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac)
/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG1_T0_INTR mapping register
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_T0_INTR_MAP_M (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
#define INTMTX_CORE0_TG1_T0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_T0_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0)
/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG1_WDT_INTR mapping register
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4)
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET0_INTR mapping register
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8)
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET1_INTR mapping register
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc)
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET2_INTR mapping register
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0
/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0)
/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_APB_ADC_INTR mapping register
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_APB_ADC_INTR_MAP_M (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
#define INTMTX_CORE0_APB_ADC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_APB_ADC_INTR_MAP_S 0
/** INTMTX_CORE0_PWM_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4)
/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PWM_INTR mapping register
*/
#define INTMTX_CORE0_PWM_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PWM_INTR_MAP_M (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
#define INTMTX_CORE0_PWM_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PWM_INTR_MAP_S 0
/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8)
/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PCNT_INTR mapping register
*/
#define INTMTX_CORE0_PCNT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PCNT_INTR_MAP_M (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
#define INTMTX_CORE0_PCNT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PCNT_INTR_MAP_S 0
/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc)
/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PARL_IO_TX_INTR mapping register
*/
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_M (INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S)
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S 0
/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0)
/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PARL_IO_RX_INTR mapping register
*/
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_M (INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S)
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4)
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH0_INTR mapping register
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8)
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH1_INTR mapping register
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc)
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH2_INTR mapping register
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0)
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH0_INTR mapping register
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4)
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH1_INTR mapping register
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8)
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH2_INTR mapping register
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S 0
/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec)
/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPSPI2_INTR mapping register
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_GPSPI2_INTR_MAP_M (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
#define INTMTX_CORE0_GPSPI2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPSPI2_INTR_MAP_S 0
/** INTMTX_CORE0_AES_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0)
/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_AES_INTR mapping register
*/
#define INTMTX_CORE0_AES_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_AES_INTR_MAP_M (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
#define INTMTX_CORE0_AES_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_AES_INTR_MAP_S 0
/** INTMTX_CORE0_SHA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4)
/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SHA_INTR mapping register
*/
#define INTMTX_CORE0_SHA_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SHA_INTR_MAP_M (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
#define INTMTX_CORE0_SHA_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SHA_INTR_MAP_S 0
/** INTMTX_CORE0_RSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8)
/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_RSA_INTR mapping register
*/
#define INTMTX_CORE0_RSA_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_RSA_INTR_MAP_M (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
#define INTMTX_CORE0_RSA_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_RSA_INTR_MAP_S 0
/** INTMTX_CORE0_ECC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc)
/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ECC_INTR mapping register
*/
#define INTMTX_CORE0_ECC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ECC_INTR_MAP_M (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
#define INTMTX_CORE0_ECC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ECC_INTR_MAP_S 0
/** INTMTX_CORE0_ECDSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100)
/** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ECDSA_INTR mapping register
*/
#define INTMTX_CORE0_ECDSA_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ECDSA_INTR_MAP_M (INTMTX_CORE0_ECDSA_INTR_MAP_V << INTMTX_CORE0_ECDSA_INTR_MAP_S)
#define INTMTX_CORE0_ECDSA_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ECDSA_INTR_MAP_S 0
/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x104)
/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 0~31 mapping register
*/
#define INTMTX_CORE0_INT_STATUS_0 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_0_M (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
#define INTMTX_CORE0_INT_STATUS_0_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_0_S 0
/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x108)
/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 32~63 mapping register
*/
#define INTMTX_CORE0_INT_STATUS_1 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_1_M (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
#define INTMTX_CORE0_INT_STATUS_1_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_1_S 0
/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x10c)
/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 64~95 mapping register
*/
#define INTMTX_CORE0_INT_STATUS_2 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_2_M (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
#define INTMTX_CORE0_INT_STATUS_2_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_2_S 0
/** INTMTX_CORE0_CLOCK_GATE_REG register
* register description
*/
#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x110)
/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Clock register
*/
#define INTMTX_CORE0_REG_CLK_EN (BIT(0))
#define INTMTX_CORE0_REG_CLK_EN_M (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
#define INTMTX_CORE0_REG_CLK_EN_V 0x00000001U
#define INTMTX_CORE0_REG_CLK_EN_S 0
/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
* register description
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc)
/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784;
* Version control register
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU
#define INTMTX_CORE0_INTERRUPT_REG_DATE_M (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
#define INTMTX_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU
#define INTMTX_CORE0_INTERRUPT_REG_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CORE0_CPU_INT_ENABLE_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0)
/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_ENABLE_M (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S)
#define INTPRI_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_ENABLE_S 0
/** INTPRI_CORE0_CPU_INT_TYPE_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4)
/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_TYPE 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_TYPE_M (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S)
#define INTPRI_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_TYPE_S 0
/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8)
/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S)
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S 0
/** INTPRI_CORE0_CPU_INT_PRI_0_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc)
/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_0_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_0_MAP_M (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S)
#define INTPRI_CORE0_CPU_PRI_0_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_0_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_1_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10)
/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_1_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_1_MAP_M (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S)
#define INTPRI_CORE0_CPU_PRI_1_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_1_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_2_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14)
/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_2_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_2_MAP_M (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S)
#define INTPRI_CORE0_CPU_PRI_2_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_2_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_3_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18)
/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_3_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_3_MAP_M (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S)
#define INTPRI_CORE0_CPU_PRI_3_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_3_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_4_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c)
/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_4_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_4_MAP_M (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S)
#define INTPRI_CORE0_CPU_PRI_4_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_4_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_5_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20)
/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_5_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_5_MAP_M (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S)
#define INTPRI_CORE0_CPU_PRI_5_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_5_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_6_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24)
/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_6_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_6_MAP_M (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S)
#define INTPRI_CORE0_CPU_PRI_6_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_6_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_7_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28)
/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_7_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_7_MAP_M (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S)
#define INTPRI_CORE0_CPU_PRI_7_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_7_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_8_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c)
/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_8_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_8_MAP_M (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S)
#define INTPRI_CORE0_CPU_PRI_8_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_8_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_9_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30)
/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_9_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_9_MAP_M (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S)
#define INTPRI_CORE0_CPU_PRI_9_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_9_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_10_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34)
/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_10_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_10_MAP_M (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S)
#define INTPRI_CORE0_CPU_PRI_10_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_10_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_11_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38)
/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_11_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_11_MAP_M (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S)
#define INTPRI_CORE0_CPU_PRI_11_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_11_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_12_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c)
/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_12_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_12_MAP_M (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S)
#define INTPRI_CORE0_CPU_PRI_12_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_12_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_13_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40)
/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_13_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_13_MAP_M (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S)
#define INTPRI_CORE0_CPU_PRI_13_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_13_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_14_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44)
/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_14_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_14_MAP_M (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S)
#define INTPRI_CORE0_CPU_PRI_14_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_14_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_15_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48)
/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_15_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_15_MAP_M (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S)
#define INTPRI_CORE0_CPU_PRI_15_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_15_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_16_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c)
/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_16_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_16_MAP_M (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S)
#define INTPRI_CORE0_CPU_PRI_16_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_16_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_17_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50)
/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_17_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_17_MAP_M (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S)
#define INTPRI_CORE0_CPU_PRI_17_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_17_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_18_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54)
/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_18_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_18_MAP_M (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S)
#define INTPRI_CORE0_CPU_PRI_18_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_18_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_19_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58)
/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_19_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_19_MAP_M (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S)
#define INTPRI_CORE0_CPU_PRI_19_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_19_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_20_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c)
/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_20_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_20_MAP_M (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S)
#define INTPRI_CORE0_CPU_PRI_20_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_20_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_21_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60)
/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_21_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_21_MAP_M (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S)
#define INTPRI_CORE0_CPU_PRI_21_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_21_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_22_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64)
/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_22_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_22_MAP_M (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S)
#define INTPRI_CORE0_CPU_PRI_22_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_22_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_23_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68)
/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_23_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_23_MAP_M (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S)
#define INTPRI_CORE0_CPU_PRI_23_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_23_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_24_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c)
/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_24_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_24_MAP_M (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S)
#define INTPRI_CORE0_CPU_PRI_24_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_24_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_25_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70)
/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_25_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_25_MAP_M (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S)
#define INTPRI_CORE0_CPU_PRI_25_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_25_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_26_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74)
/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_26_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_26_MAP_M (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S)
#define INTPRI_CORE0_CPU_PRI_26_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_26_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_27_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78)
/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_27_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_27_MAP_M (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S)
#define INTPRI_CORE0_CPU_PRI_27_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_27_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_28_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c)
/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_28_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_28_MAP_M (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S)
#define INTPRI_CORE0_CPU_PRI_28_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_28_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_29_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80)
/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_29_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_29_MAP_M (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S)
#define INTPRI_CORE0_CPU_PRI_29_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_29_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_30_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84)
/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_30_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_30_MAP_M (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S)
#define INTPRI_CORE0_CPU_PRI_30_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_30_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_31_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88)
/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_31_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_31_MAP_M (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S)
#define INTPRI_CORE0_CPU_PRI_31_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_31_MAP_S 0
/** INTPRI_CORE0_CPU_INT_THRESH_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c)
/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_THRESH 0x000000FFU
#define INTPRI_CORE0_CPU_INT_THRESH_M (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S)
#define INTPRI_CORE0_CPU_INT_THRESH_V 0x000000FFU
#define INTPRI_CORE0_CPU_INT_THRESH_S 0
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
/** INTPRI_DATE_REG register
* register description
*/
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35660416;
* Need add description
*/
#define INTPRI_DATE 0x0FFFFFFFU
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
#define INTPRI_DATE_V 0x0FFFFFFFU
#define INTPRI_DATE_S 0
/** INTPRI_CLOCK_GATE_REG register
* register description
*/
#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTPRI_CLK_EN (BIT(0))
#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
#define INTPRI_CLK_EN_V 0x00000001U
#define INTPRI_CLK_EN_S 0
/** INTPRI_CORE0_CPU_INT_CLEAR_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8)
/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_CLEAR_M (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S)
#define INTPRI_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_CLEAR_S 0
#ifdef __cplusplus
}
#endif

671
components/soc/esp32h21/register/soc/intpri_struct.h Normal file
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@ -0,0 +1,671 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of core0_cpu_int_enable register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_enable:32;
};
uint32_t val;
} intpri_core0_cpu_int_enable_reg_t;
/** Type of core0_cpu_int_type register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_type:32;
};
uint32_t val;
} intpri_core0_cpu_int_type_reg_t;
/** Type of core0_cpu_int_eip_status register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_eip_status:32;
};
uint32_t val;
} intpri_core0_cpu_int_eip_status_reg_t;
/** Type of core0_cpu_int_pri_0 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_0_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_0_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_0_reg_t;
/** Type of core0_cpu_int_pri_1 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_1_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_1_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_1_reg_t;
/** Type of core0_cpu_int_pri_2 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_2_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_2_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_2_reg_t;
/** Type of core0_cpu_int_pri_3 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_3_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_3_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_3_reg_t;
/** Type of core0_cpu_int_pri_4 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_4_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_4_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_4_reg_t;
/** Type of core0_cpu_int_pri_5 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_5_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_5_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_5_reg_t;
/** Type of core0_cpu_int_pri_6 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_6_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_6_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_6_reg_t;
/** Type of core0_cpu_int_pri_7 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_7_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_7_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_7_reg_t;
/** Type of core0_cpu_int_pri_8 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_8_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_8_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_8_reg_t;
/** Type of core0_cpu_int_pri_9 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_9_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_9_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_9_reg_t;
/** Type of core0_cpu_int_pri_10 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_10_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_10_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_10_reg_t;
/** Type of core0_cpu_int_pri_11 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_11_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_11_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_11_reg_t;
/** Type of core0_cpu_int_pri_12 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_12_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_12_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_12_reg_t;
/** Type of core0_cpu_int_pri_13 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_13_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_13_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_13_reg_t;
/** Type of core0_cpu_int_pri_14 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_14_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_14_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_14_reg_t;
/** Type of core0_cpu_int_pri_15 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_15_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_15_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_15_reg_t;
/** Type of core0_cpu_int_pri_16 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_16_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_16_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_16_reg_t;
/** Type of core0_cpu_int_pri_17 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_17_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_17_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_17_reg_t;
/** Type of core0_cpu_int_pri_18 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_18_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_18_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_18_reg_t;
/** Type of core0_cpu_int_pri_19 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_19_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_19_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_19_reg_t;
/** Type of core0_cpu_int_pri_20 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_20_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_20_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_20_reg_t;
/** Type of core0_cpu_int_pri_21 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_21_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_21_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_21_reg_t;
/** Type of core0_cpu_int_pri_22 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_22_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_22_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_22_reg_t;
/** Type of core0_cpu_int_pri_23 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_23_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_23_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_23_reg_t;
/** Type of core0_cpu_int_pri_24 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_24_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_24_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_24_reg_t;
/** Type of core0_cpu_int_pri_25 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_25_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_25_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_25_reg_t;
/** Type of core0_cpu_int_pri_26 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_26_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_26_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_26_reg_t;
/** Type of core0_cpu_int_pri_27 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_27_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_27_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_27_reg_t;
/** Type of core0_cpu_int_pri_28 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_28_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_28_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_28_reg_t;
/** Type of core0_cpu_int_pri_29 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_29_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_29_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_29_reg_t;
/** Type of core0_cpu_int_pri_30 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_30_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_30_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_30_reg_t;
/** Type of core0_cpu_int_pri_31 register
* register description
*/
typedef union {
struct {
/** core0_cpu_pri_31_map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_pri_31_map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_31_reg_t;
/** Type of core0_cpu_int_thresh register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_thresh:8;
uint32_t reserved_8:24;
};
uint32_t val;
} intpri_core0_cpu_int_thresh_reg_t;
/** Type of clock_gate register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_clock_gate_reg_t;
/** Type of core0_cpu_int_clear register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_clear:32;
};
uint32_t val;
} intpri_core0_cpu_int_clear_reg_t;
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_0 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_0:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_0_reg_t;
/** Type of cpu_intr_from_cpu_1 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_1:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_1_reg_t;
/** Type of cpu_intr_from_cpu_2 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_2:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_2_reg_t;
/** Type of cpu_intr_from_cpu_3 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_3:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_3_reg_t;
/** Group: Version Registers */
/** Type of date register
* register description
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35660416;
* Need add description
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} intpri_date_reg_t;
typedef struct {
volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable;
volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type;
volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status;
volatile intpri_core0_cpu_int_pri_0_reg_t core0_cpu_int_pri_0;
volatile intpri_core0_cpu_int_pri_1_reg_t core0_cpu_int_pri_1;
volatile intpri_core0_cpu_int_pri_2_reg_t core0_cpu_int_pri_2;
volatile intpri_core0_cpu_int_pri_3_reg_t core0_cpu_int_pri_3;
volatile intpri_core0_cpu_int_pri_4_reg_t core0_cpu_int_pri_4;
volatile intpri_core0_cpu_int_pri_5_reg_t core0_cpu_int_pri_5;
volatile intpri_core0_cpu_int_pri_6_reg_t core0_cpu_int_pri_6;
volatile intpri_core0_cpu_int_pri_7_reg_t core0_cpu_int_pri_7;
volatile intpri_core0_cpu_int_pri_8_reg_t core0_cpu_int_pri_8;
volatile intpri_core0_cpu_int_pri_9_reg_t core0_cpu_int_pri_9;
volatile intpri_core0_cpu_int_pri_10_reg_t core0_cpu_int_pri_10;
volatile intpri_core0_cpu_int_pri_11_reg_t core0_cpu_int_pri_11;
volatile intpri_core0_cpu_int_pri_12_reg_t core0_cpu_int_pri_12;
volatile intpri_core0_cpu_int_pri_13_reg_t core0_cpu_int_pri_13;
volatile intpri_core0_cpu_int_pri_14_reg_t core0_cpu_int_pri_14;
volatile intpri_core0_cpu_int_pri_15_reg_t core0_cpu_int_pri_15;
volatile intpri_core0_cpu_int_pri_16_reg_t core0_cpu_int_pri_16;
volatile intpri_core0_cpu_int_pri_17_reg_t core0_cpu_int_pri_17;
volatile intpri_core0_cpu_int_pri_18_reg_t core0_cpu_int_pri_18;
volatile intpri_core0_cpu_int_pri_19_reg_t core0_cpu_int_pri_19;
volatile intpri_core0_cpu_int_pri_20_reg_t core0_cpu_int_pri_20;
volatile intpri_core0_cpu_int_pri_21_reg_t core0_cpu_int_pri_21;
volatile intpri_core0_cpu_int_pri_22_reg_t core0_cpu_int_pri_22;
volatile intpri_core0_cpu_int_pri_23_reg_t core0_cpu_int_pri_23;
volatile intpri_core0_cpu_int_pri_24_reg_t core0_cpu_int_pri_24;
volatile intpri_core0_cpu_int_pri_25_reg_t core0_cpu_int_pri_25;
volatile intpri_core0_cpu_int_pri_26_reg_t core0_cpu_int_pri_26;
volatile intpri_core0_cpu_int_pri_27_reg_t core0_cpu_int_pri_27;
volatile intpri_core0_cpu_int_pri_28_reg_t core0_cpu_int_pri_28;
volatile intpri_core0_cpu_int_pri_29_reg_t core0_cpu_int_pri_29;
volatile intpri_core0_cpu_int_pri_30_reg_t core0_cpu_int_pri_30;
volatile intpri_core0_cpu_int_pri_31_reg_t core0_cpu_int_pri_31;
volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh;
volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
volatile intpri_date_reg_t date;
volatile intpri_clock_gate_reg_t clock_gate;
volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear;
} intpri_dev_t;
extern intpri_dev_t INTPRI;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0xac, "Invalid size of intpri_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* log config register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_BASE + 0x0)
/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
* enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu
*/
#define MEM_MONITOR_LOG_ENA 0x00000007U
#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
#define MEM_MONITOR_LOG_ENA_V 0x00000007U
#define MEM_MONITOR_LOG_ENA_S 0
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
* This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
* HALFWORD monitor, 4'b1000: BYTE monitor.
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 3
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* check data register
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_BASE + 0x4)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* check data mask register
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_BASE + 0x8)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* log boundary register
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_BASE + 0xc)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* log boundary register
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_BASE + 0x10)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MEM_START_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_BASE + 0x14)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_BASE + 0x18)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* current writing address.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_BASE + 0x1c)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* writing address update
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* full flag status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* clock gate force on register
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_BASE + 0x28)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* version register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
* version register
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/mem_monitor_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of monitor_log_setting register
* log config register
*/
typedef union {
struct {
/** monitor_log_ena : R/W; bitpos: [2:0]; default: 0;
* enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu
*/
uint32_t monitor_log_ena:3;
/** monitor_log_mode : R/W; bitpos: [6:3]; default: 0;
* This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
* HALFWORD monitor, 4'b1000: BYTE monitor.
*/
uint32_t monitor_log_mode:4;
/** monitor_log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
uint32_t monitor_log_mem_loop_enable:1;
uint32_t reserved_8:24;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of monitor_log_check_data register
* check data register
*/
typedef union {
struct {
/** monitor_log_check_data : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
uint32_t monitor_log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of monitor_log_data_mask register
* check data mask register
*/
typedef union {
struct {
/** monitor_log_data_mask : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
uint32_t monitor_log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of monitor_log_min register
* log boundary register
*/
typedef union {
struct {
/** monitor_log_min : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
uint32_t monitor_log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of monitor_log_max register
* log boundary register
*/
typedef union {
struct {
/** monitor_log_max : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
uint32_t monitor_log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of monitor_log_mem_start register
* log message store range register
*/
typedef union {
struct {
/** monitor_log_mem_start : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
uint32_t monitor_log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of monitor_log_mem_end register
* log message store range register
*/
typedef union {
struct {
/** monitor_log_mem_end : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
uint32_t monitor_log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of monitor_log_mem_current_addr register
* current writing address.
*/
typedef union {
struct {
/** monitor_log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
uint32_t monitor_log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of monitor_log_mem_addr_update register
* writing address update
*/
typedef union {
struct {
/** monitor_log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
uint32_t monitor_log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of monitor_log_mem_full_flag register
* full flag status register
*/
typedef union {
struct {
/** monitor_log_mem_full_flag : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
uint32_t monitor_log_mem_full_flag:1;
/** monitor_clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
uint32_t monitor_clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of monitor_clock_gate register
* clock gate force on register
*/
typedef union {
struct {
/** monitor_clk_en : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
uint32_t monitor_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of monitor_date register
* version register
*/
typedef union {
struct {
/** monitor_date : R/W; bitpos: [27:0]; default: 35660096;
* version register
*/
uint32_t monitor_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct {
volatile mem_monitor_log_setting_reg_t monitor_log_setting;
volatile mem_monitor_log_check_data_reg_t monitor_log_check_data;
volatile mem_monitor_log_data_mask_reg_t monitor_log_data_mask;
volatile mem_monitor_log_min_reg_t monitor_log_min;
volatile mem_monitor_log_max_reg_t monitor_log_max;
volatile mem_monitor_log_mem_start_reg_t monitor_log_mem_start;
volatile mem_monitor_log_mem_end_reg_t monitor_log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t monitor_log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t monitor_log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t monitor_log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t monitor_clock_gate;
uint32_t reserved_02c[244];
volatile mem_monitor_date_reg_t monitor_date;
} mem_monitor_dev_t;
extern mem_monitor_dev_t MEM_MONITOR;
#ifndef __cplusplus
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PARL_IO_RX_MODE_CFG_REG register
* Parallel RX Sampling mode configuration register.
*/
#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_BASE + 0x0)
/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_S 21
/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
* Write 1 to enable data sampling by software.
*/
#define PARL_IO_RX_SW_EN (BIT(25))
#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
#define PARL_IO_RX_SW_EN_V 0x00000001U
#define PARL_IO_RX_SW_EN_S 25
/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
* Write 1 to invert the external enable signal.
*/
#define PARL_IO_RX_EXT_EN_INV (BIT(26))
#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U
#define PARL_IO_RX_EXT_EN_INV_S 26
/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 0: positive pulse start(data bit included) && positive pulse end(data bit included)
* 1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
* 2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
* 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
* 4: positive pulse start(data bit included) && length end
* 5: positive pulse start(data bit excluded) && length end
*/
#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27
/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 0: external level enable mode
* 1: external pulse enable mode
* 2: internal software enable mode
*/
#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_S 30
/** PARL_IO_RX_DATA_CFG_REG register
* Parallel RX data configuration register.
*/
#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x4)
/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
#define PARL_IO_RX_BITLEN 0x0007FFFFU
#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
#define PARL_IO_RX_BITLEN_V 0x0007FFFFU
#define PARL_IO_RX_BITLEN_S 9
/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
*/
#define PARL_IO_RX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_RX_DATA_ORDER_INV_S 28
/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
#define PARL_IO_RX_BUS_WID_SEL 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_S 29
/** PARL_IO_RX_GENRL_CFG_REG register
* Parallel RX general configuration register.
*/
#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x8)
/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
#define PARL_IO_RX_GATING_EN (BIT(12))
#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
#define PARL_IO_RX_GATING_EN_V 0x00000001U
#define PARL_IO_RX_GATING_EN_S 12
/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_S 13
/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
* Write 1 to enable timeout function to generate error eof.
*/
#define PARL_IO_RX_TIMEOUT_EN (BIT(29))
#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U
#define PARL_IO_RX_TIMEOUT_EN_S 29
/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
#define PARL_IO_RX_EOF_GEN_SEL (BIT(30))
#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_RX_EOF_GEN_SEL_S 30
/** PARL_IO_RX_START_CFG_REG register
* Parallel RX Start configuration register.
*/
#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_BASE + 0xc)
/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
#define PARL_IO_RX_START (BIT(31))
#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
#define PARL_IO_RX_START_V 0x00000001U
#define PARL_IO_RX_START_S 31
/** PARL_IO_TX_DATA_CFG_REG register
* Parallel TX data configuration register.
*/
#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x10)
/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
#define PARL_IO_TX_BITLEN 0x0007FFFFU
#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
#define PARL_IO_TX_BITLEN_V 0x0007FFFFU
#define PARL_IO_TX_BITLEN_S 9
/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
*/
#define PARL_IO_TX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_TX_DATA_ORDER_INV_S 28
/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
#define PARL_IO_TX_BUS_WID_SEL 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_S 29
/** PARL_IO_TX_START_CFG_REG register
* Parallel TX Start configuration register.
*/
#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_BASE + 0x14)
/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
#define PARL_IO_TX_START (BIT(31))
#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
#define PARL_IO_TX_START_V 0x00000001U
#define PARL_IO_TX_START_S 31
/** PARL_IO_TX_GENRL_CFG_REG register
* Parallel TX general configuration register.
*/
#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x18)
/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
#define PARL_IO_TX_EOF_GEN_SEL (BIT(13))
#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_TX_EOF_GEN_SEL_S 13
/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_S 14
/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
* Write 1 to enable the clock gating of output tx clock.
*/
#define PARL_IO_TX_GATING_EN (BIT(30))
#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
#define PARL_IO_TX_GATING_EN_V 0x00000001U
#define PARL_IO_TX_GATING_EN_S 30
/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
* Write 1 to enable the output of tx data valid signal.
*/
#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31))
#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U
#define PARL_IO_TX_VALID_OUTPUT_EN_S 31
/** PARL_IO_FIFO_CFG_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_BASE + 0x1c)
/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
#define PARL_IO_TX_FIFO_SRST (BIT(30))
#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
#define PARL_IO_TX_FIFO_SRST_V 0x00000001U
#define PARL_IO_TX_FIFO_SRST_S 30
/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
* Write 1 to reset async fifo in rx module.
*/
#define PARL_IO_RX_FIFO_SRST (BIT(31))
#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
#define PARL_IO_RX_FIFO_SRST_V 0x00000001U
#define PARL_IO_RX_FIFO_SRST_S 31
/** PARL_IO_REG_UPDATE_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_BASE + 0x20)
/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
#define PARL_IO_RX_REG_UPDATE (BIT(31))
#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
#define PARL_IO_RX_REG_UPDATE_V 0x00000001U
#define PARL_IO_RX_REG_UPDATE_S 31
/** PARL_IO_ST_REG register
* Parallel IO module status register0.
*/
#define PARL_IO_ST_REG (DR_REG_PARL_BASE + 0x24)
/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
#define PARL_IO_TX_READY (BIT(31))
#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
#define PARL_IO_TX_READY_V 0x00000001U
#define PARL_IO_TX_READY_S 31
/** PARL_IO_INT_ENA_REG register
* Parallel IO interrupt enable signal configuration register.
*/
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_BASE + 0x28)
/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1
/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ENA (BIT(2))
#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ENA_S 2
/** PARL_IO_INT_RAW_REG register
* Parallel IO interrupt raw signal status register.
*/
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_BASE + 0x2c)
/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1
/** PARL_IO_TX_EOF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_RAW (BIT(2))
#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U
#define PARL_IO_TX_EOF_INT_RAW_S 2
/** PARL_IO_INT_ST_REG register
* Parallel IO interrupt signal status register.
*/
#define PARL_IO_INT_ST_REG (DR_REG_PARL_BASE + 0x30)
/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1
/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ST (BIT(2))
#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ST_S 2
/** PARL_IO_INT_CLR_REG register
* Parallel IO interrupt clear signal configuration register.
*/
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_BASE + 0x34)
/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1
/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_CLR (BIT(2))
#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U
#define PARL_IO_TX_EOF_INT_CLR_S 2
/** PARL_IO_RX_ST0_REG register
* Parallel IO RX status register0
*/
#define PARL_IO_RX_ST0_REG (DR_REG_PARL_BASE + 0x38)
/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
#define PARL_IO_RX_CNT 0x0000001FU
#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
#define PARL_IO_RX_CNT_V 0x0000001FU
#define PARL_IO_RX_CNT_S 8
/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13
/** PARL_IO_RX_ST1_REG register
* Parallel IO RX status register1
*/
#define PARL_IO_RX_ST1_REG (DR_REG_PARL_BASE + 0x3c)
/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_TX_ST0_REG register
* Parallel IO TX status register0
*/
#define PARL_IO_TX_ST0_REG (DR_REG_PARL_BASE + 0x40)
/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
#define PARL_IO_TX_CNT 0x0000007FU
#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
#define PARL_IO_TX_CNT_V 0x0000007FU
#define PARL_IO_TX_CNT_S 6
/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_RX_CLK_CFG_REG register
* Parallel IO RX clk configuration register
*/
#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x44)
/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
#define PARL_IO_RX_CLK_I_INV (BIT(30))
#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
#define PARL_IO_RX_CLK_I_INV_V 0x00000001U
#define PARL_IO_RX_CLK_I_INV_S 30
/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Rx core clock.
*/
#define PARL_IO_RX_CLK_O_INV (BIT(31))
#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
#define PARL_IO_RX_CLK_O_INV_V 0x00000001U
#define PARL_IO_RX_CLK_O_INV_S 31
/** PARL_IO_TX_CLK_CFG_REG register
* Parallel IO TX clk configuration register
*/
#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x48)
/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
#define PARL_IO_TX_CLK_I_INV (BIT(30))
#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
#define PARL_IO_TX_CLK_I_INV_V 0x00000001U
#define PARL_IO_TX_CLK_I_INV_S 30
/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Tx core clock.
*/
#define PARL_IO_TX_CLK_O_INV (BIT(31))
#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
#define PARL_IO_TX_CLK_O_INV_V 0x00000001U
#define PARL_IO_TX_CLK_O_INV_S 31
/** PARL_IO_CLK_REG register
* Parallel IO clk configuration register
*/
#define PARL_IO_CLK_REG (DR_REG_PARL_BASE + 0x120)
/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
#define PARL_IO_CLK_EN (BIT(31))
#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
#define PARL_IO_CLK_EN_V 0x00000001U
#define PARL_IO_CLK_EN_S 31
/** PARL_IO_VERSION_REG register
* Version register.
*/
#define PARL_IO_VERSION_REG (DR_REG_PARL_BASE + 0x3fc)
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
* Version of this register file
*/
#define PARL_IO_DATE 0x0FFFFFFFU
#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S)
#define PARL_IO_DATE_V 0x0FFFFFFFU
#define PARL_IO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/parl_io_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: PARL_IO RX Mode Configuration */
/** Type of io_rx_mode_cfg register
* Parallel RX Sampling mode configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** io_rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
uint32_t io_rx_ext_en_sel:4;
/** io_rx_sw_en : R/W; bitpos: [25]; default: 0;
* Write 1 to enable data sampling by software.
*/
uint32_t io_rx_sw_en:1;
/** io_rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
* Write 1 to invert the external enable signal.
*/
uint32_t io_rx_ext_en_inv:1;
/** io_rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 0: positive pulse start(data bit included) && positive pulse end(data bit included)
* 1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
* 2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
* 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
* 4: positive pulse start(data bit included) && length end
* 5: positive pulse start(data bit excluded) && length end
*/
uint32_t io_rx_pulse_submode_sel:3;
/** io_rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 0: external level enable mode
* 1: external pulse enable mode
* 2: internal software enable mode
*/
uint32_t io_rx_smp_mode_sel:2;
};
uint32_t val;
} parl_io_rx_mode_cfg_reg_t;
/** Group: PARL_IO RX Data Configuration */
/** Type of io_rx_data_cfg register
* Parallel RX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** io_rx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
uint32_t io_rx_bitlen:19;
/** io_rx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
*/
uint32_t io_rx_data_order_inv:1;
/** io_rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t io_rx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_rx_data_cfg_reg_t;
/** Group: PARL_IO RX General Configuration */
/** Type of io_rx_genrl_cfg register
* Parallel RX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** io_rx_gating_en : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
uint32_t io_rx_gating_en:1;
/** io_rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
uint32_t io_rx_timeout_thres:16;
/** io_rx_timeout_en : R/W; bitpos: [29]; default: 1;
* Write 1 to enable timeout function to generate error eof.
*/
uint32_t io_rx_timeout_en:1;
/** io_rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
uint32_t io_rx_eof_gen_sel:1;
uint32_t reserved_31:1;
};
uint32_t val;
} parl_io_rx_genrl_cfg_reg_t;
/** Group: PARL_IO RX Start Configuration */
/** Type of io_rx_start_cfg register
* Parallel RX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_rx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
uint32_t io_rx_start:1;
};
uint32_t val;
} parl_io_rx_start_cfg_reg_t;
/** Group: PARL_IO TX Data Configuration */
/** Type of io_tx_data_cfg register
* Parallel TX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** io_tx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
uint32_t io_tx_bitlen:19;
/** io_tx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
*/
uint32_t io_tx_data_order_inv:1;
/** io_tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t io_tx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_tx_data_cfg_reg_t;
/** Group: PARL_IO TX Start Configuration */
/** Type of io_tx_start_cfg register
* Parallel TX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_tx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
uint32_t io_tx_start:1;
};
uint32_t val;
} parl_io_tx_start_cfg_reg_t;
/** Group: PARL_IO TX General Configuration */
/** Type of io_tx_genrl_cfg register
* Parallel TX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** io_tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
uint32_t io_tx_eof_gen_sel:1;
/** io_tx_idle_value : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
uint32_t io_tx_idle_value:16;
/** io_tx_gating_en : R/W; bitpos: [30]; default: 0;
* Write 1 to enable the clock gating of output tx clock.
*/
uint32_t io_tx_gating_en:1;
/** io_tx_valid_output_en : R/W; bitpos: [31]; default: 0;
* Write 1 to enable the output of tx data valid signal.
*/
uint32_t io_tx_valid_output_en:1;
};
uint32_t val;
} parl_io_tx_genrl_cfg_reg_t;
/** Group: PARL_IO FIFO Configuration */
/** Type of io_fifo_cfg register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_tx_fifo_srst : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
uint32_t io_tx_fifo_srst:1;
/** io_rx_fifo_srst : R/W; bitpos: [31]; default: 0;
* Write 1 to reset async fifo in rx module.
*/
uint32_t io_rx_fifo_srst:1;
};
uint32_t val;
} parl_io_fifo_cfg_reg_t;
/** Group: PARL_IO Register Update Configuration */
/** Type of io_reg_update register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_rx_reg_update : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
uint32_t io_rx_reg_update:1;
};
uint32_t val;
} parl_io_reg_update_reg_t;
/** Group: PARL_IO Status */
/** Type of io_st register
* Parallel IO module status register0.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_tx_ready : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
uint32_t io_tx_ready:1;
};
uint32_t val;
} parl_io_st_reg_t;
/** Group: PARL_IO Interrupt Configuration and Status */
/** Type of io_int_ena register
* Parallel IO interrupt enable signal configuration register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_ena:1;
/** io_rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_ena:1;
/** io_tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INT.
*/
uint32_t io_tx_eof_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_ena_reg_t;
/** Type of io_int_raw register
* Parallel IO interrupt raw signal status register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_raw:1;
/** io_rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_raw:1;
/** io_tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
uint32_t io_tx_eof_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_raw_reg_t;
/** Type of io_int_st register
* Parallel IO interrupt signal status register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_st:1;
/** io_rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_st:1;
/** io_tx_eof_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
uint32_t io_tx_eof_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_st_reg_t;
/** Type of io_int_clr register
* Parallel IO interrupt clear signal configuration register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_clr:1;
/** io_rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_clr:1;
/** io_tx_eof_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INT.
*/
uint32_t io_tx_eof_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_clr_reg_t;
/** Group: PARL_IO Rx Status0 */
/** Type of io_rx_st0 register
* Parallel IO RX status register0
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** io_rx_cnt : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
uint32_t io_rx_cnt:5;
/** io_rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
uint32_t io_rx_fifo_wr_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st0_reg_t;
/** Group: PARL_IO Rx Status1 */
/** Type of io_rx_st1 register
* Parallel IO RX status register1
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** io_rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
uint32_t io_rx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st1_reg_t;
/** Group: PARL_IO Tx Status0 */
/** Type of io_tx_st0 register
* Parallel IO TX status register0
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** io_tx_cnt : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
uint32_t io_tx_cnt:7;
/** io_tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
uint32_t io_tx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_tx_st0_reg_t;
/** Group: PARL_IO Rx Clock Configuration */
/** Type of io_rx_clk_cfg register
* Parallel IO RX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
uint32_t io_rx_clk_i_inv:1;
/** io_rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Rx core clock.
*/
uint32_t io_rx_clk_o_inv:1;
};
uint32_t val;
} parl_io_rx_clk_cfg_reg_t;
/** Group: PARL_IO Tx Clock Configuration */
/** Type of io_tx_clk_cfg register
* Parallel IO TX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
uint32_t io_tx_clk_i_inv:1;
/** io_tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Tx core clock.
*/
uint32_t io_tx_clk_o_inv:1;
};
uint32_t val;
} parl_io_tx_clk_cfg_reg_t;
/** Group: PARL_IO Clock Configuration */
/** Type of io_clk register
* Parallel IO clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_clk_en : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
uint32_t io_clk_en:1;
};
uint32_t val;
} parl_io_clk_reg_t;
/** Group: PARL_IO Version Register */
/** Type of io_version register
* Version register.
*/
typedef union {
struct {
/** io_date : R/W; bitpos: [27:0]; default: 35725920;
* Version of this register file
*/
uint32_t io_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} parl_io_version_reg_t;
typedef struct {
volatile parl_io_rx_mode_cfg_reg_t io_rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t io_rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t io_rx_genrl_cfg;
volatile parl_io_rx_start_cfg_reg_t io_rx_start_cfg;
volatile parl_io_tx_data_cfg_reg_t io_tx_data_cfg;
volatile parl_io_tx_start_cfg_reg_t io_tx_start_cfg;
volatile parl_io_tx_genrl_cfg_reg_t io_tx_genrl_cfg;
volatile parl_io_fifo_cfg_reg_t io_fifo_cfg;
volatile parl_io_reg_update_reg_t io_reg_update;
volatile parl_io_st_reg_t io_st;
volatile parl_io_int_ena_reg_t io_int_ena;
volatile parl_io_int_raw_reg_t io_int_raw;
volatile parl_io_int_st_reg_t io_int_st;
volatile parl_io_int_clr_reg_t io_int_clr;
volatile parl_io_rx_st0_reg_t io_rx_st0;
volatile parl_io_rx_st1_reg_t io_rx_st1;
volatile parl_io_tx_st0_reg_t io_tx_st0;
volatile parl_io_rx_clk_cfg_reg_t io_rx_clk_cfg;
volatile parl_io_tx_clk_cfg_reg_t io_tx_clk_cfg;
uint32_t reserved_04c[53];
volatile parl_io_clk_reg_t io_clk;
uint32_t reserved_124[182];
volatile parl_io_version_reg_t io_version;
} parl_io_dev_t;
extern parl_io_dev_t PARL_IO;
#ifndef __cplusplus
_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
* Peri backup control register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
#define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
#define PAU_FLOW_ERR_V 0x00000007U
#define PAU_FLOW_ERR_S 0
/** PAU_START : WT; bitpos: [3]; default: 0;
* backup start signal
*/
#define PAU_START (BIT(3))
#define PAU_START_M (PAU_START_V << PAU_START_S)
#define PAU_START_V 0x00000001U
#define PAU_START_S 3
/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM (BIT(4))
#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
#define PAU_TO_MEM_V 0x00000001U
#define PAU_TO_MEM_S 4
/** PAU_LINK_SEL : R/W; bitpos: [8:5]; default: 0;
* Link select
*/
#define PAU_LINK_SEL 0x0000000FU
#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
#define PAU_LINK_SEL_V 0x0000000FU
#define PAU_LINK_SEL_S 5
/** PAU_START_MAC : WT; bitpos: [9]; default: 0;
* mac sw backup start signal
*/
#define PAU_START_MAC (BIT(9))
#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
#define PAU_START_MAC_V 0x00000001U
#define PAU_START_MAC_S 9
/** PAU_TO_MEM_MAC : R/W; bitpos: [10]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM_MAC (BIT(10))
#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
#define PAU_TO_MEM_MAC_V 0x00000001U
#define PAU_TO_MEM_MAC_S 10
/** PAU_SEL_MAC : R/W; bitpos: [11]; default: 0;
* mac hw/sw select
*/
#define PAU_SEL_MAC (BIT(11))
#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
#define PAU_SEL_MAC_V 0x00000001U
#define PAU_SEL_MAC_S 11
/** PAU_REGDMA_CLK_CONF_REG register
* Clock control register
*/
#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
* clock enable
*/
#define PAU_CLK_EN (BIT(0))
#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
#define PAU_CLK_EN_V 0x00000001U
#define PAU_CLK_EN_S 0
/** PAU_REGDMA_ETM_CTRL_REG register
* ETM start ctrl reg
*/
#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
#define PAU_ETM_START_0 (BIT(0))
#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
#define PAU_ETM_START_0_V 0x00000001U
#define PAU_ETM_START_0_S 0
/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
#define PAU_ETM_START_1 (BIT(1))
#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
#define PAU_ETM_START_1_V 0x00000001U
#define PAU_ETM_START_1_S 1
/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
#define PAU_ETM_START_2 (BIT(2))
#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
#define PAU_ETM_START_2_V 0x00000001U
#define PAU_ETM_START_2_S 2
/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
#define PAU_ETM_START_3 (BIT(3))
#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
#define PAU_ETM_START_3_V 0x00000001U
#define PAU_ETM_START_3_S 3
/** PAU_ETM_LINK_SEL_0 : R/W; bitpos: [7:4]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_0 0x0000000FU
#define PAU_ETM_LINK_SEL_0_M (PAU_ETM_LINK_SEL_0_V << PAU_ETM_LINK_SEL_0_S)
#define PAU_ETM_LINK_SEL_0_V 0x0000000FU
#define PAU_ETM_LINK_SEL_0_S 4
/** PAU_ETM_LINK_SEL_1 : R/W; bitpos: [11:8]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_1 0x0000000FU
#define PAU_ETM_LINK_SEL_1_M (PAU_ETM_LINK_SEL_1_V << PAU_ETM_LINK_SEL_1_S)
#define PAU_ETM_LINK_SEL_1_V 0x0000000FU
#define PAU_ETM_LINK_SEL_1_S 8
/** PAU_ETM_LINK_SEL_2 : R/W; bitpos: [15:12]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_2 0x0000000FU
#define PAU_ETM_LINK_SEL_2_M (PAU_ETM_LINK_SEL_2_V << PAU_ETM_LINK_SEL_2_S)
#define PAU_ETM_LINK_SEL_2_V 0x0000000FU
#define PAU_ETM_LINK_SEL_2_S 12
/** PAU_ETM_LINK_SEL_3 : R/W; bitpos: [19:16]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_3 0x0000000FU
#define PAU_ETM_LINK_SEL_3_M (PAU_ETM_LINK_SEL_3_V << PAU_ETM_LINK_SEL_3_S)
#define PAU_ETM_LINK_SEL_3_V 0x0000000FU
#define PAU_ETM_LINK_SEL_3_S 16
/** PAU_ETM_BUSY_CAUSE : RO; bitpos: [23:20]; default: 0;
* debug
*/
#define PAU_ETM_BUSY_CAUSE 0x0000000FU
#define PAU_ETM_BUSY_CAUSE_M (PAU_ETM_BUSY_CAUSE_V << PAU_ETM_BUSY_CAUSE_S)
#define PAU_ETM_BUSY_CAUSE_V 0x0000000FU
#define PAU_ETM_BUSY_CAUSE_S 20
/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
* current link addr
*/
#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0xc)
/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_S 0
/** PAU_REGDMA_PERI_ADDR_REG register
* Backup addr
*/
#define PAU_REGDMA_PERI_ADDR_REG (DR_REG_PAU_BASE + 0x10)
/** PAU_PERI_ADDR : RO; bitpos: [31:0]; default: 0;
* peri addr reg
*/
#define PAU_PERI_ADDR 0xFFFFFFFFU
#define PAU_PERI_ADDR_M (PAU_PERI_ADDR_V << PAU_PERI_ADDR_S)
#define PAU_PERI_ADDR_V 0xFFFFFFFFU
#define PAU_PERI_ADDR_S 0
/** PAU_REGDMA_MEM_ADDR_REG register
* mem addr
*/
#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x14)
/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
#define PAU_MEM_ADDR 0xFFFFFFFFU
#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
#define PAU_MEM_ADDR_V 0xFFFFFFFFU
#define PAU_MEM_ADDR_S 0
/** PAU_INT_ENA_REG register
* Read only register for error and done
*/
#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x18)
/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ENA (BIT(0))
#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
#define PAU_DONE_INT_ENA_V 0x00000001U
#define PAU_DONE_INT_ENA_S 0
/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ENA (BIT(1))
#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
#define PAU_ERROR_INT_ENA_V 0x00000001U
#define PAU_ERROR_INT_ENA_S 1
/** PAU_INT_RAW_REG register
* Read only register for error and done
*/
#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x1c)
/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_RAW (BIT(0))
#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
#define PAU_DONE_INT_RAW_V 0x00000001U
#define PAU_DONE_INT_RAW_S 0
/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_RAW (BIT(1))
#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
#define PAU_ERROR_INT_RAW_V 0x00000001U
#define PAU_ERROR_INT_RAW_S 1
/** PAU_INT_CLR_REG register
* Read only register for error and done
*/
#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x20)
/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_CLR (BIT(0))
#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
#define PAU_DONE_INT_CLR_V 0x00000001U
#define PAU_DONE_INT_CLR_S 0
/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_CLR (BIT(1))
#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
#define PAU_ERROR_INT_CLR_V 0x00000001U
#define PAU_ERROR_INT_CLR_S 1
/** PAU_INT_ST_REG register
* Read only register for error and done
*/
#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x24)
/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ST (BIT(0))
#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
#define PAU_DONE_INT_ST_V 0x00000001U
#define PAU_DONE_INT_ST_S 0
/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ST (BIT(1))
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
#define PAU_ERROR_INT_ST_V 0x00000001U
#define PAU_ERROR_INT_ST_S 1
/** PAU_DATE_REG register
* Date register.
*/
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
/** PAU_DATE : R/W; bitpos: [27:0]; default: 36737360;
* REGDMA date information/ REGDMA version information.
*/
#define PAU_DATE 0x0FFFFFFFU
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
#define PAU_DATE_V 0x0FFFFFFFU
#define PAU_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
* Peri backup control register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
* backup start signal
*/
uint32_t start:1;
/** to_mem : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem:1;
/** link_sel : R/W; bitpos: [8:5]; default: 0;
* Link select
*/
uint32_t link_sel:4;
/** start_mac : WT; bitpos: [9]; default: 0;
* mac sw backup start signal
*/
uint32_t start_mac:1;
/** to_mem_mac : R/W; bitpos: [10]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem_mac:1;
/** sel_mac : R/W; bitpos: [11]; default: 0;
* mac hw/sw select
*/
uint32_t sel_mac:1;
uint32_t reserved_12:20;
};
uint32_t val;
} pau_regdma_conf_reg_t;
/** Type of regdma_clk_conf register
* Clock control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pau_regdma_clk_conf_reg_t;
/** Type of regdma_etm_ctrl register
* ETM start ctrl reg
*/
typedef union {
struct {
/** etm_start_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
uint32_t etm_start_0:1;
/** etm_start_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
uint32_t etm_start_1:1;
/** etm_start_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
uint32_t etm_start_2:1;
/** etm_start_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
uint32_t etm_start_3:1;
/** etm_link_sel_0 : R/W; bitpos: [7:4]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_0:4;
/** etm_link_sel_1 : R/W; bitpos: [11:8]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_1:4;
/** etm_link_sel_2 : R/W; bitpos: [15:12]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_2:4;
/** etm_link_sel_3 : R/W; bitpos: [19:16]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_3:4;
/** etm_busy_cause : RO; bitpos: [23:20]; default: 0;
* debug
*/
uint32_t etm_busy_cause:4;
uint32_t reserved_24:8;
};
uint32_t val;
} pau_regdma_etm_ctrl_reg_t;
/** Type of regdma_current_link_addr register
* current link addr
*/
typedef union {
struct {
/** current_link_addr : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
uint32_t current_link_addr:32;
};
uint32_t val;
} pau_regdma_current_link_addr_reg_t;
/** Type of regdma_peri_addr register
* Backup addr
*/
typedef union {
struct {
/** peri_addr : RO; bitpos: [31:0]; default: 0;
* peri addr reg
*/
uint32_t peri_addr:32;
};
uint32_t val;
} pau_regdma_peri_addr_reg_t;
/** Type of regdma_mem_addr register
* mem addr
*/
typedef union {
struct {
/** mem_addr : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
uint32_t mem_addr:32;
};
uint32_t val;
} pau_regdma_mem_addr_reg_t;
/** Type of int_ena register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_ena : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_ena:1;
/** error_int_ena : R/W; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_ena_reg_t;
/** Type of int_raw register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_raw:1;
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_raw_reg_t;
/** Type of int_clr register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_clr : WT; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_clr:1;
/** error_int_clr : WT; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_clr_reg_t;
/** Type of int_st register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_st : RO; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_st:1;
/** error_int_st : RO; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_st_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36737360;
* REGDMA date information/ REGDMA version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} pau_date_reg_t;
typedef struct {
volatile pau_regdma_conf_reg_t regdma_conf;
volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
volatile pau_regdma_peri_addr_reg_t regdma_peri_addr;
volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
volatile pau_int_ena_reg_t int_ena;
volatile pau_int_raw_reg_t int_raw;
volatile pau_int_clr_reg_t int_clr;
volatile pau_int_st_reg_t int_st;
uint32_t reserved_028[245];
volatile pau_date_reg_t date;
} pau_dev_t;
extern pau_dev_t PAU;
#ifndef __cplusplus
_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit n
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
* Configures the maximum threshold for the filter. Any pulses with width less than
* this will be ignored when the filter is enabled.
* Measurement unit: APB_CLK cycles.
*/
uint32_t filter_thres_un:10;
/** filter_en_un : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en_un:1;
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en_un:1;
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
* the high limit interrupt.
*/
uint32_t thr_h_lim_en_un:1;
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
* the low limit interrupt.
*/
uint32_t thr_l_lim_en_un:1;
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en_un:1;
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en_un:1;
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a negative edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch0_neg_mode_un:2;
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a positive edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch0_pos_mode_un:2;
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch0_hctrl_mode_un:2;
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch0_lctrl_mode_un:2;
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a negative edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch1_neg_mode_un:2;
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a positive edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch1_pos_mode_un:2;
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch1_hctrl_mode_un:2;
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch1_lctrl_mode_un:2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit n
*/
typedef union {
struct {
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thres0 value for unit n.
*/
uint32_t cnt_thres0_un:16;
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thres1 value for unit n.
*/
uint32_t cnt_thres1_un:16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit n
*/
typedef union {
struct {
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thr_h_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_h_lim_un:16;
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thr_l_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_l_lim_un:16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of u0_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 0.
*/
uint32_t cnt_h_step_u0:16;
/** cnt_l_step_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 0.
*/
uint32_t cnt_l_step_u0:16;
};
uint32_t val;
} pcnt_u0_conf3_reg_t;
/** Type of u1_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 1.
*/
uint32_t cnt_h_step_u1:16;
/** cnt_l_step_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 1.
*/
uint32_t cnt_l_step_u1:16;
};
uint32_t val;
} pcnt_u1_conf3_reg_t;
/** Type of u2_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 2.
*/
uint32_t cnt_h_step_u2:16;
/** cnt_l_step_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 2.
*/
uint32_t cnt_l_step_u2:16;
};
uint32_t val;
} pcnt_u2_conf3_reg_t;
/** Type of u3_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u3 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 3.
*/
uint32_t cnt_h_step_u3:16;
/** cnt_l_step_u3 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 3.
*/
uint32_t cnt_l_step_u3:16;
};
uint32_t val;
} pcnt_u3_conf3_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0:1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0:1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1:1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1:1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2:1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2:1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3:1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3:1;
/** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
* Configures this bit to enable unit 0's step comparator.
*/
uint32_t dalta_change_en_u0:1;
/** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
* Configures this bit to enable unit 1's step comparator.
*/
uint32_t dalta_change_en_u1:1;
/** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
* Configures this bit to enable unit 2's step comparator.
*/
uint32_t dalta_change_en_u2:1;
/** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
* Configures this bit to enable unit 3's step comparator.
*/
uint32_t dalta_change_en_u3:1;
uint32_t reserved_12:4;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit n
*/
typedef union {
struct {
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
* Represents the current pulse count value for unit n.
*/
uint32_t pulse_cnt_un:16;
uint32_t reserved_16:16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNITn status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
* Represents the pulse counter status of PCNT_Un corresponding to 0.
* 0: pulse counter decreases from positive to 0
* 1: pulse counter increases from negative to 0
* 2: pulse counter is negative
* 3: pulse counter is positive
*/
uint32_t cnt_thr_zero_mode_un:2;
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
* Represents the latched value of thres1 event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thres1 and thres1 event is valid
*/
uint32_t cnt_thr_thres1_lat_un:1;
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
* Represents the latched value of thres0 event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thres0 and thres0 event is valid
*/
uint32_t cnt_thr_thres0_lat_un:1;
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
* Represents the latched value of low limit event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thr_l_lim and low limit event is valid.
*/
uint32_t cnt_thr_l_lim_lat_un:1;
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
* Represents the latched value of high limit event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thr_h_lim and high limit event is valid.
*/
uint32_t cnt_thr_h_lim_lat_un:1;
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
* Represents the latched value of zero threshold event of PCNT_Un when threshold
* event interrupt is valid.
* 0: others
* 1: the current pulse counter equals to 0 and zero threshold event is valid.
*/
uint32_t cnt_thr_zero_lat_un:1;
/** cnt_thr_h_step_lat_un : RO; bitpos: [7]; default: 0;
* Represents the latched value of step counter event of PCNT_Un when step counter
* event interrupt is valid. 1: the current pulse counter decrement equals to
* reg_cnt_step and step counter event is valid. 0: others
*/
uint32_t cnt_thr_h_step_lat_un:1;
/** cnt_thr_l_step_lat_un : RO; bitpos: [8]; default: 0;
* Represents the latched value of step counter event of PCNT_Un when step counter
* event interrupt is valid. 1: the current pulse counter increment equals to
* reg_cnt_step and step counter event is valid. 0: others
*/
uint32_t cnt_thr_l_step_lat_un:1;
uint32_t reserved_9:23;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw:1;
/** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw:1;
/** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw:1;
/** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st:1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st:1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st:1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena:1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena:1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena:1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr:1;
/** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr:1;
/** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr:1;
/** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 37778192;
* Version control register.
*/
uint32_t date:32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_u0_conf3_reg_t u0_conf3;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_u1_conf3_reg_t u1_conf3;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_u2_conf3_reg_t u2_conf3;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
volatile pcnt_u3_conf3_reg_t u3_conf3;
volatile pcnt_un_cnt_reg_t un_cnt[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_ctrl_reg_t ctrl;
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: FIFO R/W registers */
/** Type of chndata register
* The read and write data register for CHANNELn by apb fifo access.
*/
typedef union {
struct {
/** chndata : HRO; bitpos: [31:0]; default: 0;
* Read and write data for channel n via APB FIFO.
*/
uint32_t chndata:32;
};
uint32_t val;
} rmt_chndata_reg_t;
/** Group: Configuration registers */
/** Type of chnconf0 register
* Channel n configure register 0
*/
typedef union {
struct {
/** tx_start_chn : WT; bitpos: [0]; default: 0;
* Set this bit to start sending data on CHANNELn.
*/
uint32_t tx_start_chn:1;
/** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
* Set this bit to reset read ram address for CHANNELn by accessing transmitter.
*/
uint32_t mem_rd_rst_chn:1;
/** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo.
*/
uint32_t apb_mem_rst_chn:1;
/** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
* Set this bit to restart transmission from the first data to the last data in
* CHANNELn.
*/
uint32_t tx_conti_mode_chn:1;
/** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
* This is the channel n enable bit for wraparound mode: it will resume sending at the
* start when the data to be sent is more than its memory size.
*/
uint32_t mem_tx_wrap_en_chn:1;
/** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
* This bit configures the level of output signal in CHANNELn when the latter is in
* IDLE state.
*/
uint32_t idle_out_lv_chn:1;
/** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
* This is the output enable-control bit for CHANNELn in IDLE state.
*/
uint32_t idle_out_en_chn:1;
/** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
* Set this bit to stop the transmitter of CHANNELn sending data out.
*/
uint32_t tx_stop_chn:1;
/** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
* This register is used to configure the divider for clock of CHANNELn.
*/
uint32_t div_cnt_chn:8;
/** mem_size_chn : R/W; bitpos: [18:16]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELn.
*/
uint32_t mem_size_chn:3;
uint32_t reserved_19:1;
/** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
* 1: Add carrier modulation on the output signal only at the send data state for
* CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn.
* Only valid when RMT_CARRIER_EN_CHn is 1.
*/
uint32_t carrier_eff_en_chn:1;
/** carrier_en_chn : R/W; bitpos: [21]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_chn:1;
/** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELn.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_chn:1;
uint32_t reserved_23:1;
/** conf_update_chn : WT; bitpos: [24]; default: 0;
* synchronization bit for CHANNELn
*/
uint32_t conf_update_chn:1;
uint32_t reserved_25:7;
};
uint32_t val;
} rmt_chnconf0_reg_t;
/** Type of chmconf0 register
* Channel m configure register 0
*/
typedef union {
struct {
/** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
* This register is used to configure the divider for clock of CHANNELm.
*/
uint32_t div_cnt_chm:8;
/** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
* When no edge is detected on the input signal and continuous clock cycles is longer
* than this register value, received process is finished.
*/
uint32_t idle_thres_chm:15;
/** mem_size_chm : R/W; bitpos: [25:23]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELm.
*/
uint32_t mem_size_chm:3;
uint32_t reserved_26:2;
/** carrier_en_chm : R/W; bitpos: [28]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_chm:1;
/** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELm.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_chm:1;
uint32_t reserved_30:2;
};
uint32_t val;
} rmt_chmconf0_reg_t;
/** Type of chmconf1 register
* Channel m configure register 1
*/
typedef union {
struct {
/** rx_en_chm : R/W; bitpos: [0]; default: 0;
* Set this bit to enable receiver to receive data on CHANNELm.
*/
uint32_t rx_en_chm:1;
/** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
* Set this bit to reset write ram address for CHANNELm by accessing receiver.
*/
uint32_t mem_wr_rst_chm:1;
/** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
*/
uint32_t apb_mem_rst_chm:1;
/** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
* This register marks the ownership of CHANNELm's ram block.
*
* 1'h1: Receiver is using the ram.
*
* 1'h0: APB bus is using the ram.
*/
uint32_t mem_owner_chm:1;
/** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
* This is the receive filter's enable bit for CHANNELm.
*/
uint32_t rx_filter_en_chm:1;
/** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
* Ignores the input pulse when its width is smaller than this register value in APB
* clock periods (in receive mode).
*/
uint32_t rx_filter_thres_chm:8;
/** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
* This is the channel m enable bit for wraparound mode: it will resume receiving at
* the start when the data to be received is more than its memory size.
*/
uint32_t mem_rx_wrap_en_chm:1;
uint32_t reserved_14:1;
/** conf_update_chm : WT; bitpos: [15]; default: 0;
* synchronization bit for CHANNELm
*/
uint32_t conf_update_chm:1;
uint32_t reserved_16:16;
};
uint32_t val;
} rmt_chmconf1_reg_t;
/** Type of sys_conf register
* RMT apb configuration register
*/
typedef union {
struct {
/** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
* 1'h1: access memory directly. 1'h0: access memory by FIFO.
*/
uint32_t apb_fifo_mask:1;
/** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
* Set this bit to enable the clock for RMT memory.
*/
uint32_t mem_clk_force_on:1;
/** rmt_mem_force_pd : R/W; bitpos: [2]; default: 0;
* Set this bit to power down RMT memory.
*/
uint32_t rmt_mem_force_pd:1;
/** rmt_mem_force_pu : R/W; bitpos: [3]; default: 0;
* 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
* when RMT is in light sleep mode.
*/
uint32_t rmt_mem_force_pu:1;
/** rmt_sclk_div_num : R/W; bitpos: [11:4]; default: 1;
* the integral part of the fractional divisor
*/
uint32_t rmt_sclk_div_num:8;
/** rmt_sclk_div_a : R/W; bitpos: [17:12]; default: 0;
* the numerator of the fractional part of the fractional divisor
*/
uint32_t rmt_sclk_div_a:6;
/** rmt_sclk_div_b : R/W; bitpos: [23:18]; default: 0;
* the denominator of the fractional part of the fractional divisor
*/
uint32_t rmt_sclk_div_b:6;
/** rmt_sclk_sel : R/W; bitpos: [25:24]; default: 1;
* choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL
*/
uint32_t rmt_sclk_sel:2;
/** rmt_sclk_active : R/W; bitpos: [26]; default: 1;
* rmt_sclk switch
*/
uint32_t rmt_sclk_active:1;
uint32_t reserved_27:4;
/** clk_en : R/W; bitpos: [31]; default: 0;
* RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
* Power down the drive clock of registers
*/
uint32_t clk_en:1;
};
uint32_t val;
} rmt_sys_conf_reg_t;
/** Type of ref_cnt_rst register
* RMT clock divider reset register
*/
typedef union {
struct {
/** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
* This register is used to reset the clock divider of CHANNEL0.
*/
uint32_t ref_cnt_rst_ch0:1;
/** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
* This register is used to reset the clock divider of CHANNEL1.
*/
uint32_t ref_cnt_rst_ch1:1;
/** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
* This register is used to reset the clock divider of CHANNEL2.
*/
uint32_t ref_cnt_rst_ch2:1;
/** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
* This register is used to reset the clock divider of CHANNEL3.
*/
uint32_t ref_cnt_rst_ch3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} rmt_ref_cnt_rst_reg_t;
/** Group: Status registers */
/** Type of chnstatus register
* Channel n status register
*/
typedef union {
struct {
/** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0;
* This register records the memory address offset when transmitter of CHANNELn is
* using the RAM.
*/
uint32_t mem_raddr_ex_chn:9;
/** state_chn : RO; bitpos: [11:9]; default: 0;
* This register records the FSM status of CHANNELn.
*/
uint32_t state_chn:3;
/** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0;
* This register records the memory address offset when writes RAM over APB bus.
*/
uint32_t apb_mem_waddr_chn:9;
/** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0;
* This status bit will be set if the offset address out of memory size when reading
* via APB bus.
*/
uint32_t apb_mem_rd_err_chn:1;
/** mem_empty_chn : RO; bitpos: [22]; default: 0;
* This status bit will be set when the data to be set is more than memory size and
* the wraparound mode is disabled.
*/
uint32_t mem_empty_chn:1;
/** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0;
* This status bit will be set if the offset address out of memory size when writes
* via APB bus.
*/
uint32_t apb_mem_wr_err_chn:1;
/** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0;
* This register records the memory address offset when reading RAM over APB bus.
*/
uint32_t apb_mem_raddr_chn:8;
};
uint32_t val;
} rmt_chnstatus_reg_t;
/** Type of chmstatus register
* Channel m status register
*/
typedef union {
struct {
/** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0;
* This register records the memory address offset when receiver of CHANNELm is using
* the RAM.
*/
uint32_t mem_waddr_ex_chm:9;
uint32_t reserved_9:3;
/** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0;
* This register records the memory address offset when reads RAM over APB bus.
*/
uint32_t apb_mem_raddr_chm:9;
uint32_t reserved_21:1;
/** state_chm : RO; bitpos: [24:22]; default: 0;
* This register records the FSM status of CHANNELm.
*/
uint32_t state_chm:3;
/** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
* This status bit will be set when the ownership of memory block is wrong.
*/
uint32_t mem_owner_err_chm:1;
/** mem_full_chm : RO; bitpos: [26]; default: 0;
* This status bit will be set if the receiver receives more data than the memory size.
*/
uint32_t mem_full_chm:1;
/** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
* This status bit will be set if the offset address out of memory size when reads via
* APB bus.
*/
uint32_t apb_mem_rd_err_chm:1;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_chmstatus_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmission done.
*/
uint32_t ch0_tx_end_int_raw:1;
/** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmission done.
*/
uint32_t ch1_tx_end_int_raw:1;
/** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when reception done.
*/
uint32_t ch2_rx_end_int_raw:1;
/** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when reception done.
*/
uint32_t ch3_rx_end_int_raw:1;
/** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch0_err_int_raw:1;
/** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch1_err_int_raw:1;
/** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch2_err_int_raw:1;
/** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch3_err_int_raw:1;
/** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch0_tx_thr_event_int_raw:1;
/** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch1_tx_thr_event_int_raw:1;
/** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch2_rx_thr_event_int_raw:1;
/** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch3_rx_thr_event_int_raw:1;
/** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch0_tx_loop_int_raw:1;
/** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch1_tx_loop_int_raw:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_raw_reg_t;
/** Type of int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_st:1;
/** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_st:1;
/** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_st:1;
/** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_st:1;
/** ch0_err_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_st:1;
/** ch1_err_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_st:1;
/** ch2_err_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_st:1;
/** ch3_err_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_st:1;
/** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
* The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_st:1;
/** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
* The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_st:1;
/** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0;
* The masked interrupt status bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_st:1;
/** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0;
* The masked interrupt status bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_st:1;
/** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
* The masked interrupt status bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_st:1;
/** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
* The masked interrupt status bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_st:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_ena:1;
/** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_ena:1;
/** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_ena:1;
/** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_ena:1;
/** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_ena:1;
/** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_ena:1;
/** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_ena:1;
/** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_ena:1;
/** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_ena:1;
/** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_ena:1;
/** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_ena:1;
/** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_ena:1;
/** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_ena:1;
/** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_ena:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear theCH0_TX_END_INT interrupt.
*/
uint32_t ch0_tx_end_int_clr:1;
/** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear theCH1_TX_END_INT interrupt.
*/
uint32_t ch1_tx_end_int_clr:1;
/** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear theCH2_RX_END_INT interrupt.
*/
uint32_t ch2_rx_end_int_clr:1;
/** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear theCH3_RX_END_INT interrupt.
*/
uint32_t ch3_rx_end_int_clr:1;
/** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch0_err_int_clr:1;
/** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch1_err_int_clr:1;
/** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch2_err_int_clr:1;
/** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch3_err_int_clr:1;
/** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch0_tx_thr_event_int_clr:1;
/** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch1_tx_thr_event_int_clr:1;
/** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch2_rx_thr_event_int_clr:1;
/** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch3_rx_thr_event_int_clr:1;
/** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear theCH0_TX_LOOP_INT interrupt.
*/
uint32_t ch0_tx_loop_int_clr:1;
/** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear theCH1_TX_LOOP_INT interrupt.
*/
uint32_t ch1_tx_loop_int_clr:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_clr_reg_t;
/** Group: Carrier wave duty cycle registers */
/** Type of chncarrier_duty register
* Channel n duty cycle configuration register
*/
typedef union {
struct {
/** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
* This register is used to configure carrier wave 's low level clock period for
* CHANNELn.
*/
uint32_t carrier_low_chn:16;
/** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
* This register is used to configure carrier wave 's high level clock period for
* CHANNELn.
*/
uint32_t carrier_high_chn:16;
};
uint32_t val;
} rmt_chncarrier_duty_reg_t;
/** Type of chm_rx_carrier_rm register
* Channel m carrier remove register
*/
typedef union {
struct {
/** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
* The low level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m.
*/
uint32_t carrier_low_thres_chm:16;
/** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
* The high level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.
*/
uint32_t carrier_high_thres_chm:16;
};
uint32_t val;
} rmt_chm_rx_carrier_rm_reg_t;
/** Group: Tx event configuration registers */
/** Type of chn_tx_lim register
* Channel n Tx event configuration register
*/
typedef union {
struct {
/** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELn can send out.
*/
uint32_t tx_lim_chn:9;
/** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
* This register is used to configure the maximum loop count when tx_conti_mode is
* valid.
*/
uint32_t tx_loop_num_chn:10;
/** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
* This register is the enabled bit for loop count.
*/
uint32_t tx_loop_cnt_en_chn:1;
/** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
* This register is used to reset the loop count when tx_conti_mode is valid.
*/
uint32_t loop_count_reset_chn:1;
/** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
* This bit is used to enable the loop send stop function after the loop counter
* counts to loop number for CHANNELn.
*/
uint32_t loop_stop_en_chn:1;
uint32_t reserved_22:10;
};
uint32_t val;
} rmt_chn_tx_lim_reg_t;
/** Type of tx_sim register
* RMT TX synchronous register
*/
typedef union {
struct {
/** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
* Set this bit to enable CHANNEL0 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch0:1;
/** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
* Set this bit to enable CHANNEL1 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch1:1;
/** tx_sim_en : R/W; bitpos: [2]; default: 0;
* This register is used to enable multiple of channels to start sending data
* synchronously.
*/
uint32_t tx_sim_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} rmt_tx_sim_reg_t;
/** Group: Rx event configuration registers */
/** Type of chm_rx_lim register
* Channel m Rx event configuration register
*/
typedef union {
struct {
/** rmt_rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELm can receive.
*/
uint32_t rmt_rx_lim_chm:9;
uint32_t reserved_9:23;
};
uint32_t val;
} rmt_chm_rx_lim_reg_t;
/** Group: Version register */
/** Type of date register
* RMT version register
*/
typedef union {
struct {
/** rmt_date : R/W; bitpos: [27:0]; default: 34636307;
* This is the version register.
*/
uint32_t rmt_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_date_reg_t;
typedef struct {
volatile rmt_chndata_reg_t chndata[4];
volatile rmt_chnconf0_reg_t chnconf0[2];
volatile rmt_chmconf0_reg_t ch2conf0;
volatile rmt_chmconf1_reg_t ch2conf1;
volatile rmt_chmconf0_reg_t ch3conf0;
volatile rmt_chmconf1_reg_t ch3conf1;
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;
volatile rmt_int_st_reg_t int_st;
volatile rmt_int_ena_reg_t int_ena;
volatile rmt_int_clr_reg_t int_clr;
volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2];
volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2];
volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2];
volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2];
volatile rmt_sys_conf_reg_t sys_conf;
volatile rmt_tx_sim_reg_t tx_sim;
volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
uint32_t reserved_074[22];
volatile rmt_date_reg_t date;
} rmt_dev_t;
extern rmt_dev_t RMT;
#ifndef __cplusplus
_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/rsa_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
* Represents M
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
* Represents Z
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM register
* Represents Y
*/
#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
#define RSA_Y_MEM_SIZE_BYTES 16
/** RSA_X_MEM register
* Represents X
*/
#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
#define RSA_X_MEM_SIZE_BYTES 16
/** RSA_M_PRIME_REG register
* Represents M’
*/
#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
* Represents M’
*/
#define RSA_M_PRIME 0xFFFFFFFFU
#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S)
#define RSA_M_PRIME_V 0xFFFFFFFFU
#define RSA_M_PRIME_S 0
/** RSA_MODE_REG register
* Configures RSA length
*/
#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
#define RSA_MODE 0x0000007FU
#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S)
#define RSA_MODE_V 0x0000007FU
#define RSA_MODE_S 0
/** RSA_QUERY_CLEAN_REG register
* RSA clean register
*/
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.
*
* 0: Not complete
*
* 1: Completed
*
*/
#define RSA_QUERY_CLEAN (BIT(0))
#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
#define RSA_QUERY_CLEAN_V 0x00000001U
#define RSA_QUERY_CLEAN_S 0
/** RSA_SET_START_MODEXP_REG register
* Starts modular exponentiation
*/
#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular exponentiation.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MODEXP (BIT(0))
#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
#define RSA_SET_START_MODEXP_V 0x00000001U
#define RSA_SET_START_MODEXP_S 0
/** RSA_SET_START_MODMULT_REG register
* Starts modular multiplication
*/
#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MODMULT (BIT(0))
#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
#define RSA_SET_START_MODMULT_V 0x00000001U
#define RSA_SET_START_MODMULT_S 0
/** RSA_SET_START_MULT_REG register
* Starts multiplication
*/
#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MULT (BIT(0))
#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
#define RSA_SET_START_MULT_V 0x00000001U
#define RSA_SET_START_MULT_S 0
/** RSA_QUERY_IDLE_REG register
* Represents the RSA status
*/
#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
* Represents the RSA status.
*
* 0: Busy
*
* 1: Idle
*
*/
#define RSA_QUERY_IDLE (BIT(0))
#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
#define RSA_QUERY_IDLE_V 0x00000001U
#define RSA_QUERY_IDLE_S 0
/** RSA_INT_CLR_REG register
* Clears RSA interrupt
*/
#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
#define RSA_CLEAR_INTERRUPT (BIT(0))
#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
#define RSA_CLEAR_INTERRUPT_V 0x00000001U
#define RSA_CLEAR_INTERRUPT_S 0
/** RSA_CONSTANT_TIME_REG register
* Configures the constant_time option
*/
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option.
*
* 0: Acceleration
*
* 1: No acceleration (default)
*
*/
#define RSA_CONSTANT_TIME (BIT(0))
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
#define RSA_CONSTANT_TIME_V 0x00000001U
#define RSA_CONSTANT_TIME_S 0
/** RSA_SEARCH_ENABLE_REG register
* Configures the search option
*/
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
* Configure the search option.
*
* 0: No acceleration (default)
*
* 1: Acceleration
*
* This option should be used together with RSA_SEARCH_POS.
*/
#define RSA_SEARCH_ENABLE (BIT(0))
#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
#define RSA_SEARCH_ENABLE_V 0x00000001U
#define RSA_SEARCH_ENABLE_S 0
/** RSA_SEARCH_POS_REG register
* Configures the search position
*/
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
#define RSA_SEARCH_POS 0x00000FFFU
#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
#define RSA_SEARCH_POS_V 0x00000FFFU
#define RSA_SEARCH_POS_S 0
/** RSA_INT_ENA_REG register
* Enables the RSA interrupt
*/
#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
#define RSA_INT_ENA (BIT(0))
#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S)
#define RSA_INT_ENA_V 0x00000001U
#define RSA_INT_ENA_S 0
/** RSA_DATE_REG register
* Version control register
*/
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
#define RSA_DATE 0x3FFFFFFFU
#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S)
#define RSA_DATE_V 0x3FFFFFFFU
#define RSA_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory */
/** Group: Control / Configuration Registers */
/** Type of m_prime register
* Represents M’
*/
typedef union {
struct {
/** m_prime : R/W; bitpos: [31:0]; default: 0;
* Represents M’
*/
uint32_t m_prime:32;
};
uint32_t val;
} rsa_m_prime_reg_t;
/** Type of mode register
* Configures RSA length
*/
typedef union {
struct {
/** mode : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
uint32_t mode:7;
uint32_t reserved_7:25;
};
uint32_t val;
} rsa_mode_reg_t;
/** Type of set_start_modexp register
* Starts modular exponentiation
*/
typedef union {
struct {
/** set_start_modexp : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular exponentiation.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_modexp:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modexp_reg_t;
/** Type of set_start_modmult register
* Starts modular multiplication
*/
typedef union {
struct {
/** set_start_modmult : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_modmult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modmult_reg_t;
/** Type of set_start_mult register
* Starts multiplication
*/
typedef union {
struct {
/** set_start_mult : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_mult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_mult_reg_t;
/** Type of query_idle register
* Represents the RSA status
*/
typedef union {
struct {
/** query_idle : RO; bitpos: [0]; default: 0;
* Represents the RSA status.
*
* 0: Busy
*
* 1: Idle
*
*/
uint32_t query_idle:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_idle_reg_t;
/** Type of constant_time register
* Configures the constant_time option
*/
typedef union {
struct {
/** constant_time : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option.
*
* 0: Acceleration
*
* 1: No acceleration (default)
*
*/
uint32_t constant_time:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_constant_time_reg_t;
/** Type of search_enable register
* Configures the search option
*/
typedef union {
struct {
/** search_enable : R/W; bitpos: [0]; default: 0;
* Configure the search option.
*
* 0: No acceleration (default)
*
* 1: Acceleration
*
* This option should be used together with RSA_SEARCH_POS.
*/
uint32_t search_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_search_enable_reg_t;
/** Type of search_pos register
* Configures the search position
*/
typedef union {
struct {
/** search_pos : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
uint32_t search_pos:12;
uint32_t reserved_12:20;
};
uint32_t val;
} rsa_search_pos_reg_t;
/** Group: Status Register */
/** Type of query_clean register
* RSA clean register
*/
typedef union {
struct {
/** query_clean : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.
*
* 0: Not complete
*
* 1: Completed
*
*/
uint32_t query_clean:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_clean_reg_t;
/** Group: Interrupt Registers */
/** Type of int_clr register
* Clears RSA interrupt
*/
typedef union {
struct {
/** clear_interrupt : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_clr_reg_t;
/** Type of int_ena register
* Enables the RSA interrupt
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_ena_reg_t;
/** Group: Version Control Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} rsa_date_reg_t;
typedef struct {
volatile uint32_t m[4];
uint32_t reserved_010[124];
volatile uint32_t z[4];
uint32_t reserved_210[124];
volatile uint32_t y[4];
uint32_t reserved_410[124];
volatile uint32_t x[4];
uint32_t reserved_610[124];
volatile rsa_m_prime_reg_t m_prime;
volatile rsa_mode_reg_t mode;
volatile rsa_query_clean_reg_t query_clean;
volatile rsa_set_start_modexp_reg_t set_start_modexp;
volatile rsa_set_start_modmult_reg_t set_start_modmult;
volatile rsa_set_start_mult_reg_t set_start_mult;
volatile rsa_query_idle_reg_t query_idle;
volatile rsa_int_clr_reg_t int_clr;
volatile rsa_constant_time_reg_t constant_time;
volatile rsa_search_enable_reg_t search_enable;
volatile rsa_search_pos_reg_t search_pos;
volatile rsa_int_ena_reg_t int_ena;
volatile rsa_date_reg_t date;
} rsa_dev_t;
extern rsa_dev_t RSA;
#ifndef __cplusplus
_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
* Initial configuration register.
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* Sha mode.
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x00000007U
#define SHA_MODE_S 0
/** SHA_DMA_BLOCK_NUM_REG register
* DMA configuration register 0.
*/
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
* Dma-sha block number.
*/
#define SHA_DMA_BLOCK_NUM 0x0000003FU
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
#define SHA_DMA_BLOCK_NUM_S 0
/** SHA_START_REG register
* Typical SHA configuration register 0.
*/
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
/** SHA_START : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
#define SHA_START 0x7FFFFFFFU
#define SHA_START_M (SHA_START_V << SHA_START_S)
#define SHA_START_V 0x7FFFFFFFU
#define SHA_START_S 1
/** SHA_CONTINUE_REG register
* Typical SHA configuration register 1.
*/
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
#define SHA_CONTINUE 0x7FFFFFFFU
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
#define SHA_CONTINUE_V 0x7FFFFFFFU
#define SHA_CONTINUE_S 1
/** SHA_BUSY_REG register
* Busy register.
*/
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Sha busy state. 1'b0: idle. 1'b1: busy.
*/
#define SHA_BUSY_STATE (BIT(0))
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
#define SHA_BUSY_STATE_V 0x00000001U
#define SHA_BUSY_STATE_S 0
/** SHA_DMA_START_REG register
* DMA configuration register 1.
*/
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
* Start dma-sha.
*/
#define SHA_DMA_START (BIT(0))
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
#define SHA_DMA_START_V 0x00000001U
#define SHA_DMA_START_S 0
/** SHA_DMA_CONTINUE_REG register
* DMA configuration register 2.
*/
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
* Continue dma-sha.
*/
#define SHA_DMA_CONTINUE (BIT(0))
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
#define SHA_DMA_CONTINUE_V 0x00000001U
#define SHA_DMA_CONTINUE_S 0
/** SHA_CLEAR_IRQ_REG register
* Interrupt clear register.
*/
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
* Clear sha interrupt.
*/
#define SHA_CLEAR_INTERRUPT (BIT(0))
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
#define SHA_CLEAR_INTERRUPT_V 0x00000001U
#define SHA_CLEAR_INTERRUPT_S 0
/** SHA_IRQ_ENA_REG register
* Interrupt enable register.
*/
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
*/
#define SHA_INTERRUPT_ENA (BIT(0))
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
#define SHA_INTERRUPT_ENA_V 0x00000001U
#define SHA_INTERRUPT_ENA_S 0
/** SHA_DATE_REG register
* Date register.
*/
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
* Sha date information/ sha version information.
*/
#define SHA_DATE 0x3FFFFFFFU
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
#define SHA_DATE_V 0x3FFFFFFFU
#define SHA_DATE_S 0
/** SHA_H_MEM register
* Sha H memory which contains intermediate hash or final hash.
*/
#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
#define SHA_H_MEM_SIZE_BYTES 64
/** SHA_M_MEM register
* Sha M memory which contains message.
*/
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
#define SHA_M_MEM_SIZE_BYTES 64
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of mode register
* Initial configuration register.
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Sha mode.
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} sha_mode_reg_t;
/** Type of dma_block_num register
* DMA configuration register 0.
*/
typedef union {
struct {
/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
* Dma-sha block number.
*/
uint32_t dma_block_num:6;
uint32_t reserved_6:26;
};
uint32_t val;
} sha_dma_block_num_reg_t;
/** Type of start register
* Typical SHA configuration register 0.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** start : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t start:31;
};
uint32_t val;
} sha_start_reg_t;
/** Type of continue register
* Typical SHA configuration register 1.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** continue : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t continue:31;
};
uint32_t val;
} sha_continue_reg_t;
/** Type of dma_start register
* DMA configuration register 1.
*/
typedef union {
struct {
/** dma_start : WO; bitpos: [0]; default: 0;
* Start dma-sha.
*/
uint32_t dma_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_start_reg_t;
/** Type of dma_continue register
* DMA configuration register 2.
*/
typedef union {
struct {
/** dma_continue : WO; bitpos: [0]; default: 0;
* Continue dma-sha.
*/
uint32_t dma_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_continue_reg_t;
/** Group: Status Register */
/** Type of busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Sha busy state. 1'b0: idle. 1'b1: busy.
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_busy_reg_t;
/** Group: Interrupt Register */
/** Type of clear_irq register
* Interrupt clear register.
*/
typedef union {
struct {
/** clear_interrupt : WO; bitpos: [0]; default: 0;
* Clear sha interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_clear_irq_reg_t;
/** Type of irq_ena register
* Interrupt enable register.
*/
typedef union {
struct {
/** interrupt_ena : R/W; bitpos: [0]; default: 0;
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
*/
uint32_t interrupt_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_irq_ena_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538972713;
* Sha date information/ sha version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} sha_date_reg_t;
/** Group: memory type */
typedef struct {
volatile sha_mode_reg_t mode;
uint32_t reserved_004[2];
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t continue;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;
volatile sha_clear_irq_reg_t clear_irq;
volatile sha_irq_ena_reg_t irq_ena;
volatile sha_date_reg_t date;
uint32_t reserved_030[4];
volatile uint32_t h[16];
volatile uint32_t m[16];
} sha_dev_t;
extern sha_dev_t SHA;
#ifndef __cplusplus
_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SYSTIMER_CONF_REG register
* Configure system timer clock
*/
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
* enable systimer's etm task and event
*/
#define SYSTIMER_ETM_EN (BIT(1))
#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
#define SYSTIMER_ETM_EN_V 0x00000001U
#define SYSTIMER_ETM_EN_S 1
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET2_WORK_EN_S 22
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET1_WORK_EN_S 23
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET0_WORK_EN_S 24
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
#define SYSTIMER_CLK_EN (BIT(31))
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
#define SYSTIMER_CLK_EN_V 0x00000001U
#define SYSTIMER_CLK_EN_S 31
/** SYSTIMER_UNIT0_OP_REG register
* system timer unit0 value update register
*/
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
/** SYSTIMER_UNIT1_OP_REG register
* system timer unit1 value update register
*/
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
/** SYSTIMER_UNIT0_LOAD_HI_REG register
* system timer unit0 value high load register
*/
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 20 bits
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
/** SYSTIMER_UNIT0_LOAD_LO_REG register
* system timer unit0 value low load register
*/
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bits
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
/** SYSTIMER_UNIT1_LOAD_HI_REG register
* system timer unit1 value high load register
*/
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit1 load high 20 bits
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
/** SYSTIMER_UNIT1_LOAD_LO_REG register
* system timer unit1 value low load register
*/
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit1 load low 32 bits
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
/** SYSTIMER_TARGET0_HI_REG register
* system timer comp0 value high register
*/
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET0_HI_S 0
/** SYSTIMER_TARGET0_LO_REG register
* system timer comp0 value low register
*/
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET0_LO_S 0
/** SYSTIMER_TARGET1_HI_REG register
* system timer comp1 value high register
*/
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget1 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET1_HI_S 0
/** SYSTIMER_TARGET1_LO_REG register
* system timer comp1 value low register
*/
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget1 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET1_LO_S 0
/** SYSTIMER_TARGET2_HI_REG register
* system timer comp2 value high register
*/
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget2 high 20 bits
*/
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET2_HI_S 0
/** SYSTIMER_TARGET2_LO_REG register
* system timer comp2 value low register
*/
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget2 low 32 bits
*/
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET2_LO_S 0
/** SYSTIMER_TARGET0_CONF_REG register
* system timer comp0 target mode register
*/
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target0 period
*/
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET0_PERIOD_S 0
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
*/
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
/** SYSTIMER_TARGET1_CONF_REG register
* system timer comp1 target mode register
*/
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target1 period
*/
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET1_PERIOD_S 0
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target1 to period mode
*/
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
/** SYSTIMER_TARGET2_CONF_REG register
* system timer comp2 target mode register
*/
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET2_PERIOD_S 0
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
/** SYSTIMER_UNIT0_VALUE_HI_REG register
* system timer unit0 value high register
*/
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
/** SYSTIMER_UNIT0_VALUE_LO_REG register
* system timer unit0 value low register
*/
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
/** SYSTIMER_UNIT1_VALUE_HI_REG register
* system timer unit1 value high register
*/
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
/** SYSTIMER_UNIT1_VALUE_LO_REG register
* system timer unit1 value low register
*/
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
/** SYSTIMER_COMP0_LOAD_REG register
* system timer comp0 conf sync register
*/
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
* timer comp0 sync enable signal
*/
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
/** SYSTIMER_COMP1_LOAD_REG register
* system timer comp1 conf sync register
*/
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
* timer comp1 sync enable signal
*/
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
/** SYSTIMER_COMP2_LOAD_REG register
* system timer comp2 conf sync register
*/
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
* timer comp2 sync enable signal
*/
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
/** SYSTIMER_UNIT0_LOAD_REG register
* system timer unit0 conf sync register
*/
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
* timer unit0 sync enable signal
*/
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
/** SYSTIMER_UNIT1_LOAD_REG register
* system timer unit1 conf sync register
*/
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
* timer unit1 sync enable signal
*/
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
/** SYSTIMER_INT_ENA_REG register
* systimer interrupt enable register
*/
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET0_INT_ENA_S 0
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET1_INT_ENA_S 1
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET2_INT_ENA_S 2
/** SYSTIMER_INT_RAW_REG register
* systimer interrupt raw register
*/
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET0_INT_RAW_S 0
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET1_INT_RAW_S 1
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET2_INT_RAW_S 2
/** SYSTIMER_INT_CLR_REG register
* systimer interrupt clear register
*/
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET0_INT_CLR_S 0
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET1_INT_CLR_S 1
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET2_INT_CLR_S 2
/** SYSTIMER_INT_ST_REG register
* systimer interrupt status register
*/
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
* interupt0 status
*/
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET0_INT_ST_S 0
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
* interupt1 status
*/
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET1_INT_ST_S 1
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
* interupt2 status
*/
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET2_INT_ST_S 2
/** SYSTIMER_REAL_TARGET0_LO_REG register
* system timer comp0 actual target value low register
*/
#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET0_LO_RO_S 0
/** SYSTIMER_REAL_TARGET0_HI_REG register
* system timer comp0 actual target value high register
*/
#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET0_HI_RO_S 0
/** SYSTIMER_REAL_TARGET1_LO_REG register
* system timer comp1 actual target value low register
*/
#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET1_LO_RO_S 0
/** SYSTIMER_REAL_TARGET1_HI_REG register
* system timer comp1 actual target value high register
*/
#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET1_HI_RO_S 0
/** SYSTIMER_REAL_TARGET2_LO_REG register
* system timer comp2 actual target value low register
*/
#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET2_LO_RO_S 0
/** SYSTIMER_REAL_TARGET2_HI_REG register
* system timer comp2 actual target value high register
*/
#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET2_HI_RO_S 0
/** SYSTIMER_DATE_REG register
* system timer version control register
*/
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
* systimer register version
*/
#define SYSTIMER_DATE 0xFFFFFFFFU
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
#define SYSTIMER_DATE_V 0xFFFFFFFFU
#define SYSTIMER_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/systimer_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
* Configure system timer clock
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** etm_en : R/W; bitpos: [1]; default: 0;
* enable systimer's etm task and event
*/
uint32_t etm_en:1;
uint32_t reserved_2:20;
/** target2_work_en : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
uint32_t target2_work_en:1;
/** target1_work_en : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
uint32_t target1_work_en:1;
/** target0_work_en : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
uint32_t target0_work_en:1;
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
uint32_t timer_unit1_core1_stall_en:1;
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
uint32_t timer_unit1_core0_stall_en:1;
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
uint32_t timer_unit0_core1_stall_en:1;
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
uint32_t timer_unit0_core0_stall_en:1;
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
uint32_t timer_unit1_work_en:1;
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
uint32_t timer_unit0_work_en:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
uint32_t clk_en:1;
};
uint32_t val;
} systimer_conf_reg_t;
/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */
/** Type of unit0_op register
* system timer unit0 value update register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
uint32_t timer_unit0_value_valid:1;
/** timer_unit0_update : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
uint32_t timer_unit0_update:1;
uint32_t reserved_31:1;
};
uint32_t val;
} systimer_unit0_op_reg_t;
/** Type of unit0_load_hi register
* system timer unit0 value high load register
*/
typedef union {
struct {
/** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 20 bits
*/
uint32_t timer_unit0_load_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit0_load_hi_reg_t;
/** Type of unit0_load_lo register
* system timer unit0 value low load register
*/
typedef union {
struct {
/** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bits
*/
uint32_t timer_unit0_load_lo:32;
};
uint32_t val;
} systimer_unit0_load_lo_reg_t;
/** Type of unit0_value_hi register
* system timer unit0 value high register
*/
typedef union {
struct {
/** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
uint32_t timer_unit0_value_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit0_value_hi_reg_t;
/** Type of unit0_value_lo register
* system timer unit0 value low register
*/
typedef union {
struct {
/** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
uint32_t timer_unit0_value_lo:32;
};
uint32_t val;
} systimer_unit0_value_lo_reg_t;
/** Type of unit0_load register
* system timer unit0 conf sync register
*/
typedef union {
struct {
/** timer_unit0_load : WT; bitpos: [0]; default: 0;
* timer unit0 sync enable signal
*/
uint32_t timer_unit0_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_unit0_load_reg_t;
/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */
/** Type of unit1_op register
* system timer unit1 value update register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
uint32_t timer_unit1_value_valid:1;
/** timer_unit1_update : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
uint32_t timer_unit1_update:1;
uint32_t reserved_31:1;
};
uint32_t val;
} systimer_unit1_op_reg_t;
/** Type of unit1_load_hi register
* system timer unit1 value high load register
*/
typedef union {
struct {
/** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0;
* timer unit1 load high 20 bits
*/
uint32_t timer_unit1_load_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit1_load_hi_reg_t;
/** Type of unit1_load_lo register
* system timer unit1 value low load register
*/
typedef union {
struct {
/** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit1 load low 32 bits
*/
uint32_t timer_unit1_load_lo:32;
};
uint32_t val;
} systimer_unit1_load_lo_reg_t;
/** Type of unit1_value_hi register
* system timer unit1 value high register
*/
typedef union {
struct {
/** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bits
*/
uint32_t timer_unit1_value_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit1_value_hi_reg_t;
/** Type of unit1_value_lo register
* system timer unit1 value low register
*/
typedef union {
struct {
/** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bits
*/
uint32_t timer_unit1_value_lo:32;
};
uint32_t val;
} systimer_unit1_value_lo_reg_t;
/** Type of unit1_load register
* system timer unit1 conf sync register
*/
typedef union {
struct {
/** timer_unit1_load : WT; bitpos: [0]; default: 0;
* timer unit1 sync enable signal
*/
uint32_t timer_unit1_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_unit1_load_reg_t;
/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */
/** Type of target0_hi register
* system timer comp0 value high register
*/
typedef union {
struct {
/** timer_target0_hi : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 20 bits
*/
uint32_t timer_target0_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_target0_hi_reg_t;
/** Type of target0_lo register
* system timer comp0 value low register
*/
typedef union {
struct {
/** timer_target0_lo : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bits
*/
uint32_t timer_target0_lo:32;
};
uint32_t val;
} systimer_target0_lo_reg_t;
/** Type of target0_conf register
* system timer comp0 target mode register
*/
typedef union {
struct {
/** target0_period : R/W; bitpos: [25:0]; default: 0;
* target0 period
*/
uint32_t target0_period:26;
uint32_t reserved_26:4;
/** target0_period_mode : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
*/
uint32_t target0_period_mode:1;
/** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target0_timer_unit_sel:1;
};
uint32_t val;
} systimer_target0_conf_reg_t;
/** Type of comp0_load register
* system timer comp0 conf sync register
*/
typedef union {
struct {
/** timer_comp0_load : WT; bitpos: [0]; default: 0;
* timer comp0 sync enable signal
*/
uint32_t timer_comp0_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp0_load_reg_t;
/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */
/** Type of target1_hi register
* system timer comp1 value high register
*/
typedef union {
struct {
/** timer_target1_hi : R/W; bitpos: [19:0]; default: 0;
* timer taget1 high 20 bits
*/
uint32_t timer_target1_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_target1_hi_reg_t;
/** Type of target1_lo register
* system timer comp1 value low register
*/
typedef union {
struct {
/** timer_target1_lo : R/W; bitpos: [31:0]; default: 0;
* timer taget1 low 32 bits
*/
uint32_t timer_target1_lo:32;
};
uint32_t val;
} systimer_target1_lo_reg_t;
/** Type of target1_conf register
* system timer comp1 target mode register
*/
typedef union {
struct {
/** target1_period : R/W; bitpos: [25:0]; default: 0;
* target1 period
*/
uint32_t target1_period:26;
uint32_t reserved_26:4;
/** target1_period_mode : R/W; bitpos: [30]; default: 0;
* Set target1 to period mode
*/
uint32_t target1_period_mode:1;
/** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target1_timer_unit_sel:1;
};
uint32_t val;
} systimer_target1_conf_reg_t;
/** Type of comp1_load register
* system timer comp1 conf sync register
*/
typedef union {
struct {
/** timer_comp1_load : WT; bitpos: [0]; default: 0;
* timer comp1 sync enable signal
*/
uint32_t timer_comp1_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp1_load_reg_t;
/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */
/** Type of target2_hi register
* system timer comp2 value high register
*/
typedef union {
struct {
/** timer_target2_hi : R/W; bitpos: [19:0]; default: 0;
* timer taget2 high 20 bits
*/
uint32_t timer_target2_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_target2_hi_reg_t;
/** Type of target2_lo register
* system timer comp2 value low register
*/
typedef union {
struct {
/** timer_target2_lo : R/W; bitpos: [31:0]; default: 0;
* timer taget2 low 32 bits
*/
uint32_t timer_target2_lo:32;
};
uint32_t val;
} systimer_target2_lo_reg_t;
/** Type of target2_conf register
* system timer comp2 target mode register
*/
typedef union {
struct {
/** target2_period : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
uint32_t target2_period:26;
uint32_t reserved_26:4;
/** target2_period_mode : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
uint32_t target2_period_mode:1;
/** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target2_timer_unit_sel:1;
};
uint32_t val;
} systimer_target2_conf_reg_t;
/** Type of comp2_load register
* system timer comp2 conf sync register
*/
typedef union {
struct {
/** timer_comp2_load : WT; bitpos: [0]; default: 0;
* timer comp2 sync enable signal
*/
uint32_t timer_comp2_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp2_load_reg_t;
/** Group: SYSTEM TIMER INTERRUPT REGISTER */
/** Type of int_ena register
* systimer interrupt enable register
*/
typedef union {
struct {
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
uint32_t target0_int_ena:1;
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
uint32_t target1_int_ena:1;
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
uint32_t target2_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_ena_reg_t;
/** Type of int_raw register
* systimer interrupt raw register
*/
typedef union {
struct {
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
uint32_t target0_int_raw:1;
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
uint32_t target1_int_raw:1;
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
uint32_t target2_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_raw_reg_t;
/** Type of int_clr register
* systimer interrupt clear register
*/
typedef union {
struct {
/** target0_int_clr : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
uint32_t target0_int_clr:1;
/** target1_int_clr : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
uint32_t target1_int_clr:1;
/** target2_int_clr : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
uint32_t target2_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_clr_reg_t;
/** Type of int_st register
* systimer interrupt status register
*/
typedef union {
struct {
/** target0_int_st : RO; bitpos: [0]; default: 0;
* interupt0 status
*/
uint32_t target0_int_st:1;
/** target1_int_st : RO; bitpos: [1]; default: 0;
* interupt1 status
*/
uint32_t target1_int_st:1;
/** target2_int_st : RO; bitpos: [2]; default: 0;
* interupt2 status
*/
uint32_t target2_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_st_reg_t;
/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */
/** Type of real_target0_lo register
* system timer comp0 actual target value low register
*/
typedef union {
struct {
/** target0_lo_ro : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
uint32_t target0_lo_ro:32;
};
uint32_t val;
} systimer_real_target0_lo_reg_t;
/** Type of real_target0_hi register
* system timer comp0 actual target value high register
*/
typedef union {
struct {
/** target0_hi_ro : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
uint32_t target0_hi_ro:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_real_target0_hi_reg_t;
/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */
/** Type of real_target1_lo register
* system timer comp1 actual target value low register
*/
typedef union {
struct {
/** target1_lo_ro : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
uint32_t target1_lo_ro:32;
};
uint32_t val;
} systimer_real_target1_lo_reg_t;
/** Type of real_target1_hi register
* system timer comp1 actual target value high register
*/
typedef union {
struct {
/** target1_hi_ro : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
uint32_t target1_hi_ro:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_real_target1_hi_reg_t;
/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */
/** Type of real_target2_lo register
* system timer comp2 actual target value low register
*/
typedef union {
struct {
/** target2_lo_ro : RO; bitpos: [31:0]; default: 0;
* actual target value value low 32bits
*/
uint32_t target2_lo_ro:32;
};
uint32_t val;
} systimer_real_target2_lo_reg_t;
/** Type of real_target2_hi register
* system timer comp2 actual target value high register
*/
typedef union {
struct {
/** target2_hi_ro : RO; bitpos: [19:0]; default: 0;
* actual target value value high 20bits
*/
uint32_t target2_hi_ro:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_real_target2_hi_reg_t;
/** Group: VERSION REGISTER */
/** Type of date register
* system timer version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 35655795;
* systimer register version
*/
uint32_t date:32;
};
uint32_t val;
} systimer_date_reg_t;
typedef struct {
volatile systimer_conf_reg_t conf;
volatile systimer_unit0_op_reg_t unit0_op;
volatile systimer_unit1_op_reg_t unit1_op;
volatile systimer_unit0_load_hi_reg_t unit0_load_hi;
volatile systimer_unit0_load_lo_reg_t unit0_load_lo;
volatile systimer_unit1_load_hi_reg_t unit1_load_hi;
volatile systimer_unit1_load_lo_reg_t unit1_load_lo;
volatile systimer_target0_hi_reg_t target0_hi;
volatile systimer_target0_lo_reg_t target0_lo;
volatile systimer_target1_hi_reg_t target1_hi;
volatile systimer_target1_lo_reg_t target1_lo;
volatile systimer_target2_hi_reg_t target2_hi;
volatile systimer_target2_lo_reg_t target2_lo;
volatile systimer_target0_conf_reg_t target0_conf;
volatile systimer_target1_conf_reg_t target1_conf;
volatile systimer_target2_conf_reg_t target2_conf;
volatile systimer_unit0_value_hi_reg_t unit0_value_hi;
volatile systimer_unit0_value_lo_reg_t unit0_value_lo;
volatile systimer_unit1_value_hi_reg_t unit1_value_hi;
volatile systimer_unit1_value_lo_reg_t unit1_value_lo;
volatile systimer_comp0_load_reg_t comp0_load;
volatile systimer_comp1_load_reg_t comp1_load;
volatile systimer_comp2_load_reg_t comp2_load;
volatile systimer_unit0_load_reg_t unit0_load;
volatile systimer_unit1_load_reg_t unit1_load;
volatile systimer_int_ena_reg_t int_ena;
volatile systimer_int_raw_reg_t int_raw;
volatile systimer_int_clr_reg_t int_clr;
volatile systimer_int_st_reg_t int_st;
volatile systimer_real_target0_lo_reg_t real_target0_lo;
volatile systimer_real_target0_hi_reg_t real_target0_hi;
volatile systimer_real_target1_lo_reg_t real_target1_lo;
volatile systimer_real_target1_hi_reg_t real_target1_hi;
volatile systimer_real_target2_lo_reg_t real_target2_lo;
volatile systimer_real_target2_hi_reg_t real_target2_hi;
uint32_t reserved_08c[28];
volatile systimer_date_reg_t date;
} systimer_dev_t;
extern systimer_dev_t SYSTIMER;
#ifndef __cplusplus
_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/tee_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_M0_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M0_MODE 0x00000003U
#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S)
#define TEE_M0_MODE_V 0x00000003U
#define TEE_M0_MODE_S 0
/** TEE_M1_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3;
* M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M1_MODE 0x00000003U
#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S)
#define TEE_M1_MODE_V 0x00000003U
#define TEE_M1_MODE_S 0
/** TEE_M2_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0;
* M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M2_MODE 0x00000003U
#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S)
#define TEE_M2_MODE_V 0x00000003U
#define TEE_M2_MODE_S 0
/** TEE_M3_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3;
* M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M3_MODE 0x00000003U
#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S)
#define TEE_M3_MODE_V 0x00000003U
#define TEE_M3_MODE_S 0
/** TEE_M4_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3;
* M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M4_MODE 0x00000003U
#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S)
#define TEE_M4_MODE_V 0x00000003U
#define TEE_M4_MODE_S 0
/** TEE_M5_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3;
* M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M5_MODE 0x00000003U
#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S)
#define TEE_M5_MODE_V 0x00000003U
#define TEE_M5_MODE_S 0
/** TEE_M6_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3;
* M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M6_MODE 0x00000003U
#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S)
#define TEE_M6_MODE_V 0x00000003U
#define TEE_M6_MODE_S 0
/** TEE_M7_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3;
* M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M7_MODE 0x00000003U
#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S)
#define TEE_M7_MODE_V 0x00000003U
#define TEE_M7_MODE_S 0
/** TEE_M8_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3;
* M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M8_MODE 0x00000003U
#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S)
#define TEE_M8_MODE_V 0x00000003U
#define TEE_M8_MODE_S 0
/** TEE_M9_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3;
* M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M9_MODE 0x00000003U
#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S)
#define TEE_M9_MODE_V 0x00000003U
#define TEE_M9_MODE_S 0
/** TEE_M10_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28)
/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3;
* M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M10_MODE 0x00000003U
#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S)
#define TEE_M10_MODE_V 0x00000003U
#define TEE_M10_MODE_S 0
/** TEE_M11_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c)
/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3;
* M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M11_MODE 0x00000003U
#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S)
#define TEE_M11_MODE_V 0x00000003U
#define TEE_M11_MODE_S 0
/** TEE_M12_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30)
/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3;
* M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M12_MODE 0x00000003U
#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S)
#define TEE_M12_MODE_V 0x00000003U
#define TEE_M12_MODE_S 0
/** TEE_M13_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34)
/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3;
* M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M13_MODE 0x00000003U
#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S)
#define TEE_M13_MODE_V 0x00000003U
#define TEE_M13_MODE_S 0
/** TEE_M14_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38)
/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3;
* M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M14_MODE 0x00000003U
#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S)
#define TEE_M14_MODE_V 0x00000003U
#define TEE_M14_MODE_S 0
/** TEE_M15_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c)
/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3;
* M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M15_MODE 0x00000003U
#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S)
#define TEE_M15_MODE_V 0x00000003U
#define TEE_M15_MODE_S 0
/** TEE_M16_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40)
/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3;
* M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M16_MODE 0x00000003U
#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S)
#define TEE_M16_MODE_V 0x00000003U
#define TEE_M16_MODE_S 0
/** TEE_M17_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44)
/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3;
* M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M17_MODE 0x00000003U
#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S)
#define TEE_M17_MODE_V 0x00000003U
#define TEE_M17_MODE_S 0
/** TEE_M18_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48)
/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3;
* M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M18_MODE 0x00000003U
#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S)
#define TEE_M18_MODE_V 0x00000003U
#define TEE_M18_MODE_S 0
/** TEE_M19_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c)
/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3;
* M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M19_MODE 0x00000003U
#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S)
#define TEE_M19_MODE_V 0x00000003U
#define TEE_M19_MODE_S 0
/** TEE_M20_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50)
/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3;
* M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M20_MODE 0x00000003U
#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S)
#define TEE_M20_MODE_V 0x00000003U
#define TEE_M20_MODE_S 0
/** TEE_M21_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54)
/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3;
* M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M21_MODE 0x00000003U
#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S)
#define TEE_M21_MODE_V 0x00000003U
#define TEE_M21_MODE_S 0
/** TEE_M22_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58)
/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3;
* M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M22_MODE 0x00000003U
#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S)
#define TEE_M22_MODE_V 0x00000003U
#define TEE_M22_MODE_S 0
/** TEE_M23_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c)
/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3;
* M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M23_MODE 0x00000003U
#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S)
#define TEE_M23_MODE_V 0x00000003U
#define TEE_M23_MODE_S 0
/** TEE_M24_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60)
/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3;
* M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M24_MODE 0x00000003U
#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S)
#define TEE_M24_MODE_V 0x00000003U
#define TEE_M24_MODE_S 0
/** TEE_M25_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64)
/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3;
* M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M25_MODE 0x00000003U
#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S)
#define TEE_M25_MODE_V 0x00000003U
#define TEE_M25_MODE_S 0
/** TEE_M26_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68)
/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3;
* M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M26_MODE 0x00000003U
#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S)
#define TEE_M26_MODE_V 0x00000003U
#define TEE_M26_MODE_S 0
/** TEE_M27_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c)
/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3;
* M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M27_MODE 0x00000003U
#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S)
#define TEE_M27_MODE_V 0x00000003U
#define TEE_M27_MODE_S 0
/** TEE_M28_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70)
/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3;
* M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M28_MODE 0x00000003U
#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S)
#define TEE_M28_MODE_V 0x00000003U
#define TEE_M28_MODE_S 0
/** TEE_M29_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74)
/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3;
* M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M29_MODE 0x00000003U
#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S)
#define TEE_M29_MODE_V 0x00000003U
#define TEE_M29_MODE_S 0
/** TEE_M30_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78)
/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3;
* M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M30_MODE 0x00000003U
#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S)
#define TEE_M30_MODE_V 0x00000003U
#define TEE_M30_MODE_S 0
/** TEE_M31_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c)
/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3;
* M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M31_MODE 0x00000003U
#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S)
#define TEE_M31_MODE_V 0x00000003U
#define TEE_M31_MODE_S 0
/** TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80)
/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define TEE_CLK_EN (BIT(0))
#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S)
#define TEE_CLK_EN_V 0x00000001U
#define TEE_CLK_EN_S 0
/** TEE_DATE_REG register
* Version register
*/
#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc)
/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706;
* reg_tee_date
*/
#define TEE_DATE_REG 0x0FFFFFFFU
#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S)
#define TEE_DATE_REG_V 0x0FFFFFFFU
#define TEE_DATE_REG_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/tee_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 0;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m0_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m0_mode_ctrl_reg_t;
/** Type of m1_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m1_mode : R/W; bitpos: [1:0]; default: 3;
* M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m1_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m1_mode_ctrl_reg_t;
/** Type of m2_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m2_mode : R/W; bitpos: [1:0]; default: 0;
* M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m2_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m2_mode_ctrl_reg_t;
/** Type of m3_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m3_mode : R/W; bitpos: [1:0]; default: 3;
* M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m3_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m3_mode_ctrl_reg_t;
/** Type of m4_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m4_mode : R/W; bitpos: [1:0]; default: 3;
* M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m4_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m4_mode_ctrl_reg_t;
/** Type of m5_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m5_mode : R/W; bitpos: [1:0]; default: 3;
* M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m5_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m5_mode_ctrl_reg_t;
/** Type of m6_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m6_mode : R/W; bitpos: [1:0]; default: 3;
* M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m6_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m6_mode_ctrl_reg_t;
/** Type of m7_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m7_mode : R/W; bitpos: [1:0]; default: 3;
* M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m7_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m7_mode_ctrl_reg_t;
/** Type of m8_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m8_mode : R/W; bitpos: [1:0]; default: 3;
* M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m8_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m8_mode_ctrl_reg_t;
/** Type of m9_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m9_mode : R/W; bitpos: [1:0]; default: 3;
* M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m9_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m9_mode_ctrl_reg_t;
/** Type of m10_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m10_mode : R/W; bitpos: [1:0]; default: 3;
* M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m10_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m10_mode_ctrl_reg_t;
/** Type of m11_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m11_mode : R/W; bitpos: [1:0]; default: 3;
* M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m11_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m11_mode_ctrl_reg_t;
/** Type of m12_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m12_mode : R/W; bitpos: [1:0]; default: 3;
* M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m12_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m12_mode_ctrl_reg_t;
/** Type of m13_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m13_mode : R/W; bitpos: [1:0]; default: 3;
* M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m13_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m13_mode_ctrl_reg_t;
/** Type of m14_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m14_mode : R/W; bitpos: [1:0]; default: 3;
* M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m14_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m14_mode_ctrl_reg_t;
/** Type of m15_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m15_mode : R/W; bitpos: [1:0]; default: 3;
* M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m15_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m15_mode_ctrl_reg_t;
/** Type of m16_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m16_mode : R/W; bitpos: [1:0]; default: 3;
* M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m16_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m16_mode_ctrl_reg_t;
/** Type of m17_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m17_mode : R/W; bitpos: [1:0]; default: 3;
* M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m17_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m17_mode_ctrl_reg_t;
/** Type of m18_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m18_mode : R/W; bitpos: [1:0]; default: 3;
* M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m18_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m18_mode_ctrl_reg_t;
/** Type of m19_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m19_mode : R/W; bitpos: [1:0]; default: 3;
* M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m19_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m19_mode_ctrl_reg_t;
/** Type of m20_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m20_mode : R/W; bitpos: [1:0]; default: 3;
* M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m20_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m20_mode_ctrl_reg_t;
/** Type of m21_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m21_mode : R/W; bitpos: [1:0]; default: 3;
* M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m21_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m21_mode_ctrl_reg_t;
/** Type of m22_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m22_mode : R/W; bitpos: [1:0]; default: 3;
* M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m22_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m22_mode_ctrl_reg_t;
/** Type of m23_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m23_mode : R/W; bitpos: [1:0]; default: 3;
* M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m23_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m23_mode_ctrl_reg_t;
/** Type of m24_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m24_mode : R/W; bitpos: [1:0]; default: 3;
* M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m24_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m24_mode_ctrl_reg_t;
/** Type of m25_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m25_mode : R/W; bitpos: [1:0]; default: 3;
* M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m25_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m25_mode_ctrl_reg_t;
/** Type of m26_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m26_mode : R/W; bitpos: [1:0]; default: 3;
* M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m26_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m26_mode_ctrl_reg_t;
/** Type of m27_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m27_mode : R/W; bitpos: [1:0]; default: 3;
* M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m27_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m27_mode_ctrl_reg_t;
/** Type of m28_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m28_mode : R/W; bitpos: [1:0]; default: 3;
* M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m28_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m28_mode_ctrl_reg_t;
/** Type of m29_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m29_mode : R/W; bitpos: [1:0]; default: 3;
* M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m29_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m29_mode_ctrl_reg_t;
/** Type of m30_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m30_mode : R/W; bitpos: [1:0]; default: 3;
* M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m30_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m30_mode_ctrl_reg_t;
/** Type of m31_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m31_mode : R/W; bitpos: [1:0]; default: 3;
* M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m31_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_m31_mode_ctrl_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date_reg : R/W; bitpos: [27:0]; default: 35672706;
* reg_tee_date
*/
uint32_t date_reg:28;
uint32_t reserved_28:4;
};
uint32_t val;
} tee_date_reg_t;
typedef struct {
volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;
volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl;
volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl;
volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl;
volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl;
volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl;
volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl;
volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl;
volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl;
volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl;
volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl;
volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl;
volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl;
volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl;
volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl;
volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl;
volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl;
volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl;
volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl;
volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl;
volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl;
volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl;
volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl;
volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl;
volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl;
volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl;
volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl;
volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl;
volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl;
volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl;
volatile tee_clock_gate_reg_t clock_gate;
uint32_t reserved_084[990];
volatile tee_date_reg_t date;
} tee_dev_t;
extern tee_dev_t TEE;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/timer_group_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
#define TIMG_T0_USE_XTAL_V 0x00000001U
#define TIMG_T0_USE_XTAL_S 9
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 0 's clock divider counter will be reset.
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 0 auto-reload at alarm is enabled.
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 0 time-base counter will increment every clock tick. When
* cleared, the timer 0 time-base counter will decrement.
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer 0 time-base counter is enabled.
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
#define TIMG_T0_EN_V 0x00000001U
#define TIMG_T0_EN_S 31
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
#define TIMG_T0_LO_V 0xFFFFFFFFU
#define TIMG_T0_LO_S 0
/** TIMG_T0HI_REG register
* Timer 0 current value, high 22 bits
*/
#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
#define TIMG_T0_HI_V 0x003FFFFFU
#define TIMG_T0_HI_S 0
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
#define TIMG_T0_UPDATE_V 0x00000001U
#define TIMG_T0_UPDATE_S 31
/** TIMG_T0ALARMLO_REG register
* Timer 0 alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_S 0
/** TIMG_T0ALARMHI_REG register
* Timer 0 alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
#define TIMG_T0_ALARM_HI_S 0
/** TIMG_T0LOADLO_REG register
* Timer 0 reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer 0 time-base
* Counter.
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_S 0
/** TIMG_T0LOADHI_REG register
* Timer 0 reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
#define TIMG_T0_LOAD_HI_S 0
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer 0 time-base counter reload.
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk, 1-xtal_clk.
*/
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
#define TIMG_WDT_USE_XTAL_V 0x00000001U
#define TIMG_WDT_USE_XTAL_S 21
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
#define TIMG_WDT_EN_V 0x00000001U
#define TIMG_WDT_EN_S 31
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_S 16
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_S 0
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_S 0
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_S 0
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_S 0
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
#define TIMG_WDT_FEED_S 0
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
#define TIMG_WDT_WKEY_S 0
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
*/
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
#define TIMG_RTC_CALI_START_V 0x00000001U
#define TIMG_RTC_CALI_START_S 31
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
*/
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_S 7
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
#define TIMG_WDT_INT_ENA_V 0x00000001U
#define TIMG_WDT_INT_ENA_S 1
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
#define TIMG_WDT_INT_RAW_V 0x00000001U
#define TIMG_WDT_INT_RAW_S 1
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
#define TIMG_WDT_INT_ST_V 0x00000001U
#define TIMG_WDT_INT_ST_S 1
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
#define TIMG_WDT_INT_CLR_V 0x00000001U
#define TIMG_WDT_INT_CLR_S 1
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35676274;
* Timer version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_S 0
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
* enable timer's etm task and event
*/
#define TIMG_ETM_EN (BIT(28))
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
#define TIMG_ETM_EN_V 0x00000001U
#define TIMG_ETM_EN_S 28
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
#define TIMG_CLK_EN_V 0x00000001U
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/timer_group_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
uint32_t tx_use_xtal:1;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* When set, Timer x 's clock divider counter will be reset.
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
* cleared, the timer x time-base counter will decrement.
*/
uint32_t tx_increase:1;
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
*/
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer x current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
*/
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer x alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer x alarm trigger time-base counter value, low 32 bits.
*/
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer x alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Timer x alarm trigger time-base counter value, high 22 bits.
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer x reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer x time-base
* Counter.
*/
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer x reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer x time-base
* counter.
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer x time-base counter reload.
*/
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
/** Group: WDT Control and configuration registers */
/** Type of wdtconfig0 register
* Watchdog timer configuration register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk, 1-xtal_clk.
*/
uint32_t wdt_use_xtal:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
/** Type of wdtconfig1 register
* Watchdog timer prescaler register
*/
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
/** Type of wdtconfig2 register
* Watchdog timer stage 0 timeout value
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
/** Type of wdtconfig3 register
* Watchdog timer stage 1 timeout value
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
/** Type of wdtconfig4 register
* Watchdog timer stage 2 timeout value
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
/** Type of wdtconfig5 register
* Watchdog timer stage 3 timeout value
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
/** Type of wdtfeed register
* Write to feed the watchdog timer
*/
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
/** Type of wdtwprotect register
* Watchdog write protect register
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* indicate one-shot frequency calculation is done.
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Configure the time to calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Set this bit to start one-shot frequency calculation.
*/
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* When one-shot or periodic frequency calculation is done, read this value to
* calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena_timers register
* Interrupt enable bits
*/
typedef union {
struct {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_ena:1;
/** wdt_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
/** Type of int_raw_timers register
* Raw interrupt status
*/
typedef union {
struct {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_raw:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
/** Type of int_st_timers register
* Masked interrupt status
*/
typedef union {
struct {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_st:1;
/** wdt_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_st_timers_reg_t;
/** Type of int_clr_timers register
* Interrupt clear bits
*/
typedef union {
struct {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_clr:1;
/** wdt_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
/** Group: Version register */
/** Type of ntimers_date register
* Timer version control register
*/
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35676274;
* Timer version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
/** Group: Clock configuration registers */
/** Type of regclk register
* Timer group clock gate register
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** etm_en : R/W; bitpos: [28]; default: 1;
* enable timer's etm task and event
*/
uint32_t etm_en:1;
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
uint32_t wdt_clk_is_active:1;
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
uint32_t timer_clk_is_active:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t t0config;
volatile timg_txlo_reg_t t0lo;
volatile timg_txhi_reg_t t0hi;
volatile timg_txupdate_reg_t t0update;
volatile timg_txalarmlo_reg_t t0alarmlo;
volatile timg_txalarmhi_reg_t t0alarmhi;
volatile timg_txloadlo_reg_t t0loadlo;
volatile timg_txloadhi_reg_t t0loadhi;
volatile timg_txload_reg_t t0load;
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;
volatile timg_wdtconfig3_reg_t wdtconfig3;
volatile timg_wdtconfig4_reg_t wdtconfig4;
volatile timg_wdtconfig5_reg_t wdtconfig5;
volatile timg_wdtfeed_reg_t wdtfeed;
volatile timg_wdtwprotect_reg_t wdtwprotect;
volatile timg_rtccalicfg_reg_t rtccalicfg;
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
volatile timg_int_ena_timers_reg_t int_ena_timers;
volatile timg_int_raw_timers_reg_t int_raw_timers;
volatile timg_int_st_timers_reg_t int_st_timers;
volatile timg_int_clr_timers_reg_t int_clr_timers;
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
uint32_t reserved_084[29];
volatile timg_ntimers_date_reg_t ntimers_date;
volatile timg_regclk_reg_t regclk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#ifndef __cplusplus
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TRACE_MEM_START_ADDR_REG register
* mem start addr
*/
#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
* The start address of trace memory
*/
#define TRACE_MEM_STAET_ADDR 0xFFFFFFFFU
#define TRACE_MEM_STAET_ADDR_M (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S)
#define TRACE_MEM_STAET_ADDR_V 0xFFFFFFFFU
#define TRACE_MEM_STAET_ADDR_S 0
/** TRACE_MEM_END_ADDR_REG register
* mem end addr
*/
#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
* The end address of trace memory
*/
#define TRACE_MEM_END_ADDR 0xFFFFFFFFU
#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU
#define TRACE_MEM_END_ADDR_S 0
/** TRACE_MEM_CURRENT_ADDR_REG register
* mem current addr
*/
#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* current_mem_addr,indicate that next writing addr
*/
#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define TRACE_MEM_CURRENT_ADDR_S 0
/** TRACE_MEM_ADDR_UPDATE_REG register
* mem addr update
*/
#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* when set this reg, the current_mem_addr will update to start_addr
*/
#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0))
#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U
#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0
/** TRACE_FIFO_STATUS_REG register
* fifo status register
*/
#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
* 1 indicate that fifo is empty
*/
#define TRACE_FIFO_EMPTY (BIT(0))
#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
#define TRACE_FIFO_EMPTY_V 0x00000001U
#define TRACE_FIFO_EMPTY_S 0
/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0;
* mem_full interrupt status
*/
#define TRACE_WORK_STATUS (BIT(1))
#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
#define TRACE_WORK_STATUS_V 0x00000001U
#define TRACE_WORK_STATUS_S 1
/** TRACE_INTR_ENA_REG register
* interrupt enable register
*/
#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
* Set 1 enable fifo_overflow interrupt
*/
#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0))
#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U
#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0
/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
* Set 1 enable mem_full interrupt
*/
#define TRACE_MEM_FULL_INTR_ENA (BIT(1))
#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U
#define TRACE_MEM_FULL_INTR_ENA_S 1
/** TRACE_INTR_RAW_REG register
* interrupt status register
*/
#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
* fifo_overflow interrupt status
*/
#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0))
#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U
#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0
/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
* mem_full interrupt status
*/
#define TRACE_MEM_FULL_INTR_RAW (BIT(1))
#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U
#define TRACE_MEM_FULL_INTR_RAW_S 1
/** TRACE_INTR_CLR_REG register
* interrupt clear register
*/
#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
* Set 1 clr fifo overflow interrupt
*/
#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0))
#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U
#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0
/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
* Set 1 clr mem full interrupt
*/
#define TRACE_MEM_FULL_INTR_CLR (BIT(1))
#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U
#define TRACE_MEM_FULL_INTR_CLR_S 1
/** TRACE_TRIGGER_REG register
* trigger register
*/
#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
* [0] set 1 start trace.
*/
#define TRACE_TRIGGER_ON (BIT(0))
#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
#define TRACE_TRIGGER_ON_V 0x00000001U
#define TRACE_TRIGGER_ON_S 0
/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
* set 1 stop trace.
*/
#define TRACE_TRIGGER_OFF (BIT(1))
#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
#define TRACE_TRIGGER_OFF_V 0x00000001U
#define TRACE_TRIGGER_OFF_S 1
/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
* if this reg is 1, trace will loop write trace_mem. If is 0, when mem_current_addr
* at mem_end_addr, it will stop at the mem_end_addr
*/
#define TRACE_MEM_LOOP (BIT(2))
#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
#define TRACE_MEM_LOOP_V 0x00000001U
#define TRACE_MEM_LOOP_S 2
/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
* enable encoder auto-restart, when lost package, the encoder will end, if enable
* auto-restart, when fifo empty, encoder will restart and send a sync package.
*/
#define TRACE_RESTART_ENA (BIT(3))
#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
#define TRACE_RESTART_ENA_V 0x00000001U
#define TRACE_RESTART_ENA_S 3
/** TRACE_RESYNC_PROLONGED_REG register
* resync configuration register
*/
#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
* count number, when count to this value, send a sync package
*/
#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU
#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU
#define TRACE_RESYNC_PROLONGED_S 0
/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0;
* resyc mode sel: 0: default, cycle count 1: package num count
*/
#define TRACE_RESYNC_MODE (BIT(24))
#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
#define TRACE_RESYNC_MODE_V 0x00000001U
#define TRACE_RESYNC_MODE_S 24
/** TRACE_CLOCK_GATE_REG register
* Clock gate control register
*/
#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28)
/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
* The bit is used to enable clock gate when access all registers in this module.
*/
#define TRACE_CLK_EN (BIT(0))
#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
#define TRACE_CLK_EN_V 0x00000001U
#define TRACE_CLK_EN_S 0
/** TRACE_DATE_REG register
* Version control register
*/
#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920;
* version control register. Note that this default value stored is the latest date
* when the hardware logic was updated.
*/
#define TRACE_DATE 0x0FFFFFFFU
#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S)
#define TRACE_DATE_V 0x0FFFFFFFU
#define TRACE_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Trace memory configuration registers */
/** Type of mem_start_addr register
* mem start addr
*/
typedef union {
struct {
/** mem_staet_addr : R/W; bitpos: [31:0]; default: 0;
* The start address of trace memory
*/
uint32_t mem_staet_addr:32;
};
uint32_t val;
} trace_mem_start_addr_reg_t;
/** Type of mem_end_addr register
* mem end addr
*/
typedef union {
struct {
/** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
* The end address of trace memory
*/
uint32_t mem_end_addr:32;
};
uint32_t val;
} trace_mem_end_addr_reg_t;
/** Type of mem_current_addr register
* mem current addr
*/
typedef union {
struct {
/** mem_current_addr : RO; bitpos: [31:0]; default: 0;
* current_mem_addr,indicate that next writing addr
*/
uint32_t mem_current_addr:32;
};
uint32_t val;
} trace_mem_current_addr_reg_t;
/** Type of mem_addr_update register
* mem addr update
*/
typedef union {
struct {
/** mem_current_addr_update : WT; bitpos: [0]; default: 0;
* when set this reg, the current_mem_addr will update to start_addr
*/
uint32_t mem_current_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} trace_mem_addr_update_reg_t;
/** Group: Trace fifo status register */
/** Type of fifo_status register
* fifo status register
*/
typedef union {
struct {
/** fifo_empty : RO; bitpos: [0]; default: 1;
* 1 indicate that fifo is empty
*/
uint32_t fifo_empty:1;
/** work_status : RO; bitpos: [1]; default: 0;
* mem_full interrupt status
*/
uint32_t work_status:1;
uint32_t reserved_2:30;
};
uint32_t val;
} trace_fifo_status_reg_t;
/** Group: Trace interrupt configuration registers */
/** Type of intr_ena register
* interrupt enable register
*/
typedef union {
struct {
/** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
* Set 1 enable fifo_overflow interrupt
*/
uint32_t fifo_overflow_intr_ena:1;
/** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
* Set 1 enable mem_full interrupt
*/
uint32_t mem_full_intr_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} trace_intr_ena_reg_t;
/** Type of intr_raw register
* interrupt status register
*/
typedef union {
struct {
/** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
* fifo_overflow interrupt status
*/
uint32_t fifo_overflow_intr_raw:1;
/** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
* mem_full interrupt status
*/
uint32_t mem_full_intr_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} trace_intr_raw_reg_t;
/** Type of intr_clr register
* interrupt clear register
*/
typedef union {
struct {
/** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
* Set 1 clr fifo overflow interrupt
*/
uint32_t fifo_overflow_intr_clr:1;
/** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
* Set 1 clr mem full interrupt
*/
uint32_t mem_full_intr_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} trace_intr_clr_reg_t;
/** Group: Trace configuration register */
/** Type of trigger register
* trigger register
*/
typedef union {
struct {
/** trigger_on : WT; bitpos: [0]; default: 0;
* [0] set 1 start trace.
*/
uint32_t trigger_on:1;
/** trigger_off : WT; bitpos: [1]; default: 0;
* set 1 stop trace.
*/
uint32_t trigger_off:1;
/** mem_loop : R/W; bitpos: [2]; default: 1;
* if this reg is 1, trace will loop write trace_mem. If is 0, when mem_current_addr
* at mem_end_addr, it will stop at the mem_end_addr
*/
uint32_t mem_loop:1;
/** restart_ena : R/W; bitpos: [3]; default: 1;
* enable encoder auto-restart, when lost package, the encoder will end, if enable
* auto-restart, when fifo empty, encoder will restart and send a sync package.
*/
uint32_t restart_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} trace_trigger_reg_t;
/** Type of resync_prolonged register
* resync configuration register
*/
typedef union {
struct {
/** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
* count number, when count to this value, send a sync package
*/
uint32_t resync_prolonged:24;
/** resync_mode : R/W; bitpos: [24]; default: 0;
* resyc mode sel: 0: default, cycle count 1: package num count
*/
uint32_t resync_mode:1;
uint32_t reserved_25:7;
};
uint32_t val;
} trace_resync_prolonged_reg_t;
/** Group: Clock Gate Control and configuration register */
/** Type of clock_gate register
* Clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* The bit is used to enable clock gate when access all registers in this module.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} trace_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35663920;
* version control register. Note that this default value stored is the latest date
* when the hardware logic was updated.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} trace_date_reg_t;
typedef struct {
volatile trace_mem_start_addr_reg_t mem_start_addr;
volatile trace_mem_end_addr_reg_t mem_end_addr;
volatile trace_mem_current_addr_reg_t mem_current_addr;
volatile trace_mem_addr_update_reg_t mem_addr_update;
volatile trace_fifo_status_reg_t fifo_status;
volatile trace_intr_ena_reg_t intr_ena;
volatile trace_intr_raw_reg_t intr_raw;
volatile trace_intr_clr_reg_t intr_clr;
volatile trace_trigger_reg_t trigger;
volatile trace_resync_prolonged_reg_t resync_prolonged;
volatile trace_clock_gate_reg_t clock_gate;
uint32_t reserved_02c[244];
volatile trace_date_reg_t date;
} trace_dev_t;
extern trace_dev_t TRACE;
#ifndef __cplusplus
_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TWAI_MODE_REG register
* TWAI mode register.
*/
#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0)
/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
* 1: reset, detection of a set reset mode bit results in aborting the current
* transmission/reception of a message and entering the reset mode. 0: normal, on the
* '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
* operating mode.
*/
#define TWAI_RESET_MODE (BIT(0))
#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S)
#define TWAI_RESET_MODE_V 0x00000001U
#define TWAI_RESET_MODE_S 0
/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
* 1: listen only, in this mode the TWAI controller would give no acknowledge to the
* TWAI-bus, even if a message is received successfully. The error counters are
* stopped at the current value. 0: normal.
*/
#define TWAI_LISTEN_ONLY_MODE (BIT(1))
#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S)
#define TWAI_LISTEN_ONLY_MODE_V 0x00000001U
#define TWAI_LISTEN_ONLY_MODE_S 1
/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
* 1: self test, in this mode a full node test is possible without any other active
* node on the bus using the self reception request command. The TWAI controller will
* perform a successful transmission, even if there is no acknowledge received. 0:
* normal, an acknowledge is required for successful transmission.
*/
#define TWAI_SELF_TEST_MODE (BIT(2))
#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S)
#define TWAI_SELF_TEST_MODE_V 0x00000001U
#define TWAI_SELF_TEST_MODE_S 2
/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0;
* 1:single, the single acceptance filter option is enabled (one filter with the
* length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
* (two filters, each with the length of 16 bit are active).
*/
#define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3))
#define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S)
#define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U
#define TWAI_ACCEPTANCE_FILTER_MODE_S 3
/** TWAI_CMD_REG register
* TWAI command register.
*/
#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4)
/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
* 1: present, a message shall be transmitted. 0: absent
*/
#define TWAI_TX_REQUEST (BIT(0))
#define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S)
#define TWAI_TX_REQUEST_V 0x00000001U
#define TWAI_TX_REQUEST_S 0
/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0;
* 1: present, if not already in progress, a pending transmission request is
* cancelled. 0: absent
*/
#define TWAI_ABORT_TX (BIT(1))
#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S)
#define TWAI_ABORT_TX_V 0x00000001U
#define TWAI_ABORT_TX_S 1
/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0;
* 1: released, the receive buffer, representing the message memory space in the
* RXFIFO is released. 0: no action
*/
#define TWAI_RELEASE_BUFFER (BIT(2))
#define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S)
#define TWAI_RELEASE_BUFFER_V 0x00000001U
#define TWAI_RELEASE_BUFFER_S 2
/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0;
* 1: clear, the data overrun status bit is cleared. 0: no action.
*/
#define TWAI_CLEAR_DATA_OVERRUN (BIT(3))
#define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S)
#define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U
#define TWAI_CLEAR_DATA_OVERRUN_S 3
/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0;
* 1: present, a message shall be transmitted and received simultaneously. 0: absent.
*/
#define TWAI_SELF_RX_REQUEST (BIT(4))
#define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S)
#define TWAI_SELF_RX_REQUEST_V 0x00000001U
#define TWAI_SELF_RX_REQUEST_S 4
/** TWAI_STATUS_REG register
* TWAI status register.
*/
#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8)
/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
* 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
* message is available
*/
#define TWAI_STATUS_RECEIVE_BUFFER (BIT(0))
#define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S)
#define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U
#define TWAI_STATUS_RECEIVE_BUFFER_S 0
/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0;
* 1: overrun, a message was lost because there was not enough space for that message
* in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
* overrun command was given
*/
#define TWAI_STATUS_OVERRUN (BIT(1))
#define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S)
#define TWAI_STATUS_OVERRUN_V 0x00000001U
#define TWAI_STATUS_OVERRUN_S 1
/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0;
* 1: released, the CPU may write a message into the transmit buffer. 0: locked, the
* CPU cannot access the transmit buffer, a message is either waiting for transmission
* or is in the process of being transmitted
*/
#define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2))
#define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S)
#define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U
#define TWAI_STATUS_TRANSMIT_BUFFER_S 2
/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0;
* 1: complete, last requested transmission has been successfully completed. 0:
* incomplete, previously requested transmission is not yet completed
*/
#define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3))
#define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S)
#define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U
#define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3
/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0;
* 1: receive, the TWAI controller is receiving a message. 0: idle
*/
#define TWAI_STATUS_RECEIVE (BIT(4))
#define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S)
#define TWAI_STATUS_RECEIVE_V 0x00000001U
#define TWAI_STATUS_RECEIVE_S 4
/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0;
* 1: transmit, the TWAI controller is transmitting a message. 0: idle
*/
#define TWAI_STATUS_TRANSMIT (BIT(5))
#define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S)
#define TWAI_STATUS_TRANSMIT_V 0x00000001U
#define TWAI_STATUS_TRANSMIT_S 5
/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0;
* 1: error, at least one of the error counters has reached or exceeded the CPU
* warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
* counters are below the warning limit
*/
#define TWAI_STATUS_ERR (BIT(6))
#define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S)
#define TWAI_STATUS_ERR_V 0x00000001U
#define TWAI_STATUS_ERR_S 6
/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0;
* 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
* TWAI controller is involved in bus activities
*/
#define TWAI_STATUS_NODE_BUS_OFF (BIT(7))
#define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S)
#define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U
#define TWAI_STATUS_NODE_BUS_OFF_S 7
/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0;
* 1: current message is destroyed because of FIFO overflow.
*/
#define TWAI_STATUS_MISS (BIT(8))
#define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S)
#define TWAI_STATUS_MISS_V 0x00000001U
#define TWAI_STATUS_MISS_S 8
/** TWAI_INTERRUPT_REG register
* Interrupt signals' register.
*/
#define TWAI_INTERRUPT_REG (DR_REG_TWAI_BASE + 0xc)
/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
* 1: this bit is set while the receive FIFO is not empty and the RIE bit is set
* within the interrupt enable register. 0: reset
*/
#define TWAI_RECEIVE_INT_ST (BIT(0))
#define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S)
#define TWAI_RECEIVE_INT_ST_V 0x00000001U
#define TWAI_RECEIVE_INT_ST_S 0
/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0;
* 1: this bit is set whenever the transmit buffer status changes from '0-to-1'
* (released) and the TIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_TRANSMIT_INT_ST (BIT(1))
#define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S)
#define TWAI_TRANSMIT_INT_ST_V 0x00000001U
#define TWAI_TRANSMIT_INT_ST_S 1
/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
* 1: this bit is set on every change (set and clear) of either the error status or
* bus status bits and the EIE bit is set within the interrupt enable register. 0:
* reset
*/
#define TWAI_ERR_WARNING_INT_ST (BIT(2))
#define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S)
#define TWAI_ERR_WARNING_INT_ST_V 0x00000001U
#define TWAI_ERR_WARNING_INT_ST_S 2
/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
* 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
* DOIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_DATA_OVERRUN_INT_ST (BIT(3))
#define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S)
#define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U
#define TWAI_DATA_OVERRUN_INT_ST_S 3
/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0;
* 1: this bit is set whenever the TWAI controller has reached the error passive
* status (at least one error counter exceeds the protocol-defined level of 127) or if
* the TWAI controller is in the error passive status and enters the error active
* status again and the EPIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_ERR_PASSIVE_INT_ST (BIT(5))
#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S)
#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U
#define TWAI_ERR_PASSIVE_INT_ST_S 5
/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0;
* 1: this bit is set when the TWAI controller lost the arbitration and becomes a
* receiver and the ALIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_ARBITRATION_LOST_INT_ST (BIT(6))
#define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S)
#define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U
#define TWAI_ARBITRATION_LOST_INT_ST_S 6
/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0;
* 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
* the BEIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_BUS_ERR_INT_ST (BIT(7))
#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S)
#define TWAI_BUS_ERR_INT_ST_V 0x00000001U
#define TWAI_BUS_ERR_INT_ST_S 7
/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0;
* 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
* this interrupt enable bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_IDLE_INT_ST (BIT(8))
#define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S)
#define TWAI_IDLE_INT_ST_V 0x00000001U
#define TWAI_IDLE_INT_ST_S 8
/** TWAI_INTERRUPT_ENABLE_REG register
* Interrupt enable register.
*/
#define TWAI_INTERRUPT_ENABLE_REG (DR_REG_TWAI_BASE + 0x10)
/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
* 1: enabled, when the receive buffer status is 'full' the TWAI controller requests
* the respective interrupt. 0: disable
*/
#define TWAI_EXT_RECEIVE_INT_ENA (BIT(0))
#define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S)
#define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U
#define TWAI_EXT_RECEIVE_INT_ENA_S 0
/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
* 1: enabled, when a message has been successfully transmitted or the transmit buffer
* is accessible again (e.g. after an abort transmission command), the TWAI controller
* requests the respective interrupt. 0: disable
*/
#define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1))
#define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S)
#define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U
#define TWAI_EXT_TRANSMIT_INT_ENA_S 1
/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
* 1: enabled, if the error or bus status change (see status register. Table 14), the
* TWAI controllerrequests the respective interrupt. 0: disable
*/
#define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2))
#define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S)
#define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U
#define TWAI_EXT_ERR_WARNING_INT_ENA_S 2
/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
* 1: enabled, if the data overrun status bit is set (see status register. Table 14),
* the TWAI controllerrequests the respective interrupt. 0: disable
*/
#define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3))
#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S)
#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U
#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3
/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0;
* 1: enabled, if the error status of the TWAI controller changes from error active to
* error passive or vice versa, the respective interrupt is requested. 0: disable
*/
#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5))
#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S)
#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U
#define TWAI_ERR_PASSIVE_INT_ENA_S 5
/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
* 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
* is requested. 0: disable
*/
#define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6))
#define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S)
#define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U
#define TWAI_ARBITRATION_LOST_INT_ENA_S 6
/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
* 1: enabled, if an bus error has been detected, the TWAI controller requests the
* respective interrupt. 0: disable
*/
#define TWAI_BUS_ERR_INT_ENA (BIT(7))
#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S)
#define TWAI_BUS_ERR_INT_ENA_V 0x00000001U
#define TWAI_BUS_ERR_INT_ENA_S 7
/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0;
* 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
* respective interrupt. 0: disable
*/
#define TWAI_IDLE_INT_ENA (BIT(8))
#define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S)
#define TWAI_IDLE_INT_ENA_V 0x00000001U
#define TWAI_IDLE_INT_ENA_S 8
/** TWAI_BUS_TIMING_0_REG register
* Bit timing configuration register 0.
*/
#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18)
/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
* The period of the TWAI system clock is programmable and determines the individual
* bit timing. Software has R/W permission in reset mode and RO permission in
* operation mode.
*/
#define TWAI_BAUD_PRESC 0x00003FFFU
#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S)
#define TWAI_BAUD_PRESC_V 0x00003FFFU
#define TWAI_BAUD_PRESC_S 0
/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0;
* The synchronization jump width defines the maximum number of clock cycles a bit
* period may be shortened or lengthened. Software has R/W permission in reset mode
* and RO in operation mode.
*/
#define TWAI_SYNC_JUMP_WIDTH 0x00000003U
#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S)
#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U
#define TWAI_SYNC_JUMP_WIDTH_S 14
/** TWAI_BUS_TIMING_1_REG register
* Bit timing configuration register 1.
*/
#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c)
/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
* The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
#define TWAI_TIME_SEGMENT1 0x0000000FU
#define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S)
#define TWAI_TIME_SEGMENT1_V 0x0000000FU
#define TWAI_TIME_SEGMENT1_S 0
/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0;
* The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
#define TWAI_TIME_SEGMENT2 0x00000007U
#define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S)
#define TWAI_TIME_SEGMENT2_V 0x00000007U
#define TWAI_TIME_SEGMENT2_S 4
/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0;
* 1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
* Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_TIME_SAMPLING (BIT(7))
#define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S)
#define TWAI_TIME_SAMPLING_V 0x00000001U
#define TWAI_TIME_SAMPLING_S 7
/** TWAI_ARB_LOST_CAP_REG register
* TWAI arbiter lost capture register.
*/
#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c)
/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
* This register contains information about the bit position of losing arbitration.
*/
#define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU
#define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S)
#define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU
#define TWAI_ARBITRATION_LOST_CAPTURE_S 0
/** TWAI_ERR_CODE_CAP_REG register
* TWAI error info capture register.
*/
#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30)
/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
* This register contains information about the location of errors on the bus.
*/
#define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU
#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S)
#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU
#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0
/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0;
* 1: RX, error occurred during reception. 0: TX, error occurred during transmission.
*/
#define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5))
#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S)
#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U
#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5
/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0;
* 00: bit error. 01: form error. 10:stuff error. 11:other type of error.
*/
#define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U
#define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S)
#define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U
#define TWAI_ERR_CAPTURE_CODE_TYPE_S 6
/** TWAI_ERR_WARNING_LIMIT_REG register
* TWAI error threshold configuration register.
*/
#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34)
/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
* The threshold that trigger error warning interrupt when this interrupt is enabled.
* Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_ERR_WARNING_LIMIT 0x000000FFU
#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S)
#define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU
#define TWAI_ERR_WARNING_LIMIT_S 0
/** TWAI_RX_ERR_CNT_REG register
* Rx error counter register.
*/
#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38)
/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
* The RX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_RX_ERR_CNT 0x000000FFU
#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S)
#define TWAI_RX_ERR_CNT_V 0x000000FFU
#define TWAI_RX_ERR_CNT_S 0
/** TWAI_TX_ERR_CNT_REG register
* Tx error counter register.
*/
#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c)
/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
* The TX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_TX_ERR_CNT 0x000000FFU
#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S)
#define TWAI_TX_ERR_CNT_V 0x000000FFU
#define TWAI_TX_ERR_CNT_S 0
/** TWAI_DATA_0_REG register
* Data register 0.
*/
#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40)
/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 0 and when
* software initiate read operation, it is rx data register 0.
*/
#define TWAI_DATA_0 0x000000FFU
#define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S)
#define TWAI_DATA_0_V 0x000000FFU
#define TWAI_DATA_0_S 0
/** TWAI_DATA_1_REG register
* Data register 1.
*/
#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44)
/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 1 and when
* software initiate read operation, it is rx data register 1.
*/
#define TWAI_DATA_1 0x000000FFU
#define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S)
#define TWAI_DATA_1_V 0x000000FFU
#define TWAI_DATA_1_S 0
/** TWAI_DATA_2_REG register
* Data register 2.
*/
#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48)
/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 2 and when
* software initiate read operation, it is rx data register 2.
*/
#define TWAI_DATA_2 0x000000FFU
#define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S)
#define TWAI_DATA_2_V 0x000000FFU
#define TWAI_DATA_2_S 0
/** TWAI_DATA_3_REG register
* Data register 3.
*/
#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c)
/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 3 and when
* software initiate read operation, it is rx data register 3.
*/
#define TWAI_DATA_3 0x000000FFU
#define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S)
#define TWAI_DATA_3_V 0x000000FFU
#define TWAI_DATA_3_S 0
/** TWAI_DATA_4_REG register
* Data register 4.
*/
#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50)
/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 4 and when
* software initiate read operation, it is rx data register 4.
*/
#define TWAI_DATA_4 0x000000FFU
#define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S)
#define TWAI_DATA_4_V 0x000000FFU
#define TWAI_DATA_4_S 0
/** TWAI_DATA_5_REG register
* Data register 5.
*/
#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54)
/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 5 and when
* software initiate read operation, it is rx data register 5.
*/
#define TWAI_DATA_5 0x000000FFU
#define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S)
#define TWAI_DATA_5_V 0x000000FFU
#define TWAI_DATA_5_S 0
/** TWAI_DATA_6_REG register
* Data register 6.
*/
#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58)
/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 6 and when
* software initiate read operation, it is rx data register 6.
*/
#define TWAI_DATA_6 0x000000FFU
#define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S)
#define TWAI_DATA_6_V 0x000000FFU
#define TWAI_DATA_6_S 0
/** TWAI_DATA_7_REG register
* Data register 7.
*/
#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c)
/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 7 and when
* software initiate read operation, it is rx data register 7.
*/
#define TWAI_DATA_7 0x000000FFU
#define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S)
#define TWAI_DATA_7_V 0x000000FFU
#define TWAI_DATA_7_S 0
/** TWAI_DATA_8_REG register
* Data register 8.
*/
#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60)
/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 8 and when software initiate read operation, it
* is rx data register 8.
*/
#define TWAI_DATA_8 0x000000FFU
#define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S)
#define TWAI_DATA_8_V 0x000000FFU
#define TWAI_DATA_8_S 0
/** TWAI_DATA_9_REG register
* Data register 9.
*/
#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64)
/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 9 and when software initiate read operation, it
* is rx data register 9.
*/
#define TWAI_DATA_9 0x000000FFU
#define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S)
#define TWAI_DATA_9_V 0x000000FFU
#define TWAI_DATA_9_S 0
/** TWAI_DATA_10_REG register
* Data register 10.
*/
#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68)
/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 10 and when software initiate read operation, it
* is rx data register 10.
*/
#define TWAI_DATA_10 0x000000FFU
#define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S)
#define TWAI_DATA_10_V 0x000000FFU
#define TWAI_DATA_10_S 0
/** TWAI_DATA_11_REG register
* Data register 11.
*/
#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c)
/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 11 and when software initiate read operation, it
* is rx data register 11.
*/
#define TWAI_DATA_11 0x000000FFU
#define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S)
#define TWAI_DATA_11_V 0x000000FFU
#define TWAI_DATA_11_S 0
/** TWAI_DATA_12_REG register
* Data register 12.
*/
#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70)
/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 12 and when software initiate read operation, it
* is rx data register 12.
*/
#define TWAI_DATA_12 0x000000FFU
#define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S)
#define TWAI_DATA_12_V 0x000000FFU
#define TWAI_DATA_12_S 0
/** TWAI_RX_MESSAGE_COUNTER_REG register
* Received message counter register.
*/
#define TWAI_RX_MESSAGE_COUNTER_REG (DR_REG_TWAI_BASE + 0x74)
/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
* Reflects the number of messages available within the RXFIFO. The value is
* incremented with each receive event and decremented by the release receive buffer
* command.
*/
#define TWAI_RX_MESSAGE_COUNTER 0x0000007FU
#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S)
#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU
#define TWAI_RX_MESSAGE_COUNTER_S 0
/** TWAI_CLOCK_DIVIDER_REG register
* Clock divider register.
*/
#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c)
/** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
* These bits are used to define the frequency at the external CLKOUT pin.
*/
#define TWAI_CD 0x000000FFU
#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S)
#define TWAI_CD_V 0x000000FFU
#define TWAI_CD_S 0
/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0;
* 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
* R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_CLOCK_OFF (BIT(8))
#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S)
#define TWAI_CLOCK_OFF_V 0x00000001U
#define TWAI_CLOCK_OFF_S 8
/** TWAI_SW_STANDBY_CFG_REG register
* Software configure standby pin directly.
*/
#define TWAI_SW_STANDBY_CFG_REG (DR_REG_TWAI_BASE + 0x80)
/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
* Enable standby pin.
*/
#define TWAI_SW_STANDBY_EN (BIT(0))
#define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S)
#define TWAI_SW_STANDBY_EN_V 0x00000001U
#define TWAI_SW_STANDBY_EN_S 0
/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1;
* Clear standby pin.
*/
#define TWAI_SW_STANDBY_CLR (BIT(1))
#define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S)
#define TWAI_SW_STANDBY_CLR_V 0x00000001U
#define TWAI_SW_STANDBY_CLR_S 1
/** TWAI_HW_CFG_REG register
* Hardware configure standby pin.
*/
#define TWAI_HW_CFG_REG (DR_REG_TWAI_BASE + 0x84)
/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
* Enable function that hardware control standby pin.
*/
#define TWAI_HW_STANDBY_EN (BIT(0))
#define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S)
#define TWAI_HW_STANDBY_EN_V 0x00000001U
#define TWAI_HW_STANDBY_EN_S 0
/** TWAI_HW_STANDBY_CNT_REG register
* Configure standby counter.
*/
#define TWAI_HW_STANDBY_CNT_REG (DR_REG_TWAI_BASE + 0x88)
/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
* is enabled.
*/
#define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU
#define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S)
#define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU
#define TWAI_STANDBY_WAIT_CNT_S 0
/** TWAI_IDLE_INTR_CNT_REG register
* Configure idle interrupt counter.
*/
#define TWAI_IDLE_INTR_CNT_REG (DR_REG_TWAI_BASE + 0x8c)
/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before triggering idle interrupt.
*/
#define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU
#define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S)
#define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU
#define TWAI_IDLE_INTR_CNT_S 0
/** TWAI_ECO_CFG_REG register
* ECO configuration register.
*/
#define TWAI_ECO_CFG_REG (DR_REG_TWAI_BASE + 0x90)
/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
* Enable eco module.
*/
#define TWAI_RDN_ENA (BIT(0))
#define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S)
#define TWAI_RDN_ENA_V 0x00000001U
#define TWAI_RDN_ENA_S 0
/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1;
* Output of eco module.
*/
#define TWAI_RDN_RESULT (BIT(1))
#define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S)
#define TWAI_RDN_RESULT_V 0x00000001U
#define TWAI_RDN_RESULT_S 1
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/soc/twai_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of mode register
* TWAI mode register.
*/
typedef union {
struct {
/** reset_mode : R/W; bitpos: [0]; default: 1;
* 1: reset, detection of a set reset mode bit results in aborting the current
* transmission/reception of a message and entering the reset mode. 0: normal, on the
* '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
* operating mode.
*/
uint32_t reset_mode:1;
/** listen_only_mode : R/W; bitpos: [1]; default: 0;
* 1: listen only, in this mode the TWAI controller would give no acknowledge to the
* TWAI-bus, even if a message is received successfully. The error counters are
* stopped at the current value. 0: normal.
*/
uint32_t listen_only_mode:1;
/** self_test_mode : R/W; bitpos: [2]; default: 0;
* 1: self test, in this mode a full node test is possible without any other active
* node on the bus using the self reception request command. The TWAI controller will
* perform a successful transmission, even if there is no acknowledge received. 0:
* normal, an acknowledge is required for successful transmission.
*/
uint32_t self_test_mode:1;
/** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
* 1:single, the single acceptance filter option is enabled (one filter with the
* length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
* (two filters, each with the length of 16 bit are active).
*/
uint32_t acceptance_filter_mode:1;
uint32_t reserved_4:28;
};
uint32_t val;
} twai_mode_reg_t;
/** Type of cmd register
* TWAI command register.
*/
typedef union {
struct {
/** tx_request : WO; bitpos: [0]; default: 0;
* 1: present, a message shall be transmitted. 0: absent
*/
uint32_t tx_request:1;
/** abort_tx : WO; bitpos: [1]; default: 0;
* 1: present, if not already in progress, a pending transmission request is
* cancelled. 0: absent
*/
uint32_t abort_tx:1;
/** release_buffer : WO; bitpos: [2]; default: 0;
* 1: released, the receive buffer, representing the message memory space in the
* RXFIFO is released. 0: no action
*/
uint32_t release_buffer:1;
/** clear_data_overrun : WO; bitpos: [3]; default: 0;
* 1: clear, the data overrun status bit is cleared. 0: no action.
*/
uint32_t clear_data_overrun:1;
/** self_rx_request : WO; bitpos: [4]; default: 0;
* 1: present, a message shall be transmitted and received simultaneously. 0: absent.
*/
uint32_t self_rx_request:1;
uint32_t reserved_5:27;
};
uint32_t val;
} twai_cmd_reg_t;
/** Type of bus_timing_0 register
* Bit timing configuration register 0.
*/
typedef union {
struct {
/** baud_presc : R/W; bitpos: [13:0]; default: 0;
* The period of the TWAI system clock is programmable and determines the individual
* bit timing. Software has R/W permission in reset mode and RO permission in
* operation mode.
*/
uint32_t baud_presc:14;
/** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
* The synchronization jump width defines the maximum number of clock cycles a bit
* period may be shortened or lengthened. Software has R/W permission in reset mode
* and RO in operation mode.
*/
uint32_t sync_jump_width:2;
uint32_t reserved_16:16;
};
uint32_t val;
} twai_bus_timing_0_reg_t;
/** Type of bus_timing_1 register
* Bit timing configuration register 1.
*/
typedef union {
struct {
/** time_segment1 : R/W; bitpos: [3:0]; default: 0;
* The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
uint32_t time_segment1:4;
/** time_segment2 : R/W; bitpos: [6:4]; default: 0;
* The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
uint32_t time_segment2:3;
/** time_sampling : R/W; bitpos: [7]; default: 0;
* 1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
* Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t time_sampling:1;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_bus_timing_1_reg_t;
/** Type of err_warning_limit register
* TWAI error threshold configuration register.
*/
typedef union {
struct {
/** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
* The threshold that trigger error warning interrupt when this interrupt is enabled.
* Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t err_warning_limit:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_err_warning_limit_reg_t;
/** Type of clock_divider register
* Clock divider register.
*/
typedef union {
struct {
/** cd : R/W; bitpos: [7:0]; default: 0;
* These bits are used to define the frequency at the external CLKOUT pin.
*/
uint32_t cd:8;
/** clock_off : R/W; bitpos: [8]; default: 0;
* 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
* R/W permission in reset mode and RO in operation mode.
*/
uint32_t clock_off:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_clock_divider_reg_t;
/** Type of sw_standby_cfg register
* Software configure standby pin directly.
*/
typedef union {
struct {
/** sw_standby_en : R/W; bitpos: [0]; default: 0;
* Enable standby pin.
*/
uint32_t sw_standby_en:1;
/** sw_standby_clr : R/W; bitpos: [1]; default: 1;
* Clear standby pin.
*/
uint32_t sw_standby_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} twai_sw_standby_cfg_reg_t;
/** Type of hw_cfg register
* Hardware configure standby pin.
*/
typedef union {
struct {
/** hw_standby_en : R/W; bitpos: [0]; default: 0;
* Enable function that hardware control standby pin.
*/
uint32_t hw_standby_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} twai_hw_cfg_reg_t;
/** Type of hw_standby_cnt register
* Configure standby counter.
*/
typedef union {
struct {
/** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
* is enabled.
*/
uint32_t standby_wait_cnt:32;
};
uint32_t val;
} twai_hw_standby_cnt_reg_t;
/** Type of idle_intr_cnt register
* Configure idle interrupt counter.
*/
typedef union {
struct {
/** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before triggering idle interrupt.
*/
uint32_t idle_intr_cnt:32;
};
uint32_t val;
} twai_idle_intr_cnt_reg_t;
/** Type of eco_cfg register
* ECO configuration register.
*/
typedef union {
struct {
/** rdn_ena : R/W; bitpos: [0]; default: 0;
* Enable eco module.
*/
uint32_t rdn_ena:1;
/** rdn_result : RO; bitpos: [1]; default: 1;
* Output of eco module.
*/
uint32_t rdn_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} twai_eco_cfg_reg_t;
/** Group: Status Registers */
/** Type of status register
* TWAI status register.
*/
typedef union {
struct {
/** status_receive_buffer : RO; bitpos: [0]; default: 0;
* 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
* message is available
*/
uint32_t status_receive_buffer:1;
/** status_overrun : RO; bitpos: [1]; default: 0;
* 1: overrun, a message was lost because there was not enough space for that message
* in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
* overrun command was given
*/
uint32_t status_overrun:1;
/** status_transmit_buffer : RO; bitpos: [2]; default: 0;
* 1: released, the CPU may write a message into the transmit buffer. 0: locked, the
* CPU cannot access the transmit buffer, a message is either waiting for transmission
* or is in the process of being transmitted
*/
uint32_t status_transmit_buffer:1;
/** status_transmission_complete : RO; bitpos: [3]; default: 0;
* 1: complete, last requested transmission has been successfully completed. 0:
* incomplete, previously requested transmission is not yet completed
*/
uint32_t status_transmission_complete:1;
/** status_receive : RO; bitpos: [4]; default: 0;
* 1: receive, the TWAI controller is receiving a message. 0: idle
*/
uint32_t status_receive:1;
/** status_transmit : RO; bitpos: [5]; default: 0;
* 1: transmit, the TWAI controller is transmitting a message. 0: idle
*/
uint32_t status_transmit:1;
/** status_err : RO; bitpos: [6]; default: 0;
* 1: error, at least one of the error counters has reached or exceeded the CPU
* warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
* counters are below the warning limit
*/
uint32_t status_err:1;
/** status_node_bus_off : RO; bitpos: [7]; default: 0;
* 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
* TWAI controller is involved in bus activities
*/
uint32_t status_node_bus_off:1;
/** status_miss : RO; bitpos: [8]; default: 0;
* 1: current message is destroyed because of FIFO overflow.
*/
uint32_t status_miss:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_status_reg_t;
/** Type of arb_lost_cap register
* TWAI arbiter lost capture register.
*/
typedef union {
struct {
/** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
* This register contains information about the bit position of losing arbitration.
*/
uint32_t arbitration_lost_capture:5;
uint32_t reserved_5:27;
};
uint32_t val;
} twai_arb_lost_cap_reg_t;
/** Type of err_code_cap register
* TWAI error info capture register.
*/
typedef union {
struct {
/** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
* This register contains information about the location of errors on the bus.
*/
uint32_t err_capture_code_segment:5;
/** err_capture_code_direction : RO; bitpos: [5]; default: 0;
* 1: RX, error occurred during reception. 0: TX, error occurred during transmission.
*/
uint32_t err_capture_code_direction:1;
/** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
* 00: bit error. 01: form error. 10:stuff error. 11:other type of error.
*/
uint32_t err_capture_code_type:2;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_err_code_cap_reg_t;
/** Type of rx_err_cnt register
* Rx error counter register.
*/
typedef union {
struct {
/** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
* The RX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t rx_err_cnt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_rx_err_cnt_reg_t;
/** Type of tx_err_cnt register
* Tx error counter register.
*/
typedef union {
struct {
/** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
* The TX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t tx_err_cnt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_tx_err_cnt_reg_t;
/** Type of rx_message_counter register
* Received message counter register.
*/
typedef union {
struct {
/** rx_message_counter : RO; bitpos: [6:0]; default: 0;
* Reflects the number of messages available within the RXFIFO. The value is
* incremented with each receive event and decremented by the release receive buffer
* command.
*/
uint32_t rx_message_counter:7;
uint32_t reserved_7:25;
};
uint32_t val;
} twai_rx_message_counter_reg_t;
/** Group: Interrupt Registers */
/** Type of interrupt register
* Interrupt signals' register.
*/
typedef union {
struct {
/** receive_int_st : RO; bitpos: [0]; default: 0;
* 1: this bit is set while the receive FIFO is not empty and the RIE bit is set
* within the interrupt enable register. 0: reset
*/
uint32_t receive_int_st:1;
/** transmit_int_st : RO; bitpos: [1]; default: 0;
* 1: this bit is set whenever the transmit buffer status changes from '0-to-1'
* (released) and the TIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t transmit_int_st:1;
/** err_warning_int_st : RO; bitpos: [2]; default: 0;
* 1: this bit is set on every change (set and clear) of either the error status or
* bus status bits and the EIE bit is set within the interrupt enable register. 0:
* reset
*/
uint32_t err_warning_int_st:1;
/** data_overrun_int_st : RO; bitpos: [3]; default: 0;
* 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
* DOIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t data_overrun_int_st:1;
uint32_t reserved_4:1;
/** err_passive_int_st : RO; bitpos: [5]; default: 0;
* 1: this bit is set whenever the TWAI controller has reached the error passive
* status (at least one error counter exceeds the protocol-defined level of 127) or if
* the TWAI controller is in the error passive status and enters the error active
* status again and the EPIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t err_passive_int_st:1;
/** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
* 1: this bit is set when the TWAI controller lost the arbitration and becomes a
* receiver and the ALIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t arbitration_lost_int_st:1;
/** bus_err_int_st : RO; bitpos: [7]; default: 0;
* 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
* the BEIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t bus_err_int_st:1;
/** idle_int_st : RO; bitpos: [8]; default: 0;
* 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
* this interrupt enable bit is set within the interrupt enable register. 0: reset
*/
uint32_t idle_int_st:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_interrupt_reg_t;
/** Type of interrupt_enable register
* Interrupt enable register.
*/
typedef union {
struct {
/** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
* 1: enabled, when the receive buffer status is 'full' the TWAI controller requests
* the respective interrupt. 0: disable
*/
uint32_t ext_receive_int_ena:1;
/** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
* 1: enabled, when a message has been successfully transmitted or the transmit buffer
* is accessible again (e.g. after an abort transmission command), the TWAI controller
* requests the respective interrupt. 0: disable
*/
uint32_t ext_transmit_int_ena:1;
/** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
* 1: enabled, if the error or bus status change (see status register. Table 14), the
* TWAI controllerrequests the respective interrupt. 0: disable
*/
uint32_t ext_err_warning_int_ena:1;
/** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
* 1: enabled, if the data overrun status bit is set (see status register. Table 14),
* the TWAI controllerrequests the respective interrupt. 0: disable
*/
uint32_t ext_data_overrun_int_ena:1;
uint32_t reserved_4:1;
/** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
* 1: enabled, if the error status of the TWAI controller changes from error active to
* error passive or vice versa, the respective interrupt is requested. 0: disable
*/
uint32_t err_passive_int_ena:1;
/** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
* 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
* is requested. 0: disable
*/
uint32_t arbitration_lost_int_ena:1;
/** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
* 1: enabled, if an bus error has been detected, the TWAI controller requests the
* respective interrupt. 0: disable
*/
uint32_t bus_err_int_ena:1;
/** idle_int_ena : RO; bitpos: [8]; default: 0;
* 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
* respective interrupt. 0: disable
*/
uint32_t idle_int_ena:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_interrupt_enable_reg_t;
/** Group: Data Registers */
/** Type of data_0 register
* Data register 0.
*/
typedef union {
struct {
/** data_0 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 0 and when
* software initiate read operation, it is rx data register 0.
*/
uint32_t data_0:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_0_reg_t;
/** Type of data_1 register
* Data register 1.
*/
typedef union {
struct {
/** data_1 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 1 and when
* software initiate read operation, it is rx data register 1.
*/
uint32_t data_1:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_1_reg_t;
/** Type of data_2 register
* Data register 2.
*/
typedef union {
struct {
/** data_2 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 2 and when
* software initiate read operation, it is rx data register 2.
*/
uint32_t data_2:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_2_reg_t;
/** Type of data_3 register
* Data register 3.
*/
typedef union {
struct {
/** data_3 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 3 and when
* software initiate read operation, it is rx data register 3.
*/
uint32_t data_3:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_3_reg_t;
/** Type of data_4 register
* Data register 4.
*/
typedef union {
struct {
/** data_4 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 4 and when
* software initiate read operation, it is rx data register 4.
*/
uint32_t data_4:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_4_reg_t;
/** Type of data_5 register
* Data register 5.
*/
typedef union {
struct {
/** data_5 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 5 and when
* software initiate read operation, it is rx data register 5.
*/
uint32_t data_5:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_5_reg_t;
/** Type of data_6 register
* Data register 6.
*/
typedef union {
struct {
/** data_6 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 6 and when
* software initiate read operation, it is rx data register 6.
*/
uint32_t data_6:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_6_reg_t;
/** Type of data_7 register
* Data register 7.
*/
typedef union {
struct {
/** data_7 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 7 and when
* software initiate read operation, it is rx data register 7.
*/
uint32_t data_7:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_7_reg_t;
/** Type of data_8 register
* Data register 8.
*/
typedef union {
struct {
/** data_8 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 8 and when software initiate read operation, it
* is rx data register 8.
*/
uint32_t data_8:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_8_reg_t;
/** Type of data_9 register
* Data register 9.
*/
typedef union {
struct {
/** data_9 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 9 and when software initiate read operation, it
* is rx data register 9.
*/
uint32_t data_9:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_9_reg_t;
/** Type of data_10 register
* Data register 10.
*/
typedef union {
struct {
/** data_10 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 10 and when software initiate read operation, it
* is rx data register 10.
*/
uint32_t data_10:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_10_reg_t;
/** Type of data_11 register
* Data register 11.
*/
typedef union {
struct {
/** data_11 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 11 and when software initiate read operation, it
* is rx data register 11.
*/
uint32_t data_11:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_11_reg_t;
/** Type of data_12 register
* Data register 12.
*/
typedef union {
struct {
/** data_12 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 12 and when software initiate read operation, it
* is rx data register 12.
*/
uint32_t data_12:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_12_reg_t;
typedef struct {
volatile twai_mode_reg_t mode;
volatile twai_cmd_reg_t cmd;
volatile twai_status_reg_t status;
volatile twai_interrupt_reg_t interrupt;
volatile twai_interrupt_enable_reg_t interrupt_enable;
uint32_t reserved_014;
volatile twai_bus_timing_0_reg_t bus_timing_0;
volatile twai_bus_timing_1_reg_t bus_timing_1;
uint32_t reserved_020[3];
volatile twai_arb_lost_cap_reg_t arb_lost_cap;
volatile twai_err_code_cap_reg_t err_code_cap;
volatile twai_err_warning_limit_reg_t err_warning_limit;
volatile twai_rx_err_cnt_reg_t rx_err_cnt;
volatile twai_tx_err_cnt_reg_t tx_err_cnt;
volatile twai_data_0_reg_t data_0;
volatile twai_data_1_reg_t data_1;
volatile twai_data_2_reg_t data_2;
volatile twai_data_3_reg_t data_3;
volatile twai_data_4_reg_t data_4;
volatile twai_data_5_reg_t data_5;
volatile twai_data_6_reg_t data_6;
volatile twai_data_7_reg_t data_7;
volatile twai_data_8_reg_t data_8;
volatile twai_data_9_reg_t data_9;
volatile twai_data_10_reg_t data_10;
volatile twai_data_11_reg_t data_11;
volatile twai_data_12_reg_t data_12;
volatile twai_rx_message_counter_reg_t rx_message_counter;
uint32_t reserved_078;
volatile twai_clock_divider_reg_t clock_divider;
volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
volatile twai_hw_cfg_reg_t hw_cfg;
volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
volatile twai_eco_cfg_reg_t eco_cfg;
} twai_dev_t;
extern twai_dev_t TWAI;
#ifndef __cplusplus
_Static_assert(sizeof(twai_dev_t) == 0x94, "Invalid size of twai_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** UHCI_CONF0_REG register
* a
*/
#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0)
/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0;
* Write 1 then write 0 to this bit to reset decode state machine.
*/
#define UHCI_TX_RST (BIT(0))
#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S)
#define UHCI_TX_RST_V 0x00000001U
#define UHCI_TX_RST_S 0
/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0;
* Write 1 then write 0 to this bit to reset encode state machine.
*/
#define UHCI_RX_RST (BIT(1))
#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S)
#define UHCI_RX_RST_V 0x00000001U
#define UHCI_RX_RST_S 1
/** UHCI_UART0_CE : R/W; bitpos: [2]; default: 0;
* Set this bit to link up HCI and UART0.
*/
#define UHCI_UART0_CE (BIT(2))
#define UHCI_UART0_CE_M (UHCI_UART0_CE_V << UHCI_UART0_CE_S)
#define UHCI_UART0_CE_V 0x00000001U
#define UHCI_UART0_CE_S 2
/** UHCI_UART1_CE : R/W; bitpos: [3]; default: 0;
* Set this bit to link up HCI and UART1.
*/
#define UHCI_UART1_CE (BIT(3))
#define UHCI_UART1_CE_M (UHCI_UART1_CE_V << UHCI_UART1_CE_S)
#define UHCI_UART1_CE_V 0x00000001U
#define UHCI_UART1_CE_S 3
/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1;
* Set this bit to separate the data frame using a special char.
*/
#define UHCI_SEPER_EN (BIT(5))
#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S)
#define UHCI_SEPER_EN_V 0x00000001U
#define UHCI_SEPER_EN_S 5
/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1;
* Set this bit to encode the data packet with a formatting header.
*/
#define UHCI_HEAD_EN (BIT(6))
#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S)
#define UHCI_HEAD_EN_V 0x00000001U
#define UHCI_HEAD_EN_S 6
/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1;
* Set this bit to enable UHCI to receive the 16 bit CRC.
*/
#define UHCI_CRC_REC_EN (BIT(7))
#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S)
#define UHCI_CRC_REC_EN_V 0x00000001U
#define UHCI_CRC_REC_EN_S 7
/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0;
* If this bit is set to 1 UHCI will end the payload receiving process when UART has
* been in idle state.
*/
#define UHCI_UART_IDLE_EOF_EN (BIT(8))
#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S)
#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U
#define UHCI_UART_IDLE_EOF_EN_S 8
/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1;
* If this bit is set to 1 UHCI decoder receiving payload data is end when the
* receiving byte count has reached the specified value. The value is payload length
* indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
* configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
* receiving payload data is end when 0xc0 is received.
*/
#define UHCI_LEN_EOF_EN (BIT(9))
#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S)
#define UHCI_LEN_EOF_EN_V 0x00000001U
#define UHCI_LEN_EOF_EN_S 9
/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1;
* Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
* end of the payload.
*/
#define UHCI_ENCODE_CRC_EN (BIT(10))
#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S)
#define UHCI_ENCODE_CRC_EN_V 0x00000001U
#define UHCI_ENCODE_CRC_EN_S 10
/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0;
* 1'b1: Force clock on for register. 1'b0: Support clock only when application writes
* registers.
*/
#define UHCI_CLK_EN (BIT(11))
#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S)
#define UHCI_CLK_EN_V 0x00000001U
#define UHCI_CLK_EN_S 11
/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0;
* If this bit is set to 1 UHCI will end payload receive process when NULL frame is
* received by UART.
*/
#define UHCI_UART_RX_BRK_EOF_EN (BIT(12))
#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S)
#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U
#define UHCI_UART_RX_BRK_EOF_EN_S 12
/** UHCI_INT_RAW_REG register
* a
*/
#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4)
/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* a
*/
#define UHCI_RX_START_INT_RAW (BIT(0))
#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S)
#define UHCI_RX_START_INT_RAW_V 0x00000001U
#define UHCI_RX_START_INT_RAW_S 0
/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* a
*/
#define UHCI_TX_START_INT_RAW (BIT(1))
#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S)
#define UHCI_TX_START_INT_RAW_V 0x00000001U
#define UHCI_TX_START_INT_RAW_S 1
/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* a
*/
#define UHCI_RX_HUNG_INT_RAW (BIT(2))
#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S)
#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U
#define UHCI_RX_HUNG_INT_RAW_S 2
/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* a
*/
#define UHCI_TX_HUNG_INT_RAW (BIT(3))
#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S)
#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U
#define UHCI_TX_HUNG_INT_RAW_S 3
/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* a
*/
#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4))
#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S)
#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U
#define UHCI_SEND_S_REG_Q_INT_RAW_S 4
/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* a
*/
#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5))
#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S)
#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U
#define UHCI_SEND_A_REG_Q_INT_RAW_S 5
/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
* This is the interrupt raw bit. Triggered when there are some errors in EOF in the
*/
#define UHCI_OUT_EOF_INT_RAW (BIT(6))
#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S)
#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U
#define UHCI_OUT_EOF_INT_RAW_S 6
/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0;
* Soft control int raw bit.
*/
#define UHCI_APP_CTRL0_INT_RAW (BIT(7))
#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S)
#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U
#define UHCI_APP_CTRL0_INT_RAW_S 7
/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0;
* Soft control int raw bit.
*/
#define UHCI_APP_CTRL1_INT_RAW (BIT(8))
#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S)
#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U
#define UHCI_APP_CTRL1_INT_RAW_S 8
/** UHCI_INT_ST_REG register
* a
*/
#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8)
/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0;
* a
*/
#define UHCI_RX_START_INT_ST (BIT(0))
#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S)
#define UHCI_RX_START_INT_ST_V 0x00000001U
#define UHCI_RX_START_INT_ST_S 0
/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0;
* a
*/
#define UHCI_TX_START_INT_ST (BIT(1))
#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S)
#define UHCI_TX_START_INT_ST_V 0x00000001U
#define UHCI_TX_START_INT_ST_S 1
/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
* a
*/
#define UHCI_RX_HUNG_INT_ST (BIT(2))
#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S)
#define UHCI_RX_HUNG_INT_ST_V 0x00000001U
#define UHCI_RX_HUNG_INT_ST_S 2
/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
* a
*/
#define UHCI_TX_HUNG_INT_ST (BIT(3))
#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S)
#define UHCI_TX_HUNG_INT_ST_V 0x00000001U
#define UHCI_TX_HUNG_INT_ST_S 3
/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0;
* a
*/
#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4))
#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S)
#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U
#define UHCI_SEND_S_REG_Q_INT_ST_S 4
/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0;
* a
*/
#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5))
#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S)
#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U
#define UHCI_SEND_A_REG_Q_INT_ST_S 5
/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0;
* a
*/
#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S)
#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U
#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6
/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0;
* a
*/
#define UHCI_APP_CTRL0_INT_ST (BIT(7))
#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S)
#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U
#define UHCI_APP_CTRL0_INT_ST_S 7
/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0;
* a
*/
#define UHCI_APP_CTRL1_INT_ST (BIT(8))
#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S)
#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U
#define UHCI_APP_CTRL1_INT_ST_S 8
/** UHCI_INT_ENA_REG register
* a
*/
#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc)
/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0;
* a
*/
#define UHCI_RX_START_INT_ENA (BIT(0))
#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S)
#define UHCI_RX_START_INT_ENA_V 0x00000001U
#define UHCI_RX_START_INT_ENA_S 0
/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0;
* a
*/
#define UHCI_TX_START_INT_ENA (BIT(1))
#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S)
#define UHCI_TX_START_INT_ENA_V 0x00000001U
#define UHCI_TX_START_INT_ENA_S 1
/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
* a
*/
#define UHCI_RX_HUNG_INT_ENA (BIT(2))
#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S)
#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U
#define UHCI_RX_HUNG_INT_ENA_S 2
/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
* a
*/
#define UHCI_TX_HUNG_INT_ENA (BIT(3))
#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S)
#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U
#define UHCI_TX_HUNG_INT_ENA_S 3
/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0;
* a
*/
#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4))
#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S)
#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U
#define UHCI_SEND_S_REG_Q_INT_ENA_S 4
/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0;
* a
*/
#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5))
#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S)
#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U
#define UHCI_SEND_A_REG_Q_INT_ENA_S 5
/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
* a
*/
#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S)
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6
/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0;
* a
*/
#define UHCI_APP_CTRL0_INT_ENA (BIT(7))
#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S)
#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U
#define UHCI_APP_CTRL0_INT_ENA_S 7
/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0;
* a
*/
#define UHCI_APP_CTRL1_INT_ENA (BIT(8))
#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S)
#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U
#define UHCI_APP_CTRL1_INT_ENA_S 8
/** UHCI_INT_CLR_REG register
* a
*/
#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10)
/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0;
* a
*/
#define UHCI_RX_START_INT_CLR (BIT(0))
#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S)
#define UHCI_RX_START_INT_CLR_V 0x00000001U
#define UHCI_RX_START_INT_CLR_S 0
/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0;
* a
*/
#define UHCI_TX_START_INT_CLR (BIT(1))
#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S)
#define UHCI_TX_START_INT_CLR_V 0x00000001U
#define UHCI_TX_START_INT_CLR_S 1
/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
* a
*/
#define UHCI_RX_HUNG_INT_CLR (BIT(2))
#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S)
#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U
#define UHCI_RX_HUNG_INT_CLR_S 2
/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
* a
*/
#define UHCI_TX_HUNG_INT_CLR (BIT(3))
#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S)
#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U
#define UHCI_TX_HUNG_INT_CLR_S 3
/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0;
* a
*/
#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4))
#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S)
#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U
#define UHCI_SEND_S_REG_Q_INT_CLR_S 4
/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0;
* a
*/
#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5))
#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S)
#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U
#define UHCI_SEND_A_REG_Q_INT_CLR_S 5
/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
* a
*/
#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S)
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6
/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0;
* a
*/
#define UHCI_APP_CTRL0_INT_CLR (BIT(7))
#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S)
#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U
#define UHCI_APP_CTRL0_INT_CLR_S 7
/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0;
* a
*/
#define UHCI_APP_CTRL1_INT_CLR (BIT(8))
#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S)
#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U
#define UHCI_APP_CTRL1_INT_CLR_S 8
/** UHCI_CONF1_REG register
* a
*/
#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14)
/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1;
* a
*/
#define UHCI_CHECK_SUM_EN (BIT(0))
#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S)
#define UHCI_CHECK_SUM_EN_V 0x00000001U
#define UHCI_CHECK_SUM_EN_S 0
/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1;
* a
*/
#define UHCI_CHECK_SEQ_EN (BIT(1))
#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S)
#define UHCI_CHECK_SEQ_EN_V 0x00000001U
#define UHCI_CHECK_SEQ_EN_S 1
/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0;
* a
*/
#define UHCI_CRC_DISABLE (BIT(2))
#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S)
#define UHCI_CRC_DISABLE_V 0x00000001U
#define UHCI_CRC_DISABLE_S 2
/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0;
* a
*/
#define UHCI_SAVE_HEAD (BIT(3))
#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S)
#define UHCI_SAVE_HEAD_V 0x00000001U
#define UHCI_SAVE_HEAD_S 3
/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1;
* a
*/
#define UHCI_TX_CHECK_SUM_RE (BIT(4))
#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S)
#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U
#define UHCI_TX_CHECK_SUM_RE_S 4
/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1;
* a
*/
#define UHCI_TX_ACK_NUM_RE (BIT(5))
#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S)
#define UHCI_TX_ACK_NUM_RE_V 0x00000001U
#define UHCI_TX_ACK_NUM_RE_S 5
/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0;
* a
*/
#define UHCI_WAIT_SW_START (BIT(7))
#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S)
#define UHCI_WAIT_SW_START_V 0x00000001U
#define UHCI_WAIT_SW_START_S 7
/** UHCI_SW_START : WT; bitpos: [8]; default: 0;
* a
*/
#define UHCI_SW_START (BIT(8))
#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S)
#define UHCI_SW_START_V 0x00000001U
#define UHCI_SW_START_S 8
/** UHCI_STATE0_REG register
* a
*/
#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18)
/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0;
* a
*/
#define UHCI_RX_ERR_CAUSE 0x00000007U
#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S)
#define UHCI_RX_ERR_CAUSE_V 0x00000007U
#define UHCI_RX_ERR_CAUSE_S 0
/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0;
* a
*/
#define UHCI_DECODE_STATE 0x00000007U
#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S)
#define UHCI_DECODE_STATE_V 0x00000007U
#define UHCI_DECODE_STATE_S 3
/** UHCI_STATE1_REG register
* a
*/
#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c)
/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0;
* a
*/
#define UHCI_ENCODE_STATE 0x00000007U
#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S)
#define UHCI_ENCODE_STATE_V 0x00000007U
#define UHCI_ENCODE_STATE_S 0
/** UHCI_ESCAPE_CONF_REG register
* a
*/
#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20)
/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1;
* a
*/
#define UHCI_TX_C0_ESC_EN (BIT(0))
#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S)
#define UHCI_TX_C0_ESC_EN_V 0x00000001U
#define UHCI_TX_C0_ESC_EN_S 0
/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1;
* a
*/
#define UHCI_TX_DB_ESC_EN (BIT(1))
#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S)
#define UHCI_TX_DB_ESC_EN_V 0x00000001U
#define UHCI_TX_DB_ESC_EN_S 1
/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0;
* a
*/
#define UHCI_TX_11_ESC_EN (BIT(2))
#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S)
#define UHCI_TX_11_ESC_EN_V 0x00000001U
#define UHCI_TX_11_ESC_EN_S 2
/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0;
* a
*/
#define UHCI_TX_13_ESC_EN (BIT(3))
#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S)
#define UHCI_TX_13_ESC_EN_V 0x00000001U
#define UHCI_TX_13_ESC_EN_S 3
/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1;
* a
*/
#define UHCI_RX_C0_ESC_EN (BIT(4))
#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S)
#define UHCI_RX_C0_ESC_EN_V 0x00000001U
#define UHCI_RX_C0_ESC_EN_S 4
/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1;
* a
*/
#define UHCI_RX_DB_ESC_EN (BIT(5))
#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S)
#define UHCI_RX_DB_ESC_EN_V 0x00000001U
#define UHCI_RX_DB_ESC_EN_S 5
/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0;
* a
*/
#define UHCI_RX_11_ESC_EN (BIT(6))
#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S)
#define UHCI_RX_11_ESC_EN_V 0x00000001U
#define UHCI_RX_11_ESC_EN_S 6
/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0;
* a
*/
#define UHCI_RX_13_ESC_EN (BIT(7))
#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S)
#define UHCI_RX_13_ESC_EN_V 0x00000001U
#define UHCI_RX_13_ESC_EN_S 7
/** UHCI_HUNG_CONF_REG register
* a
*/
#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24)
/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
* a
*/
#define UHCI_TXFIFO_TIMEOUT 0x000000FFU
#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S)
#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU
#define UHCI_TXFIFO_TIMEOUT_S 0
/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
* a
*/
#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U
#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S)
#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U
#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8
/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
* a
*/
#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11))
#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S)
#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U
#define UHCI_TXFIFO_TIMEOUT_ENA_S 11
/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16;
* a
*/
#define UHCI_RXFIFO_TIMEOUT 0x000000FFU
#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S)
#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU
#define UHCI_RXFIFO_TIMEOUT_S 12
/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0;
* a
*/
#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U
#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S)
#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U
#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1;
* a
*/
#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23))
#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S)
#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U
#define UHCI_RXFIFO_TIMEOUT_ENA_S 23
/** UHCI_ACK_NUM_REG register
* a
*/
#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28)
/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0;
* a
*/
#define UHCI_ACK_NUM 0x00000007U
#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S)
#define UHCI_ACK_NUM_V 0x00000007U
#define UHCI_ACK_NUM_S 0
/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0;
* a
*/
#define UHCI_ACK_NUM_LOAD (BIT(3))
#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S)
#define UHCI_ACK_NUM_LOAD_V 0x00000001U
#define UHCI_ACK_NUM_LOAD_S 3
/** UHCI_RX_HEAD_REG register
* a
*/
#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c)
/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_RX_HEAD 0xFFFFFFFFU
#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S)
#define UHCI_RX_HEAD_V 0xFFFFFFFFU
#define UHCI_RX_HEAD_S 0
/** UHCI_QUICK_SENT_REG register
* a
*/
#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30)
/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0;
* a
*/
#define UHCI_SINGLE_SEND_NUM 0x00000007U
#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S)
#define UHCI_SINGLE_SEND_NUM_V 0x00000007U
#define UHCI_SINGLE_SEND_NUM_S 0
/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0;
* a
*/
#define UHCI_SINGLE_SEND_EN (BIT(3))
#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S)
#define UHCI_SINGLE_SEND_EN_V 0x00000001U
#define UHCI_SINGLE_SEND_EN_S 3
/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0;
* a
*/
#define UHCI_ALWAYS_SEND_NUM 0x00000007U
#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S)
#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U
#define UHCI_ALWAYS_SEND_NUM_S 4
/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0;
* a
*/
#define UHCI_ALWAYS_SEND_EN (BIT(7))
#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S)
#define UHCI_ALWAYS_SEND_EN_V 0x00000001U
#define UHCI_ALWAYS_SEND_EN_S 7
/** UHCI_REG_Q0_WORD0_REG register
* a
*/
#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34)
/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU
#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S)
#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU
#define UHCI_SEND_Q0_WORD0_S 0
/** UHCI_REG_Q0_WORD1_REG register
* a
*/
#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38)
/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU
#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S)
#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU
#define UHCI_SEND_Q0_WORD1_S 0
/** UHCI_REG_Q1_WORD0_REG register
* a
*/
#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c)
/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU
#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S)
#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU
#define UHCI_SEND_Q1_WORD0_S 0
/** UHCI_REG_Q1_WORD1_REG register
* a
*/
#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40)
/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU
#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S)
#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU
#define UHCI_SEND_Q1_WORD1_S 0
/** UHCI_REG_Q2_WORD0_REG register
* a
*/
#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44)
/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU
#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S)
#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU
#define UHCI_SEND_Q2_WORD0_S 0
/** UHCI_REG_Q2_WORD1_REG register
* a
*/
#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48)
/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU
#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S)
#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU
#define UHCI_SEND_Q2_WORD1_S 0
/** UHCI_REG_Q3_WORD0_REG register
* a
*/
#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c)
/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU
#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S)
#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU
#define UHCI_SEND_Q3_WORD0_S 0
/** UHCI_REG_Q3_WORD1_REG register
* a
*/
#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50)
/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU
#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S)
#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU
#define UHCI_SEND_Q3_WORD1_S 0
/** UHCI_REG_Q4_WORD0_REG register
* a
*/
#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54)
/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU
#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S)
#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU
#define UHCI_SEND_Q4_WORD0_S 0
/** UHCI_REG_Q4_WORD1_REG register
* a
*/
#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58)
/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU
#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S)
#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU
#define UHCI_SEND_Q4_WORD1_S 0
/** UHCI_REG_Q5_WORD0_REG register
* a
*/
#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c)
/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU
#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S)
#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU
#define UHCI_SEND_Q5_WORD0_S 0
/** UHCI_REG_Q5_WORD1_REG register
* a
*/
#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60)
/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU
#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S)
#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU
#define UHCI_SEND_Q5_WORD1_S 0
/** UHCI_REG_Q6_WORD0_REG register
* a
*/
#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64)
/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU
#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S)
#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU
#define UHCI_SEND_Q6_WORD0_S 0
/** UHCI_REG_Q6_WORD1_REG register
* a
*/
#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68)
/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU
#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S)
#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU
#define UHCI_SEND_Q6_WORD1_S 0
/** UHCI_ESC_CONF0_REG register
* a
*/
#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c)
/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192;
* a
*/
#define UHCI_SEPER_CHAR 0x000000FFU
#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S)
#define UHCI_SEPER_CHAR_V 0x000000FFU
#define UHCI_SEPER_CHAR_S 0
/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
#define UHCI_SEPER_ESC_CHAR0 0x000000FFU
#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S)
#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU
#define UHCI_SEPER_ESC_CHAR0_S 8
/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220;
* a
*/
#define UHCI_SEPER_ESC_CHAR1 0x000000FFU
#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S)
#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU
#define UHCI_SEPER_ESC_CHAR1_S 16
/** UHCI_ESC_CONF1_REG register
* a
*/
#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70)
/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219;
* a
*/
#define UHCI_ESC_SEQ0 0x000000FFU
#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S)
#define UHCI_ESC_SEQ0_V 0x000000FFU
#define UHCI_ESC_SEQ0_S 0
/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU
#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S)
#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU
#define UHCI_ESC_SEQ0_CHAR0_S 8
/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221;
* a
*/
#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU
#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S)
#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU
#define UHCI_ESC_SEQ0_CHAR1_S 16
/** UHCI_ESC_CONF2_REG register
* a
*/
#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74)
/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17;
* a
*/
#define UHCI_ESC_SEQ1 0x000000FFU
#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S)
#define UHCI_ESC_SEQ1_V 0x000000FFU
#define UHCI_ESC_SEQ1_S 0
/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU
#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S)
#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU
#define UHCI_ESC_SEQ1_CHAR0_S 8
/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222;
* a
*/
#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU
#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S)
#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU
#define UHCI_ESC_SEQ1_CHAR1_S 16
/** UHCI_ESC_CONF3_REG register
* a
*/
#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78)
/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19;
* a
*/
#define UHCI_ESC_SEQ2 0x000000FFU
#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S)
#define UHCI_ESC_SEQ2_V 0x000000FFU
#define UHCI_ESC_SEQ2_S 0
/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU
#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S)
#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU
#define UHCI_ESC_SEQ2_CHAR0_S 8
/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223;
* a
*/
#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU
#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S)
#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU
#define UHCI_ESC_SEQ2_CHAR1_S 16
/** UHCI_PKT_THRES_REG register
* a
*/
#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c)
/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128;
* a
*/
#define UHCI_PKT_THRS 0x00001FFFU
#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S)
#define UHCI_PKT_THRS_V 0x00001FFFU
#define UHCI_PKT_THRS_S 0
/** UHCI_DATE_REG register
* a
*/
#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80)
/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936;
* a
*/
#define UHCI_DATE 0xFFFFFFFFU
#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S)
#define UHCI_DATE_V 0xFFFFFFFFU
#define UHCI_DATE_S 0
#ifdef __cplusplus
}
#endif

821
components/soc/esp32h21/register/soc/uhci_struct.h Normal file
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@ -0,0 +1,821 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of conf0 register
* a
*/
typedef union {
struct {
/** tx_rst : R/W; bitpos: [0]; default: 0;
* Write 1 then write 0 to this bit to reset decode state machine.
*/
uint32_t tx_rst:1;
/** rx_rst : R/W; bitpos: [1]; default: 0;
* Write 1 then write 0 to this bit to reset encode state machine.
*/
uint32_t rx_rst:1;
/** uart0_ce : R/W; bitpos: [2]; default: 0;
* Set this bit to link up HCI and UART0.
*/
uint32_t uart0_ce:1;
/** uart1_ce : R/W; bitpos: [3]; default: 0;
* Set this bit to link up HCI and UART1.
*/
uint32_t uart1_ce:1;
uint32_t reserved_4:1;
/** seper_en : R/W; bitpos: [5]; default: 1;
* Set this bit to separate the data frame using a special char.
*/
uint32_t seper_en:1;
/** head_en : R/W; bitpos: [6]; default: 1;
* Set this bit to encode the data packet with a formatting header.
*/
uint32_t head_en:1;
/** crc_rec_en : R/W; bitpos: [7]; default: 1;
* Set this bit to enable UHCI to receive the 16 bit CRC.
*/
uint32_t crc_rec_en:1;
/** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
* If this bit is set to 1 UHCI will end the payload receiving process when UART has
* been in idle state.
*/
uint32_t uart_idle_eof_en:1;
/** len_eof_en : R/W; bitpos: [9]; default: 1;
* If this bit is set to 1 UHCI decoder receiving payload data is end when the
* receiving byte count has reached the specified value. The value is payload length
* indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
* configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
* receiving payload data is end when 0xc0 is received.
*/
uint32_t len_eof_en:1;
/** encode_crc_en : R/W; bitpos: [10]; default: 1;
* Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
* end of the payload.
*/
uint32_t encode_crc_en:1;
/** clk_en : R/W; bitpos: [11]; default: 0;
* 1'b1: Force clock on for register. 1'b0: Support clock only when application writes
* registers.
*/
uint32_t clk_en:1;
/** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
* If this bit is set to 1 UHCI will end payload receive process when NULL frame is
* received by UART.
*/
uint32_t uart_rx_brk_eof_en:1;
uint32_t reserved_13:19;
};
uint32_t val;
} uhci_conf0_reg_t;
/** Type of conf1 register
* a
*/
typedef union {
struct {
/** check_sum_en : R/W; bitpos: [0]; default: 1;
* a
*/
uint32_t check_sum_en:1;
/** check_seq_en : R/W; bitpos: [1]; default: 1;
* a
*/
uint32_t check_seq_en:1;
/** crc_disable : R/W; bitpos: [2]; default: 0;
* a
*/
uint32_t crc_disable:1;
/** save_head : R/W; bitpos: [3]; default: 0;
* a
*/
uint32_t save_head:1;
/** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
* a
*/
uint32_t tx_check_sum_re:1;
/** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
* a
*/
uint32_t tx_ack_num_re:1;
uint32_t reserved_6:1;
/** wait_sw_start : R/W; bitpos: [7]; default: 0;
* a
*/
uint32_t wait_sw_start:1;
/** sw_start : WT; bitpos: [8]; default: 0;
* a
*/
uint32_t sw_start:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_conf1_reg_t;
/** Type of escape_conf register
* a
*/
typedef union {
struct {
/** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
* a
*/
uint32_t tx_c0_esc_en:1;
/** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
* a
*/
uint32_t tx_db_esc_en:1;
/** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
* a
*/
uint32_t tx_11_esc_en:1;
/** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
* a
*/
uint32_t tx_13_esc_en:1;
/** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
* a
*/
uint32_t rx_c0_esc_en:1;
/** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
* a
*/
uint32_t rx_db_esc_en:1;
/** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
* a
*/
uint32_t rx_11_esc_en:1;
/** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
* a
*/
uint32_t rx_13_esc_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} uhci_escape_conf_reg_t;
/** Type of hung_conf register
* a
*/
typedef union {
struct {
/** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
* a
*/
uint32_t txfifo_timeout:8;
/** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
* a
*/
uint32_t txfifo_timeout_shift:3;
/** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
* a
*/
uint32_t txfifo_timeout_ena:1;
/** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
* a
*/
uint32_t rxfifo_timeout:8;
/** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
* a
*/
uint32_t rxfifo_timeout_shift:3;
/** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
* a
*/
uint32_t rxfifo_timeout_ena:1;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_hung_conf_reg_t;
/** Type of ack_num register
* a
*/
typedef union {
struct {
/** ack_num : R/W; bitpos: [2:0]; default: 0;
* a
*/
uint32_t ack_num:3;
/** ack_num_load : WT; bitpos: [3]; default: 0;
* a
*/
uint32_t ack_num_load:1;
uint32_t reserved_4:28;
};
uint32_t val;
} uhci_ack_num_reg_t;
/** Type of quick_sent register
* a
*/
typedef union {
struct {
/** single_send_num : R/W; bitpos: [2:0]; default: 0;
* a
*/
uint32_t single_send_num:3;
/** single_send_en : WT; bitpos: [3]; default: 0;
* a
*/
uint32_t single_send_en:1;
/** always_send_num : R/W; bitpos: [6:4]; default: 0;
* a
*/
uint32_t always_send_num:3;
/** always_send_en : R/W; bitpos: [7]; default: 0;
* a
*/
uint32_t always_send_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} uhci_quick_sent_reg_t;
/** Type of reg_q0_word0 register
* a
*/
typedef union {
struct {
/** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q0_word0:32;
};
uint32_t val;
} uhci_reg_q0_word0_reg_t;
/** Type of reg_q0_word1 register
* a
*/
typedef union {
struct {
/** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q0_word1:32;
};
uint32_t val;
} uhci_reg_q0_word1_reg_t;
/** Type of reg_q1_word0 register
* a
*/
typedef union {
struct {
/** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q1_word0:32;
};
uint32_t val;
} uhci_reg_q1_word0_reg_t;
/** Type of reg_q1_word1 register
* a
*/
typedef union {
struct {
/** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q1_word1:32;
};
uint32_t val;
} uhci_reg_q1_word1_reg_t;
/** Type of reg_q2_word0 register
* a
*/
typedef union {
struct {
/** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q2_word0:32;
};
uint32_t val;
} uhci_reg_q2_word0_reg_t;
/** Type of reg_q2_word1 register
* a
*/
typedef union {
struct {
/** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q2_word1:32;
};
uint32_t val;
} uhci_reg_q2_word1_reg_t;
/** Type of reg_q3_word0 register
* a
*/
typedef union {
struct {
/** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q3_word0:32;
};
uint32_t val;
} uhci_reg_q3_word0_reg_t;
/** Type of reg_q3_word1 register
* a
*/
typedef union {
struct {
/** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q3_word1:32;
};
uint32_t val;
} uhci_reg_q3_word1_reg_t;
/** Type of reg_q4_word0 register
* a
*/
typedef union {
struct {
/** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q4_word0:32;
};
uint32_t val;
} uhci_reg_q4_word0_reg_t;
/** Type of reg_q4_word1 register
* a
*/
typedef union {
struct {
/** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q4_word1:32;
};
uint32_t val;
} uhci_reg_q4_word1_reg_t;
/** Type of reg_q5_word0 register
* a
*/
typedef union {
struct {
/** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q5_word0:32;
};
uint32_t val;
} uhci_reg_q5_word0_reg_t;
/** Type of reg_q5_word1 register
* a
*/
typedef union {
struct {
/** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q5_word1:32;
};
uint32_t val;
} uhci_reg_q5_word1_reg_t;
/** Type of reg_q6_word0 register
* a
*/
typedef union {
struct {
/** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q6_word0:32;
};
uint32_t val;
} uhci_reg_q6_word0_reg_t;
/** Type of reg_q6_word1 register
* a
*/
typedef union {
struct {
/** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q6_word1:32;
};
uint32_t val;
} uhci_reg_q6_word1_reg_t;
/** Type of esc_conf0 register
* a
*/
typedef union {
struct {
/** seper_char : R/W; bitpos: [7:0]; default: 192;
* a
*/
uint32_t seper_char:8;
/** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
uint32_t seper_esc_char0:8;
/** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
* a
*/
uint32_t seper_esc_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf0_reg_t;
/** Type of esc_conf1 register
* a
*/
typedef union {
struct {
/** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
* a
*/
uint32_t esc_seq0:8;
/** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
uint32_t esc_seq0_char0:8;
/** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
* a
*/
uint32_t esc_seq0_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf1_reg_t;
/** Type of esc_conf2 register
* a
*/
typedef union {
struct {
/** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
* a
*/
uint32_t esc_seq1:8;
/** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
uint32_t esc_seq1_char0:8;
/** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
* a
*/
uint32_t esc_seq1_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf2_reg_t;
/** Type of esc_conf3 register
* a
*/
typedef union {
struct {
/** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
* a
*/
uint32_t esc_seq2:8;
/** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
* a
*/
uint32_t esc_seq2_char0:8;
/** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
* a
*/
uint32_t esc_seq2_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf3_reg_t;
/** Type of pkt_thres register
* a
*/
typedef union {
struct {
/** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
* a
*/
uint32_t pkt_thrs:13;
uint32_t reserved_13:19;
};
uint32_t val;
} uhci_pkt_thres_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* a
*/
typedef union {
struct {
/** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* a
*/
uint32_t rx_start_int_raw:1;
/** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* a
*/
uint32_t tx_start_int_raw:1;
/** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* a
*/
uint32_t rx_hung_int_raw:1;
/** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* a
*/
uint32_t tx_hung_int_raw:1;
/** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* a
*/
uint32_t send_s_reg_q_int_raw:1;
/** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* a
*/
uint32_t send_a_reg_q_int_raw:1;
/** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* This is the interrupt raw bit. Triggered when there are some errors in EOF in the
*/
uint32_t out_eof_int_raw:1;
/** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
* Soft control int raw bit.
*/
uint32_t app_ctrl0_int_raw:1;
/** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
* Soft control int raw bit.
*/
uint32_t app_ctrl1_int_raw:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_raw_reg_t;
/** Type of int_st register
* a
*/
typedef union {
struct {
/** rx_start_int_st : RO; bitpos: [0]; default: 0;
* a
*/
uint32_t rx_start_int_st:1;
/** tx_start_int_st : RO; bitpos: [1]; default: 0;
* a
*/
uint32_t tx_start_int_st:1;
/** rx_hung_int_st : RO; bitpos: [2]; default: 0;
* a
*/
uint32_t rx_hung_int_st:1;
/** tx_hung_int_st : RO; bitpos: [3]; default: 0;
* a
*/
uint32_t tx_hung_int_st:1;
/** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
* a
*/
uint32_t send_s_reg_q_int_st:1;
/** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
* a
*/
uint32_t send_a_reg_q_int_st:1;
/** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
* a
*/
uint32_t outlink_eof_err_int_st:1;
/** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
* a
*/
uint32_t app_ctrl0_int_st:1;
/** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
* a
*/
uint32_t app_ctrl1_int_st:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_st_reg_t;
/** Type of int_ena register
* a
*/
typedef union {
struct {
/** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
* a
*/
uint32_t rx_start_int_ena:1;
/** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
* a
*/
uint32_t tx_start_int_ena:1;
/** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
* a
*/
uint32_t rx_hung_int_ena:1;
/** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
* a
*/
uint32_t tx_hung_int_ena:1;
/** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
* a
*/
uint32_t send_s_reg_q_int_ena:1;
/** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
* a
*/
uint32_t send_a_reg_q_int_ena:1;
/** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
* a
*/
uint32_t outlink_eof_err_int_ena:1;
/** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
* a
*/
uint32_t app_ctrl0_int_ena:1;
/** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
* a
*/
uint32_t app_ctrl1_int_ena:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_ena_reg_t;
/** Type of int_clr register
* a
*/
typedef union {
struct {
/** rx_start_int_clr : WT; bitpos: [0]; default: 0;
* a
*/
uint32_t rx_start_int_clr:1;
/** tx_start_int_clr : WT; bitpos: [1]; default: 0;
* a
*/
uint32_t tx_start_int_clr:1;
/** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
* a
*/
uint32_t rx_hung_int_clr:1;
/** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
* a
*/
uint32_t tx_hung_int_clr:1;
/** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
* a
*/
uint32_t send_s_reg_q_int_clr:1;
/** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
* a
*/
uint32_t send_a_reg_q_int_clr:1;
/** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
* a
*/
uint32_t outlink_eof_err_int_clr:1;
/** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
* a
*/
uint32_t app_ctrl0_int_clr:1;
/** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
* a
*/
uint32_t app_ctrl1_int_clr:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_clr_reg_t;
/** Group: UHCI Status Register */
/** Type of state0 register
* a
*/
typedef union {
struct {
/** rx_err_cause : RO; bitpos: [2:0]; default: 0;
* a
*/
uint32_t rx_err_cause:3;
/** decode_state : RO; bitpos: [5:3]; default: 0;
* a
*/
uint32_t decode_state:3;
uint32_t reserved_6:26;
};
uint32_t val;
} uhci_state0_reg_t;
/** Type of state1 register
* a
*/
typedef union {
struct {
/** encode_state : RO; bitpos: [2:0]; default: 0;
* a
*/
uint32_t encode_state:3;
uint32_t reserved_3:29;
};
uint32_t val;
} uhci_state1_reg_t;
/** Type of rx_head register
* a
*/
typedef union {
struct {
/** rx_head : RO; bitpos: [31:0]; default: 0;
* a
*/
uint32_t rx_head:32;
};
uint32_t val;
} uhci_rx_head_reg_t;
/** Group: Version Register */
/** Type of date register
* a
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 35655936;
* a
*/
uint32_t date:32;
};
uint32_t val;
} uhci_date_reg_t;
typedef struct {
volatile uhci_conf0_reg_t conf0;
volatile uhci_int_raw_reg_t int_raw;
volatile uhci_int_st_reg_t int_st;
volatile uhci_int_ena_reg_t int_ena;
volatile uhci_int_clr_reg_t int_clr;
volatile uhci_conf1_reg_t conf1;
volatile uhci_state0_reg_t state0;
volatile uhci_state1_reg_t state1;
volatile uhci_escape_conf_reg_t escape_conf;
volatile uhci_hung_conf_reg_t hung_conf;
volatile uhci_ack_num_reg_t ack_num;
volatile uhci_rx_head_reg_t rx_head;
volatile uhci_quick_sent_reg_t quick_sent;
volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
volatile uhci_esc_conf0_reg_t esc_conf0;
volatile uhci_esc_conf1_reg_t esc_conf1;
volatile uhci_esc_conf2_reg_t esc_conf2;
volatile uhci_esc_conf3_reg_t esc_conf3;
volatile uhci_pkt_thres_reg_t pkt_thres;
volatile uhci_date_reg_t date;
} uhci_dev_t;
extern uhci_dev_t UHCI0;
#ifndef __cplusplus
_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of serial_jtag_ep1 register
* FIFO access for the CDC-ACM data IN and OUT endpoints.
*/
typedef union {
struct {
/** serial_jtag_rdwr_byte : R/W; bitpos: [7:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field. When
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
* bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t serial_jtag_rdwr_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
/** Type of serial_jtag_ep1_conf register
* Configuration and control registers for the CDC-ACM FIFOs.
*/
typedef union {
struct {
/** serial_jtag_wr_done : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
*/
uint32_t serial_jtag_wr_done:1;
/** serial_jtag_serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
* 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
* USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
* USB Host.
*/
uint32_t serial_jtag_serial_in_ep_data_free:1;
/** serial_jtag_serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
* 1'b1: Indicate there is data in UART Rx FIFO.
*/
uint32_t serial_jtag_serial_out_ep_data_avail:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_ep1_conf_reg_t;
/** Type of serial_jtag_conf0 register
* PHY hardware configuration.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** serial_jtag_exchg_pins_override : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D- exchange
*/
uint32_t serial_jtag_exchg_pins_override:1;
/** serial_jtag_exchg_pins : R/W; bitpos: [2]; default: 0;
* USB D+ D- exchange
*/
uint32_t serial_jtag_exchg_pins:1;
/** serial_jtag_vrefh : R/W; bitpos: [4:3]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV
*/
uint32_t serial_jtag_vrefh:2;
/** serial_jtag_vrefl : R/W; bitpos: [6:5]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV
*/
uint32_t serial_jtag_vrefl:2;
/** serial_jtag_vref_override : R/W; bitpos: [7]; default: 0;
* Enable software control input threshold
*/
uint32_t serial_jtag_vref_override:1;
/** serial_jtag_pad_pull_override : R/W; bitpos: [8]; default: 0;
* Enable software control USB D+ D- pullup pulldown
*/
uint32_t serial_jtag_pad_pull_override:1;
/** serial_jtag_dp_pullup : R/W; bitpos: [9]; default: 1;
* Control USB D+ pull up.
*/
uint32_t serial_jtag_dp_pullup:1;
/** serial_jtag_dp_pulldown : R/W; bitpos: [10]; default: 0;
* Control USB D+ pull down.
*/
uint32_t serial_jtag_dp_pulldown:1;
/** serial_jtag_dm_pullup : R/W; bitpos: [11]; default: 0;
* Control USB D- pull up.
*/
uint32_t serial_jtag_dm_pullup:1;
/** serial_jtag_dm_pulldown : R/W; bitpos: [12]; default: 0;
* Control USB D- pull down.
*/
uint32_t serial_jtag_dm_pulldown:1;
/** serial_jtag_pullup_value : R/W; bitpos: [13]; default: 0;
* Control pull up value.
*/
uint32_t serial_jtag_pullup_value:1;
/** serial_jtag_usb_pad_enable : R/W; bitpos: [14]; default: 1;
* Enable USB pad function.
*/
uint32_t serial_jtag_usb_pad_enable:1;
/** serial_jtag_usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
* Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
* disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
* through GPIO Matrix.
*/
uint32_t serial_jtag_usb_jtag_bridge_en:1;
/** serial_jtag_usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0;
* Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at
* clock negative edge. 1: tx output at clock positive edge.
*/
uint32_t serial_jtag_usb_phy_tx_edge_sel:1;
uint32_t reserved_17:15;
};
uint32_t val;
} usb_serial_jtag_conf0_reg_t;
/** Type of serial_jtag_test register
* Registers used for debugging the PHY.
*/
typedef union {
struct {
/** serial_jtag_test_enable : R/W; bitpos: [0]; default: 0;
* Enable test of the USB pad
*/
uint32_t serial_jtag_test_enable:1;
/** serial_jtag_test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
*/
uint32_t serial_jtag_test_usb_oe:1;
/** serial_jtag_test_tx_dp : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in test
*/
uint32_t serial_jtag_test_tx_dp:1;
/** serial_jtag_test_tx_dm : R/W; bitpos: [3]; default: 0;
* USB D- tx value in test
*/
uint32_t serial_jtag_test_tx_dm:1;
/** serial_jtag_test_rx_rcv : RO; bitpos: [4]; default: 1;
* USB RCV value in test
*/
uint32_t serial_jtag_test_rx_rcv:1;
/** serial_jtag_test_rx_dp : RO; bitpos: [5]; default: 1;
* USB D+ rx value in test
*/
uint32_t serial_jtag_test_rx_dp:1;
/** serial_jtag_test_rx_dm : RO; bitpos: [6]; default: 0;
* USB D- rx value in test
*/
uint32_t serial_jtag_test_rx_dm:1;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_serial_jtag_test_reg_t;
/** Type of serial_jtag_misc_conf register
* Clock enable control
*/
typedef union {
struct {
/** serial_jtag_clk_en : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when application writes
* registers.
*/
uint32_t serial_jtag_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_misc_conf_reg_t;
/** Type of serial_jtag_mem_conf register
* Memory power control
*/
typedef union {
struct {
/** serial_jtag_usb_mem_pd : R/W; bitpos: [0]; default: 0;
* 1: power down usb memory.
*/
uint32_t serial_jtag_usb_mem_pd:1;
/** serial_jtag_usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
* 1: Force clock on for usb memory.
*/
uint32_t serial_jtag_usb_mem_clk_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_serial_jtag_mem_conf_reg_t;
/** Type of serial_jtag_chip_rst register
* CDC-ACM chip reset control.
*/
typedef union {
struct {
/** serial_jtag_rts : RO; bitpos: [0]; default: 0;
* 1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
*/
uint32_t serial_jtag_rts:1;
/** serial_jtag_dtr : RO; bitpos: [1]; default: 0;
* 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
*/
uint32_t serial_jtag_dtr:1;
/** serial_jtag_usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
* Set this bit to disable chip reset from usb serial channel to reset chip.
*/
uint32_t serial_jtag_usb_uart_chip_rst_dis:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_chip_rst_reg_t;
/** Type of serial_jtag_get_line_code_w0 register
* W0 of GET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
* The value of dwDTERate set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_dw_dte_rate:32;
};
uint32_t val;
} usb_serial_jtag_get_line_code_w0_reg_t;
/** Type of serial_jtag_get_line_code_w1 register
* W1 of GET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
* The value of bCharFormat set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_bdata_bits:8;
/** serial_jtag_get_bparity_type : R/W; bitpos: [15:8]; default: 0;
* The value of bParityTpye set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_bparity_type:8;
/** serial_jtag_get_bchar_format : R/W; bitpos: [23:16]; default: 0;
* The value of bDataBits set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_bchar_format:8;
uint32_t reserved_24:8;
};
uint32_t val;
} usb_serial_jtag_get_line_code_w1_reg_t;
/** Type of serial_jtag_config_update register
* Configuration registers' value update
*/
typedef union {
struct {
/** serial_jtag_config_update : WT; bitpos: [0]; default: 0;
* Write 1 to this register would update the value of configure registers from APB
* clock domain to 48MHz clock domain.
*/
uint32_t serial_jtag_config_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_config_update_reg_t;
/** Type of serial_jtag_ser_afifo_config register
* Serial AFIFO configure register
*/
typedef union {
struct {
/** serial_jtag_serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
* Write 1 to reset CDC_ACM IN async FIFO write clock domain.
*/
uint32_t serial_jtag_serial_in_afifo_reset_wr:1;
/** serial_jtag_serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
* Write 1 to reset CDC_ACM IN async FIFO read clock domain.
*/
uint32_t serial_jtag_serial_in_afifo_reset_rd:1;
/** serial_jtag_serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
* Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
*/
uint32_t serial_jtag_serial_out_afifo_reset_wr:1;
/** serial_jtag_serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
* Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
*/
uint32_t serial_jtag_serial_out_afifo_reset_rd:1;
/** serial_jtag_serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/
uint32_t serial_jtag_serial_out_afifo_rempty:1;
/** serial_jtag_serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
* CDC_ACM OUT IN async FIFO empty signal in write clock domain.
*/
uint32_t serial_jtag_serial_in_afifo_wfull:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_serial_jtag_ser_afifo_config_reg_t;
/** Type of serial_jtag_serial_ep_timeout0 register
* USB uart out endpoint timeout configuration.
*/
typedef union {
struct {
/** serial_jtag_serial_timeout_en : R/W; bitpos: [0]; default: 0;
* USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
* is automatically cleared and reg_serial_timeout_status is asserted.
*/
uint32_t serial_jtag_serial_timeout_en:1;
/** serial_jtag_serial_timeout_status : R/WTC/SS; bitpos: [1]; default: 0;
* Serial out ep triggers a timeout event.
*/
uint32_t serial_jtag_serial_timeout_status:1;
/** serial_jtag_serial_timeout_status_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear reg_serial_timeout_status.
*/
uint32_t serial_jtag_serial_timeout_status_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_serial_ep_timeout0_reg_t;
/** Type of serial_jtag_serial_ep_timeout1 register
* USB uart out endpoint timeout configuration.
*/
typedef union {
struct {
/** serial_jtag_serial_timeout_max : R/W; bitpos: [31:0]; default: 4800768;
* USB serial out ep timeout max threshold value, indicates the maximum time that
* waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
*/
uint32_t serial_jtag_serial_timeout_max:32;
};
uint32_t val;
} usb_serial_jtag_serial_ep_timeout1_reg_t;
/** Group: Interrupt Registers */
/** Type of serial_jtag_int_raw register
* Interrupt raw status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when flush cmd is received for IN
* endpoint 2 of JTAG.
*/
uint32_t serial_jtag_jtag_in_flush_int_raw:1;
/** serial_jtag_sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when SOF frame is received.
*/
uint32_t serial_jtag_sof_int_raw:1;
/** serial_jtag_serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
* one packet.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_raw:1;
/** serial_jtag_serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
* The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
*/
uint32_t serial_jtag_serial_in_empty_int_raw:1;
/** serial_jtag_pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when pid error is detected.
*/
uint32_t serial_jtag_pid_err_int_raw:1;
/** serial_jtag_crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt bit turns to high level when CRC5 error is detected.
*/
uint32_t serial_jtag_crc5_err_int_raw:1;
/** serial_jtag_crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt bit turns to high level when CRC16 error is detected.
*/
uint32_t serial_jtag_crc16_err_int_raw:1;
/** serial_jtag_stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt bit turns to high level when stuff error is detected.
*/
uint32_t serial_jtag_stuff_err_int_raw:1;
/** serial_jtag_in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
* received.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_raw:1;
/** serial_jtag_usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The raw interrupt bit turns to high level when usb bus reset is detected.
*/
uint32_t serial_jtag_usb_bus_reset_int_raw:1;
/** serial_jtag_out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
* zero palyload.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_raw:1;
/** serial_jtag_out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
* zero palyload.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_raw:1;
/** serial_jtag_rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The raw interrupt bit turns to high level when level of RTS from usb serial channel
* is changed.
*/
uint32_t serial_jtag_rts_chg_int_raw:1;
/** serial_jtag_dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The raw interrupt bit turns to high level when level of DTR from usb serial channel
* is changed.
*/
uint32_t serial_jtag_dtr_chg_int_raw:1;
/** serial_jtag_get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
* The raw interrupt bit turns to high level when level of GET LINE CODING request is
* received.
*/
uint32_t serial_jtag_get_line_code_int_raw:1;
/** serial_jtag_set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
* The raw interrupt bit turns to high level when level of SET LINE CODING request is
* received.
*/
uint32_t serial_jtag_set_line_code_int_raw:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_raw_reg_t;
/** Type of serial_jtag_int_st register
* Interrupt status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t serial_jtag_jtag_in_flush_int_st:1;
/** serial_jtag_sof_int_st : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t serial_jtag_sof_int_st:1;
/** serial_jtag_serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_st:1;
/** serial_jtag_serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_jtag_serial_in_empty_int_st:1;
/** serial_jtag_pid_err_int_st : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t serial_jtag_pid_err_int_st:1;
/** serial_jtag_crc5_err_int_st : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc5_err_int_st:1;
/** serial_jtag_crc16_err_int_st : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc16_err_int_st:1;
/** serial_jtag_stuff_err_int_st : RO; bitpos: [7]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t serial_jtag_stuff_err_int_st:1;
/** serial_jtag_in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_st:1;
/** serial_jtag_usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t serial_jtag_usb_bus_reset_int_st:1;
/** serial_jtag_out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_st:1;
/** serial_jtag_out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_st:1;
/** serial_jtag_rts_chg_int_st : RO; bitpos: [12]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t serial_jtag_rts_chg_int_st:1;
/** serial_jtag_dtr_chg_int_st : RO; bitpos: [13]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t serial_jtag_dtr_chg_int_st:1;
/** serial_jtag_get_line_code_int_st : RO; bitpos: [14]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_get_line_code_int_st:1;
/** serial_jtag_set_line_code_int_st : RO; bitpos: [15]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_set_line_code_int_st:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_st_reg_t;
/** Type of serial_jtag_int_ena register
* Interrupt enable status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t serial_jtag_jtag_in_flush_int_ena:1;
/** serial_jtag_sof_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t serial_jtag_sof_int_ena:1;
/** serial_jtag_serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_ena:1;
/** serial_jtag_serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_jtag_serial_in_empty_int_ena:1;
/** serial_jtag_pid_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t serial_jtag_pid_err_int_ena:1;
/** serial_jtag_crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc5_err_int_ena:1;
/** serial_jtag_crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc16_err_int_ena:1;
/** serial_jtag_stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t serial_jtag_stuff_err_int_ena:1;
/** serial_jtag_in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_ena:1;
/** serial_jtag_usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t serial_jtag_usb_bus_reset_int_ena:1;
/** serial_jtag_out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_ena:1;
/** serial_jtag_out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_ena:1;
/** serial_jtag_rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t serial_jtag_rts_chg_int_ena:1;
/** serial_jtag_dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t serial_jtag_dtr_chg_int_ena:1;
/** serial_jtag_get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_get_line_code_int_ena:1;
/** serial_jtag_set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_set_line_code_int_ena:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_ena_reg_t;
/** Type of serial_jtag_int_clr register
* Interrupt clear status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t serial_jtag_jtag_in_flush_int_clr:1;
/** serial_jtag_sof_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
*/
uint32_t serial_jtag_sof_int_clr:1;
/** serial_jtag_serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_clr:1;
/** serial_jtag_serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_jtag_serial_in_empty_int_clr:1;
/** serial_jtag_pid_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t serial_jtag_pid_err_int_clr:1;
/** serial_jtag_crc5_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc5_err_int_clr:1;
/** serial_jtag_crc16_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc16_err_int_clr:1;
/** serial_jtag_stuff_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t serial_jtag_stuff_err_int_clr:1;
/** serial_jtag_in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_clr:1;
/** serial_jtag_usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t serial_jtag_usb_bus_reset_int_clr:1;
/** serial_jtag_out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_clr:1;
/** serial_jtag_out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_clr:1;
/** serial_jtag_rts_chg_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t serial_jtag_rts_chg_int_clr:1;
/** serial_jtag_dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t serial_jtag_dtr_chg_int_clr:1;
/** serial_jtag_get_line_code_int_clr : WT; bitpos: [14]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_get_line_code_int_clr:1;
/** serial_jtag_set_line_code_int_clr : WT; bitpos: [15]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_set_line_code_int_clr:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_clr_reg_t;
/** Group: Status Registers */
/** Type of serial_jtag_jfifo_st register
* JTAG FIFO status and control registers.
*/
typedef union {
struct {
/** serial_jtag_in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
* JTAT in fifo counter.
*/
uint32_t serial_jtag_in_fifo_cnt:2;
/** serial_jtag_in_fifo_empty : RO; bitpos: [2]; default: 1;
* 1: JTAG in fifo is empty.
*/
uint32_t serial_jtag_in_fifo_empty:1;
/** serial_jtag_in_fifo_full : RO; bitpos: [3]; default: 0;
* 1: JTAG in fifo is full.
*/
uint32_t serial_jtag_in_fifo_full:1;
/** serial_jtag_out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
* JTAT out fifo counter.
*/
uint32_t serial_jtag_out_fifo_cnt:2;
/** serial_jtag_out_fifo_empty : RO; bitpos: [6]; default: 1;
* 1: JTAG out fifo is empty.
*/
uint32_t serial_jtag_out_fifo_empty:1;
/** serial_jtag_out_fifo_full : RO; bitpos: [7]; default: 0;
* 1: JTAG out fifo is full.
*/
uint32_t serial_jtag_out_fifo_full:1;
/** serial_jtag_in_fifo_reset : R/W; bitpos: [8]; default: 0;
* Write 1 to reset JTAG in fifo.
*/
uint32_t serial_jtag_in_fifo_reset:1;
/** serial_jtag_out_fifo_reset : R/W; bitpos: [9]; default: 0;
* Write 1 to reset JTAG out fifo.
*/
uint32_t serial_jtag_out_fifo_reset:1;
uint32_t reserved_10:22;
};
uint32_t val;
} usb_serial_jtag_jfifo_st_reg_t;
/** Type of serial_jtag_fram_num register
* Last received SOF frame index register.
*/
typedef union {
struct {
/** serial_jtag_sof_frame_index : RO; bitpos: [10:0]; default: 0;
* Frame index of received SOF frame.
*/
uint32_t serial_jtag_sof_frame_index:11;
uint32_t reserved_11:21;
};
uint32_t val;
} usb_serial_jtag_fram_num_reg_t;
/** Type of serial_jtag_in_ep0_st register
* Control IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep0_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 0.
*/
uint32_t serial_jtag_in_ep0_state:2;
/** serial_jtag_in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 0.
*/
uint32_t serial_jtag_in_ep0_wr_addr:7;
/** serial_jtag_in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 0.
*/
uint32_t serial_jtag_in_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep0_st_reg_t;
/** Type of serial_jtag_in_ep1_st register
* CDC-ACM IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep1_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 1.
*/
uint32_t serial_jtag_in_ep1_state:2;
/** serial_jtag_in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 1.
*/
uint32_t serial_jtag_in_ep1_wr_addr:7;
/** serial_jtag_in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 1.
*/
uint32_t serial_jtag_in_ep1_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep1_st_reg_t;
/** Type of serial_jtag_in_ep2_st register
* CDC-ACM interrupt IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep2_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 2.
*/
uint32_t serial_jtag_in_ep2_state:2;
/** serial_jtag_in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 2.
*/
uint32_t serial_jtag_in_ep2_wr_addr:7;
/** serial_jtag_in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 2.
*/
uint32_t serial_jtag_in_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep2_st_reg_t;
/** Type of serial_jtag_in_ep3_st register
* JTAG IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep3_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 3.
*/
uint32_t serial_jtag_in_ep3_state:2;
/** serial_jtag_in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 3.
*/
uint32_t serial_jtag_in_ep3_wr_addr:7;
/** serial_jtag_in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 3.
*/
uint32_t serial_jtag_in_ep3_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep3_st_reg_t;
/** Type of serial_jtag_out_ep0_st register
* Control OUT endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_out_ep0_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 0.
*/
uint32_t serial_jtag_out_ep0_state:2;
/** serial_jtag_out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
*/
uint32_t serial_jtag_out_ep0_wr_addr:7;
/** serial_jtag_out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 0.
*/
uint32_t serial_jtag_out_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep0_st_reg_t;
/** Type of serial_jtag_out_ep1_st register
* CDC-ACM OUT endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_out_ep1_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 1.
*/
uint32_t serial_jtag_out_ep1_state:2;
/** serial_jtag_out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
*/
uint32_t serial_jtag_out_ep1_wr_addr:7;
/** serial_jtag_out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 1.
*/
uint32_t serial_jtag_out_ep1_rd_addr:7;
/** serial_jtag_out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
* Data count in OUT endpoint 1 when one packet is received.
*/
uint32_t serial_jtag_out_ep1_rec_data_cnt:7;
uint32_t reserved_23:9;
};
uint32_t val;
} usb_serial_jtag_out_ep1_st_reg_t;
/** Type of serial_jtag_out_ep2_st register
* JTAG OUT endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_out_ep2_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 2.
*/
uint32_t serial_jtag_out_ep2_state:2;
/** serial_jtag_out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
*/
uint32_t serial_jtag_out_ep2_wr_addr:7;
/** serial_jtag_out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 2.
*/
uint32_t serial_jtag_out_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep2_st_reg_t;
/** Type of serial_jtag_set_line_code_w0 register
* W0 of SET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_dw_dte_rate : RO; bitpos: [31:0]; default: 0;
* The value of dwDTERate set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_dw_dte_rate:32;
};
uint32_t val;
} usb_serial_jtag_set_line_code_w0_reg_t;
/** Type of serial_jtag_set_line_code_w1 register
* W1 of SET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_bchar_format : RO; bitpos: [7:0]; default: 0;
* The value of bCharFormat set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_bchar_format:8;
/** serial_jtag_bparity_type : RO; bitpos: [15:8]; default: 0;
* The value of bParityTpye set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_bparity_type:8;
/** serial_jtag_bdata_bits : RO; bitpos: [23:16]; default: 0;
* The value of bDataBits set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_bdata_bits:8;
uint32_t reserved_24:8;
};
uint32_t val;
} usb_serial_jtag_set_line_code_w1_reg_t;
/** Type of serial_jtag_bus_reset_st register
* USB Bus reset status register
*/
typedef union {
struct {
/** serial_jtag_usb_bus_reset_st : RO; bitpos: [0]; default: 1;
* USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
* reset is released.
*/
uint32_t serial_jtag_usb_bus_reset_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_bus_reset_st_reg_t;
/** Group: Version Registers */
/** Type of serial_jtag_date register
* Date register
*/
typedef union {
struct {
/** serial_jtag_date : R/W; bitpos: [31:0]; default: 37777456;
* register version.
*/
uint32_t serial_jtag_date:32;
};
uint32_t val;
} usb_serial_jtag_date_reg_t;
typedef struct {
volatile usb_serial_jtag_ep1_reg_t serial_jtag_ep1;
volatile usb_serial_jtag_ep1_conf_reg_t serial_jtag_ep1_conf;
volatile usb_serial_jtag_int_raw_reg_t serial_jtag_int_raw;
volatile usb_serial_jtag_int_st_reg_t serial_jtag_int_st;
volatile usb_serial_jtag_int_ena_reg_t serial_jtag_int_ena;
volatile usb_serial_jtag_int_clr_reg_t serial_jtag_int_clr;
volatile usb_serial_jtag_conf0_reg_t serial_jtag_conf0;
volatile usb_serial_jtag_test_reg_t serial_jtag_test;
volatile usb_serial_jtag_jfifo_st_reg_t serial_jtag_jfifo_st;
volatile usb_serial_jtag_fram_num_reg_t serial_jtag_fram_num;
volatile usb_serial_jtag_in_ep0_st_reg_t serial_jtag_in_ep0_st;
volatile usb_serial_jtag_in_ep1_st_reg_t serial_jtag_in_ep1_st;
volatile usb_serial_jtag_in_ep2_st_reg_t serial_jtag_in_ep2_st;
volatile usb_serial_jtag_in_ep3_st_reg_t serial_jtag_in_ep3_st;
volatile usb_serial_jtag_out_ep0_st_reg_t serial_jtag_out_ep0_st;
volatile usb_serial_jtag_out_ep1_st_reg_t serial_jtag_out_ep1_st;
volatile usb_serial_jtag_out_ep2_st_reg_t serial_jtag_out_ep2_st;
volatile usb_serial_jtag_misc_conf_reg_t serial_jtag_misc_conf;
volatile usb_serial_jtag_mem_conf_reg_t serial_jtag_mem_conf;
volatile usb_serial_jtag_chip_rst_reg_t serial_jtag_chip_rst;
volatile usb_serial_jtag_set_line_code_w0_reg_t serial_jtag_set_line_code_w0;
volatile usb_serial_jtag_set_line_code_w1_reg_t serial_jtag_set_line_code_w1;
volatile usb_serial_jtag_get_line_code_w0_reg_t serial_jtag_get_line_code_w0;
volatile usb_serial_jtag_get_line_code_w1_reg_t serial_jtag_get_line_code_w1;
volatile usb_serial_jtag_config_update_reg_t serial_jtag_config_update;
volatile usb_serial_jtag_ser_afifo_config_reg_t serial_jtag_ser_afifo_config;
volatile usb_serial_jtag_bus_reset_st_reg_t serial_jtag_bus_reset_st;
volatile usb_serial_jtag_serial_ep_timeout0_reg_t serial_jtag_serial_ep_timeout0;
volatile usb_serial_jtag_serial_ep_timeout1_reg_t serial_jtag_serial_ep_timeout1;
uint32_t reserved_074[3];
volatile usb_serial_jtag_date_reg_t serial_jtag_date;
} usb_serial_jtag_dev_t;
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
#ifndef __cplusplus
_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif