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feat(bitscrambler): add hal driver support

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This commit is contained in:
Jeroen Domburg
2023-12-06 15:13:45 +08:00
committed by morris
parent 7ff774905a
commit ab75a94877
13 changed files with 619 additions and 68 deletions
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6
components/esp_system/port/soc/esp32p4/clk.c
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@@ -253,9 +253,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
_pau_ll_enable_bus_clock(false);
_parlio_ll_enable_bus_clock(0, false);
_etm_ll_enable_bus_clock(0, false);
REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN);
// Non-Console UART
#if CONFIG_ESP_CONSOLE_UART_NUM != 0

5
components/hal/CMakeLists.txt
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@@ -30,6 +30,11 @@ if(CONFIG_SOC_KEY_MANAGER_SUPPORTED)
list(APPEND srcs "huk_hal.c")
endif()
if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED)
list(APPEND srcs "${target}/bitscrambler_periph.c")
endif()
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
if(CONFIG_SOC_MMU_PERIPH_NUM)
list(APPEND srcs "mmu_hal.c")

29
components/hal/esp32p4/bitscrambler_periph.c Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/bitscrambler_hal.h"
const bitscrambler_regs_t bitscramblers_reg[2]={
{ //BITSCRAMBLER_DIR_TX
.inst_cfg0=&BITSCRAMBLER.tx_inst_cfg0,
.inst_cfg1=&BITSCRAMBLER.tx_inst_cfg1,
.lut_cfg0=&BITSCRAMBLER.tx_lut_cfg0,
.lut_cfg1=&BITSCRAMBLER.tx_lut_cfg1,
.trailing_bits=&BITSCRAMBLER.tx_tailing_bits,
.ctrl=&BITSCRAMBLER.tx_ctrl,
.state=&BITSCRAMBLER.tx_state,
},
{ //BITSCRAMBLER_DIR_RX
//Note that this assumes the RX and TX registers are exactly the same. If there's
//ever a chip where this is not the case, we need to rework this.
.inst_cfg0=(bitscrambler_tx_inst_cfg0_reg_t*)&BITSCRAMBLER.rx_inst_cfg0,
.inst_cfg1=(bitscrambler_tx_inst_cfg1_reg_t*)&BITSCRAMBLER.rx_inst_cfg1,
.lut_cfg0=(bitscrambler_tx_lut_cfg0_reg_t*)&BITSCRAMBLER.rx_lut_cfg0,
.lut_cfg1=(bitscrambler_tx_lut_cfg1_reg_t*)&BITSCRAMBLER.rx_lut_cfg1,
.trailing_bits=(bitscrambler_tx_tailing_bits_reg_t*)&BITSCRAMBLER.rx_tailing_bits,
.ctrl=(bitscrambler_tx_ctrl_reg_t*)&BITSCRAMBLER.rx_ctrl,
.state=(bitscrambler_tx_state_reg_t*)&BITSCRAMBLER.rx_state,
}
};

345
components/hal/esp32p4/include/hal/bitscrambler_ll.h Normal file
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@@ -0,0 +1,345 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <limits.h>
#include <stdlib.h>
#include <stdbool.h>
#include "soc/bitscrambler_struct.h"
#include "hal/bitscrambler_types.h"
#include "hal/bitscrambler_hal.h"
#include "hal/misc.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/hp_system_struct.h"
#include "hal/hal_utils.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define BITSCRAMBLER_LL_GET_HW(num) (((num) == 0) ? (&BITSCRAMBLER) : NULL)
//Note: Most of the register operations refer tx_something fields. Because they
//are done to bitscramblers_reg[dir] members and rx register fields are the
//same, this code works for RX as well.
//Note: This code entirely ignores the 'hw' argument, which is fine, as for now
//we only have one BitScrambler peripheral. If we have a chip that has more, we
//need to do something to use hw to select one of multiple bitscramblers_reg
//versions.
/**
* @brief Select peripheral BitScrambler is attached to
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_select_peripheral(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int peri)
{
if (dir == BITSCRAMBLER_DIR_TX) {
HP_SYSTEM.bitscrambler_peri_sel.bitscrambler_peri_tx_sel = peri;
} else { // RX
HP_SYSTEM.bitscrambler_peri_sel.bitscrambler_peri_rx_sel = peri;
}
}
/**
* @brief Enable the BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_enable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
bitscramblers_reg[dir].ctrl->tx_ena=1;
}
/**
* @brief Disable the BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_disable(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
bitscramblers_reg[dir].ctrl->tx_ena=0;
}
/**
* @brief Write a word to the instruction memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param inst_idx Instruction to write to
* @param word_idx Word within the instruction to write to
* @param data Data to write
*/
static inline void bitscrambler_ll_instmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx, uint32_t data)
{
bitscramblers_reg[dir].inst_cfg0->tx_inst_idx=inst_idx;
bitscramblers_reg[dir].inst_cfg0->tx_inst_pos=word_idx;
bitscramblers_reg[dir].inst_cfg1->tx_inst=data;
}
/**
* @brief Read a word from the instruction memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param inst_idx Instruction to write to
* @param word_idx Word within the instruction to write to
*
* @returns Word read from instruction memory
*/
static inline uint32_t bitscrambler_ll_instmem_read(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int inst_idx, int word_idx)
{
bitscramblers_reg[dir].inst_cfg0->tx_inst_idx=inst_idx;
bitscramblers_reg[dir].inst_cfg0->tx_inst_pos=word_idx;
return bitscramblers_reg[dir].inst_cfg1->tx_inst;
}
/**
* @brief Write a word to LUT memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param word_idx Word within the LUT to write to
* @param data Data to write
*/
static inline void bitscrambler_ll_lutmem_write(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int word_idx, uint32_t data) {
bitscramblers_reg[dir].lut_cfg0->tx_lut_idx=word_idx;
bitscramblers_reg[dir].lut_cfg1->tx_lut=data;
}
/**
* @brief Set width of LUT memory (as seen by Bitscrambler, not by host)
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param width Width selection
*/
static inline void bitscrambler_ll_set_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_lut_width_t width)
{
bitscramblers_reg[dir].lut_cfg0->tx_lut_mode=width;
}
/**
* @brief Get width of LUT memory
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline int bitscrambler_ll_get_lut_width(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
return bitscramblers_reg[dir].lut_cfg0->tx_lut_mode;
}
/**
* @brief Enable loopback mode, where the RX BitScrambler is disabled and the TX BitScrambler loops
* back to the receive DMA path to memory.
*
* @param hw BitScrambler hardware instance address.
* @param en True if loopback mode is enabled; false otherwise
*/
static inline void bitscrambler_ll_enable_loopback(bitscrambler_dev_t *hw, bool en)
{
hw->sys.loop_mode=en?1:0;
}
/**
* @brief Set condition-checking mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_cond_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_cond_mode_t mode)
{
bitscramblers_reg[dir].ctrl->tx_cond_mode=mode;
}
/**
* @brief Set prefetch mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_prefetch_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_prefetch_mode_t mode)
{
bitscramblers_reg[dir].ctrl->tx_fetch_mode=mode;
}
/**
* @brief Set EOF mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_eof_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_eof_mode_t mode)
{
bitscramblers_reg[dir].ctrl->tx_eof_mode=mode;
}
/**
* @brief Set mode of dummy-reading after EOF
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_dummy_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_dummy_mode_t mode)
{
bitscramblers_reg[dir].ctrl->tx_rd_dummy=mode;
}
/**
* @brief Set halting mode
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param mode Mode to set
*/
static inline void bitscrambler_ll_set_halt_mode(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_halt_mode_t mode)
{
bitscramblers_reg[dir].ctrl->tx_halt_mode=mode;
}
/**
* @brief Set amount of bits to ignore after EOF
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param bitcount Number of bits to ignore
*/
static inline void bitscrambler_ll_set_tailing_bits(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, int bitcount)
{
HAL_FORCE_MODIFY_U32_REG_FIELD((*bitscramblers_reg[dir].trailing_bits), tx_tailing_bits, bitcount);
}
/**
* @brief Reset BitScrambler FIFO
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_reset_fifo(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
bitscramblers_reg[dir].ctrl->tx_fifo_rst=1;
bitscramblers_reg[dir].ctrl->tx_fifo_rst=0;
}
/**
* @brief Clear trace of EOF counts
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*/
static inline void bitscrambler_ll_clear_eof_trace(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
bitscramblers_reg[dir].state->tx_eof_trace_clr=1;
bitscramblers_reg[dir].state->tx_eof_trace_clr=0;
}
/**
* @brief Set state of BitScrambler
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
* @param state One of BITSCRAMBLER_SET_STATE_[RUN|HALT|PAUSE]. Note the WAIT state cannot be set externally.
*/
static inline void bitscrambler_ll_set_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir, bitscrambler_set_state_t state)
{
bitscramblers_reg[dir].ctrl->tx_pause=(state==BITSCRAMBLER_SET_STATE_PAUSE)?1:0;
bitscramblers_reg[dir].ctrl->tx_halt=(state==BITSCRAMBLER_SET_STATE_HALT)?1:0;
}
/**
* @brief Return current BitScrambler state
*
* @param hw BitScrambler hardware instance address.
* @param dir Direction, BITSCRAMBLER_DIR_TX or BITSCRAMBLER_DIR_RX
*
* @returns one of BITSCRAMBLER_STATE_* values
*/
static inline bitscrambler_state_t bitscrambler_ll_current_state(bitscrambler_dev_t *hw, bitscrambler_direction_t dir)
{
if (bitscramblers_reg[dir].state->tx_in_idle) return BITSCRAMBLER_STATE_IDLE;
if (bitscramblers_reg[dir].state->tx_in_run) return BITSCRAMBLER_STATE_RUN;
if (bitscramblers_reg[dir].state->tx_in_wait) return BITSCRAMBLER_STATE_WAIT;
if (bitscramblers_reg[dir].state->tx_in_pause) return BITSCRAMBLER_STATE_PAUSED;
return BITSCRAMBLER_STATE_UNKNOWN;
}
/**
* @brief Enable the bus clock for BitScrambler module
*/
static inline void _bitscrambler_ll_set_bus_clock_sys_enable(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl1.reg_bitscrambler_sys_clk_en = enable;
}
/**
* @brief Enable the bus clock for RX BitScrambler module
*/
static inline void _bitscrambler_ll_set_bus_clock_rx_enable(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl1.reg_bitscrambler_rx_sys_clk_en = enable;
}
/**
* @brief Enable the bus clock for TX BitScrambler module
*/
static inline void _bitscrambler_ll_set_bus_clock_tx_enable(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl1.reg_bitscrambler_tx_sys_clk_en = enable;
}
/**
* @brief Reset the BitScrambler module
*/
static inline void _bitscrambler_ll_reset_sys(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler = 0;
}
/**
* @brief Reset the BitScrambler RX module
*/
static inline void _bitscrambler_ll_reset_rx(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_rx = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_rx = 0;
}
/**
* @brief Reset the BitScrambler TX module
*/
static inline void _bitscrambler_ll_reset_tx(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_tx = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_bitscrambler_tx = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define bitscrambler_ll_set_bus_clock_sys_enable(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _bitscrambler_ll_set_bus_clock_sys_enable(__VA_ARGS__)
#define bitscrambler_ll_set_bus_clock_rx_enable(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _bitscrambler_ll_set_bus_clock_rx_enable(__VA_ARGS__)
#define bitscrambler_ll_set_bus_clock_tx_enable(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _bitscrambler_ll_set_bus_clock_tx_enable(__VA_ARGS__)
#define bitscrambler_ll_reset_sys(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _bitscrambler_ll_reset_sys(__VA_ARGS__)
#define bitscrambler_ll_reset_rx(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _bitscrambler_ll_reset_rx(__VA_ARGS__)
#define bitscrambler_ll_reset_tx(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _bitscrambler_ll_reset_tx(__VA_ARGS__)
#ifdef __cplusplus
}
#endif

40
components/hal/include/hal/bitscrambler_hal.h Normal file
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@@ -0,0 +1,40 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
#if CONFIG_SOC_BITSCRAMBLER_SUPPORTED
#include "soc/bitscrambler_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* @brief The TX and RX BitScramblers have registers that work in the same way, but that are
* in different locations. This struct defines those registers; if we address the TX and
* RX bitscramblers through this we can mostly use the same code for both.
*/
typedef struct {
volatile bitscrambler_tx_inst_cfg0_reg_t *inst_cfg0;
volatile bitscrambler_tx_inst_cfg1_reg_t *inst_cfg1;
volatile bitscrambler_tx_lut_cfg0_reg_t *lut_cfg0;
volatile bitscrambler_tx_lut_cfg1_reg_t *lut_cfg1;
volatile bitscrambler_tx_tailing_bits_reg_t *trailing_bits;
volatile bitscrambler_tx_ctrl_reg_t *ctrl;
volatile bitscrambler_tx_state_reg_t *state;
} bitscrambler_regs_t;
extern const bitscrambler_regs_t bitscramblers_reg[2];
#ifdef __cplusplus
}
#endif
#endif

103
components/hal/include/hal/bitscrambler_types.h Normal file
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@@ -0,0 +1,103 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief BitScrambler transport direction
*/
typedef enum {
BITSCRAMBLER_DIR_TX = 0, /*!< Transmit, so mem to device (or mem to mem in loopback mode) */
BITSCRAMBLER_DIR_RX = 1 /*!< Receive, so device to memory */
} bitscrambler_direction_t;
/**
* @brief BitScrambler LUT width
*/
typedef enum {
BITSCRAMBLER_LUT_WIDTH_8BIT = 0,
BITSCRAMBLER_LUT_WIDTH_16BIT = 1,
BITSCRAMBLER_LUT_WIDTH_32BIT = 2
} bitscrambler_lut_width_t;
/**
* @brief BitScrambler loopback select
*/
typedef enum {
BITSCRAMBLER_LOOP_DISABLE = 0,
BITSCRAMBLER_LOOP_ENABLE = 1
} bitscrambler_loop_mode_t;
/**
* @brief EOF mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_EOF_MODE_READ = 0,
BITSCRAMBLER_EOF_MODE_WRITE = 1
} bitscrambler_eof_mode_t;
/**
* @brief Condition mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_COND_MODE_LESSTHAN = 0,
BITSCRAMBLER_COND_MODE_NOTEQUAL = 1
} bitscrambler_cond_mode_t;
/**
* @brief Condition mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_PREFETCH_ENABLED = 0,
BITSCRAMBLER_PREFETCH_DISABLED = 1
} bitscrambler_prefetch_mode_t;
/**
* @brief Condition mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_HALT_WAIT_WRITES = 0,
BITSCRAMBLER_HALT_IGNORE_WRITES = 1
} bitscrambler_halt_mode_t;
/**
* @brief Condition mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_DUMMY_MODE_HALT = 0,
BITSCRAMBLER_DUMMY_MODE_DUMMY = 1
} bitscrambler_dummy_mode_t;
/**
* @brief Condition mode of bitscrambler
*/
typedef enum {
BITSCRAMBLER_SET_STATE_RUN,
BITSCRAMBLER_SET_STATE_HALT,
BITSCRAMBLER_SET_STATE_PAUSE
} bitscrambler_set_state_t;
/**
* @brief Status of bitscrambler
*/
typedef enum {
BITSCRAMBLER_STATE_IDLE,
BITSCRAMBLER_STATE_RUN,
BITSCRAMBLER_STATE_WAIT,
BITSCRAMBLER_STATE_PAUSED,
BITSCRAMBLER_STATE_UNKNOWN /*!< Invalid, should never be returned */
} bitscrambler_state_t;
#ifdef __cplusplus
}
#endif

27
components/soc/esp32p4/include/soc/bitscrambler_peri_select.h Normal file
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@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/*
* @brief BitScrambler attachment targets
* Note that these are the values written to HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG.
*/
#define SOC_BITSCRAMBLER_ATTACH_LCD_CAM 0
#define SOC_BITSCRAMBLER_ATTACH_GPSPI2 1
#define SOC_BITSCRAMBLER_ATTACH_GPSPI3 2
#define SOC_BITSCRAMBLER_ATTACH_PARL_IO 3
#define SOC_BITSCRAMBLER_ATTACH_AES 4
#define SOC_BITSCRAMBLER_ATTACH_SHA 5
#define SOC_BITSCRAMBLER_ATTACH_ADC 6
#define SOC_BITSCRAMBLER_ATTACH_I2S0 7
#define SOC_BITSCRAMBLER_ATTACH_I2S1 8
#define SOC_BITSCRAMBLER_ATTACH_I2S2 9
#define SOC_BITSCRAMBLER_ATTACH_I3C_MST 10
#define SOC_BITSCRAMBLER_ATTACH_UHCI 11
#define SOC_BITSCRAMBLER_ATTACH_RMT 12
#define SOC_BITSCRAMBLER_ATTACH_MAX 12

2
components/soc/esp32p4/include/soc/periph_defs.h
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@@ -69,7 +69,7 @@ typedef enum {
PERIPH_UHCI_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
PERIPH_BITSCRAMBLER_MODULE,
/* LP peripherals */
PERIPH_LP_I2C0_MODULE,
PERIPH_LP_UART0_MODULE,

1
components/soc/esp32p4/ld/esp32p4.peripherals.ld
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@@ -38,6 +38,7 @@ PROVIDE ( TWAI2 = 0x500D9000 );
PROVIDE ( ADC = 0x500DE000 );
PROVIDE ( USB_SERIAL_JTAG = 0x500D2000 );
PROVIDE ( SDMMC = 0x50083000 );
PROVIDE ( BITSCRAMBLER = 0x500A3000 );
PROVIDE ( INTMTX = 0x500D6000 );
PROVIDE ( PCNT = 0x500C9000 );

1
components/soc/esp32p4/register/soc/bitscrambler_struct.h
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@@ -426,6 +426,7 @@ typedef struct {
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
extern bitscrambler_dev_t BITSCRAMBLER;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");

90
components/soc/esp32p4/register/soc/hp_sys_clkrst_reg.h
View File

@@ -570,27 +570,27 @@ extern "C" {
#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S)
#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S 27
/** HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN : R/W; bitpos: [28]; default: 1;
/** HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN : R/W; bitpos: [28]; default: 1;
* Reserved
*/
#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN (BIT(28))
#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S)
#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S 28
/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [29]; default: 1;
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN (BIT(28))
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_S)
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_SYS_CLK_EN_S 28
/** HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [29]; default: 1;
* Reserved
*/
#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN (BIT(29))
#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S)
#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S 29
/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [30]; default: 1;
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN (BIT(29))
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_S)
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_RX_SYS_CLK_EN_S 29
/** HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [30]; default: 1;
* Reserved
*/
#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN (BIT(30))
#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S)
#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S 30
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN (BIT(30))
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_M (HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_S)
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLKRST_REG_BITSCRAMBLER_TX_SYS_CLK_EN_S 30
/** HP_SYS_CLKRST_REG_H264_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
* Reserved
*/
@@ -3597,27 +3597,27 @@ extern "C" {
#define HP_SYS_CLKRST_REG_RST_EN_ADC_M (HP_SYS_CLKRST_REG_RST_EN_ADC_V << HP_SYS_CLKRST_REG_RST_EN_ADC_S)
#define HP_SYS_CLKRST_REG_RST_EN_ADC_V 0x00000001U
#define HP_SYS_CLKRST_REG_RST_EN_ADC_S 10
/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER : R/W; bitpos: [11]; default: 0;
/** HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER : R/W; bitpos: [11]; default: 0;
* Reserved
*/
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER (BIT(11))
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_M (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S)
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V 0x00000001U
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S 11
/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX : R/W; bitpos: [12]; default: 0;
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER (BIT(11))
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_M (HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_V << HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_S)
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_V 0x00000001U
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_S 11
/** HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX : R/W; bitpos: [12]; default: 0;
* Reserved
*/
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX (BIT(12))
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_M (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S)
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V 0x00000001U
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S 12
/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX : R/W; bitpos: [13]; default: 0;
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX (BIT(12))
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_M (HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_V << HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_S)
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_V 0x00000001U
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_RX_S 12
/** HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX : R/W; bitpos: [13]; default: 0;
* Reserved
*/
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX (BIT(13))
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_M (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S)
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V 0x00000001U
#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S 13
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX (BIT(13))
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_M (HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_V << HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_S)
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_V 0x00000001U
#define HP_SYS_CLKRST_REG_RST_EN_BITSCRAMBLER_TX_S 13
/** HP_SYS_CLKRST_REG_RST_EN_CRYPTO : R/W; bitpos: [14]; default: 0;
* Reserved
*/
@@ -4090,27 +4090,27 @@ extern "C" {
#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_M (HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V << HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S)
#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V 0x00000001U
#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S 22
/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER : R/W; bitpos: [23]; default: 0;
/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER : R/W; bitpos: [23]; default: 0;
* Reserved
*/
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER (BIT(23))
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S)
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V 0x00000001U
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S 23
/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX : R/W; bitpos: [24]; default: 0;
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER (BIT(23))
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_S)
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_V 0x00000001U
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_S 23
/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX : R/W; bitpos: [24]; default: 0;
* Reserved
*/
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX (BIT(24))
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S)
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V 0x00000001U
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S 24
/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX : R/W; bitpos: [25]; default: 0;
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX (BIT(24))
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_S)
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_V 0x00000001U
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_RX_S 24
/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX : R/W; bitpos: [25]; default: 0;
* Reserved
*/
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX (BIT(25))
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S)
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V 0x00000001U
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S 25
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX (BIT(25))
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_M (HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_S)
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_V 0x00000001U
#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSCRAMBLER_TX_S 25
/** HP_SYS_CLKRST_REG_FORCE_NORST_H264 : R/W; bitpos: [26]; default: 0;
* Reserved
*/

36
components/soc/esp32p4/register/soc/hp_sys_clkrst_struct.h
View File

@@ -377,18 +377,18 @@ typedef union {
* Reserved
*/
uint32_t reg_key_manager_sys_clk_en:1;
/** reg_bitsrambler_sys_clk_en : R/W; bitpos: [28]; default: 1;
/** reg_bitscrambler_sys_clk_en : R/W; bitpos: [28]; default: 1;
* Reserved
*/
uint32_t reg_bitsrambler_sys_clk_en:1;
/** reg_bitsrambler_rx_sys_clk_en : R/W; bitpos: [29]; default: 1;
uint32_t reg_bitscrambler_sys_clk_en:1;
/** reg_bitscrambler_rx_sys_clk_en : R/W; bitpos: [29]; default: 1;
* Reserved
*/
uint32_t reg_bitsrambler_rx_sys_clk_en:1;
/** reg_bitsrambler_tx_sys_clk_en : R/W; bitpos: [30]; default: 1;
uint32_t reg_bitscrambler_rx_sys_clk_en:1;
/** reg_bitscrambler_tx_sys_clk_en : R/W; bitpos: [30]; default: 1;
* Reserved
*/
uint32_t reg_bitsrambler_tx_sys_clk_en:1;
uint32_t reg_bitscrambler_tx_sys_clk_en:1;
/** reg_h264_sys_clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
@@ -2427,18 +2427,18 @@ typedef union {
* Reserved
*/
uint32_t reg_rst_en_adc:1;
/** reg_rst_en_bitsrambler : R/W; bitpos: [11]; default: 0;
/** reg_rst_en_bitscrambler : R/W; bitpos: [11]; default: 0;
* Reserved
*/
uint32_t reg_rst_en_bitsrambler:1;
/** reg_rst_en_bitsrambler_rx : R/W; bitpos: [12]; default: 0;
uint32_t reg_rst_en_bitscrambler:1;
/** reg_rst_en_bitscrambler_rx : R/W; bitpos: [12]; default: 0;
* Reserved
*/
uint32_t reg_rst_en_bitsrambler_rx:1;
/** reg_rst_en_bitsrambler_tx : R/W; bitpos: [13]; default: 0;
uint32_t reg_rst_en_bitscrambler_rx:1;
/** reg_rst_en_bitscrambler_tx : R/W; bitpos: [13]; default: 0;
* Reserved
*/
uint32_t reg_rst_en_bitsrambler_tx:1;
uint32_t reg_rst_en_bitscrambler_tx:1;
/** reg_rst_en_crypto : R/W; bitpos: [14]; default: 0;
* Reserved
*/
@@ -2724,18 +2724,18 @@ typedef union {
* Reserved
*/
uint32_t reg_force_norst_adc:1;
/** reg_force_norst_bitsrambler : R/W; bitpos: [23]; default: 0;
/** reg_force_norst_bitscrambler : R/W; bitpos: [23]; default: 0;
* Reserved
*/
uint32_t reg_force_norst_bitsrambler:1;
/** reg_force_norst_bitsrambler_rx : R/W; bitpos: [24]; default: 0;
uint32_t reg_force_norst_bitscrambler:1;
/** reg_force_norst_bitscrambler_rx : R/W; bitpos: [24]; default: 0;
* Reserved
*/
uint32_t reg_force_norst_bitsrambler_rx:1;
/** reg_force_norst_bitsrambler_tx : R/W; bitpos: [25]; default: 0;
uint32_t reg_force_norst_bitscrambler_rx:1;
/** reg_force_norst_bitscrambler_tx : R/W; bitpos: [25]; default: 0;
* Reserved
*/
uint32_t reg_force_norst_bitsrambler_tx:1;
uint32_t reg_force_norst_bitscrambler_tx:1;
/** reg_force_norst_h264 : R/W; bitpos: [26]; default: 0;
* Reserved
*/

2
components/soc/esp32p4/register/soc/reg_base.h
View File

@@ -64,7 +64,7 @@
#define DR_REG_DSI_BRG_BASE (DR_REG_HPPERIPH0_BASE + 0xA0800)
#define DR_REG_ISP_BASE (DR_REG_HPPERIPH0_BASE + 0xA1000)
#define DR_REG_RMT_BASE (DR_REG_HPPERIPH0_BASE + 0xA2000)
#define DR_REG_BITSCRAM_BASE (DR_REG_HPPERIPH0_BASE + 0xA3000)
#define DR_REG_BITSCRAMBLER_BASE (DR_REG_HPPERIPH0_BASE + 0xA3000)
#define DR_REG_AXI_ICM_BASE (DR_REG_HPPERIPH0_BASE + 0xA4000)
#define DR_REG_AXI_ICM_QOS_BASE (DR_REG_AXI_ICM_BASE + 0x400)
#define DR_REG_HP_PERI_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA5000)