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fix(ledc): align ledc register typo with TRM

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This commit is contained in:
Song Ruo Jing
2025-04-07 16:07:22 +08:00
parent dd72141b78
commit afccb78720
10 changed files with 148 additions and 148 deletions
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42
components/soc/esp32c5/register/soc/ledc_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1731,38 +1731,38 @@ extern "C" {
#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U
#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19
/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0;
/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME0_CMP_EN (BIT(20))
#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S)
#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME0_CMP_EN_S 20
/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0;
#define LEDC_EVT_TIMER0_CMP_EN (BIT(20))
#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S)
#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER0_CMP_EN_S 20
/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME1_CMP_EN (BIT(21))
#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S)
#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME1_CMP_EN_S 21
/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0;
#define LEDC_EVT_TIMER1_CMP_EN (BIT(21))
#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S)
#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER1_CMP_EN_S 21
/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME2_CMP_EN (BIT(22))
#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S)
#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME2_CMP_EN_S 22
/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0;
#define LEDC_EVT_TIMER2_CMP_EN (BIT(22))
#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S)
#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER2_CMP_EN_S 22
/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME3_CMP_EN (BIT(23))
#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S)
#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME3_CMP_EN_S 23
#define LEDC_EVT_TIMER3_CMP_EN (BIT(23))
#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S)
#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER3_CMP_EN_S 23
/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.\\0:
* Disable\\1: Enable

18
components/soc/esp32c5/register/soc/ledc_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -249,26 +249,26 @@ typedef union {
* Disable\\1: Enable
*/
uint32_t evt_time_ovf_timer3_en:1;
/** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0;
/** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time0_cmp_en:1;
/** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0;
uint32_t evt_timer0_cmp_en:1;
/** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time1_cmp_en:1;
/** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0;
uint32_t evt_timer1_cmp_en:1;
/** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time2_cmp_en:1;
/** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0;
uint32_t evt_timer2_cmp_en:1;
/** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time3_cmp_en:1;
uint32_t evt_timer3_cmp_en:1;
/** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.\\0:
* Disable\\1: Enable

42
components/soc/esp32c61/register/soc/ledc_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1731,38 +1731,38 @@ extern "C" {
#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U
#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19
/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0;
/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME0_CMP_EN (BIT(20))
#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S)
#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME0_CMP_EN_S 20
/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0;
#define LEDC_EVT_TIMER0_CMP_EN (BIT(20))
#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S)
#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER0_CMP_EN_S 20
/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME1_CMP_EN (BIT(21))
#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S)
#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME1_CMP_EN_S 21
/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0;
#define LEDC_EVT_TIMER1_CMP_EN (BIT(21))
#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S)
#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER1_CMP_EN_S 21
/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME2_CMP_EN (BIT(22))
#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S)
#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME2_CMP_EN_S 22
/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0;
#define LEDC_EVT_TIMER2_CMP_EN (BIT(22))
#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S)
#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER2_CMP_EN_S 22
/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME3_CMP_EN (BIT(23))
#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S)
#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME3_CMP_EN_S 23
#define LEDC_EVT_TIMER3_CMP_EN (BIT(23))
#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S)
#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER3_CMP_EN_S 23
/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.\\0:
* Disable\\1: Enable

18
components/soc/esp32c61/register/soc/ledc_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -249,26 +249,26 @@ typedef union {
* Disable\\1: Enable
*/
uint32_t evt_time_ovf_timer3_en:1;
/** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0;
/** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time0_cmp_en:1;
/** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0;
uint32_t evt_timer0_cmp_en:1;
/** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time1_cmp_en:1;
/** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0;
uint32_t evt_timer1_cmp_en:1;
/** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time2_cmp_en:1;
/** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0;
uint32_t evt_timer2_cmp_en:1;
/** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time3_cmp_en:1;
uint32_t evt_timer3_cmp_en:1;
/** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.\\0:
* Disable\\1: Enable

42
components/soc/esp32h21/register/soc/ledc_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -2135,34 +2135,34 @@ extern "C" {
#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U
#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19
/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0;
/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0;
* Ledc timer0 compare event enable register, write 1 to enable this event.
*/
#define LEDC_EVT_TIME0_CMP_EN (BIT(20))
#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S)
#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME0_CMP_EN_S 20
/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0;
#define LEDC_EVT_TIMER0_CMP_EN (BIT(20))
#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S)
#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER0_CMP_EN_S 20
/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0;
* Ledc timer1 compare event enable register, write 1 to enable this event.
*/
#define LEDC_EVT_TIME1_CMP_EN (BIT(21))
#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S)
#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME1_CMP_EN_S 21
/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0;
#define LEDC_EVT_TIMER1_CMP_EN (BIT(21))
#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S)
#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER1_CMP_EN_S 21
/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0;
* Ledc timer2 compare event enable register, write 1 to enable this event.
*/
#define LEDC_EVT_TIME2_CMP_EN (BIT(22))
#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S)
#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME2_CMP_EN_S 22
/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0;
#define LEDC_EVT_TIMER2_CMP_EN (BIT(22))
#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S)
#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER2_CMP_EN_S 22
/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0;
* Ledc timer3 compare event enable register, write 1 to enable this event.
*/
#define LEDC_EVT_TIME3_CMP_EN (BIT(23))
#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S)
#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME3_CMP_EN_S 23
#define LEDC_EVT_TIMER3_CMP_EN (BIT(23))
#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S)
#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER3_CMP_EN_S 23
/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
* Ledc ch0 duty scale update task enable register, write 1 to enable this task.
*/

18
components/soc/esp32h21/register/soc/ledc_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -144,22 +144,22 @@ typedef union {
* Ledc timer3 overflow event enable register, write 1 to enable this event.
*/
uint32_t evt_time_ovf_timer3_en:1;
/** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0;
/** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0;
* Ledc timer0 compare event enable register, write 1 to enable this event.
*/
uint32_t evt_time0_cmp_en:1;
/** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0;
uint32_t evt_timer0_cmp_en:1;
/** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0;
* Ledc timer1 compare event enable register, write 1 to enable this event.
*/
uint32_t evt_time1_cmp_en:1;
/** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0;
uint32_t evt_timer1_cmp_en:1;
/** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0;
* Ledc timer2 compare event enable register, write 1 to enable this event.
*/
uint32_t evt_time2_cmp_en:1;
/** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0;
uint32_t evt_timer2_cmp_en:1;
/** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0;
* Ledc timer3 compare event enable register, write 1 to enable this event.
*/
uint32_t evt_time3_cmp_en:1;
uint32_t evt_timer3_cmp_en:1;
/** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
* Ledc ch0 duty scale update task enable register, write 1 to enable this task.
*/

40
components/soc/esp32h4/register/soc/ledc_reg.h
View File

@@ -2219,42 +2219,42 @@ extern "C" {
#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U
#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19
/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0;
/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.
* 0: Disable
* 1: Enable
*/
#define LEDC_EVT_TIME0_CMP_EN (BIT(20))
#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S)
#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME0_CMP_EN_S 20
/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0;
#define LEDC_EVT_TIMER0_CMP_EN (BIT(20))
#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S)
#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER0_CMP_EN_S 20
/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.
* 0: Disable
* 1: Enable
*/
#define LEDC_EVT_TIME1_CMP_EN (BIT(21))
#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S)
#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME1_CMP_EN_S 21
/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0;
#define LEDC_EVT_TIMER1_CMP_EN (BIT(21))
#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S)
#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER1_CMP_EN_S 21
/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.
* 0: Disable
* 1: Enable
*/
#define LEDC_EVT_TIME2_CMP_EN (BIT(22))
#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S)
#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME2_CMP_EN_S 22
/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0;
#define LEDC_EVT_TIMER2_CMP_EN (BIT(22))
#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S)
#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER2_CMP_EN_S 22
/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.
* 0: Disable
* 1: Enable
*/
#define LEDC_EVT_TIME3_CMP_EN (BIT(23))
#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S)
#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME3_CMP_EN_S 23
#define LEDC_EVT_TIMER3_CMP_EN (BIT(23))
#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S)
#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER3_CMP_EN_S 23
/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.
* 0: Disable

16
components/soc/esp32h4/register/soc/ledc_struct.h
View File

@@ -298,30 +298,30 @@ typedef union {
* 1: Enable
*/
uint32_t evt_time_ovf_timer3_en:1;
/** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0;
/** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER0_CMP event.
* 0: Disable
* 1: Enable
*/
uint32_t evt_time0_cmp_en:1;
/** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0;
uint32_t evt_timer0_cmp_en:1;
/** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER1_CMP event.
* 0: Disable
* 1: Enable
*/
uint32_t evt_time1_cmp_en:1;
/** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0;
uint32_t evt_timer1_cmp_en:1;
/** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER2_CMP event.
* 0: Disable
* 1: Enable
*/
uint32_t evt_time2_cmp_en:1;
/** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0;
uint32_t evt_timer2_cmp_en:1;
/** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the LEDC_EVT_TIMER3_CMP event.
* 0: Disable
* 1: Enable
*/
uint32_t evt_time3_cmp_en:1;
uint32_t evt_timer3_cmp_en:1;
/** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CH0 task.
* 0: Disable

42
components/soc/esp32p4/register/soc/ledc_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -2163,38 +2163,38 @@ extern "C" {
#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U
#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19
/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0;
/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME0_CMP_EN (BIT(20))
#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S)
#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME0_CMP_EN_S 20
/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0;
#define LEDC_EVT_TIMER0_CMP_EN (BIT(20))
#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S)
#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER0_CMP_EN_S 20
/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME1_CMP_EN (BIT(21))
#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S)
#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME1_CMP_EN_S 21
/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0;
#define LEDC_EVT_TIMER1_CMP_EN (BIT(21))
#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S)
#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER1_CMP_EN_S 21
/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME2_CMP_EN (BIT(22))
#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S)
#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME2_CMP_EN_S 22
/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0;
#define LEDC_EVT_TIMER2_CMP_EN (BIT(22))
#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S)
#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER2_CMP_EN_S 22
/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1:
* Enable
*/
#define LEDC_EVT_TIME3_CMP_EN (BIT(23))
#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S)
#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIME3_CMP_EN_S 23
#define LEDC_EVT_TIMER3_CMP_EN (BIT(23))
#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S)
#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U
#define LEDC_EVT_TIMER3_CMP_EN_S 23
/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0:
* Disable\\1: Enable

18
components/soc/esp32p4/register/soc/ledc_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -703,26 +703,26 @@ typedef union {
* Enable
*/
uint32_t evt_time_ovf_timer3_en:1;
/** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0;
/** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0;
* Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time0_cmp_en:1;
/** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0;
uint32_t evt_timer0_cmp_en:1;
/** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0;
* Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time1_cmp_en:1;
/** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0;
uint32_t evt_timer1_cmp_en:1;
/** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time2_cmp_en:1;
/** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0;
uint32_t evt_timer2_cmp_en:1;
/** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1:
* Enable
*/
uint32_t evt_time3_cmp_en:1;
uint32_t evt_timer3_cmp_en:1;
/** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0:
* Disable\\1: Enable