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Merge branch 'task/esp32p4_int_vectors_cleanup' into 'master'

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fix(interrupts): Cleanup pending tags in the code base regarding interrupt vectors

Closes IDF-7863

See merge request espressif/esp-idf!25698
This commit is contained in:
Sudeep Mohanty
2023-09-04 09:54:23 +08:00
parent 62ee4135e0 5cd989f23b
commit b1e85404f1
3 changed files with 9 additions and 7 deletions
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4
components/esp_hw_support/include/esp_cpu.h
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@@ -234,12 +234,12 @@ FORCE_INLINE_ATTR void esp_cpu_intr_set_ivt_addr(const void *ivt_addr)
} }
#if SOC_INT_CLIC_SUPPORTED #if SOC_INT_CLIC_SUPPORTED
//TODO: IDF-7863
//"MTVT is only implemented in RISC-V arch"
/** /**
* @brief Set the base address of the current CPU's Interrupt Vector Table (MTVT) * @brief Set the base address of the current CPU's Interrupt Vector Table (MTVT)
* *
* @param mtvt_addr Interrupt Vector Table's base address * @param mtvt_addr Interrupt Vector Table's base address
*
* @note The MTVT table is only applicable when CLIC is supported
*/ */
FORCE_INLINE_ATTR void esp_cpu_intr_set_mtvt_addr(const void *mtvt_addr) FORCE_INLINE_ATTR void esp_cpu_intr_set_mtvt_addr(const void *mtvt_addr)
{ {

8
components/esp_system/port/cpu_start.c
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@@ -204,7 +204,9 @@ void IRAM_ATTR call_start_cpu1(void)
esp_cpu_intr_set_ivt_addr(&_vector_table); esp_cpu_intr_set_ivt_addr(&_vector_table);
#if SOC_INT_CLIC_SUPPORTED #if SOC_INT_CLIC_SUPPORTED
//TODO: IDF-7863 /* When hardware vectored interrupts are enabled in CLIC,
* the CPU jumps to this base address + 4 * interrupt_id.
*/
esp_cpu_intr_set_mtvt_addr(&_mtvt_table); esp_cpu_intr_set_mtvt_addr(&_mtvt_table);
#endif #endif
@@ -400,7 +402,9 @@ void IRAM_ATTR call_start_cpu0(void)
// Move exception vectors to IRAM // Move exception vectors to IRAM
esp_cpu_intr_set_ivt_addr(&_vector_table); esp_cpu_intr_set_ivt_addr(&_vector_table);
#if SOC_INT_CLIC_SUPPORTED #if SOC_INT_CLIC_SUPPORTED
//TODO: IDF-7863 /* When hardware vectored interrupts are enabled in CLIC,
* the CPU jumps to this base address + 4 * interrupt_id.
*/
esp_cpu_intr_set_mtvt_addr(&_mtvt_table); esp_cpu_intr_set_mtvt_addr(&_mtvt_table);
#endif #endif

4
components/riscv/include/riscv/rv_utils.h
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@@ -96,7 +96,6 @@ FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_set_cycle_count(u
// --------------- Interrupt Configuration ----------------- // --------------- Interrupt Configuration -----------------
#if SOC_INT_CLIC_SUPPORTED #if SOC_INT_CLIC_SUPPORTED
//TODO: IDF-7863
FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val) FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val)
{ {
#define MTVT 0x307 #define MTVT 0x307
@@ -107,8 +106,7 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val)
FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val) FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val)
{ {
#if SOC_INT_CLIC_SUPPORTED #if SOC_INT_CLIC_SUPPORTED
//TODO: IDF-7863 mtvec_val |= 3; // Set MODE field to 3 to treat MTVT + 4*interrupt_id as the service entry address for HW vectored interrupts
mtvec_val |= 3;
#else #else
mtvec_val |= 1; // Set MODE field to treat MTVEC as a vector base address mtvec_val |= 1; // Set MODE field to treat MTVEC as a vector base address
#endif #endif