feat(panic): support HWSG for esp32c5, esp32c61 and enable testing

components/esp_system/port/include/private/esp_private/hw_stack_guard.h

@@ -34,26 +34,26 @@ uint32_t esp_hw_stack_guard_get_pc(uint32_t core_id);
 
 #include "hal/assist_debug_ll.h"
 
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM (ASSIST_DEBUG_CORE_0_INTR_ENA_REG >> 12)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG_IMM  (ASSIST_DEBUG_CORE_0_MONITOR_REG >> 12)
 #define ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET    (ASSIST_DEBUG_CORE_0_SP_MIN_REG - DR_REG_ASSIST_DEBUG_BASE)
 #define ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET    (ASSIST_DEBUG_CORE_0_SP_MAX_REG - DR_REG_ASSIST_DEBUG_BASE)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET  (ASSIST_DEBUG_CORE_0_INTR_ENA_REG - DR_REG_ASSIST_DEBUG_BASE)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET  (ASSIST_DEBUG_CORE_0_MONITOR_REG - DR_REG_ASSIST_DEBUG_BASE)
 
 .macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 reg1
-lui     \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
+lui     \reg1, ASSIST_DEBUG_CORE_0_MONITOR_REG_IMM
 sw      a0, ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET(\reg1)
 sw      a1, ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET(\reg1)
 .endm
 
 .macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 reg1 reg2
-lui     \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
+lui     \reg1, ASSIST_DEBUG_CORE_0_MONITOR_REG_IMM
 lw      \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
 andi    \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
 sw      \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
 .endm
 
 .macro ESP_HW_STACK_GUARD_MONITOR_START_CPU0 reg1 reg2
-lui     \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
+lui     \reg1, ASSIST_DEBUG_CORE_0_MONITOR_REG_IMM
 lw      \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
 ori     \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
 sw      \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
@@ -61,26 +61,26 @@ sw      \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
 
 #if SOC_CPU_CORES_NUM > 1
 
-#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM (ASSIST_DEBUG_CORE_1_INTR_ENA_REG >> 12)
+#define ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM  (ASSIST_DEBUG_CORE_1_MONITOR_REG >> 12)
 #define ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET    (ASSIST_DEBUG_CORE_1_SP_MIN_REG - DR_REG_ASSIST_DEBUG_BASE)
 #define ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET    (ASSIST_DEBUG_CORE_1_SP_MAX_REG - DR_REG_ASSIST_DEBUG_BASE)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET  (ASSIST_DEBUG_CORE_1_INTR_ENA_REG - DR_REG_ASSIST_DEBUG_BASE)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET  (ASSIST_DEBUG_CORE_1_MONITOR_REG - DR_REG_ASSIST_DEBUG_BASE)
 
 .macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 reg1
-lui     \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
+lui     \reg1, ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM
 sw      a0, ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET(\reg1)
 sw      a1, ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET(\reg1)
 .endm
 
 .macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU1 reg1 reg2
-lui     \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
+lui     \reg1, ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM
 lw      \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
 andi    \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
 sw      \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
 .endm
 
 .macro ESP_HW_STACK_GUARD_MONITOR_START_CPU1 reg1 reg2
-lui     \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
+lui     \reg1, ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM
 lw      \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
 ori     \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
 sw      \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)

components/hal/esp32c2/include/hal/assist_debug_ll.h

@@ -9,7 +9,8 @@
 #pragma once
 
 #include "soc/assist_debug_reg.h"
-#define ASSIST_DEBUG_SP_SPILL_BITS  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_SP_SPILL_BITS      (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
 
 #ifndef __ASSEMBLER__
 

components/hal/esp32c3/include/hal/assist_debug_ll.h

@@ -9,7 +9,8 @@
 #pragma once
 
 #include "soc/assist_debug_reg.h"
-#define ASSIST_DEBUG_SP_SPILL_BITS  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_SP_SPILL_BITS      (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
 
 #ifndef __ASSEMBLER__
 

components/hal/esp32c5/include/hal/assist_debug_ll.h

@@ -0,0 +1,131 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for DEBUG_ASSIST peripheral
+
+#pragma once
+
+#include "soc/assist_debug_reg.h"
+#define ASSIST_DEBUG_SP_SPILL_BITS      (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG  ASSIST_DEBUG_CORE_0_MONTR_ENA_REG
+
+#ifndef __ASSEMBLER__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "esp_attr.h"
+#include "hal/assert.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Most other peripherals have 4 interrupt-related registers: INT_ENA_REG, INT_CLR_REG, INT_RAW_REG, INT_ST_REG, the
+ * meaning of which is well-understood.
+ *
+ * Assist_debug peripheral uses a different structure of interrupt registers:
+ *     MONTR_ENA_REG, INT_ENA_REG, INT_CLR_REG, INT_RAW_REG.
+ *
+ * Their behavior can be explained using the following (verilog-like) pseudo-code:
+ *      reg sp_spill_max_st
+ *      assign sp_spill_max = (sp > SP_MAX_REG)
+ *      assign SP_SPILL_MAX_RAW = sp_spill_max & SPILL_MAX_MONTR_ENA
+ *      always (@posedge clk) begin
+ *          if (reset) then sp_spill_max_st <= 0
+ *          elif SP_SPILL_MAX_CLR then sp_spill_max_st <= 0
+ *          else sp_spill_max_st <= SP_SPILL_MAX_RAW & SP_SPILL_MAX_ENA
+ *      end
+ *      // ...same for sp_spill_min and other things debug_assist can check.
+ *
+ *      // this is the final interrupt line coming out of the peripheral:
+ *      assign DEBUG_ASSIST_INT = sp_spill_max_st | sp_spill_min_st | ...
+ *
+ * Basically, there is no "ST" register showing the final (latched) interrupt state, and there is an additional
+ * "MONTR_ENA" register which just like "ENA" can be used to mask monitor on/off state.
+ * Note that writing to CLR clears the (internal) latched interrupt state 'sp_spill_max_st',
+ * but doesn't affect the software-readable RAW register.
+ *
+ * In this code, we use "MONTR_ENA" to enable monitoring of a particular condition, and "ENA" to enable the interrupt.
+ * This allows checking whether the condition (e.g. sp > SP_MAX) has occurred by reading the RAW register, without
+ * actually triggering the interrupt.
+ */
+
+ /* These functions are optimized and designed for internal usage.
+  * So, the API may differ from general ll layer pattern */
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_SET_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_CLR_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS;
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id)
+{
+    REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min)
+{
+    REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min);
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max)
+{
+    REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max);
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG);
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+{
+    PCR.assist_conf.assist_clk_en = enable;
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_reset_register(void)
+{
+    PCR.assist_conf.assist_rst_en = true;
+    PCR.assist_conf.assist_rst_en = false;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ASSEMBLER__

components/hal/esp32c6/include/hal/assist_debug_ll.h

@@ -9,7 +9,8 @@
 #pragma once
 
 #include "soc/assist_debug_reg.h"
-#define ASSIST_DEBUG_SP_SPILL_BITS  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_SP_SPILL_BITS      (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
 
 #ifndef __ASSEMBLER__
 

components/hal/esp32c61/include/hal/assist_debug_ll.h

@@ -0,0 +1,131 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for DEBUG_ASSIST peripheral
+
+#pragma once
+
+#include "soc/assist_debug_reg.h"
+#define ASSIST_DEBUG_SP_SPILL_BITS      (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG  ASSIST_DEBUG_CORE_0_MONTR_ENA_REG
+
+#ifndef __ASSEMBLER__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "esp_attr.h"
+#include "hal/assert.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Most other peripherals have 4 interrupt-related registers: INT_ENA_REG, INT_CLR_REG, INT_RAW_REG, INT_ST_REG, the
+ * meaning of which is well-understood.
+ *
+ * Assist_debug peripheral uses a different structure of interrupt registers:
+ *     MONTR_ENA_REG, INT_ENA_REG, INT_CLR_REG, INT_RAW_REG.
+ *
+ * Their behavior can be explained using the following (verilog-like) pseudo-code:
+ *      reg sp_spill_max_st
+ *      assign sp_spill_max = (sp > SP_MAX_REG)
+ *      assign SP_SPILL_MAX_RAW = sp_spill_max & SPILL_MAX_MONTR_ENA
+ *      always (@posedge clk) begin
+ *          if (reset) then sp_spill_max_st <= 0
+ *          elif SP_SPILL_MAX_CLR then sp_spill_max_st <= 0
+ *          else sp_spill_max_st <= SP_SPILL_MAX_RAW & SP_SPILL_MAX_ENA
+ *      end
+ *      // ...same for sp_spill_min and other things debug_assist can check.
+ *
+ *      // this is the final interrupt line coming out of the peripheral:
+ *      assign DEBUG_ASSIST_INT = sp_spill_max_st | sp_spill_min_st | ...
+ *
+ * Basically, there is no "ST" register showing the final (latched) interrupt state, and there is an additional
+ * "MONTR_ENA" register which just like "ENA" can be used to mask monitor on/off state.
+ * Note that writing to CLR clears the (internal) latched interrupt state 'sp_spill_max_st',
+ * but doesn't affect the software-readable RAW register.
+ *
+ * In this code, we use "MONTR_ENA" to enable monitoring of a particular condition, and "ENA" to enable the interrupt.
+ * This allows checking whether the condition (e.g. sp > SP_MAX) has occurred by reading the RAW register, without
+ * actually triggering the interrupt.
+ */
+
+ /* These functions are optimized and designed for internal usage.
+  * So, the API may differ from general ll layer pattern */
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_SET_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_CLR_BIT(ASSIST_DEBUG_CORE_0_MONTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id)
+{
+    REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS;
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id)
+{
+    REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min)
+{
+    REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min);
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max)
+{
+    REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max);
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG);
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id)
+{
+    return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+{
+    PCR.assist_conf.assist_clk_en = enable;
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_reset_register(void)
+{
+    PCR.assist_conf.assist_rst_en = true;
+    PCR.assist_conf.assist_rst_en = false;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ASSEMBLER__

components/hal/esp32h2/include/hal/assist_debug_ll.h

@@ -9,7 +9,8 @@
 #pragma once
 
 #include "soc/assist_debug_reg.h"
-#define ASSIST_DEBUG_SP_SPILL_BITS  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_SP_SPILL_BITS      (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
 
 #ifndef __ASSEMBLER__
 

components/hal/esp32p4/include/hal/assist_debug_ll.h

@@ -9,7 +9,9 @@
 #pragma once
 
 #include "soc/assist_debug_reg.h"
-#define ASSIST_DEBUG_SP_SPILL_BITS  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_SP_SPILL_BITS      (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
+#define ASSIST_DEBUG_CORE_1_MONITOR_REG  ASSIST_DEBUG_CORE_1_INTR_ENA_REG
 
 #ifndef __ASSEMBLER__
 

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -203,6 +203,10 @@ config SOC_CLK_TREE_SUPPORTED
     bool
     default y
 
+config SOC_ASSIST_DEBUG_SUPPORTED
+    bool
+    default y
+
 config SOC_WDT_SUPPORTED
     bool
     default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -68,7 +68,7 @@
 #define SOC_LP_I2C_SUPPORTED            1
 #define SOC_ULP_LP_UART_SUPPORTED       1
 #define SOC_CLK_TREE_SUPPORTED          1
-// #define SOC_ASSIST_DEBUG_SUPPORTED      1  // TODO: [ESP32C5] IDF-8662
+#define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1     // TODO: [ESP32C5] IDF-8715
 // #define SOC_BITSCRAMBLER_SUPPORTED      1  // TODO: [ESP32C5] IDF-8711

components/soc/esp32c5/register/soc/assist_debug_reg.h

@@ -5,7 +5,6 @@
  */
 #pragma once
 
-#include <stdint.h>
 #include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -131,6 +131,10 @@ config SOC_CLK_TREE_SUPPORTED
     bool
     default y
 
+config SOC_ASSIST_DEBUG_SUPPORTED
+    bool
+    default y
+
 config SOC_WDT_SUPPORTED
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -51,7 +51,7 @@
 #define SOC_LP_TIMER_SUPPORTED          1
 #define SOC_LP_AON_SUPPORTED            1
 #define SOC_CLK_TREE_SUPPORTED          1
-//  \#define SOC_ASSIST_DEBUG_SUPPORTED      1    //TODO: [ESP32C61] IDF-9269
+#define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1       //TODO: [ESP32C61] IDF-9314
 //  \#define SOC_RNG_SUPPORTED               1    //TODO: [ESP32C61] IDF-9236

components/soc/esp32c61/register/soc/assist_debug_reg.h

@@ -5,7 +5,6 @@
  */
 #pragma once
 
-#include <stdint.h>
 #include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {

tools/test_apps/system/esp_intr_dump/expected_output/esp32c5.txt

@@ -27,10 +27,10 @@ CPU 0 interrupt status:
  24     *      *    Reserved
  25     *      *    Reserved
  26     *      *    Free
- 27     *      *    Free
+ 27     *      *    Reserved
  28     *      *    Free
  29     *      *    Free
  30     *      *    Free
  31     *      *    Free
-Interrupts available for general use: 23
-Shared interrupts: 1
+Interrupts available for general use: 22
+Shared interrupts: 1

tools/test_apps/system/esp_intr_dump/expected_output/esp32c61.txt

@@ -27,10 +27,10 @@ CPU 0 interrupt status:
  24     *      *    Reserved
  25     *      *    Reserved
  26     *      *    Free
- 27     *      *    Free
+ 27     *      *    Reserved
  28     *      *    Free
  29     *      *    Free
  30     *      *    Free
  31     *      *    Free
-Interrupts available for general use: 23
+Interrupts available for general use: 22
 Shared interrupts: 1

tools/test_apps/system/panic/pytest_panic.py

@@ -981,7 +981,6 @@ def test_hw_stack_guard_cpu(dut: PanicTestDut, cpu: int) -> None:
     assert end_addr > start_addr
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='TODO: IDF-8662 and IDF-9269')
 @pytest.mark.parametrize('config', CONFIGS_HW_STACK_GUARD, indirect=True)
 @pytest.mark.generic
 def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> None: