Merge branch 'bugfix/fix_modem_state_rx_bcn_failed' into 'master'

fix(wifi):fix modem state rx bcn failed when tbtt update, support modem state for coexist

Closes WIFI-6538, WIFIBUG-1052, WIFIBUG-128, WIFIBUG-1064, and WIFIBUG-1088

See merge request espressif/esp-idf!37238

components/esp_coex/include/private/esp_coexist_internal.h

@@ -396,6 +396,15 @@ int coex_schm_flexible_period_set(uint8_t period);
 uint8_t coex_schm_flexible_period_get(void);
 #endif
 
+/**
+ * @brief     Get coexistence scheme phase by phase index.
+ *
+ * @param     phase_idx    Coexistence phase index
+ *
+ * @return    Coexistence scheme phase
+ */
+void * coex_schm_get_phase_by_idx(int phase_idx);
+
 /**
   * @brief     Check the MD5 values of the coexistence adapter header files in IDF and WiFi library
   *

components/esp_hw_support/include/esp_private/esp_pmu.h

@@ -12,6 +12,7 @@
 #include <stdlib.h>
 
 #include "soc/soc_caps.h"
+#include "soc/clk_tree_defs.h"
 
 #if SOC_PMU_SUPPORTED
 #include "hal/pmu_hal.h"
@@ -228,12 +229,13 @@ uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t sleep_flags, uint32_t slow
  * @brief Calculate the hardware time overhead during sleep to compensate for sleep time
  *
  * @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
+ * @param slowclk_src slow clock source of pmu
  * @param slowclk_period re-calibrated slow clock period
  * @param fastclk_period re-calibrated fast clock period
  *
  * @return hardware time overhead in us
  */
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period);
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period);
 
 /**
  * @brief Get default sleep configuration
@@ -241,6 +243,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk
  * @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
  * @param clk_flags indicates the clock ICG cell that will be ungated
  * @param adjustment total software and hardware time overhead
+ * @param slowclk_src slow clock source of pmu
  * @param slowclk_period re-calibrated slow clock period in microseconds,
  *                       Q13.19 fixed point format
  * @param fastclk_period re-calibrated fast clock period in microseconds,
@@ -249,7 +252,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk
 
  * @return hardware time overhead in us
  */
-const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, uint32_t clk_flags, uint32_t adjustment, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
+const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, uint32_t clk_flags, uint32_t adjustment, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
 
 /**
  * @brief Prepare the chip to enter sleep mode

components/esp_hw_support/port/esp32/include/soc/rtc.h

@@ -481,6 +481,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief sleep configuration for rtc_sleep_init function
  */

components/esp_hw_support/port/esp32/rtc_time.c

@@ -191,6 +191,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32c2/include/soc/rtc.h

@@ -508,6 +508,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power down flags for rtc_sleep_pd function
  */

components/esp_hw_support/port/esp32c2/rtc_time.c

@@ -191,6 +191,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32c3/include/soc/rtc.h

@@ -536,6 +536,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power down flags for rtc_sleep_pd function
  */

components/esp_hw_support/port/esp32c3/rtc_time.c

@@ -194,6 +194,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32c5/include/soc/rtc.h

@@ -416,6 +416,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32c5/pmu_sleep.c

@@ -51,7 +51,7 @@ void pmu_sleep_disable_regdma_backup(void)
     }
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -98,8 +98,20 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk
      *                     |                           wake-up delay                          |
      */
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+    int min_slp_time_adjustment_us = 0;
+#if SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    if (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
+        const uint32_t slowclk_period_fixed = rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX);
+        const int min_slp_cycle_fixed = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
+        const int min_slp_cycle_calib = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+        const int min_slp_cycle_diff = (min_slp_cycle_calib > min_slp_cycle_fixed) ? \
+                       (min_slp_cycle_calib - min_slp_cycle_fixed) : (min_slp_cycle_fixed - min_slp_cycle_calib);
+        const int min_slp_time_diff = rtc_time_slowclk_to_us(min_slp_cycle_diff, slowclk_period_fixed);
+        min_slp_time_adjustment_us = (min_slp_cycle_calib > min_slp_cycle_fixed) ? min_slp_time_diff : -min_slp_time_diff;
+    }
+#endif
     const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
-    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us;
+    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us + min_slp_time_adjustment_us;
 #else
     const int rf_on_protect_time_us = 0;
     const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
@@ -114,13 +126,20 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
         pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
         const uint32_t sleep_flags,
         const uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         const uint32_t slowclk_period,
         const uint32_t fastclk_period
     )
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
-    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
+    const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
+#else
+    const uint32_t slowclk_period_fixed = slowclk_period;
+#endif
+
+    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
     param->hp_sys.analog_wait_target_cycle        = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
@@ -128,12 +147,12 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
     param->hp_sys.isolate_wait_cycle              = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period);
     param->hp_sys.reset_wait_cycle                = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period);
 
-    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
+    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_src, slowclk_period, fastclk_period);
     const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
     const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
     param->hp_sys.modem_wakeup_wait_cycle         = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
 
-    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
+    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period_fixed);
     param->lp_sys.analog_wait_target_cycle        = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
     param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
     param->lp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
@@ -153,6 +172,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         uint32_t sleep_flags,
         uint32_t clk_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
@@ -162,7 +182,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
     config->power = power_default;
 
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
-    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
 
     if (dslp) {
         config->param.lp_sys.analog_wait_target_cycle  = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);

components/esp_hw_support/port/esp32c5/rtc_time.c

@@ -196,6 +196,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32c6/include/soc/rtc.h

@@ -447,6 +447,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 
 // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
 // **WARNING**: The following are only for backwards compatibility.

components/esp_hw_support/port/esp32c6/pmu_sleep.c

@@ -105,7 +105,7 @@ void pmu_sleep_disable_regdma_backup(void)
     }
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -150,8 +150,20 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk
      *                     |                           wake-up delay                          |
      */
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+    int min_slp_time_adjustment_us = 0;
+#if SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    if (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
+        const uint32_t slowclk_period_fixed = rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX);
+        const int min_slp_cycle_fixed = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
+        const int min_slp_cycle_calib = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+        const int min_slp_cycle_diff = (min_slp_cycle_calib > min_slp_cycle_fixed) ? \
+                       (min_slp_cycle_calib - min_slp_cycle_fixed) : (min_slp_cycle_fixed - min_slp_cycle_calib);
+        const int min_slp_time_diff = rtc_time_slowclk_to_us(min_slp_cycle_diff, slowclk_period_fixed);
+        min_slp_time_adjustment_us = (min_slp_cycle_calib > min_slp_cycle_fixed) ? min_slp_time_diff : -min_slp_time_diff;
+    }
+#endif
     const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
-    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us;
+    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us + min_slp_time_adjustment_us;
 #else
     const int rf_on_protect_time_us = 0;
     const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
@@ -166,24 +178,31 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
         pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
         const uint32_t sleep_flags,
         const uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         const uint32_t slowclk_period,
         const uint32_t fastclk_period
     )
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
-    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
+    const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
+#else
+    const uint32_t slowclk_period_fixed = slowclk_period;
+#endif
+
+    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
     param->hp_sys.analog_wait_target_cycle        = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
     param->hp_sys.pll_stable_wait_cycle           = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
 
-    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
+    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_src, slowclk_period, fastclk_period);
     const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
     const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
     param->hp_sys.modem_wakeup_wait_cycle         = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
 
-    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
+    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period_fixed);
     param->lp_sys.analog_wait_target_cycle        = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
     param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
     param->lp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
@@ -201,6 +220,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         uint32_t sleep_flags,
         uint32_t clk_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
@@ -210,7 +230,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
     config->power = power_default;
 
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
-    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
 
     if (dslp) {
         config->param.lp_sys.analog_wait_target_cycle  = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);

components/esp_hw_support/port/esp32c6/rtc_time.c

@@ -271,6 +271,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32c61/include/soc/rtc.h

@@ -416,6 +416,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32c61/pmu_sleep.c

@@ -51,7 +51,7 @@ void pmu_sleep_disable_regdma_backup(void)
     }
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -98,8 +98,20 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk
      *                     |                           wake-up delay                          |
      */
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+    int min_slp_time_adjustment_us = 0;
+#if SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    if (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
+        const uint32_t slowclk_period_fixed = rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX);
+        const int min_slp_cycle_fixed = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
+        const int min_slp_cycle_calib = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+        const int min_slp_cycle_diff = (min_slp_cycle_calib > min_slp_cycle_fixed) ? \
+                       (min_slp_cycle_calib - min_slp_cycle_fixed) : (min_slp_cycle_fixed - min_slp_cycle_calib);
+        const int min_slp_time_diff = rtc_time_slowclk_to_us(min_slp_cycle_diff, slowclk_period_fixed);
+        min_slp_time_adjustment_us = (min_slp_cycle_calib > min_slp_cycle_fixed) ? min_slp_time_diff : -min_slp_time_diff;
+    }
+#endif
     const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
-    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us;
+    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us + min_slp_time_adjustment_us;
 #else
     const int rf_on_protect_time_us = 0;
     const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
@@ -114,13 +126,20 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
         pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
         const uint32_t sleep_flags,
         const uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         const uint32_t slowclk_period,
         const uint32_t fastclk_period
     )
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
-    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
+    const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
+#else
+    const uint32_t slowclk_period_fixed = slowclk_period;
+#endif
+
+    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
     param->hp_sys.analog_wait_target_cycle        = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
@@ -128,12 +147,12 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
     param->hp_sys.isolate_wait_cycle              = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period);
     param->hp_sys.reset_wait_cycle                = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period);
 
-    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
+    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_src, slowclk_period, fastclk_period);
     const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
     const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
     param->hp_sys.modem_wakeup_wait_cycle         = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
 
-    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
+    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period_fixed);
     param->lp_sys.analog_wait_target_cycle        = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
     param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
     param->lp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
@@ -153,6 +172,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         uint32_t sleep_flags,
         uint32_t clk_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
@@ -162,7 +182,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
     config->power = power_default;
 
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
-    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
 
     if (dslp) {
         config->param.lp_sys.analog_wait_target_cycle  = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);

components/esp_hw_support/port/esp32c61/rtc_time.c

@@ -196,6 +196,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32h2/include/soc/rtc.h

@@ -445,6 +445,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
 // **WARNING**: The following are only for backwards compatibility.
 // Please use the declarations in soc/clk_tree_defs.h instead.

components/esp_hw_support/port/esp32h2/pmu_sleep.c

@@ -63,7 +63,7 @@ void pmu_sleep_disable_regdma_backup(void)
     pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -133,6 +133,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         uint32_t sleep_flags,
         uint32_t clk_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp

components/esp_hw_support/port/esp32h2/rtc_time.c

@@ -271,6 +271,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32h21/include/soc/rtc.h

@@ -444,6 +444,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
 // **WARNING**: The following are only for backwards compatibility.
 // Please use the declarations in soc/clk_tree_defs.h instead.

components/esp_hw_support/port/esp32h21/pmu_sleep.c

@@ -64,7 +64,7 @@ void pmu_sleep_disable_regdma_backup(void)
     pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -133,6 +133,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         pmu_sleep_config_t *config,
         uint32_t sleep_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp

components/esp_hw_support/port/esp32h21/rtc_time.c

@@ -274,6 +274,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32h4/include/soc/rtc.h

@@ -448,6 +448,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32h4/rtc_time.c

@@ -262,6 +262,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32p4/include/soc/rtc.h

@@ -460,6 +460,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Enable or disable APLL
  *

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -106,7 +106,7 @@ uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t sleep_flags, uint32_t slow
     return (uint32_t)hp_hw_wait_time_us;
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     const uint32_t lp_hw_wait_time_us = pmu_sleep_calculate_lp_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
     const uint32_t hp_hw_wait_time_us = pmu_sleep_calculate_hp_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
@@ -121,6 +121,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
         pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
         const uint32_t sleep_flags,
         const uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         const uint32_t slowclk_period,
         const uint32_t fastclk_period
     )
@@ -151,6 +152,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         uint32_t sleep_flags,
         uint32_t clk_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
@@ -226,7 +228,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
 
     config->power = power_default;
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
-    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
 
     return config;
 }

components/esp_hw_support/port/esp32p4/rtc_time.c

@@ -222,6 +222,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32s2/include/soc/rtc.h

@@ -569,6 +569,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power down flags for rtc_sleep_pd function
  */

components/esp_hw_support/port/esp32s2/rtc_time.c

@@ -259,6 +259,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/port/esp32s3/include/soc/rtc.h

@@ -547,6 +547,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power up flags for rtc_sleep_pd function
  */

components/esp_hw_support/port/esp32s3/rtc_time.c

@@ -193,6 +193,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)

components/esp_hw_support/sleep_modes.c

@@ -953,7 +953,8 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t clk_fl
 
     pmu_sleep_config_t config;
     pmu_sleep_init(pmu_sleep_config_default(&config, sleep_flags, clk_flags, s_config.sleep_time_adjustment,
-            s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period, deep_sleep), deep_sleep);
+            rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
+            deep_sleep), deep_sleep);
 #else
     rtc_sleep_config_t config;
     rtc_sleep_get_default_config(sleep_flags, &config);
@@ -1409,7 +1410,7 @@ esp_err_t esp_light_sleep_start(void)
      */
 #if SOC_PMU_SUPPORTED
     int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out;
-    int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(sleep_flags, s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
+    int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(sleep_flags, rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
     s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment;
 #if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
     int sleep_time_sw_mmu_table_restore = (sleep_flags & PMU_SLEEP_PD_TOP) ? SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US : 0;

components/esp_rom/esp32c2/ld/esp32c2.rom.ld

@@ -529,7 +529,7 @@ pm_enable_active_timer = 0x40001b84;
 pm_enable_sleep_delay_timer = 0x40001b88;
 pm_local_tsf_process = 0x40001b8c;
 pm_set_beacon_filter = 0x40001b90;
-pm_is_in_wifi_slice_threshold = 0x40001b94;
+/*pm_is_in_wifi_slice_threshold = 0x40001b94;*/
 pm_is_waked = 0x40001b98;
 /*pm_keep_alive = 0x40001b9c;*/
 /* pm_on_beacon_rx = 0x40001ba0; */

components/esp_rom/esp32c3/ld/esp32c3.rom.ld

@@ -718,7 +718,7 @@ pm_enable_active_timer = 0x40001660;
 pm_enable_sleep_delay_timer = 0x40001664;
 pm_local_tsf_process = 0x40001668;
 pm_set_beacon_filter = 0x4000166c;
-pm_is_in_wifi_slice_threshold = 0x40001670;
+/*pm_is_in_wifi_slice_threshold = 0x40001670;*/
 pm_is_waked = 0x40001674;
 /*pm_keep_alive = 0x40001678;*/
 /* pm_on_beacon_rx = 0x4000167c; */

components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld

@@ -116,7 +116,7 @@ pm_mac_sleep = 0x40000d5c;
 pm_enable_sleep_delay_timer = 0x40000d64;
 pm_local_tsf_process = 0x40000d68;
 pm_set_beacon_filter = 0x40000d6c;
-pm_is_in_wifi_slice_threshold = 0x40000d70;
+/*pm_is_in_wifi_slice_threshold = 0x40000d70;*/
 pm_is_waked = 0x40000d74;
 /*pm_keep_alive = 0x40000d78;*/
 /*pm_on_beacon_rx = 0x40000d7c;*/
@@ -151,7 +151,7 @@ pm_is_twt_start = 0x40000dec;
 pm_twt_set_target_wdev_time = 0x40000df0;
 pm_twt_set_target_tsf = 0x40000df4;
 pm_enable_twt_keep_alive_timer = 0x40000df8;
-pm_mac_try_enable_modem_state = 0x40000dfc;
+/*pm_mac_try_enable_modem_state = 0x40000dfc;*/
 pm_beacon_monitor_tbtt_timeout_process = 0x40000e00;
 /*pm_update_next_tbtt = 0x40000e04;*/
 pm_twt_disallow_tx = 0x40000e08;

components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld

@@ -66,7 +66,7 @@ pm_mac_sleep = 0x40000c84;
 pm_enable_sleep_delay_timer = 0x40000c8c;
 pm_local_tsf_process = 0x40000c90;
 //pm_set_beacon_filter = 0x40000c94;
-pm_is_in_wifi_slice_threshold = 0x40000c98;
+/*pm_is_in_wifi_slice_threshold = 0x40000c98;*/
 pm_is_waked = 0x40000c9c;
 //pm_keep_alive = 0x40000ca0;
 /* pm_on_beacon_rx = 0x40000ca4; */

components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld

@@ -120,10 +120,10 @@ pm_mac_sleep = 0x40000cc8;
 pm_enable_sleep_delay_timer = 0x40000cd0;
 pm_local_tsf_process = 0x40000cd4;
 pm_set_beacon_filter = 0x40000cd8;
-pm_is_in_wifi_slice_threshold = 0x40000cdc;
+/*pm_is_in_wifi_slice_threshold = 0x40000cdc;*/
 pm_is_waked = 0x40000ce0;
 //pm_keep_alive = 0x40000ce4;
-pm_on_beacon_rx = 0x40000ce8;
+/*pm_on_beacon_rx = 0x40000ce8;*/
 pm_on_data_rx = 0x40000cec;
 pm_on_data_tx = 0x40000cf0;
 pm_on_tbtt = 0x40000cf4;
@@ -155,7 +155,7 @@ pm_is_twt_start = 0x40000d58;
 pm_twt_set_target_wdev_time = 0x40000d5c;
 pm_twt_set_target_tsf = 0x40000d60;
 pm_enable_twt_keep_alive_timer = 0x40000d64;
-pm_mac_try_enable_modem_state = 0x40000d68;
+/*pm_mac_try_enable_modem_state = 0x40000d68;*/
 pm_beacon_monitor_tbtt_timeout_process = 0x40000d6c;
 pm_update_next_tbtt = 0x40000d70;
 pm_twt_disallow_tx = 0x40000d74;

components/esp_rom/esp32s3/ld/esp32s3.rom.ld

@@ -972,7 +972,7 @@ pm_enable_active_timer = 0x40005460;
 pm_enable_sleep_delay_timer = 0x4000546c;
 pm_local_tsf_process = 0x40005478;
 pm_set_beacon_filter = 0x40005484;
-pm_is_in_wifi_slice_threshold = 0x40005490;
+/*pm_is_in_wifi_slice_threshold = 0x40005490;*/
 pm_is_waked = 0x4000549c;
 /*pm_keep_alive = 0x400054a8;*/
 /* pm_on_beacon_rx = 0x400054b4; */

components/esp_wifi/esp32/esp_adapter.c

@@ -594,6 +594,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -730,5 +739,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32c2/esp_adapter.c

@@ -535,6 +535,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -670,5 +679,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32c3/esp_adapter.c

@@ -552,6 +552,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -687,5 +696,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32c5/esp_adapter.c

@@ -610,6 +610,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -754,5 +763,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32c6/esp_adapter.c

@@ -541,6 +541,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -692,5 +701,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32c61/esp_adapter.c

@@ -610,6 +610,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -754,5 +763,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32p4/esp_adapter.c

@@ -554,6 +554,11 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
     return 1;
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+    return NULL;
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -810,5 +815,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32s2/esp_adapter.c

@@ -589,6 +589,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -724,5 +733,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/esp32s3/esp_adapter.c

@@ -606,6 +606,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -741,5 +750,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };

components/esp_wifi/include/esp_private/wifi_os_adapter.h

@@ -155,6 +155,7 @@ typedef struct wifi_osi_funcs_t {
 #endif
     int (*_coex_schm_flexible_period_set)(uint8_t);
     uint8_t (*_coex_schm_flexible_period_get)(void);
+    void * (*_coex_schm_get_phase_by_idx)(int);
     int32_t _magic;
 } wifi_osi_funcs_t;
 

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1547,6 +1547,10 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
     bool
     default y
 
+config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    bool
+    default y
+
 config SOC_PM_RETENTION_MODULE_NUM
     int
     default 32

components/soc/esp32c5/include/soc/soc_caps.h

@@ -618,6 +618,7 @@
 #define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC  (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
+#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
 
 #define SOC_PM_RETENTION_MODULE_NUM         (32)
 

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -1491,6 +1491,10 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
     bool
     default y
 
+config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    bool
+    default y
+
 config SOC_PM_RETENTION_MODULE_NUM
     int
     default 32

components/soc/esp32c6/include/soc/soc_caps.h

@@ -580,6 +580,7 @@
 #define SOC_PM_PAU_REGDMA_LINK_WIFIMAC      (1)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
+#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
 
 #define SOC_PM_RETENTION_MODULE_NUM         (32)
 

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -1155,6 +1155,10 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
     bool
     default y
 
+config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    bool
+    default y
+
 config SOC_PM_RETENTION_MODULE_NUM
     int
     default 32

components/soc/esp32c61/include/soc/soc_caps.h

@@ -474,6 +474,7 @@
 #define SOC_PM_PAU_REGDMA_LINK_WIFIMAC      (1)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
+#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
 
 #define SOC_PM_RETENTION_MODULE_NUM         (32)