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Merge branch 'bugfix/fix_esp32c5_external_coex_enable_fail_issue' into 'master'

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Bugfix/fix esp32c5 and esp32c6 external coex enable fail issue

Closes WIFI-6611, IDF-9141, and IDF-10531

See merge request espressif/esp-idf!33689
This commit is contained in:
Jiang Jiang Jian
2024-09-23 17:33:52 +08:00
parent 559e554178 63bb1c6719
commit bd4818413d
3 changed files with 34 additions and 17 deletions
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39
components/esp_coex/src/coexist.c
View File

@@ -1,21 +1,24 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_coexist.h"
#include "private/esp_coexist_internal.h"
#include "soc/soc_caps.h"
#if CONFIG_EXTERNAL_COEX_ENABLE
#include "esp_log.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "hal/gpio_hal.h"
#include "hal/gpio_types.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "esp_attr.h"
#include "esp_private/gpio.h"
#endif
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
#if SOC_EXTERNAL_COEX_ADVANCE
@@ -163,9 +166,6 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
return ESP_ERR_INVALID_ARG;
}
esp_coex_external_set_wire_type(wire_type);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_coex_external_params(g_external_coex_params, 0, 0);
#endif
if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
switch (wire_type)
@@ -174,7 +174,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
case EXTERN_COEX_WIRE_4:
{
esp_coex_external_set_txline(true);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.tx_line], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.tx_line));
esp_rom_gpio_connect_out_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_O1_TXLINE_IDX, false, false);
@@ -183,7 +183,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
#endif
case EXTERN_COEX_WIRE_3:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.priority], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.priority, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC1_BYPASS, 2);
@@ -192,7 +192,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.grant], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.grant, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.grant));
esp_rom_gpio_connect_out_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_O0_IDX, false, false);
@@ -200,7 +200,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.request], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.request, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC1_BYPASS, 2);
@@ -218,7 +218,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
{
case EXTERN_COEX_WIRE_4:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.tx_line], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC1_BYPASS, 2);
@@ -227,7 +227,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_3:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.priority], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.priority, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.priority));
esp_rom_gpio_connect_out_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_O1_IDX, false, false);
@@ -235,7 +235,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.grant], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.grant, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC1_BYPASS, 2);
@@ -244,7 +244,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.request], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.request, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.request));
esp_rom_gpio_connect_out_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_O0_IDX, false, false);
@@ -259,7 +259,16 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
return ESP_ERR_INVALID_ARG;
#endif /* SOC_EXTERNAL_COEX_ADVANCE */
}
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#endif
#if SOC_EXTERNAL_COEX_ADVANCE
esp_coex_external_params(g_external_coex_params, 0, 0);
#endif
esp_err_t ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#endif
if (ESP_OK != ret) {
return ESP_FAIL;
}

8
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -1235,6 +1235,14 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12

4
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -529,8 +529,8 @@
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
// #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)