forked from espressif/esp-idf
Merge branch 'feature/support_i2s_on_h21' into 'master'
feat(i2s): support i2s on esp32h21 Closes IDF-11606, IDF-11607, and IDF-11608 See merge request espressif/esp-idf!41767
This commit is contained in:
Kevin (Lao Kaiyao)
@@ -1,2 +1,2 @@
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| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
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| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
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@@ -1,3 +1,3 @@
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| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
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| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
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| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
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| ----------------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/i2s_periph.h"
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#include "soc/i2s_reg.h"
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#include "soc/gpio_sig_map.h"
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/*
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Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
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{
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.mck_out_sig = I2S_MCLK_OUT_IDX,
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.mck_in_sig = I2S_MCLK_IN_IDX,
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.m_tx_bck_sig = I2SO_BCK_OUT_IDX,
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.m_rx_bck_sig = I2SI_BCK_OUT_IDX,
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.m_tx_ws_sig = I2SO_WS_OUT_IDX,
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.m_rx_ws_sig = I2SI_WS_OUT_IDX,
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.s_tx_bck_sig = I2SO_BCK_IN_IDX,
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.s_rx_bck_sig = I2SI_BCK_IN_IDX,
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.s_tx_ws_sig = I2SO_WS_IN_IDX,
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.s_rx_ws_sig = I2SI_WS_IN_IDX,
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.data_out_sig = I2SO_SD_OUT_IDX,
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.data_in_sig = I2SI_SD_IN_IDX,
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.irq = ETS_I2S0_INTR_SOURCE,
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}
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};
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/**
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* I2S Registers to be saved during sleep retention
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* - I2S_RX_CONF_REG
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* - I2S_TX_CONF_REG
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* - I2S_RX_CONF1_REG
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* - I2S_TX_CONF1_REG
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* - I2S_TX_PCM2PDM_CONF_REG
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* - I2S_TX_PCM2PDM_CONF1_REG
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* - I2S_RX_TDM_CTRL_REG
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* - I2S_TX_TDM_CTRL_REG
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* - I2S_RXEOF_NUM_REG
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* - I2S_ETM_CONF_REG
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*/
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#define I2S_RETENTION_REGS_CNT 10
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#define I2S_RETENTION_REGS_BASE(i) I2S_RX_CONF_REG
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static const uint32_t i2s_regs_map[4] = {0x12330f, 0x0, 0x0, 0x0};
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#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) { \
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/* Save/restore the register values */ \
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \
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REGDMA_I2S_LINK(0x00), \
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I2S_RETENTION_REGS_BASE(i2s_port), \
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I2S_RETENTION_REGS_BASE(i2s_port), \
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I2S_RETENTION_REGS_CNT, 0, 0, \
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i2s_regs_map[0], i2s_regs_map[1], \
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i2s_regs_map[2], i2s_regs_map[3]), \
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.owner = ENTRY(0) | ENTRY(2)}, \
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};
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static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
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const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)] = {
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[0] = {
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.retention_module = SLEEP_RETENTION_MODULE_I2S0,
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.entry_array = i2s0_regs_retention,
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.array_size = ARRAY_SIZE(i2s0_regs_retention)
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},
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};
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@@ -43,6 +43,10 @@ config SOC_RTC_MEM_SUPPORTED
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bool
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default y
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config SOC_I2S_SUPPORTED
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bool
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default y
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config SOC_GPSPI_SUPPORTED
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bool
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default y
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@@ -471,6 +475,34 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
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bool
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default y
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config SOC_I2S_HW_VERSION_2
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bool
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default y
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config SOC_I2S_SUPPORTS_ETM
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bool
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default y
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config SOC_I2S_SUPPORTS_PCM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM_TX
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bool
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default y
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config SOC_I2S_PDM_MAX_TX_LINES
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int
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default 2
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config SOC_I2S_SUPPORTS_TDM
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bool
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default y
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config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
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bool
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default y
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@@ -373,6 +373,24 @@ typedef enum {
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CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
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} soc_clk_freq_calculation_src_t;
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///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of I2S
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*/
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#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
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/**
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* @brief I2S clock source enum
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*/
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
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I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
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// I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select PLL_F64M as the source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
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} soc_periph_i2s_clk_src_t;
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#ifdef __cplusplus
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}
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#endif
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@@ -47,7 +47,7 @@ typedef enum {
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ETS_HP_APM_M2_INTR_SOURCE,
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ETS_HP_APM_M3_INTR_SOURCE,
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ETS_MSPI_INTR_SOURCE,
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ETS_I2S1_INTR_SOURCE,
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ETS_I2S0_INTR_SOURCE,
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ETS_UHCI0_INTR_SOURCE,
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ETS_UART0_INTR_SOURCE,
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ETS_UART1_INTR_SOURCE,
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@@ -42,7 +42,7 @@
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#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11507
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#define SOC_RTC_FAST_MEM_SUPPORTED 1
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#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548
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// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608
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#define SOC_I2S_SUPPORTED 1
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// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573
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#define SOC_GPSPI_SUPPORTED 1
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#define SOC_LEDC_SUPPORTED 1
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@@ -268,13 +268,13 @@
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// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
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/*-------------------------- I2S CAPS ----------------------------------------*/
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// #define SOC_I2S_HW_VERSION_2 (1)
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// // #define SOC_I2S_SUPPORTS_ETM (1)
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// #define SOC_I2S_SUPPORTS_PCM (1)
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// #define SOC_I2S_SUPPORTS_PDM (1)
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// #define SOC_I2S_SUPPORTS_PDM_TX (1)
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// #define SOC_I2S_PDM_MAX_TX_LINES (2)
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// #define SOC_I2S_SUPPORTS_TDM (1)
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#define SOC_I2S_HW_VERSION_2 (1)
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#define SOC_I2S_SUPPORTS_ETM (1)
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#define SOC_I2S_SUPPORTS_PCM (1)
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#define SOC_I2S_SUPPORTS_PDM (1)
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#define SOC_I2S_SUPPORTS_PDM_TX (1)
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#define SOC_I2S_PDM_MAX_TX_LINES (2)
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#define SOC_I2S_SUPPORTS_TDM (1)
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/*-------------------------- LEDC CAPS ---------------------------------------*/
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#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
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@@ -25,4 +25,4 @@
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/*------------------------------- I2S ---------------------------------------*/
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// helper macros to access module attributes
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// #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
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#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
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@@ -38,7 +38,7 @@ const char *const esp_isr_names[] = {
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[28] = "HP_APM_M2",
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[29] = "HP_APM_M3",
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[30] = "MSPI",
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[31] = "I2S1",
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[31] = "I2S0",
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[32] = "UHCI0",
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[33] = "UART0",
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[34] = "UART1",
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@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -14,7 +14,7 @@ extern "C" {
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/** I2S_INT_RAW_REG register
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* I2S interrupt raw register, valid in level.
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*/
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#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
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#define I2S_INT_RAW_REG (DR_REG_I2S0_BASE + 0xc)
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/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the i2s_rx_done_int interrupt
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*/
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@@ -47,7 +47,7 @@ extern "C" {
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/** I2S_INT_ST_REG register
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* I2S interrupt status register.
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*/
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#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
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#define I2S_INT_ST_REG (DR_REG_I2S0_BASE + 0x10)
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/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the i2s_rx_done_int interrupt
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*/
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@@ -80,7 +80,7 @@ extern "C" {
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/** I2S_INT_ENA_REG register
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* I2S interrupt enable register.
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*/
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#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
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#define I2S_INT_ENA_REG (DR_REG_I2S0_BASE + 0x14)
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/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the i2s_rx_done_int interrupt
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*/
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@@ -113,7 +113,7 @@ extern "C" {
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/** I2S_INT_CLR_REG register
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* I2S interrupt clear register.
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*/
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#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
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#define I2S_INT_CLR_REG (DR_REG_I2S0_BASE + 0x18)
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/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the i2s_rx_done_int interrupt
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*/
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@@ -146,7 +146,7 @@ extern "C" {
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/** I2S_RX_CONF_REG register
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* I2S RX configure register
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*/
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#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
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#define I2S_RX_CONF_REG (DR_REG_I2S0_BASE + 0x20)
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/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
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* Set this bit to reset receiver
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*/
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@@ -290,7 +290,7 @@ extern "C" {
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/** I2S_TX_CONF_REG register
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* I2S TX configure register
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*/
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#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
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#define I2S_TX_CONF_REG (DR_REG_I2S0_BASE + 0x24)
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/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
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* Set this bit to reset transmitter
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*/
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@@ -466,7 +466,7 @@ extern "C" {
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/** I2S_RX_CONF1_REG register
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* I2S RX configure register 1
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*/
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#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
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#define I2S_RX_CONF1_REG (DR_REG_I2S0_BASE + 0x28)
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/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
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* The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
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* T_bck
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@@ -503,7 +503,7 @@ extern "C" {
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/** I2S_TX_CONF1_REG register
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* I2S TX configure register 1
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*/
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#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
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#define I2S_TX_CONF1_REG (DR_REG_I2S0_BASE + 0x2c)
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/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
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* The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
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* T_bck
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@@ -540,7 +540,7 @@ extern "C" {
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/** I2S_RX_CLKM_CONF_REG register
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* I2S RX clock configure register
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*/
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#define I2S_RX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x30)
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#define I2S_RX_CLKM_CONF_REG (DR_REG_I2S0_BASE + 0x30)
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/** I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
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* Integral I2S clock divider value
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*/
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@@ -574,7 +574,7 @@ extern "C" {
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/** I2S_TX_CLKM_CONF_REG register
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* I2S TX clock configure register
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*/
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#define I2S_TX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x34)
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#define I2S_TX_CLKM_CONF_REG (DR_REG_I2S0_BASE + 0x34)
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/** I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
|
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* Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
|
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* (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
|
||||
@@ -611,7 +611,7 @@ extern "C" {
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/** I2S_RX_CLKM_DIV_CONF_REG register
|
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* I2S RX module clock divider configure register
|
||||
*/
|
||||
#define I2S_RX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x38)
|
||||
#define I2S_RX_CLKM_DIV_CONF_REG (DR_REG_I2S0_BASE + 0x38)
|
||||
/** I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
|
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* For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
|
||||
* I2S_RX_CLKM_DIV_Z is (a-b).
|
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@@ -648,7 +648,7 @@ extern "C" {
|
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/** I2S_TX_CLKM_DIV_CONF_REG register
|
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* I2S TX module clock divider configure register
|
||||
*/
|
||||
#define I2S_TX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x3c)
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#define I2S_TX_CLKM_DIV_CONF_REG (DR_REG_I2S0_BASE + 0x3c)
|
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/** I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
|
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* For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
|
||||
* I2S_TX_CLKM_DIV_Z is (a-b).
|
||||
@@ -685,7 +685,7 @@ extern "C" {
|
||||
/** I2S_TX_PCM2PDM_CONF_REG register
|
||||
* I2S TX PCM2PDM configuration register
|
||||
*/
|
||||
#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40)
|
||||
#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S0_BASE + 0x40)
|
||||
/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
|
||||
* I2S TX PDM OSR2 value
|
||||
*/
|
||||
@@ -767,7 +767,7 @@ extern "C" {
|
||||
/** I2S_TX_PCM2PDM_CONF1_REG register
|
||||
* I2S TX PCM2PDM configuration register
|
||||
*/
|
||||
#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44)
|
||||
#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S0_BASE + 0x44)
|
||||
/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
|
||||
* I2S TX PDM Fp
|
||||
*/
|
||||
@@ -802,7 +802,7 @@ extern "C" {
|
||||
/** I2S_RX_TDM_CTRL_REG register
|
||||
* I2S TX TDM mode control register
|
||||
*/
|
||||
#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
|
||||
#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S0_BASE + 0x50)
|
||||
/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
|
||||
* 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
|
||||
* input 0 in this channel.
|
||||
@@ -942,7 +942,7 @@ extern "C" {
|
||||
/** I2S_TX_TDM_CTRL_REG register
|
||||
* I2S TX TDM mode control register
|
||||
*/
|
||||
#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
|
||||
#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S0_BASE + 0x54)
|
||||
/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
|
||||
* 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
|
||||
* 0 in this channel.
|
||||
@@ -1091,7 +1091,7 @@ extern "C" {
|
||||
/** I2S_RX_TIMING_REG register
|
||||
* I2S RX timing control register
|
||||
*/
|
||||
#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
|
||||
#define I2S_RX_TIMING_REG (DR_REG_I2S0_BASE + 0x58)
|
||||
/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
|
||||
* The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
|
||||
* delay by neg edge. 3: not used.
|
||||
@@ -1136,7 +1136,7 @@ extern "C" {
|
||||
/** I2S_TX_TIMING_REG register
|
||||
* I2S TX timing control register
|
||||
*/
|
||||
#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
|
||||
#define I2S_TX_TIMING_REG (DR_REG_I2S0_BASE + 0x5c)
|
||||
/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
|
||||
* The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
|
||||
* delay by neg edge. 3: not used.
|
||||
@@ -1189,7 +1189,7 @@ extern "C" {
|
||||
/** I2S_LC_HUNG_CONF_REG register
|
||||
* I2S HUNG configure register.
|
||||
*/
|
||||
#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
|
||||
#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S0_BASE + 0x60)
|
||||
/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
|
||||
* the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
|
||||
* when fifo hung counter is equal to this value
|
||||
@@ -1217,7 +1217,7 @@ extern "C" {
|
||||
/** I2S_RXEOF_NUM_REG register
|
||||
* I2S RX data number control register.
|
||||
*/
|
||||
#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
|
||||
#define I2S_RXEOF_NUM_REG (DR_REG_I2S0_BASE + 0x64)
|
||||
/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
|
||||
* The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
|
||||
* 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
|
||||
@@ -1230,7 +1230,7 @@ extern "C" {
|
||||
/** I2S_CONF_SIGLE_DATA_REG register
|
||||
* I2S signal data register
|
||||
*/
|
||||
#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
|
||||
#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S0_BASE + 0x68)
|
||||
/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
|
||||
* The configured constant channel data to be sent out.
|
||||
*/
|
||||
@@ -1242,7 +1242,7 @@ extern "C" {
|
||||
/** I2S_STATE_REG register
|
||||
* I2S TX status register
|
||||
*/
|
||||
#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
|
||||
#define I2S_STATE_REG (DR_REG_I2S0_BASE + 0x6c)
|
||||
/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
|
||||
* 1: i2s_tx is idle state. 0: i2s_tx is working.
|
||||
*/
|
||||
@@ -1254,7 +1254,7 @@ extern "C" {
|
||||
/** I2S_ETM_CONF_REG register
|
||||
* I2S ETM configure register
|
||||
*/
|
||||
#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
|
||||
#define I2S_ETM_CONF_REG (DR_REG_I2S0_BASE + 0x70)
|
||||
/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
|
||||
* I2S ETM send x words event. When sending word number of
|
||||
* reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
|
||||
@@ -1275,7 +1275,7 @@ extern "C" {
|
||||
/** I2S_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80)
|
||||
#define I2S_DATE_REG (DR_REG_I2S0_BASE + 0x80)
|
||||
/** I2S_DATE : R/W; bitpos: [27:0]; default: 35684944;
|
||||
* I2S version control register
|
||||
*/
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -445,7 +445,7 @@ typedef union {
|
||||
uint32_t val;
|
||||
} i2s_rx_tdm_ctrl_reg_t;
|
||||
|
||||
/** Type of rxeof_num register
|
||||
/** Type of rx_eof_num register
|
||||
* I2S RX data number control register.
|
||||
*/
|
||||
typedef union {
|
||||
@@ -458,7 +458,7 @@ typedef union {
|
||||
uint32_t reserved_12:20;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rxeof_num_reg_t;
|
||||
} i2s_rx_eof_num_reg_t;
|
||||
|
||||
|
||||
/** Group: TX Control and configuration registers */
|
||||
@@ -909,7 +909,7 @@ typedef union {
|
||||
uint32_t val;
|
||||
} i2s_lc_hung_conf_reg_t;
|
||||
|
||||
/** Type of conf_sigle_data register
|
||||
/** Type of conf_single_data register
|
||||
* I2S signal data register
|
||||
*/
|
||||
typedef union {
|
||||
@@ -920,7 +920,7 @@ typedef union {
|
||||
uint32_t single_data:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_conf_sigle_data_reg_t;
|
||||
} i2s_conf_single_data_reg_t;
|
||||
|
||||
|
||||
/** Group: TX status registers */
|
||||
@@ -1000,8 +1000,8 @@ typedef struct {
|
||||
volatile i2s_rx_timing_reg_t rx_timing;
|
||||
volatile i2s_tx_timing_reg_t tx_timing;
|
||||
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
|
||||
volatile i2s_rxeof_num_reg_t rxeof_num;
|
||||
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
|
||||
volatile i2s_rx_eof_num_reg_t rx_eof_num;
|
||||
volatile i2s_conf_single_data_reg_t conf_single_data;
|
||||
volatile i2s_state_reg_t state;
|
||||
volatile i2s_etm_conf_reg_t etm_conf;
|
||||
uint32_t reserved_074[3];
|
||||
|
||||
@@ -132,7 +132,6 @@ api-reference/peripherals/i2c_slave_v1.rst
|
||||
api-reference/peripherals/adc_continuous.rst
|
||||
api-reference/peripherals/sdspi_host.rst
|
||||
api-reference/peripherals/vad.rst
|
||||
api-reference/peripherals/i2s.rst
|
||||
api-reference/peripherals/isp.rst
|
||||
api-reference/peripherals/usb_host/usb_host_notes_usbh.rst
|
||||
api-reference/peripherals/usb_host/usb_host_notes_ext_hub.rst
|
||||
|
||||
@@ -116,13 +116,9 @@ Overview of All Modes
|
||||
========= ======== ============ ============ ========= ======== ======== ==========
|
||||
ESP32 I2S 0/1 I2S 0 I2S 0 I2S 0/1 none I2S 0 I2S 0
|
||||
ESP32-S2 I2S 0 none none none none none I2S 0
|
||||
ESP32-C3 I2S 0 I2S 0 none I2S 0 I2S 0 none none
|
||||
ESP32-C6 I2S 0 I2S 0 none I2S 0 I2S 0 none none
|
||||
ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 I2S 0/1 none none
|
||||
ESP32-H2 I2S 0 I2S 0 none I2S 0 I2S 0 none none
|
||||
ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 I2S 0~2 none none
|
||||
ESP32-C5 I2S 0 I2S 0 none I2S 0 I2S 0 none none
|
||||
ESP32-C61 I2S 0 I2S 0 none I2S 0 I2S 0 none none
|
||||
others I2S 0 I2S 0 none I2S 0 I2S 0 none none
|
||||
========= ======== ============ ============ ========= ======== ======== ==========
|
||||
|
||||
.. note::
|
||||
@@ -225,11 +221,11 @@ In standard mode, there are always two sound channels, i.e., the left and right
|
||||
|
||||
TDM (Time Division Multiplexing) mode supports up to 16 slots. These slots can be enabled by :cpp:member:`i2s_tdm_slot_config_t::slot_mask`.
|
||||
|
||||
.. only:: SOC_I2S_TDM_FULL_DATA_WIDTH
|
||||
.. only:: not esp32c3 or esp32c6 or esp32s3
|
||||
|
||||
Any data bit-width is supported no matter how many slots are enabled, which means there can be up to ``32 bit-width * 16 slots = 512 bit`` data in one frame.
|
||||
|
||||
.. only:: not SOC_I2S_TDM_FULL_DATA_WIDTH
|
||||
.. only:: esp32c3 or esp32c6 or esp32s3
|
||||
|
||||
But due to the hardware limitation, only up to 4 slots are supported while the slot is set to 32 bit-width, and 8 slots for 16 bit-width, 16 slots for 8 bit-width. The slot communication format of TDM is almost the same as the standard mode, yet with some small differences.
|
||||
|
||||
|
||||
@@ -116,13 +116,9 @@ I2S 通信模式
|
||||
========= ======== ========== ========== =========== ========== ======== ===========
|
||||
ESP32 I2S 0/1 I2S 0 I2S 0 I2S 0/1 无 I2S 0 I2S 0
|
||||
ESP32-S2 I2S 0 无 无 无 无 无 I2S 0
|
||||
ESP32-C3 I2S 0 I2S 0 无 I2S 0 I2S 0 无 无
|
||||
ESP32-C6 I2S 0 I2S 0 无 I2S 0 I2S 0 无 无
|
||||
ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 I2S 0/1 无 无
|
||||
ESP32-H2 I2S 0 I2S 0 无 I2S 0 I2S 0 无 无
|
||||
ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 I2S 0~2 无 无
|
||||
ESP32-C5 I2S 0 I2S 0 无 I2S 0 I2S 0 无 无
|
||||
ESP32-C61 I2S 0 I2S 0 无 I2S 0 I2S 0 无 无
|
||||
others I2S 0 I2S 0 无 I2S 0 I2S 0 无 无
|
||||
========= ======== ========== ========== =========== ========== ======== ===========
|
||||
|
||||
.. note::
|
||||
@@ -225,11 +221,11 @@ ESP32-C61 I2S 0 I2S 0 无 I2S 0 I2S 0 无
|
||||
|
||||
TDM（Time Division Multiplexing，时分多路复用）模式最多支持 16 个声道，可通过 :cpp:member:`i2s_tdm_slot_config_t::slot_mask` 启用通道。
|
||||
|
||||
.. only:: SOC_I2S_TDM_FULL_DATA_WIDTH
|
||||
.. only:: not esp32c3 or esp32c6 or esp32s3
|
||||
|
||||
该模式下无论启用多少声道，都支持任意数据位宽，也即一个帧中最多可以有 ``32 位宽 * 16 个声道 = 512 位`` 的数据。
|
||||
|
||||
.. only:: not SOC_I2S_TDM_FULL_DATA_WIDTH
|
||||
.. only:: esp32c3 or esp32c6 or esp32s3
|
||||
|
||||
但由于硬件限制，声道设置为 32 位宽时最多只能支持 4 个声道，16 位宽时最多只能支持 8 个声道，8 位宽时最多只能支持 16 个声道。TDM 的声道通信格式与标准模式基本相同，但有一些细微差别。
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S Basic PDM Mode Example
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S Basic Standard Mode Example
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S Basic TDM Mode Example
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S TDM Example -- ES7210 4-Ch ADC Codec
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S ES8311 Example
|
||||
|
||||
|
||||
Reference in New Issue
Block a user