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feat(esp32h4): add soc register header files (stage2_1)

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generated soc headers from csv folder(part1)
This commit is contained in:
Chen Jichang
2025-02-17 18:16:51 +08:00
parent 68b79fc138
commit c1149f24e0
79 changed files with 135957 additions and 0 deletions
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components/soc/esp32h4/include/soc/spi_mem_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/spi_mem_c_reg.h"
#include "soc/spi1_mem_reg.h"

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components/soc/esp32h4/include/soc/spi_mem_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/spi_mem_c_struct.h"
#include "soc/spi1_mem_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct spi1_mem_dev_s spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM1;
extern spi_mem_c_dev_t SPIMEM0;
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/ahb_dma_reg.h Normal file
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components/soc/esp32h4/register/soc/ahb_dma_struct.h Normal file
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components/soc/esp32h4/register/soc/apb_saradc_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** APB_SARADC_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
#define APB_SARADC_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U
#define APB_SARADC_SARADC_START_FORCE_S 0
/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
#define APB_SARADC_SARADC_START (BIT(1))
#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
#define APB_SARADC_SARADC_START_V 0x00000001U
#define APB_SARADC_SARADC_START_S 1
/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U
#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6
/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7
/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15
/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23
/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27
/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29))
#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U
#define APB_SARADC_SARADC2_PWDET_DRV_S 29
/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30
/** APB_SARADC_CTRL2_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0
/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1
/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR1_INV_S 9
/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR2_INV_S 10
/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_S 12
/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define APB_SARADC_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U
#define APB_SARADC_SARADC_TIMER_EN_S 24
/** APB_SARADC_FILTER_CTRL1_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26
/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29
/** APB_SARADC_SAR_PATT_TAB1_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0
/** APB_SARADC_SAR_PATT_TAB2_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0
/** APB_SARADC_ONETIME_SAMPLE_REG register
* digital saradc configure register
*/
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23
/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25
/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
#define APB_SARADC_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U
#define APB_SARADC_SARADC_ONETIME_START_S 29
/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30
/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31
/** APB_SARADC_ARB_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/** APB_SARADC_FILTER_CTRL0_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22
/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U
#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31
/** APB_SARADC_SAR1DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_S 0
/** APB_SARADC_SAR2DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_S 0
/** APB_SARADC_THRES0_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18
/** APB_SARADC_THRES1_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18
/** APB_SARADC_THRES_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27
/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_EN_S 30
/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_EN_S 31
/** APB_SARADC_INT_ENA_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31
/** APB_SARADC_INT_RAW_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31
/** APB_SARADC_INT_ST_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31
/** APB_SARADC_INT_CLR_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31
/** APB_SARADC_DMA_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U
#define APB_SARADC_APB_ADC_TRANS_S 31
/** APB_SARADC_CLKM_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_S 0
/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
#define APB_SARADC_CLKM_DIV_B 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_S 8
/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
#define APB_SARADC_CLKM_DIV_A 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_S 14
/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
#define APB_SARADC_CLK_EN_V 0x00000001U
#define APB_SARADC_CLK_EN_S 20
/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
#define APB_SARADC_CLK_SEL 0x00000003U
#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
#define APB_SARADC_CLK_SEL_V 0x00000003U
#define APB_SARADC_CLK_SEL_S 21
/** APB_SARADC_APB_TSENS_CTRL_REG register
* digital tsens configure register
*/
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
#define APB_SARADC_TSENS_OUT 0x000000FFU
#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
#define APB_SARADC_TSENS_OUT_V 0x000000FFU
#define APB_SARADC_TSENS_OUT_S 0
/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
#define APB_SARADC_TSENS_IN_INV_V 0x00000001U
#define APB_SARADC_TSENS_IN_INV_S 13
/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_S 14
/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
#define APB_SARADC_TSENS_PU_V 0x00000001U
#define APB_SARADC_TSENS_PU_S 22
/** APB_SARADC_TSENS_CTRL2_REG register
* digital tsens configure register
*/
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U
#define APB_SARADC_TSENS_CLK_SEL_S 15
/** APB_SARADC_CALI_REG register
* digital saradc configure register
*/
#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_S 0
/** APB_TSENS_WAKE_REG register
* digital tsens configure register
*/
#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_S 0
/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_S 8
/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16
/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
#define APB_SARADC_WAKEUP_MODE (BIT(17))
#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
#define APB_SARADC_WAKEUP_MODE_V 0x00000001U
#define APB_SARADC_WAKEUP_MODE_S 17
/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
#define APB_SARADC_WAKEUP_EN (BIT(18))
#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
#define APB_SARADC_WAKEUP_EN_V 0x00000001U
#define APB_SARADC_WAKEUP_EN_S 18
/** APB_TSENS_SAMPLE_REG register
* digital tsens configure register
*/
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_S 0
/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16))
#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U
#define APB_SARADC_TSENS_SAMPLE_EN_S 16
/** APB_SARADC_CTRL_DATE_REG register
* version
*/
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
#define APB_SARADC_DATE 0xFFFFFFFFU
#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
#define APB_SARADC_DATE_V 0xFFFFFFFFU
#define APB_SARADC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of saradc_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
uint32_t saradc_saradc_start_force:1;
/** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
uint32_t saradc_saradc_start:1;
uint32_t reserved_2:4;
/** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
uint32_t saradc_saradc_sar_clk_gated:1;
/** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
uint32_t saradc_saradc_sar_clk_div:8;
/** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t saradc_saradc_sar_patt_len:3;
uint32_t reserved_18:5;
/** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t saradc_saradc_sar_patt_p_clear:1;
uint32_t reserved_24:3;
/** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
uint32_t saradc_saradc_xpd_sar_force:2;
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
uint32_t saradc_saradc2_pwdet_drv:1;
/** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t saradc_saradc_wait_arb_cycle:2;
};
uint32_t val;
} apb_saradc_ctrl_reg_t;
/** Type of saradc_ctrl2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
uint32_t saradc_saradc_meas_num_limit:1;
/** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t saradc_saradc_max_meas_num:8;
/** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar1_inv:1;
/** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar2_inv:1;
uint32_t reserved_11:1;
/** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t saradc_saradc_timer_target:12;
/** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t saradc_saradc_timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} apb_saradc_ctrl2_reg_t;
/** Type of saradc_filter_ctrl1 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
uint32_t saradc_apb_saradc_filter_factor1:3;
/** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
uint32_t saradc_apb_saradc_filter_factor0:3;
};
uint32_t val;
} apb_saradc_filter_ctrl1_reg_t;
/** Type of saradc_sar_patt_tab1 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab1_reg_t;
/** Type of saradc_sar_patt_tab2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab2_reg_t;
/** Type of saradc_onetime_sample register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
uint32_t saradc_saradc_onetime_atten:2;
/** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
uint32_t saradc_saradc_onetime_channel:4;
/** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
uint32_t saradc_saradc_onetime_start:1;
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
uint32_t saradc_saradc2_onetime_sample:1;
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
uint32_t saradc_saradc1_onetime_sample:1;
};
uint32_t val;
} apb_saradc_onetime_sample_reg_t;
/** Type of saradc_arb_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t saradc_adc_arb_apb_force:1;
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t saradc_adc_arb_rtc_force:1;
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t saradc_adc_arb_wifi_force:1;
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t saradc_adc_arb_grant_force:1;
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t saradc_adc_arb_apb_priority:2;
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t saradc_adc_arb_rtc_priority:2;
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t saradc_adc_arb_wifi_priority:2;
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t saradc_adc_arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} apb_saradc_arb_ctrl_reg_t;
/** Type of saradc_filter_ctrl0 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:18;
/** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel1:4;
/** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel0:4;
uint32_t reserved_26:5;
/** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t saradc_apb_saradc_filter_reset:1;
};
uint32_t val;
} apb_saradc_filter_ctrl0_reg_t;
/** Type of saradc_sar1data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
uint32_t saradc_apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar1data_status_reg_t;
/** Type of saradc_sar2data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
uint32_t saradc_apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar2data_status_reg_t;
/** Type of saradc_thres0_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
uint32_t saradc_apb_saradc_thres0_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_high:13;
/** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres0_ctrl_reg_t;
/** Type of saradc_thres1_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
uint32_t saradc_apb_saradc_thres1_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_high:13;
/** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres1_ctrl_reg_t;
/** Type of saradc_thres_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
uint32_t saradc_apb_saradc_thres_all_en:1;
uint32_t reserved_28:2;
/** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
uint32_t saradc_apb_saradc_thres1_en:1;
/** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
uint32_t saradc_apb_saradc_thres0_en:1;
};
uint32_t val;
} apb_saradc_thres_ctrl_reg_t;
/** Type of saradc_int_ena register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
uint32_t saradc_apb_saradc_tsens_int_ena:1;
/** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
/** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
/** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
/** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
/** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
uint32_t saradc_apb_saradc2_done_int_ena:1;
/** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
uint32_t saradc_apb_saradc1_done_int_ena:1;
};
uint32_t val;
} apb_saradc_int_ena_reg_t;
/** Type of saradc_int_raw register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
uint32_t saradc_apb_saradc_tsens_int_raw:1;
/** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
/** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
/** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
/** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
/** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
uint32_t saradc_apb_saradc2_done_int_raw:1;
/** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
uint32_t saradc_apb_saradc1_done_int_raw:1;
};
uint32_t val;
} apb_saradc_int_raw_reg_t;
/** Type of saradc_int_st register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
uint32_t saradc_apb_saradc_tsens_int_st:1;
/** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
uint32_t saradc_apb_saradc_thres1_low_int_st:1;
/** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
uint32_t saradc_apb_saradc_thres0_low_int_st:1;
/** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
uint32_t saradc_apb_saradc_thres1_high_int_st:1;
/** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
uint32_t saradc_apb_saradc_thres0_high_int_st:1;
/** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
uint32_t saradc_apb_saradc2_done_int_st:1;
/** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
uint32_t saradc_apb_saradc1_done_int_st:1;
};
uint32_t val;
} apb_saradc_int_st_reg_t;
/** Type of saradc_int_clr register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
uint32_t saradc_apb_saradc_tsens_int_clr:1;
/** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
/** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
/** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
/** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
/** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
uint32_t saradc_apb_saradc2_done_int_clr:1;
/** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
uint32_t saradc_apb_saradc1_done_int_clr:1;
};
uint32_t val;
} apb_saradc_int_clr_reg_t;
/** Type of saradc_dma_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t saradc_apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t saradc_apb_adc_reset_fsm:1;
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t saradc_apb_adc_trans:1;
};
uint32_t val;
} apb_saradc_dma_conf_reg_t;
/** Type of saradc_clkm_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t saradc_clkm_div_b:6;
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t saradc_clkm_div_a:6;
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
uint32_t saradc_clk_en:1;
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
uint32_t saradc_clk_sel:2;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_clkm_conf_reg_t;
/** Type of saradc_apb_tsens_ctrl register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
uint32_t saradc_tsens_out:8;
uint32_t reserved_8:5;
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
uint32_t saradc_tsens_in_inv:1;
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
uint32_t saradc_tsens_clk_div:8;
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
uint32_t saradc_tsens_pu:1;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_apb_tsens_ctrl_reg_t;
/** Type of saradc_tsens_ctrl2 register
* digital tsens configure register
*/
typedef union {
struct {
uint32_t reserved_0:15;
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
uint32_t saradc_tsens_clk_sel:1;
uint32_t reserved_16:16;
};
uint32_t val;
} apb_saradc_tsens_ctrl2_reg_t;
/** Type of saradc_cali register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
uint32_t saradc_apb_saradc_cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_cali_reg_t;
/** Type of tsens_wake register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
uint32_t saradc_wakeup_th_low:8;
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
uint32_t saradc_wakeup_th_high:8;
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
uint32_t saradc_wakeup_over_upper_th:1;
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
uint32_t saradc_wakeup_mode:1;
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
uint32_t saradc_wakeup_en:1;
uint32_t reserved_19:13;
};
uint32_t val;
} apb_tsens_wake_reg_t;
/** Type of tsens_sample register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
uint32_t saradc_tsens_sample_rate:16;
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
uint32_t saradc_tsens_sample_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_tsens_sample_reg_t;
/** Type of saradc_ctrl_date register
* version
*/
typedef union {
struct {
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
uint32_t saradc_date:32;
};
uint32_t val;
} apb_saradc_ctrl_date_reg_t;
typedef struct {
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
uint32_t reserved_00c[3];
volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
volatile apb_saradc_int_ena_reg_t saradc_int_ena;
volatile apb_saradc_int_raw_reg_t saradc_int_raw;
volatile apb_saradc_int_st_reg_t saradc_int_st;
volatile apb_saradc_int_clr_reg_t saradc_int_clr;
volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
volatile apb_saradc_cali_reg_t saradc_cali;
volatile apb_tsens_wake_reg_t tsens_wake;
volatile apb_tsens_sample_reg_t tsens_sample;
uint32_t reserved_06c[228];
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
} apb_dev_t;
extern apb_dev_t APB_SARADC;
#ifndef __cplusplus
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/asrc_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASRC_CHNL0_CFG0_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG0_REG (DR_REG_ASRC_BASE + 0x0)
/** ASRC_CHNL0_RS2_STG1_BYPASS : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel0.
*/
#define ASRC_CHNL0_RS2_STG1_BYPASS (BIT(0))
#define ASRC_CHNL0_RS2_STG1_BYPASS_M (ASRC_CHNL0_RS2_STG1_BYPASS_V << ASRC_CHNL0_RS2_STG1_BYPASS_S)
#define ASRC_CHNL0_RS2_STG1_BYPASS_V 0x00000001U
#define ASRC_CHNL0_RS2_STG1_BYPASS_S 0
/** ASRC_CHNL0_RS2_STG0_BYPASS : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel0.
*/
#define ASRC_CHNL0_RS2_STG0_BYPASS (BIT(1))
#define ASRC_CHNL0_RS2_STG0_BYPASS_M (ASRC_CHNL0_RS2_STG0_BYPASS_V << ASRC_CHNL0_RS2_STG0_BYPASS_S)
#define ASRC_CHNL0_RS2_STG0_BYPASS_V 0x00000001U
#define ASRC_CHNL0_RS2_STG0_BYPASS_S 1
/** ASRC_CHNL0_FRAC_BYPASS : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel0.
*/
#define ASRC_CHNL0_FRAC_BYPASS (BIT(2))
#define ASRC_CHNL0_FRAC_BYPASS_M (ASRC_CHNL0_FRAC_BYPASS_V << ASRC_CHNL0_FRAC_BYPASS_S)
#define ASRC_CHNL0_FRAC_BYPASS_V 0x00000001U
#define ASRC_CHNL0_FRAC_BYPASS_S 2
/** ASRC_CHNL0_RS2_STG1_MODE : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL0_RS2_STG1_MODE (BIT(3))
#define ASRC_CHNL0_RS2_STG1_MODE_M (ASRC_CHNL0_RS2_STG1_MODE_V << ASRC_CHNL0_RS2_STG1_MODE_S)
#define ASRC_CHNL0_RS2_STG1_MODE_V 0x00000001U
#define ASRC_CHNL0_RS2_STG1_MODE_S 3
/** ASRC_CHNL0_RS2_STG0_MODE : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL0_RS2_STG0_MODE (BIT(4))
#define ASRC_CHNL0_RS2_STG0_MODE_M (ASRC_CHNL0_RS2_STG0_MODE_V << ASRC_CHNL0_RS2_STG0_MODE_S)
#define ASRC_CHNL0_RS2_STG0_MODE_V 0x00000001U
#define ASRC_CHNL0_RS2_STG0_MODE_S 4
/** ASRC_CHNL0_FRAC_AHEAD : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel0, it should
* be 1 when input frequency is higher the output.
*/
#define ASRC_CHNL0_FRAC_AHEAD (BIT(5))
#define ASRC_CHNL0_FRAC_AHEAD_M (ASRC_CHNL0_FRAC_AHEAD_V << ASRC_CHNL0_FRAC_AHEAD_S)
#define ASRC_CHNL0_FRAC_AHEAD_V 0x00000001U
#define ASRC_CHNL0_FRAC_AHEAD_S 5
/** ASRC_CHNL0_MODE : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
#define ASRC_CHNL0_MODE 0x00000003U
#define ASRC_CHNL0_MODE_M (ASRC_CHNL0_MODE_V << ASRC_CHNL0_MODE_S)
#define ASRC_CHNL0_MODE_V 0x00000003U
#define ASRC_CHNL0_MODE_S 7
/** ASRC_CHNL0_SEL : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
#define ASRC_CHNL0_SEL (BIT(9))
#define ASRC_CHNL0_SEL_M (ASRC_CHNL0_SEL_V << ASRC_CHNL0_SEL_S)
#define ASRC_CHNL0_SEL_V 0x00000001U
#define ASRC_CHNL0_SEL_S 9
/** ASRC_CHNL0_CFG1_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG1_REG (DR_REG_ASRC_BASE + 0x4)
/** ASRC_CHNL0_FRAC_M : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
#define ASRC_CHNL0_FRAC_M 0x000003FFU
#define ASRC_CHNL0_FRAC_M_M (ASRC_CHNL0_FRAC_M_V << ASRC_CHNL0_FRAC_M_S)
#define ASRC_CHNL0_FRAC_M_V 0x000003FFU
#define ASRC_CHNL0_FRAC_M_S 0
/** ASRC_CHNL0_FRAC_L : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
#define ASRC_CHNL0_FRAC_L 0x000003FFU
#define ASRC_CHNL0_FRAC_L_M (ASRC_CHNL0_FRAC_L_V << ASRC_CHNL0_FRAC_L_S)
#define ASRC_CHNL0_FRAC_L_V 0x000003FFU
#define ASRC_CHNL0_FRAC_L_S 10
/** ASRC_CHNL0_CFG2_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG2_REG (DR_REG_ASRC_BASE + 0x8)
/** ASRC_CHNL0_FRAC_RECIPL : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel0.
*/
#define ASRC_CHNL0_FRAC_RECIPL 0x000FFFFFU
#define ASRC_CHNL0_FRAC_RECIPL_M (ASRC_CHNL0_FRAC_RECIPL_V << ASRC_CHNL0_FRAC_RECIPL_S)
#define ASRC_CHNL0_FRAC_RECIPL_V 0x000FFFFFU
#define ASRC_CHNL0_FRAC_RECIPL_S 0
/** ASRC_CHNL0_CFG3_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG3_REG (DR_REG_ASRC_BASE + 0xc)
/** ASRC_CHNL0_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel0.
*/
#define ASRC_CHNL0_RESET (BIT(0))
#define ASRC_CHNL0_RESET_M (ASRC_CHNL0_RESET_V << ASRC_CHNL0_RESET_S)
#define ASRC_CHNL0_RESET_V 0x00000001U
#define ASRC_CHNL0_RESET_S 0
/** ASRC_CHNL0_CFG4_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG4_REG (DR_REG_ASRC_BASE + 0x10)
/** ASRC_CHNL0_START : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel0.
*/
#define ASRC_CHNL0_START (BIT(0))
#define ASRC_CHNL0_START_M (ASRC_CHNL0_START_V << ASRC_CHNL0_START_S)
#define ASRC_CHNL0_START_V 0x00000001U
#define ASRC_CHNL0_START_S 0
/** ASRC_CHNL0_CFG5_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG5_REG (DR_REG_ASRC_BASE + 0x14)
/** ASRC_CHNL0_IN_CNT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
#define ASRC_CHNL0_IN_CNT_ENA (BIT(0))
#define ASRC_CHNL0_IN_CNT_ENA_M (ASRC_CHNL0_IN_CNT_ENA_V << ASRC_CHNL0_IN_CNT_ENA_S)
#define ASRC_CHNL0_IN_CNT_ENA_V 0x00000001U
#define ASRC_CHNL0_IN_CNT_ENA_S 0
/** ASRC_CHNL0_IN_CNT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
#define ASRC_CHNL0_IN_CNT_CLR (BIT(1))
#define ASRC_CHNL0_IN_CNT_CLR_M (ASRC_CHNL0_IN_CNT_CLR_V << ASRC_CHNL0_IN_CNT_CLR_S)
#define ASRC_CHNL0_IN_CNT_CLR_V 0x00000001U
#define ASRC_CHNL0_IN_CNT_CLR_S 1
/** ASRC_CHNL0_IN_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data from the DMA
*/
#define ASRC_CHNL0_IN_LEN 0x00FFFFFFU
#define ASRC_CHNL0_IN_LEN_M (ASRC_CHNL0_IN_LEN_V << ASRC_CHNL0_IN_LEN_S)
#define ASRC_CHNL0_IN_LEN_V 0x00FFFFFFU
#define ASRC_CHNL0_IN_LEN_S 8
/** ASRC_CHNL0_CFG6_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG6_REG (DR_REG_ASRC_BASE + 0x18)
/** ASRC_CHNL0_OUT_EOF_GEN_MODE : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
#define ASRC_CHNL0_OUT_EOF_GEN_MODE 0x00000003U
#define ASRC_CHNL0_OUT_EOF_GEN_MODE_M (ASRC_CHNL0_OUT_EOF_GEN_MODE_V << ASRC_CHNL0_OUT_EOF_GEN_MODE_S)
#define ASRC_CHNL0_OUT_EOF_GEN_MODE_V 0x00000003U
#define ASRC_CHNL0_OUT_EOF_GEN_MODE_S 0
/** ASRC_CHNL0_OUT_CNT_ENA : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
#define ASRC_CHNL0_OUT_CNT_ENA (BIT(2))
#define ASRC_CHNL0_OUT_CNT_ENA_M (ASRC_CHNL0_OUT_CNT_ENA_V << ASRC_CHNL0_OUT_CNT_ENA_S)
#define ASRC_CHNL0_OUT_CNT_ENA_V 0x00000001U
#define ASRC_CHNL0_OUT_CNT_ENA_S 2
/** ASRC_CHNL0_OUT_CNT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
#define ASRC_CHNL0_OUT_CNT_CLR (BIT(3))
#define ASRC_CHNL0_OUT_CNT_CLR_M (ASRC_CHNL0_OUT_CNT_CLR_V << ASRC_CHNL0_OUT_CNT_CLR_S)
#define ASRC_CHNL0_OUT_CNT_CLR_V 0x00000001U
#define ASRC_CHNL0_OUT_CNT_CLR_S 3
/** ASRC_CHNL0_OUT_LEN_COMP : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl0_out_cnt >=
* reg_chnl0_out_len
*/
#define ASRC_CHNL0_OUT_LEN_COMP (BIT(4))
#define ASRC_CHNL0_OUT_LEN_COMP_M (ASRC_CHNL0_OUT_LEN_COMP_V << ASRC_CHNL0_OUT_LEN_COMP_S)
#define ASRC_CHNL0_OUT_LEN_COMP_V 0x00000001U
#define ASRC_CHNL0_OUT_LEN_COMP_S 4
/** ASRC_CHNL0_OUT_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
#define ASRC_CHNL0_OUT_LEN 0x00FFFFFFU
#define ASRC_CHNL0_OUT_LEN_M (ASRC_CHNL0_OUT_LEN_V << ASRC_CHNL0_OUT_LEN_S)
#define ASRC_CHNL0_OUT_LEN_V 0x00FFFFFFU
#define ASRC_CHNL0_OUT_LEN_S 8
/** ASRC_CHNL0_FIFO_CTRL_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_FIFO_CTRL_REG (DR_REG_ASRC_BASE + 0x1c)
/** ASRC_CHNL0_INFIFO_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
#define ASRC_CHNL0_INFIFO_RESET (BIT(0))
#define ASRC_CHNL0_INFIFO_RESET_M (ASRC_CHNL0_INFIFO_RESET_V << ASRC_CHNL0_INFIFO_RESET_S)
#define ASRC_CHNL0_INFIFO_RESET_V 0x00000001U
#define ASRC_CHNL0_INFIFO_RESET_S 0
/** ASRC_CHNL0_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
#define ASRC_CHNL0_OUTFIFO_RESET (BIT(1))
#define ASRC_CHNL0_OUTFIFO_RESET_M (ASRC_CHNL0_OUTFIFO_RESET_V << ASRC_CHNL0_OUTFIFO_RESET_S)
#define ASRC_CHNL0_OUTFIFO_RESET_V 0x00000001U
#define ASRC_CHNL0_OUTFIFO_RESET_S 1
/** ASRC_CHNL0_INT_RAW_REG register
* Raw interrupt status
*/
#define ASRC_CHNL0_INT_RAW_REG (DR_REG_ASRC_BASE + 0x20)
/** ASRC_CHNL0_OUTCNT_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_M (ASRC_CHNL0_OUTCNT_EOF_INT_RAW_V << ASRC_CHNL0_OUTCNT_EOF_INT_RAW_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_S 0
/** ASRC_CHNL0_INT_ST_REG register
* Masked interrupt status
*/
#define ASRC_CHNL0_INT_ST_REG (DR_REG_ASRC_BASE + 0x24)
/** ASRC_CHNL0_OUTCNT_EOF_INT_ST : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_M (ASRC_CHNL0_OUTCNT_EOF_INT_ST_V << ASRC_CHNL0_OUTCNT_EOF_INT_ST_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_S 0
/** ASRC_CHNL0_INT_ENA_REG register
* Interrupt enable bits
*/
#define ASRC_CHNL0_INT_ENA_REG (DR_REG_ASRC_BASE + 0x28)
/** ASRC_CHNL0_OUTCNT_EOF_INT_ENA : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_M (ASRC_CHNL0_OUTCNT_EOF_INT_ENA_V << ASRC_CHNL0_OUTCNT_EOF_INT_ENA_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_S 0
/** ASRC_CHNL0_INT_CLR_REG register
* Interrupt clear bits
*/
#define ASRC_CHNL0_INT_CLR_REG (DR_REG_ASRC_BASE + 0x2c)
/** ASRC_CHNL0_OUTCNT_EOF_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_M (ASRC_CHNL0_OUTCNT_EOF_INT_CLR_V << ASRC_CHNL0_OUTCNT_EOF_INT_CLR_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_S 0
/** ASRC_CHNL0_OUT_CNT_REG register
* Status Registers
*/
#define ASRC_CHNL0_OUT_CNT_REG (DR_REG_ASRC_BASE + 0x30)
/** ASRC_CHNL0_OUT_CNT : RO; bitpos: [23:0]; default: 0;
* Represents the bytes numbers send to the DMA when EOF occurs.
*/
#define ASRC_CHNL0_OUT_CNT 0x00FFFFFFU
#define ASRC_CHNL0_OUT_CNT_M (ASRC_CHNL0_OUT_CNT_V << ASRC_CHNL0_OUT_CNT_S)
#define ASRC_CHNL0_OUT_CNT_V 0x00FFFFFFU
#define ASRC_CHNL0_OUT_CNT_S 0
/** ASRC_CHNL0_TRACE1_REG register
* Debug Register1
*/
#define ASRC_CHNL0_TRACE1_REG (DR_REG_ASRC_BASE + 0x38)
/** ASRC_CHNL0_OUT_INC : RO; bitpos: [23:0]; default: 0;
* Represents the samples numbers send to the DMA
*/
#define ASRC_CHNL0_OUT_INC 0x00FFFFFFU
#define ASRC_CHNL0_OUT_INC_M (ASRC_CHNL0_OUT_INC_V << ASRC_CHNL0_OUT_INC_S)
#define ASRC_CHNL0_OUT_INC_V 0x00FFFFFFU
#define ASRC_CHNL0_OUT_INC_S 0
/** ASRC_CHNL1_CFG0_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG0_REG (DR_REG_ASRC_BASE + 0x3c)
/** ASRC_CHNL1_RS2_STG1_BYPASS : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel1.
*/
#define ASRC_CHNL1_RS2_STG1_BYPASS (BIT(0))
#define ASRC_CHNL1_RS2_STG1_BYPASS_M (ASRC_CHNL1_RS2_STG1_BYPASS_V << ASRC_CHNL1_RS2_STG1_BYPASS_S)
#define ASRC_CHNL1_RS2_STG1_BYPASS_V 0x00000001U
#define ASRC_CHNL1_RS2_STG1_BYPASS_S 0
/** ASRC_CHNL1_RS2_STG0_BYPASS : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel1.
*/
#define ASRC_CHNL1_RS2_STG0_BYPASS (BIT(1))
#define ASRC_CHNL1_RS2_STG0_BYPASS_M (ASRC_CHNL1_RS2_STG0_BYPASS_V << ASRC_CHNL1_RS2_STG0_BYPASS_S)
#define ASRC_CHNL1_RS2_STG0_BYPASS_V 0x00000001U
#define ASRC_CHNL1_RS2_STG0_BYPASS_S 1
/** ASRC_CHNL1_FRAC_BYPASS : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel1.
*/
#define ASRC_CHNL1_FRAC_BYPASS (BIT(2))
#define ASRC_CHNL1_FRAC_BYPASS_M (ASRC_CHNL1_FRAC_BYPASS_V << ASRC_CHNL1_FRAC_BYPASS_S)
#define ASRC_CHNL1_FRAC_BYPASS_V 0x00000001U
#define ASRC_CHNL1_FRAC_BYPASS_S 2
/** ASRC_CHNL1_RS2_STG1_MODE : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL1_RS2_STG1_MODE (BIT(3))
#define ASRC_CHNL1_RS2_STG1_MODE_M (ASRC_CHNL1_RS2_STG1_MODE_V << ASRC_CHNL1_RS2_STG1_MODE_S)
#define ASRC_CHNL1_RS2_STG1_MODE_V 0x00000001U
#define ASRC_CHNL1_RS2_STG1_MODE_S 3
/** ASRC_CHNL1_RS2_STG0_MODE : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL1_RS2_STG0_MODE (BIT(4))
#define ASRC_CHNL1_RS2_STG0_MODE_M (ASRC_CHNL1_RS2_STG0_MODE_V << ASRC_CHNL1_RS2_STG0_MODE_S)
#define ASRC_CHNL1_RS2_STG0_MODE_V 0x00000001U
#define ASRC_CHNL1_RS2_STG0_MODE_S 4
/** ASRC_CHNL1_FRAC_AHEAD : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel1, it should
* be 1 when input frequency is higher the output.
*/
#define ASRC_CHNL1_FRAC_AHEAD (BIT(5))
#define ASRC_CHNL1_FRAC_AHEAD_M (ASRC_CHNL1_FRAC_AHEAD_V << ASRC_CHNL1_FRAC_AHEAD_S)
#define ASRC_CHNL1_FRAC_AHEAD_V 0x00000001U
#define ASRC_CHNL1_FRAC_AHEAD_S 5
/** ASRC_CHNL1_MODE : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
#define ASRC_CHNL1_MODE 0x00000003U
#define ASRC_CHNL1_MODE_M (ASRC_CHNL1_MODE_V << ASRC_CHNL1_MODE_S)
#define ASRC_CHNL1_MODE_V 0x00000003U
#define ASRC_CHNL1_MODE_S 7
/** ASRC_CHNL1_SEL : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
#define ASRC_CHNL1_SEL (BIT(9))
#define ASRC_CHNL1_SEL_M (ASRC_CHNL1_SEL_V << ASRC_CHNL1_SEL_S)
#define ASRC_CHNL1_SEL_V 0x00000001U
#define ASRC_CHNL1_SEL_S 9
/** ASRC_CHNL1_CFG1_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG1_REG (DR_REG_ASRC_BASE + 0x40)
/** ASRC_CHNL1_FRAC_M : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
#define ASRC_CHNL1_FRAC_M 0x000003FFU
#define ASRC_CHNL1_FRAC_M_M (ASRC_CHNL1_FRAC_M_V << ASRC_CHNL1_FRAC_M_S)
#define ASRC_CHNL1_FRAC_M_V 0x000003FFU
#define ASRC_CHNL1_FRAC_M_S 0
/** ASRC_CHNL1_FRAC_L : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
#define ASRC_CHNL1_FRAC_L 0x000003FFU
#define ASRC_CHNL1_FRAC_L_M (ASRC_CHNL1_FRAC_L_V << ASRC_CHNL1_FRAC_L_S)
#define ASRC_CHNL1_FRAC_L_V 0x000003FFU
#define ASRC_CHNL1_FRAC_L_S 10
/** ASRC_CHNL1_CFG2_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG2_REG (DR_REG_ASRC_BASE + 0x44)
/** ASRC_CHNL1_FRAC_RECIPL : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel1.
*/
#define ASRC_CHNL1_FRAC_RECIPL 0x000FFFFFU
#define ASRC_CHNL1_FRAC_RECIPL_M (ASRC_CHNL1_FRAC_RECIPL_V << ASRC_CHNL1_FRAC_RECIPL_S)
#define ASRC_CHNL1_FRAC_RECIPL_V 0x000FFFFFU
#define ASRC_CHNL1_FRAC_RECIPL_S 0
/** ASRC_CHNL1_CFG3_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG3_REG (DR_REG_ASRC_BASE + 0x48)
/** ASRC_CHNL1_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel1.
*/
#define ASRC_CHNL1_RESET (BIT(0))
#define ASRC_CHNL1_RESET_M (ASRC_CHNL1_RESET_V << ASRC_CHNL1_RESET_S)
#define ASRC_CHNL1_RESET_V 0x00000001U
#define ASRC_CHNL1_RESET_S 0
/** ASRC_CHNL1_CFG4_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG4_REG (DR_REG_ASRC_BASE + 0x4c)
/** ASRC_CHNL1_START : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel1.
*/
#define ASRC_CHNL1_START (BIT(0))
#define ASRC_CHNL1_START_M (ASRC_CHNL1_START_V << ASRC_CHNL1_START_S)
#define ASRC_CHNL1_START_V 0x00000001U
#define ASRC_CHNL1_START_S 0
/** ASRC_CHNL1_CFG5_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG5_REG (DR_REG_ASRC_BASE + 0x50)
/** ASRC_CHNL1_IN_CNT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
#define ASRC_CHNL1_IN_CNT_ENA (BIT(0))
#define ASRC_CHNL1_IN_CNT_ENA_M (ASRC_CHNL1_IN_CNT_ENA_V << ASRC_CHNL1_IN_CNT_ENA_S)
#define ASRC_CHNL1_IN_CNT_ENA_V 0x00000001U
#define ASRC_CHNL1_IN_CNT_ENA_S 0
/** ASRC_CHNL1_IN_CNT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
#define ASRC_CHNL1_IN_CNT_CLR (BIT(1))
#define ASRC_CHNL1_IN_CNT_CLR_M (ASRC_CHNL1_IN_CNT_CLR_V << ASRC_CHNL1_IN_CNT_CLR_S)
#define ASRC_CHNL1_IN_CNT_CLR_V 0x00000001U
#define ASRC_CHNL1_IN_CNT_CLR_S 1
/** ASRC_CHNL1_IN_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte numbers of data from the DMA
*/
#define ASRC_CHNL1_IN_LEN 0x00FFFFFFU
#define ASRC_CHNL1_IN_LEN_M (ASRC_CHNL1_IN_LEN_V << ASRC_CHNL1_IN_LEN_S)
#define ASRC_CHNL1_IN_LEN_V 0x00FFFFFFU
#define ASRC_CHNL1_IN_LEN_S 8
/** ASRC_CHNL1_CFG6_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG6_REG (DR_REG_ASRC_BASE + 0x54)
/** ASRC_CHNL1_OUT_EOF_GEN_MODE : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
#define ASRC_CHNL1_OUT_EOF_GEN_MODE 0x00000003U
#define ASRC_CHNL1_OUT_EOF_GEN_MODE_M (ASRC_CHNL1_OUT_EOF_GEN_MODE_V << ASRC_CHNL1_OUT_EOF_GEN_MODE_S)
#define ASRC_CHNL1_OUT_EOF_GEN_MODE_V 0x00000003U
#define ASRC_CHNL1_OUT_EOF_GEN_MODE_S 0
/** ASRC_CHNL1_OUT_CNT_ENA : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
#define ASRC_CHNL1_OUT_CNT_ENA (BIT(2))
#define ASRC_CHNL1_OUT_CNT_ENA_M (ASRC_CHNL1_OUT_CNT_ENA_V << ASRC_CHNL1_OUT_CNT_ENA_S)
#define ASRC_CHNL1_OUT_CNT_ENA_V 0x00000001U
#define ASRC_CHNL1_OUT_CNT_ENA_S 2
/** ASRC_CHNL1_OUT_CNT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
#define ASRC_CHNL1_OUT_CNT_CLR (BIT(3))
#define ASRC_CHNL1_OUT_CNT_CLR_M (ASRC_CHNL1_OUT_CNT_CLR_V << ASRC_CHNL1_OUT_CNT_CLR_S)
#define ASRC_CHNL1_OUT_CNT_CLR_V 0x00000001U
#define ASRC_CHNL1_OUT_CNT_CLR_S 3
/** ASRC_CHNL1_OUT_SAMPLES_COMP : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl1_out_cnt >=
* reg_chnl1_out_len
*/
#define ASRC_CHNL1_OUT_SAMPLES_COMP (BIT(4))
#define ASRC_CHNL1_OUT_SAMPLES_COMP_M (ASRC_CHNL1_OUT_SAMPLES_COMP_V << ASRC_CHNL1_OUT_SAMPLES_COMP_S)
#define ASRC_CHNL1_OUT_SAMPLES_COMP_V 0x00000001U
#define ASRC_CHNL1_OUT_SAMPLES_COMP_S 4
/** ASRC_CHNL1_OUT_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
#define ASRC_CHNL1_OUT_LEN 0x00FFFFFFU
#define ASRC_CHNL1_OUT_LEN_M (ASRC_CHNL1_OUT_LEN_V << ASRC_CHNL1_OUT_LEN_S)
#define ASRC_CHNL1_OUT_LEN_V 0x00FFFFFFU
#define ASRC_CHNL1_OUT_LEN_S 8
/** ASRC_CHNL1_FIFO_CTRL_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_FIFO_CTRL_REG (DR_REG_ASRC_BASE + 0x58)
/** ASRC_CHNL1_INFIFO_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
#define ASRC_CHNL1_INFIFO_RESET (BIT(0))
#define ASRC_CHNL1_INFIFO_RESET_M (ASRC_CHNL1_INFIFO_RESET_V << ASRC_CHNL1_INFIFO_RESET_S)
#define ASRC_CHNL1_INFIFO_RESET_V 0x00000001U
#define ASRC_CHNL1_INFIFO_RESET_S 0
/** ASRC_CHNL1_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
#define ASRC_CHNL1_OUTFIFO_RESET (BIT(1))
#define ASRC_CHNL1_OUTFIFO_RESET_M (ASRC_CHNL1_OUTFIFO_RESET_V << ASRC_CHNL1_OUTFIFO_RESET_S)
#define ASRC_CHNL1_OUTFIFO_RESET_V 0x00000001U
#define ASRC_CHNL1_OUTFIFO_RESET_S 1
/** ASRC_CHNL1_INT_RAW_REG register
* Raw interrupt status
*/
#define ASRC_CHNL1_INT_RAW_REG (DR_REG_ASRC_BASE + 0x5c)
/** ASRC_CHNL1_OUTCNT_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_M (ASRC_CHNL1_OUTCNT_EOF_INT_RAW_V << ASRC_CHNL1_OUTCNT_EOF_INT_RAW_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_S 0
/** ASRC_CHNL1_INT_ST_REG register
* Masked interrupt status
*/
#define ASRC_CHNL1_INT_ST_REG (DR_REG_ASRC_BASE + 0x60)
/** ASRC_CHNL1_OUTCNT_EOF_INT_ST : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_M (ASRC_CHNL1_OUTCNT_EOF_INT_ST_V << ASRC_CHNL1_OUTCNT_EOF_INT_ST_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_S 0
/** ASRC_CHNL1_INT_ENA_REG register
* Interrupt enable bits
*/
#define ASRC_CHNL1_INT_ENA_REG (DR_REG_ASRC_BASE + 0x64)
/** ASRC_CHNL1_OUTCNT_EOF_INT_ENA : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_M (ASRC_CHNL1_OUTCNT_EOF_INT_ENA_V << ASRC_CHNL1_OUTCNT_EOF_INT_ENA_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_S 0
/** ASRC_CHNL1_INT_CLR_REG register
* Interrupt clear bits
*/
#define ASRC_CHNL1_INT_CLR_REG (DR_REG_ASRC_BASE + 0x68)
/** ASRC_CHNL1_OUTCNT_EOF_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_M (ASRC_CHNL1_OUTCNT_EOF_INT_CLR_V << ASRC_CHNL1_OUTCNT_EOF_INT_CLR_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_S 0
/** ASRC_CHNL1_OUT_CNT_REG register
* Status Registers
*/
#define ASRC_CHNL1_OUT_CNT_REG (DR_REG_ASRC_BASE + 0x6c)
/** ASRC_CHNL1_OUT_CNT : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA when EOF occurs.
*/
#define ASRC_CHNL1_OUT_CNT 0x00FFFFFFU
#define ASRC_CHNL1_OUT_CNT_M (ASRC_CHNL1_OUT_CNT_V << ASRC_CHNL1_OUT_CNT_S)
#define ASRC_CHNL1_OUT_CNT_V 0x00FFFFFFU
#define ASRC_CHNL1_OUT_CNT_S 0
/** ASRC_CHNL1_TRACE1_REG register
* Debug Register1
*/
#define ASRC_CHNL1_TRACE1_REG (DR_REG_ASRC_BASE + 0x74)
/** ASRC_CHNL1_OUT_INC : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA
*/
#define ASRC_CHNL1_OUT_INC 0x00FFFFFFU
#define ASRC_CHNL1_OUT_INC_M (ASRC_CHNL1_OUT_INC_V << ASRC_CHNL1_OUT_INC_S)
#define ASRC_CHNL1_OUT_INC_V 0x00FFFFFFU
#define ASRC_CHNL1_OUT_INC_S 0
/** ASRC_SYS_REG register
* Control and configuration
*/
#define ASRC_SYS_REG (DR_REG_ASRC_BASE + 0xf8)
/** ASRC_CLK_EN : R/W; bitpos: [0]; default: 0;
* Reserved
*/
#define ASRC_CLK_EN (BIT(0))
#define ASRC_CLK_EN_M (ASRC_CLK_EN_V << ASRC_CLK_EN_S)
#define ASRC_CLK_EN_V 0x00000001U
#define ASRC_CLK_EN_S 0
/** ASRC_CHNL0_CLK_FO : R/W; bitpos: [1]; default: 0;
* Set this bit to make channel0 clock free run.
*/
#define ASRC_CHNL0_CLK_FO (BIT(1))
#define ASRC_CHNL0_CLK_FO_M (ASRC_CHNL0_CLK_FO_V << ASRC_CHNL0_CLK_FO_S)
#define ASRC_CHNL0_CLK_FO_V 0x00000001U
#define ASRC_CHNL0_CLK_FO_S 1
/** ASRC_CHNL1_CLK_FO : R/W; bitpos: [2]; default: 0;
* Set this bit to make channel1 clock free run.
*/
#define ASRC_CHNL1_CLK_FO (BIT(2))
#define ASRC_CHNL1_CLK_FO_M (ASRC_CHNL1_CLK_FO_V << ASRC_CHNL1_CLK_FO_S)
#define ASRC_CHNL1_CLK_FO_V 0x00000001U
#define ASRC_CHNL1_CLK_FO_S 2
/** ASRC_CHNL0_OUTFIFO_CLK_FO : R/W; bitpos: [3]; default: 0;
* Set this bit to make channel0 outfifo clock free run.
*/
#define ASRC_CHNL0_OUTFIFO_CLK_FO (BIT(3))
#define ASRC_CHNL0_OUTFIFO_CLK_FO_M (ASRC_CHNL0_OUTFIFO_CLK_FO_V << ASRC_CHNL0_OUTFIFO_CLK_FO_S)
#define ASRC_CHNL0_OUTFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL0_OUTFIFO_CLK_FO_S 3
/** ASRC_CHNL0_INFIFO_CLK_FO : R/W; bitpos: [4]; default: 0;
* Set this bit to make channel0 infifo clock free run.
*/
#define ASRC_CHNL0_INFIFO_CLK_FO (BIT(4))
#define ASRC_CHNL0_INFIFO_CLK_FO_M (ASRC_CHNL0_INFIFO_CLK_FO_V << ASRC_CHNL0_INFIFO_CLK_FO_S)
#define ASRC_CHNL0_INFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL0_INFIFO_CLK_FO_S 4
/** ASRC_CHNL1_OUTFIFO_CLK_FO : R/W; bitpos: [5]; default: 0;
* Set this bit to make channel1 outfifo clock free run.
*/
#define ASRC_CHNL1_OUTFIFO_CLK_FO (BIT(5))
#define ASRC_CHNL1_OUTFIFO_CLK_FO_M (ASRC_CHNL1_OUTFIFO_CLK_FO_V << ASRC_CHNL1_OUTFIFO_CLK_FO_S)
#define ASRC_CHNL1_OUTFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL1_OUTFIFO_CLK_FO_S 5
/** ASRC_CHNL1_INFIFO_CLK_FO : R/W; bitpos: [6]; default: 0;
* Set this bit to make channel1 infifo clock free run.
*/
#define ASRC_CHNL1_INFIFO_CLK_FO (BIT(6))
#define ASRC_CHNL1_INFIFO_CLK_FO_M (ASRC_CHNL1_INFIFO_CLK_FO_V << ASRC_CHNL1_INFIFO_CLK_FO_S)
#define ASRC_CHNL1_INFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL1_INFIFO_CLK_FO_S 6
/** ASRC_DATE_REG register
* Control and configuration registers
*/
#define ASRC_DATE_REG (DR_REG_ASRC_BASE + 0xfc)
/** ASRC_DATE : R/W; bitpos: [27:0]; default: 37777984;
* Reserved
*/
#define ASRC_DATE 0x0FFFFFFFU
#define ASRC_DATE_M (ASRC_DATE_V << ASRC_DATE_S)
#define ASRC_DATE_V 0x0FFFFFFFU
#define ASRC_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/asrc_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of chnl0_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel0.
*/
uint32_t chnl0_rs2_stg1_bypass:1;
/** chnl0_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel0.
*/
uint32_t chnl0_rs2_stg0_bypass:1;
/** chnl0_frac_bypass : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel0.
*/
uint32_t chnl0_frac_bypass:1;
/** chnl0_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl0_rs2_stg1_mode:1;
/** chnl0_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl0_rs2_stg0_mode:1;
/** chnl0_frac_ahead : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel0, it should
* be 1 when input frequency is higher the output.
*/
uint32_t chnl0_frac_ahead:1;
uint32_t reserved_6:1;
/** chnl0_mode : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
uint32_t chnl0_mode:2;
/** chnl0_sel : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
uint32_t chnl0_sel:1;
uint32_t reserved_10:22;
};
uint32_t val;
} asrc_chnl0_cfg0_reg_t;
/** Type of chnl0_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_frac_m : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
uint32_t chnl0_frac_m:10;
/** chnl0_frac_l : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
uint32_t chnl0_frac_l:10;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl0_cfg1_reg_t;
/** Type of chnl0_cfg2 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_frac_recipl : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel0.
*/
uint32_t chnl0_frac_recipl:20;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl0_cfg2_reg_t;
/** Type of chnl0_cfg3 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel0.
*/
uint32_t chnl0_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_cfg3_reg_t;
/** Type of chnl0_cfg4 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_start : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel0.
*/
uint32_t chnl0_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_cfg4_reg_t;
/** Type of chnl0_cfg5 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_in_cnt_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
uint32_t chnl0_in_cnt_ena:1;
/** chnl0_in_cnt_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
uint32_t chnl0_in_cnt_clr:1;
uint32_t reserved_2:6;
/** chnl0_in_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data from the DMA
*/
uint32_t chnl0_in_len:24;
};
uint32_t val;
} asrc_chnl0_cfg5_reg_t;
/** Type of chnl0_cfg6 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
uint32_t chnl0_out_eof_gen_mode:2;
/** chnl0_out_cnt_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
uint32_t chnl0_out_cnt_ena:1;
/** chnl0_out_cnt_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
uint32_t chnl0_out_cnt_clr:1;
/** chnl0_out_len_comp : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl0_out_cnt >=
* reg_chnl0_out_len
*/
uint32_t chnl0_out_len_comp:1;
uint32_t reserved_5:3;
/** chnl0_out_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
uint32_t chnl0_out_len:24;
};
uint32_t val;
} asrc_chnl0_cfg6_reg_t;
/** Type of chnl0_fifo_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_infifo_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
uint32_t chnl0_infifo_reset:1;
/** chnl0_outfifo_reset : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
uint32_t chnl0_outfifo_reset:1;
uint32_t reserved_2:30;
};
uint32_t val;
} asrc_chnl0_fifo_ctrl_reg_t;
/** Type of chnl1_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel1.
*/
uint32_t chnl1_rs2_stg1_bypass:1;
/** chnl1_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel1.
*/
uint32_t chnl1_rs2_stg0_bypass:1;
/** chnl1_frac_bypass : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel1.
*/
uint32_t chnl1_frac_bypass:1;
/** chnl1_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl1_rs2_stg1_mode:1;
/** chnl1_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl1_rs2_stg0_mode:1;
/** chnl1_frac_ahead : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel1, it should
* be 1 when input frequency is higher the output.
*/
uint32_t chnl1_frac_ahead:1;
uint32_t reserved_6:1;
/** chnl1_mode : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
uint32_t chnl1_mode:2;
/** chnl1_sel : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
uint32_t chnl1_sel:1;
uint32_t reserved_10:22;
};
uint32_t val;
} asrc_chnl1_cfg0_reg_t;
/** Type of chnl1_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_frac_m : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
uint32_t chnl1_frac_m:10;
/** chnl1_frac_l : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
uint32_t chnl1_frac_l:10;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl1_cfg1_reg_t;
/** Type of chnl1_cfg2 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_frac_recipl : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel1.
*/
uint32_t chnl1_frac_recipl:20;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl1_cfg2_reg_t;
/** Type of chnl1_cfg3 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel1.
*/
uint32_t chnl1_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_cfg3_reg_t;
/** Type of chnl1_cfg4 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_start : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel1.
*/
uint32_t chnl1_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_cfg4_reg_t;
/** Type of chnl1_cfg5 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_in_cnt_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
uint32_t chnl1_in_cnt_ena:1;
/** chnl1_in_cnt_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
uint32_t chnl1_in_cnt_clr:1;
uint32_t reserved_2:6;
/** chnl1_in_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte numbers of data from the DMA
*/
uint32_t chnl1_in_len:24;
};
uint32_t val;
} asrc_chnl1_cfg5_reg_t;
/** Type of chnl1_cfg6 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
uint32_t chnl1_out_eof_gen_mode:2;
/** chnl1_out_cnt_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
uint32_t chnl1_out_cnt_ena:1;
/** chnl1_out_cnt_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
uint32_t chnl1_out_cnt_clr:1;
/** chnl1_out_samples_comp : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl1_out_cnt >=
* reg_chnl1_out_len
*/
uint32_t chnl1_out_samples_comp:1;
uint32_t reserved_5:3;
/** chnl1_out_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
uint32_t chnl1_out_len:24;
};
uint32_t val;
} asrc_chnl1_cfg6_reg_t;
/** Type of chnl1_fifo_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_infifo_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
uint32_t chnl1_infifo_reset:1;
/** chnl1_outfifo_reset : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
uint32_t chnl1_outfifo_reset:1;
uint32_t reserved_2:30;
};
uint32_t val;
} asrc_chnl1_fifo_ctrl_reg_t;
/** Group: Interrupt Register */
/** Type of chnl0_int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
uint32_t chnl0_outcnt_eof_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_raw_reg_t;
/** Type of chnl0_int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
uint32_t chnl0_outcnt_eof_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_st_reg_t;
/** Type of chnl0_int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
uint32_t chnl0_outcnt_eof_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_ena_reg_t;
/** Type of chnl0_int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
uint32_t chnl0_outcnt_eof_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_clr_reg_t;
/** Type of chnl1_int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
uint32_t chnl1_outcnt_eof_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_raw_reg_t;
/** Type of chnl1_int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
uint32_t chnl1_outcnt_eof_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_st_reg_t;
/** Type of chnl1_int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
uint32_t chnl1_outcnt_eof_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_ena_reg_t;
/** Type of chnl1_int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
uint32_t chnl1_outcnt_eof_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_clr_reg_t;
/** Group: Status registers */
/** Type of chnl0_out_cnt register
* Status Registers
*/
typedef union {
struct {
/** chnl0_out_cnt : RO; bitpos: [23:0]; default: 0;
* Represents the bytes numbers send to the DMA when EOF occurs.
*/
uint32_t chnl0_out_cnt:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl0_out_cnt_reg_t;
/** Type of chnl1_out_cnt register
* Status Registers
*/
typedef union {
struct {
/** chnl1_out_cnt : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA when EOF occurs.
*/
uint32_t chnl1_out_cnt:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl1_out_cnt_reg_t;
/** Group: DEBUG registers */
/** Type of chnl0_trace1 register
* Debug Register1
*/
typedef union {
struct {
/** chnl0_out_inc : RO; bitpos: [23:0]; default: 0;
* Represents the samples numbers send to the DMA
*/
uint32_t chnl0_out_inc:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl0_trace1_reg_t;
/** Type of chnl1_trace1 register
* Debug Register1
*/
typedef union {
struct {
/** chnl1_out_inc : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA
*/
uint32_t chnl1_out_inc:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl1_trace1_reg_t;
/** Group: Configuration registers */
/** Type of sys register
* Control and configuration
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
/** chnl0_clk_fo : R/W; bitpos: [1]; default: 0;
* Set this bit to make channel0 clock free run.
*/
uint32_t chnl0_clk_fo:1;
/** chnl1_clk_fo : R/W; bitpos: [2]; default: 0;
* Set this bit to make channel1 clock free run.
*/
uint32_t chnl1_clk_fo:1;
/** chnl0_outfifo_clk_fo : R/W; bitpos: [3]; default: 0;
* Set this bit to make channel0 outfifo clock free run.
*/
uint32_t chnl0_outfifo_clk_fo:1;
/** chnl0_infifo_clk_fo : R/W; bitpos: [4]; default: 0;
* Set this bit to make channel0 infifo clock free run.
*/
uint32_t chnl0_infifo_clk_fo:1;
/** chnl1_outfifo_clk_fo : R/W; bitpos: [5]; default: 0;
* Set this bit to make channel1 outfifo clock free run.
*/
uint32_t chnl1_outfifo_clk_fo:1;
/** chnl1_infifo_clk_fo : R/W; bitpos: [6]; default: 0;
* Set this bit to make channel1 infifo clock free run.
*/
uint32_t chnl1_infifo_clk_fo:1;
uint32_t reserved_7:25;
};
uint32_t val;
} asrc_sys_reg_t;
/** Group: Version register */
/** Type of date register
* Control and configuration registers
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37777984;
* Reserved
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} asrc_date_reg_t;
typedef struct {
volatile asrc_chnl0_cfg0_reg_t chnl0_cfg0;
volatile asrc_chnl0_cfg1_reg_t chnl0_cfg1;
volatile asrc_chnl0_cfg2_reg_t chnl0_cfg2;
volatile asrc_chnl0_cfg3_reg_t chnl0_cfg3;
volatile asrc_chnl0_cfg4_reg_t chnl0_cfg4;
volatile asrc_chnl0_cfg5_reg_t chnl0_cfg5;
volatile asrc_chnl0_cfg6_reg_t chnl0_cfg6;
volatile asrc_chnl0_fifo_ctrl_reg_t chnl0_fifo_ctrl;
volatile asrc_chnl0_int_raw_reg_t chnl0_int_raw;
volatile asrc_chnl0_int_st_reg_t chnl0_int_st;
volatile asrc_chnl0_int_ena_reg_t chnl0_int_ena;
volatile asrc_chnl0_int_clr_reg_t chnl0_int_clr;
volatile asrc_chnl0_out_cnt_reg_t chnl0_out_cnt;
uint32_t reserved_034;
volatile asrc_chnl0_trace1_reg_t chnl0_trace1;
volatile asrc_chnl1_cfg0_reg_t chnl1_cfg0;
volatile asrc_chnl1_cfg1_reg_t chnl1_cfg1;
volatile asrc_chnl1_cfg2_reg_t chnl1_cfg2;
volatile asrc_chnl1_cfg3_reg_t chnl1_cfg3;
volatile asrc_chnl1_cfg4_reg_t chnl1_cfg4;
volatile asrc_chnl1_cfg5_reg_t chnl1_cfg5;
volatile asrc_chnl1_cfg6_reg_t chnl1_cfg6;
volatile asrc_chnl1_fifo_ctrl_reg_t chnl1_fifo_ctrl;
volatile asrc_chnl1_int_raw_reg_t chnl1_int_raw;
volatile asrc_chnl1_int_st_reg_t chnl1_int_st;
volatile asrc_chnl1_int_ena_reg_t chnl1_int_ena;
volatile asrc_chnl1_int_clr_reg_t chnl1_int_clr;
volatile asrc_chnl1_out_cnt_reg_t chnl1_out_cnt;
uint32_t reserved_070;
volatile asrc_chnl1_trace1_reg_t chnl1_trace1;
uint32_t reserved_078[32];
volatile asrc_sys_reg_t sys;
volatile asrc_date_reg_t date;
} asrc_dev_t;
extern asrc_dev_t SAMPLE_RATE_CONVERTER;
#ifndef __cplusplus
_Static_assert(sizeof(asrc_dev_t) == 0x100, "Invalid size of asrc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of apm_region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** apm_region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t apm_region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} cpu_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of apm_regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** apm_regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region n.
*/
uint32_t apm_regionn_addr_start_l:12;
/** apm_regionn_addr_start : R/W; bitpos: [18:12]; default: 0;
* Configures start address of region n.
*/
uint32_t apm_regionn_addr_start:7;
/** apm_regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, start address of region n.
*/
uint32_t apm_regionn_addr_start_h:13;
};
uint32_t val;
} cpu_apm_regionn_addr_start_reg_t;
/** Type of apm_regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** apm_regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region n.
*/
uint32_t apm_regionn_addr_end_l:12;
/** apm_regionn_addr_end : R/W; bitpos: [18:12]; default: 127;
* Configures end address of region n.
*/
uint32_t apm_regionn_addr_end:7;
/** apm_regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, end address of region n.
*/
uint32_t apm_regionn_addr_end_h:13;
};
uint32_t val;
} cpu_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of apm_regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** apm_regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_x:1;
/** apm_regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_w:1;
/** apm_regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_r:1;
uint32_t reserved_3:1;
/** apm_regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_x:1;
/** apm_regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_w:1;
/** apm_regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_r:1;
uint32_t reserved_7:1;
/** apm_regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_x:1;
/** apm_regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_w:1;
/** apm_regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_r:1;
/** apm_regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t apm_regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} cpu_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of apm_func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** apm_m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t apm_m0_func_en:1;
/** apm_m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t apm_m1_func_en:1;
/** apm_m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t apm_m2_func_en:1;
/** apm_m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t apm_m3_func_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cpu_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of apm_m0_status register
* M0 status register
*/
typedef union {
struct {
/** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of apm_m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** apm_m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of apm_m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** apm_m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m0_exception_region:16;
/** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m0_exception_mode:2;
/** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of apm_m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m0_exception_addr:32;
};
uint32_t val;
} cpu_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of apm_m1_status register
* M1 status register
*/
typedef union {
struct {
/** apm_m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of apm_m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** apm_m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of apm_m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** apm_m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m1_exception_region:16;
/** apm_m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m1_exception_mode:2;
/** apm_m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of apm_m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** apm_m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m1_exception_addr:32;
};
uint32_t val;
} cpu_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of apm_m2_status register
* M2 status register
*/
typedef union {
struct {
/** apm_m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of apm_m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** apm_m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of apm_m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** apm_m2_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m2_exception_region:16;
/** apm_m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m2_exception_mode:2;
/** apm_m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m2_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of apm_m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** apm_m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m2_exception_addr:32;
};
uint32_t val;
} cpu_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of apm_m3_status register
* M3 status register
*/
typedef union {
struct {
/** apm_m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of apm_m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** apm_m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of apm_m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** apm_m3_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m3_exception_region:16;
/** apm_m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m3_exception_mode:2;
/** apm_m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m3_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of apm_m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** apm_m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m3_exception_addr:32;
};
uint32_t val;
} cpu_apm_m3_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of apm_int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m0_apm_int_en:1;
/** apm_m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m1_apm_int_en:1;
/** apm_m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m2_apm_int_en:1;
/** apm_m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m3_apm_int_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cpu_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Type of apm_clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** apm_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t apm_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of apm_date register
* Version control register
*/
typedef union {
struct {
/** apm_date : R/W; bitpos: [27:0]; default: 37769360;
* Version control register.
*/
uint32_t apm_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} cpu_apm_date_reg_t;
typedef struct {
volatile cpu_apm_region_filter_en_reg_t apm_region_filter_en;
volatile cpu_apm_regionn_addr_start_reg_t apm_region0_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region0_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region0_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region1_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region1_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region1_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region2_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region2_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region2_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region3_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region3_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region3_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region4_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region4_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region4_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region5_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region5_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region5_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region6_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region6_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region6_attr;
volatile cpu_apm_regionn_addr_start_reg_t apm_region7_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t apm_region7_addr_end;
volatile cpu_apm_regionn_attr_reg_t apm_region7_attr;
uint32_t reserved_064[24];
volatile cpu_apm_func_ctrl_reg_t apm_func_ctrl;
volatile cpu_apm_m0_status_reg_t apm_m0_status;
volatile cpu_apm_m0_status_clr_reg_t apm_m0_status_clr;
volatile cpu_apm_m0_exception_info0_reg_t apm_m0_exception_info0;
volatile cpu_apm_m0_exception_info1_reg_t apm_m0_exception_info1;
volatile cpu_apm_m1_status_reg_t apm_m1_status;
volatile cpu_apm_m1_status_clr_reg_t apm_m1_status_clr;
volatile cpu_apm_m1_exception_info0_reg_t apm_m1_exception_info0;
volatile cpu_apm_m1_exception_info1_reg_t apm_m1_exception_info1;
volatile cpu_apm_m2_status_reg_t apm_m2_status;
volatile cpu_apm_m2_status_clr_reg_t apm_m2_status_clr;
volatile cpu_apm_m2_exception_info0_reg_t apm_m2_exception_info0;
volatile cpu_apm_m2_exception_info1_reg_t apm_m2_exception_info1;
volatile cpu_apm_m3_status_reg_t apm_m3_status;
volatile cpu_apm_m3_status_clr_reg_t apm_m3_status_clr;
volatile cpu_apm_m3_exception_info0_reg_t apm_m3_exception_info0;
volatile cpu_apm_m3_exception_info1_reg_t apm_m3_exception_info1;
uint32_t reserved_108[4];
volatile cpu_apm_int_en_reg_t apm_int_en;
uint32_t reserved_11c[439];
volatile cpu_apm_clock_gate_reg_t apm_clock_gate;
volatile cpu_apm_date_reg_t apm_date;
} cpu_dev_t;
extern cpu_dev_t CPU_APM_REG;
#ifndef __cplusplus
_Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of ext_sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
/** ext_sigmadelta_clk_en : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the clock for sigma delta modulation.
* 0: Not enable
* 1: Enable
* %\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved.
*/
uint32_t ext_sigmadelta_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_ext_sigmadelta_misc_reg_t;
/** Type of ext_sigmadeltan register
* Duty cycle configuration register for SDM channel n
*/
typedef union {
struct {
/** ext_sdn_in : R/W; bitpos: [7:0]; default: 0;
* Configures the duty cycle of sigma delta modulation output.
*/
uint32_t ext_sdn_in:8;
/** ext_sdn_prescale : R/W; bitpos: [15:8]; default: 255;
* Configures the divider value to divide IO MUX operating clock.
*/
uint32_t ext_sdn_prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_ext_sigmadeltan_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of ext_glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** ext_filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable channel n of Glitch Filter.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_filter_ch0_en:1;
/** ext_filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Configures to select the input GPIO for Glitch Filter.
* 0: Select GPIO0
* 1: Select GPIO1
* ......
* 38: Select GPIO38
* 39: Select GPIO39
* 40 ~ 63: Reserved
*/
uint32_t ext_filter_ch0_input_io_num:6;
uint32_t reserved_7:1;
/** ext_filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0;
* Configures the window threshold for Glitch Filter. The window threshold should be
* less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.
* %see DOC-4768
* Measurement unit: IO MUX operating clock cycle
*/
uint32_t ext_filter_ch0_window_thres:6;
/** ext_filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0;
* Configures the window width for Glitch Filter. The effective value of window width
* is 0 ~ 63.
* Measurement unit: IO MUX operating clock cycle
*/
uint32_t ext_filter_ch0_window_width:6;
uint32_t reserved_20:12;
};
uint32_t val;
} gpio_ext_glitch_filter_chn_reg_t;
/** Group: ETM Configuration Registers */
/** Type of ext_etm_event_chn_cfg register
* ETM configuration register for channel n
*/
typedef union {
struct {
/** ext_etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
* Configures to select GPIO for ETM event channel.
* 0: Select GPIO0
* 1: Select GPIO1
* ......
* 38: Select GPIO38
* 39: Select GPIO39
* 40 ~ 63: Reserved
*/
uint32_t ext_etm_chn_event_sel:6;
uint32_t reserved_6:1;
/** ext_etm_chn_event_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable ETM event send.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_chn_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_ext_etm_event_chn_cfg_reg_t;
/** Type of ext_etm_task_p0_cfg register
* GPIO selection register 0 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO0.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio0_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio0_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO0 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio0_en:1;
/** ext_etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO1.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio1_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio1_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO1 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio1_en:1;
/** ext_etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO2.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio2_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio2_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO2 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio2_en:1;
/** ext_etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO3.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio3_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio3_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO3 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio3_en:1;
/** ext_etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO4.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio4_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio4_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO4 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio4_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p0_cfg_reg_t;
/** Type of ext_etm_task_p1_cfg register
* GPIO selection register 1 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO5.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio5_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO5 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio5_en:1;
/** ext_etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO6.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio6_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO6 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio6_en:1;
/** ext_etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO7.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio7_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO7 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio7_en:1;
/** ext_etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO8.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio8_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO8 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio8_en:1;
/** ext_etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO9.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio9_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO9 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio9_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p1_cfg_reg_t;
/** Type of ext_etm_task_p2_cfg register
* GPIO selection register 2 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO10.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio10_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO10 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio10_en:1;
/** ext_etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO11.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio11_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO11 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio11_en:1;
/** ext_etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO12.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio12_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO12 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio12_en:1;
/** ext_etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO13.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio13_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO13 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio13_en:1;
/** ext_etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO14.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio14_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO14 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio14_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p2_cfg_reg_t;
/** Type of ext_etm_task_p3_cfg register
* GPIO selection register 3 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO15.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio15_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO15 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio15_en:1;
/** ext_etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO16.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio16_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO16 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio16_en:1;
/** ext_etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO17.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio17_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO17 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio17_en:1;
/** ext_etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO18.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio18_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO18 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio18_en:1;
/** ext_etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO19.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio19_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO19 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio19_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p3_cfg_reg_t;
/** Type of ext_etm_task_p4_cfg register
* GPIO selection register 4 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO20.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio20_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO20 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio20_en:1;
/** ext_etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO21.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio21_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO21 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio21_en:1;
/** ext_etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO22.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio22_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO22 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio22_en:1;
/** ext_etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO23.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio23_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO23 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio23_en:1;
/** ext_etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO24.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio24_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO24 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio24_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p4_cfg_reg_t;
/** Type of ext_etm_task_p5_cfg register
* GPIO selection register 5 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO25.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio25_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO25 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio25_en:1;
/** ext_etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO26.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio26_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio26_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO26 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio26_en:1;
/** ext_etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO27.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio27_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio27_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO27 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio27_en:1;
/** ext_etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO28.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio28_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio28_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO28 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio28_en:1;
/** ext_etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO29.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio29_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio29_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO29 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio29_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p5_cfg_reg_t;
/** Type of ext_etm_task_p6_cfg register
* GPIO selection register 6 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio30_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO30.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio30_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio30_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO30 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio30_en:1;
/** ext_etm_task_gpio31_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO31.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio31_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio31_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO31 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio31_en:1;
/** ext_etm_task_gpio32_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO32.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio32_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio32_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO32 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio32_en:1;
/** ext_etm_task_gpio33_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO33.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio33_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio33_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO33 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio33_en:1;
/** ext_etm_task_gpio34_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO34.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio34_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio34_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO34 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio34_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p6_cfg_reg_t;
/** Type of ext_etm_task_p7_cfg register
* GPIO selection register 7 for ETM
*/
typedef union {
struct {
/** ext_etm_task_gpio35_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO35.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio35_sel:3;
uint32_t reserved_3:2;
/** ext_etm_task_gpio35_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO35 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio35_en:1;
/** ext_etm_task_gpio36_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO36.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio36_sel:3;
uint32_t reserved_9:2;
/** ext_etm_task_gpio36_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO36 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio36_en:1;
/** ext_etm_task_gpio37_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO37.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio37_sel:3;
uint32_t reserved_15:2;
/** ext_etm_task_gpio37_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO37 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio37_en:1;
/** ext_etm_task_gpio38_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO38.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio38_sel:3;
uint32_t reserved_21:2;
/** ext_etm_task_gpio38_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO38 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio38_en:1;
/** ext_etm_task_gpio39_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO39.
* 0: Select channel 0
* 1: Select channel 1
* ......
* 7: Select channel 7
*/
uint32_t ext_etm_task_gpio39_sel:3;
uint32_t reserved_27:2;
/** ext_etm_task_gpio39_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO39 to response ETM task.
* 0: Not enable
* 1: Enable
*/
uint32_t ext_etm_task_gpio39_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p7_cfg_reg_t;
/** Group: Version Register */
/** Type of ext_version register
* Version control register
*/
typedef union {
struct {
/** ext_date : R/W; bitpos: [27:0]; default: 37818704;
* Version control register.
*/
uint32_t ext_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct {
uint32_t reserved_000;
volatile gpio_ext_sigmadelta_misc_reg_t ext_sigmadelta_misc;
volatile gpio_ext_sigmadeltan_reg_t ext_sigmadeltan[4];
uint32_t reserved_018[48];
volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8];
uint32_t reserved_0f8[8];
volatile gpio_ext_etm_event_chn_cfg_reg_t ext_etm_event_chn_cfg[8];
uint32_t reserved_138[8];
volatile gpio_ext_etm_task_p0_cfg_reg_t ext_etm_task_p0_cfg;
volatile gpio_ext_etm_task_p1_cfg_reg_t ext_etm_task_p1_cfg;
volatile gpio_ext_etm_task_p2_cfg_reg_t ext_etm_task_p2_cfg;
volatile gpio_ext_etm_task_p3_cfg_reg_t ext_etm_task_p3_cfg;
volatile gpio_ext_etm_task_p4_cfg_reg_t ext_etm_task_p4_cfg;
volatile gpio_ext_etm_task_p5_cfg_reg_t ext_etm_task_p5_cfg;
volatile gpio_ext_etm_task_p6_cfg_reg_t ext_etm_task_p6_cfg;
volatile gpio_ext_etm_task_p7_cfg_reg_t ext_etm_task_p7_cfg;
uint32_t reserved_178[33];
volatile gpio_ext_version_reg_t ext_version;
} gpio_dev_t;
extern gpio_dev_t GPIO_EXT;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0x200, "Invalid size of gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of strap register
* Strapping pin register
*/
typedef union {
struct {
/** strapping : RO; bitpos: [15:0]; default: 0;
* Represents the values of GPIO strapping pins. (need update the description, for
* example)
*
* - bit0: invalid
* - bit1: MTMS
* - bit2: MTDI
* - bit3: GPIO27
* - bit4: GPIO28
* - bit5: GPIO7
* - bit6 ~ bit15: invalid
*/
uint32_t strapping:16;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_strap_reg_t;
/** Type of out register
* GPIO output register
*/
typedef union {
struct {
/** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
* Configures the output value of GPIO0 ~ 31 output in simple GPIO output mode.
* 0: Low level
* 1: High level
* The value of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31
* respectively. Bitxx ~ bitxx is invalid.
*/
uint32_t out_data_orig:32;
};
uint32_t val;
} gpio_out_reg_t;
/** Type of out_w1ts register
* GPIO output set register
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [31:0]; default: 0;
* Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ GPIO31.
* 0: Not set
* 1: The corresponding bit in GPIO_OUT_REG will be set to 1
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set GPIO_OUT_REG.
*/
uint32_t out_w1ts:32;
};
uint32_t val;
} gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* GPIO output clear register
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [31:0]; default: 0;
* Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
* GPIO31 output.
* 0: Not clear
* 1: The corresponding bit in GPIO_OUT_REG will be cleared.
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear GPIO_OUT_REG.
*/
uint32_t out_w1tc:32;
};
uint32_t val;
} gpio_out_w1tc_reg_t;
/** Type of out1 register
* GPIO output register
*/
typedef union {
struct {
/** out1_data_orig : R/W/SC/WTC; bitpos: [11:0]; default: 0;
* Configures the output value of GPIO32 ~ 43 output in simple GPIO output mode.
* 0: Low level
* 1: High level
* The value of bit32 ~ bit43 correspond to the output value of GPIO32 ~ GPIO43
* respectively. Bitxx ~ bitxx is invalid.
*/
uint32_t out1_data_orig:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_out1_reg_t;
/** Type of out1_w1ts register
* GPIO output set register
*/
typedef union {
struct {
/** out1_w1ts : WT; bitpos: [11:0]; default: 0;
* Configures whether or not to set the output register GPIO_OUT1_REG of GPIO32 ~
* GPIO43.
* 0: Not set
* 1: The corresponding bit in GPIO_OUT1_REG will be set to 1
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set GPIO_OUT1_REG.
*/
uint32_t out1_w1ts:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_out1_w1ts_reg_t;
/** Type of out1_w1tc register
* GPIO output clear register
*/
typedef union {
struct {
/** out1_w1tc : WT; bitpos: [11:0]; default: 0;
* Configures whether or not to clear the output register GPIO_OUT1_REG of GPIO32 ~
* GPIO43 output.
* 0: Not clear
* 1: The corresponding bit in GPIO_OUT1_REG will be cleared.
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear GPIO_OUT1_REG.
*/
uint32_t out1_w1tc:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_out1_w1tc_reg_t;
/** Type of enable register
* GPIO output enable register
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
* Configures whether or not to enable the output of GPIO0 ~ GPIO31.
* 0: Not enable
* 1: Enable
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
*/
uint32_t enable_data:32;
};
uint32_t val;
} gpio_enable_reg_t;
/** Type of enable_w1ts register
* GPIO output enable set register
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [31:0]; default: 0;
* Configures whether or not to set the output enable register GPIO_ENABLE_REG of
* GPIO0 ~ GPIO31.
* 0: Not set
* 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set GPIO_ENABLE_REG.
*/
uint32_t enable_w1ts:32;
};
uint32_t val;
} gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* GPIO output enable clear register
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [31:0]; default: 0;
* Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
* GPIO0 ~ GPIO31.
* 0: Not clear
* 1: The corresponding bit in GPIO_ENABLE_REG will be cleared
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear GPIO_ENABLE_REG.
*/
uint32_t enable_w1tc:32;
};
uint32_t val;
} gpio_enable_w1tc_reg_t;
/** Type of enable1 register
* GPIO output enable register
*/
typedef union {
struct {
/** enable1_data : R/W/WTC; bitpos: [11:0]; default: 0;
* Configures whether or not to enable the output of GPIO32 ~ GPIO43.
* 0: Not enable
* 1: Enable
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
*/
uint32_t enable1_data:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_enable1_reg_t;
/** Type of enable1_w1ts register
* GPIO output enable set register
*/
typedef union {
struct {
/** enable1_w1ts : WT; bitpos: [11:0]; default: 0;
* Configures whether or not to set the output enable register GPIO_ENABLE1_REG of
* GPIO32 ~ GPIO43.
* 0: Not set
* 1: The corresponding bit in GPIO_ENABLE1_REG will be set to 1
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set GPIO_ENABLE1_REG.
*/
uint32_t enable1_w1ts:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_enable1_w1ts_reg_t;
/** Type of enable1_w1tc register
* GPIO output enable clear register
*/
typedef union {
struct {
/** enable1_w1tc : WT; bitpos: [11:0]; default: 0;
* Configures whether or not to clear the output enable register GPIO_ENABLE1_REG of
* GPIO32 ~ GPIO43.
* 0: Not clear
* 1: The corresponding bit in GPIO_ENABLE1_REG will be cleared
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear GPIO_ENABLE1_REG.
*/
uint32_t enable1_w1tc:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_enable1_w1tc_reg_t;
/** Type of in register
* GPIO input register
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [31:0]; default: 0;
* Represents the input value of GPIO0 ~ GPIO31. Each bit represents a pin input value:
* 0: Low level
* 1: High level
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
*/
uint32_t in_data_next:32;
};
uint32_t val;
} gpio_in_reg_t;
/** Type of in1 register
* GPIO input register
*/
typedef union {
struct {
/** in1_data_next : RO; bitpos: [11:0]; default: 0;
* Represents the input value of GPIO32 ~ GPIO43. Each bit represents a pin input
* value:
* 0: Low level
* 1: High level
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
*/
uint32_t in1_data_next:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_in1_reg_t;
/** Group: Interrupt Status Registers */
/** Type of status register
* GPIO interrupt status register
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
* The interrupt status of GPIO0 ~ GPIO31, can be configured by the software.
*
* - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
* - Each bit represents the status of its corresponding GPIO:
*
* - 0: Represents the GPIO does not generate the interrupt configured by
* GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
* - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
* or this bit is configured to 1 by the software.
*
*/
uint32_t status_interrupt:32;
};
uint32_t val;
} gpio_status_reg_t;
/** Type of status_w1ts register
* GPIO interrupt status set register
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [31:0]; default: 0;
* Configures whether or not to set the interrupt status register
* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31.
*
* - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
* register to set GPIO_STATUS_INTERRUPT.
*/
uint32_t status_w1ts:32;
};
uint32_t val;
} gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* GPIO interrupt status clear register
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [31:0]; default: 0;
* Configures whether or not to clear the interrupt status register
* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31.
*
* - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
* register to clear GPIO_STATUS_INTERRUPT.
*/
uint32_t status_w1tc:32;
};
uint32_t val;
} gpio_status_w1tc_reg_t;
/** Type of status1 register
* GPIO interrupt status register
*/
typedef union {
struct {
/** status1_interrupt : R/W/WTC; bitpos: [11:0]; default: 0;
* The interrupt status of GPIO32 ~ GPIO43, can be configured by the software.
*
* - Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
* - Each bit represents the status of its corresponding GPIO:
*
* - 0: Represents the GPIO does not generate the interrupt configured by
* GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
* - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
* or this bit is configured to 1 by the software.
*
*/
uint32_t status1_interrupt:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_status1_reg_t;
/** Type of status1_w1ts register
* GPIO interrupt status set register
*/
typedef union {
struct {
/** status1_w1ts : WT; bitpos: [11:0]; default: 0;
* Configures whether or not to set the interrupt status register
* GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO43.
*
* - Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* GPIO_STATUS1_INTERRUPT will be set to 1. \item Recommended operation: use this
* register to set GPIO_STATUS1_INTERRUPT.
*/
uint32_t status1_w1ts:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_status1_w1ts_reg_t;
/** Type of status1_w1tc register
* GPIO interrupt status clear register
*/
typedef union {
struct {
/** status1_w1tc : WT; bitpos: [11:0]; default: 0;
* Configures whether or not to clear the interrupt status register
* GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO43.
*
* - Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* GPIO_STATUS1_INTERRUPT will be cleared. \item Recommended operation: use this
* register to clear GPIO_STATUS1_INTERRUPT.
*/
uint32_t status1_w1tc:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_status1_w1tc_reg_t;
/** Type of procpu_int register
* GPIO_PROCPU_INT interrupt status register
*/
typedef union {
struct {
/** procpu_int : RO; bitpos: [31:0]; default: 0;
* Represents the GPIO_PROCPU_INT interrupt status of GPIO0 ~ GPIO31. Each bit
* represents:(need update in different project)
* 0: Represents GPIO_PROCPU_INT interrupt is not enabled, or the GPIO does not
* generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
* 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
* after the GPIO_PROCPU_INT interrupt is enabled.
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
* interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
* enable signal (bit13 of GPIO_PIN$n_REG).
*/
uint32_t procpu_int:32;
};
uint32_t val;
} gpio_procpu_int_reg_t;
/** Type of interrupt_2 register
* GPIO_INTERRUPT_2 interrupt status register
*/
typedef union {
struct {
/** interrupt_2 : RO; bitpos: [31:0]; default: 0;
* Represents the GPIO_INTERRUPT_2 interrupt status of GPIO0 ~ GPIO31. Each bit
* represents:(need update in different project)
* 0: Represents GPIO_INTERRUPT_2 interrupt is not enabled, or the GPIO does not
* generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
* 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
* after the GPIO_INTERRUPT_2 interrupt is enabled.
* Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
* interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
* enable signal (bit13 of GPIO_PIN$n_REG).
*/
uint32_t interrupt_2:32;
};
uint32_t val;
} gpio_interrupt_2_reg_t;
/** Type of procpu_int1 register
* GPIO_PROCPU_INT interrupt status register
*/
typedef union {
struct {
/** procpu_int1 : RO; bitpos: [11:0]; default: 0;
* Represents the GPIO_PROCPU_INT interrupt status of GPIO32 ~ GPIO43. Each bit
* represents:(need update in different project)
* 0: Represents GPIO_PROCPU_INT interrupt is not enabled, or the GPIO does not
* generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
* 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
* after the GPIO_PROCPU_INT interrupt is enabled.
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid. This
* interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
* enable signal (bit13 of GPIO_PIN$n_REG).
*/
uint32_t procpu_int1:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_procpu_int1_reg_t;
/** Type of interrupt_21 register
* GPIO_INTERRUPT_2 interrupt status register
*/
typedef union {
struct {
/** interrupt_21 : RO; bitpos: [11:0]; default: 0;
* Represents the GPIO_INTERRUPT_2 interrupt status of GPIO32 ~ GPIO43. Each bit
* represents:(need update in different project)
* 0: Represents GPIO_INTERRUPT_2 interrupt is not enabled, or the GPIO does not
* generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
* 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
* after the GPIO_INTERRUPT_2 interrupt is enabled.
* Bit32 ~ bit43 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid. This
* interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
* enable signal (bit13 of GPIO_PIN$n_REG).
*/
uint32_t interrupt_21:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_interrupt_21_reg_t;
/** Type of status_next register
* GPIO interrupt source register
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
* Represents the interrupt source signal of GPIO0 ~ GPIO31.
* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. Each
* bit represents:
* 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
* 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
* The interrupt could be rising edge interrupt, falling edge interrupt, level
* sensitive interrupt and any edge interrupt.
*/
uint32_t status_interrupt_next:32;
};
uint32_t val;
} gpio_status_next_reg_t;
/** Type of status_next1 register
* GPIO interrupt source register
*/
typedef union {
struct {
/** status_interrupt_next1 : RO; bitpos: [11:0]; default: 0;
* Represents the interrupt source signal of GPIO32 ~ GPIO43.
* Bit0 ~ bit24 are corresponding to GPIO32 ~ GPIO43. Bitxx ~ bitxx is invalid. Each
* bit represents:
* 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
* 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
* The interrupt could be rising edge interrupt, falling edge interrupt, level
* sensitive interrupt and any edge interrupt.
*/
uint32_t status_interrupt_next1:12;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_status_next1_reg_t;
/** Group: Pin Configuration Registers */
/** Type of pinn register
* GPIOn configuration register
*/
typedef union {
struct {
/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
uint32_t pinn_sync2_bypass:2;
/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
uint32_t pinn_pad_driver:1;
/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
uint32_t pinn_sync1_bypass:2;
uint32_t reserved_5:2;
/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.
* 0: GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
uint32_t pinn_int_type:3;
/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
uint32_t pinn_wakeup_enable:1;
uint32_t reserved_11:2;
/** pinn_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable gpio_procpu_int or gpio_interrupt_2(need update
* in different project).
*
* - bit13: Configures whether or not to enable gpio_procpu_int(need update in
* different project):
* 0: Disable
* 1: Enable
* - bit14: Configures whether or not to enable gpio_interrupt_2(need update in
* different project):
* 0: Disable
* 1: Enable
* - bit15 ~ bit17: invalid
*/
uint32_t pinn_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pinn_reg_t;
/** Group: Input Configuration Registers */
/** Type of func_in_sel_cfg register
* Configuration register for input signal 0
*/
typedef union {
struct {
/** func_in_sel : R/W; bitpos: [6:0]; default: 96;
* Configures to select a pin from the 40 GPIO pins to connect the input signal 0.
* 0: Select GPIO0
* 1: Select GPIO1
* ......
* 38: Select GPIO38
* 39: Select GPIO39
* Or
* 0x40: A constantly high input
* 0x60: A constantly low input
*/
uint32_t func_in_sel:7;
/** func_in_inv_sel : R/W; bitpos: [7]; default: 0;
* Configures whether or not to invert the input value.
* 0: Not invert
* 1: Invert
*/
uint32_t func_in_inv_sel:1;
/** sig_in_sel : R/W; bitpos: [8]; default: 0;
* Configures whether or not to route signals via GPIO matrix.
* 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
* IO MUX.
* 1: Route signals via GPIO matrix.
*/
uint32_t sig_in_sel:1;
uint32_t reserved_9:23;
};
uint32_t val;
} gpio_func_in_sel_cfg_reg_t;
/** Group: Output Configuration Registers */
/** Type of funcn_out_sel_cfg register
* Configuration register for GPIOn output
*/
typedef union {
struct {
/** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIOn.
* 0: Select signal 0
* 1: Select signal 1
* ......
* 254: Select signal 254
* 255: Select signal 255
* Or
* 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
* output enable.
*
* For the detailed signal list, see Table .
* "
*/
uint32_t funcn_out_sel:9;
/** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
uint32_t funcn_out_inv_sel:1;
/** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.
* 0: Use output enable signal from peripheral.
* 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG.
*/
uint32_t funcn_oe_sel:1;
/** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
uint32_t funcn_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_funcn_out_sel_cfg_reg_t;
/** Group: Clock Gate Register */
/** Type of clock_gate register
* GPIO clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable clock gate.
* 0: Not enable
* 1: Enable, the clock is free running.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_clock_gate_reg_t;
/** Group: Version Register */
/** Type of date register
* GPIO version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37818960;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_date_reg_t;
typedef struct {
volatile gpio_strap_reg_t strap;
volatile gpio_out_reg_t out;
volatile gpio_out_w1ts_reg_t out_w1ts;
volatile gpio_out_w1tc_reg_t out_w1tc;
volatile gpio_out1_reg_t out1;
volatile gpio_out1_w1ts_reg_t out1_w1ts;
volatile gpio_out1_w1tc_reg_t out1_w1tc;
uint32_t reserved_01c[6];
volatile gpio_enable_reg_t enable;
volatile gpio_enable_w1ts_reg_t enable_w1ts;
volatile gpio_enable_w1tc_reg_t enable_w1tc;
volatile gpio_enable1_reg_t enable1;
volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
uint32_t reserved_04c[6];
volatile gpio_in_reg_t in;
volatile gpio_in1_reg_t in1;
uint32_t reserved_06c[2];
volatile gpio_status_reg_t status;
volatile gpio_status_w1ts_reg_t status_w1ts;
volatile gpio_status_w1tc_reg_t status_w1tc;
volatile gpio_status1_reg_t status1;
volatile gpio_status1_w1ts_reg_t status1_w1ts;
volatile gpio_status1_w1tc_reg_t status1_w1tc;
uint32_t reserved_08c[6];
volatile gpio_procpu_int_reg_t procpu_int;
volatile gpio_interrupt_2_reg_t interrupt_2;
volatile gpio_procpu_int1_reg_t procpu_int1;
volatile gpio_interrupt_21_reg_t interrupt_21;
uint32_t reserved_0b4[4];
volatile gpio_status_next_reg_t status_next;
volatile gpio_status_next1_reg_t status_next1;
uint32_t reserved_0cc[2];
volatile gpio_pinn_reg_t pinn[40];
uint32_t reserved_174[88];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-7, 20-28, 38-42, 48, 70-74, 94-96, 101, 118-154, 172-181, 190-255
uint32_t reserved_60e[256];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[40];
uint32_t reserved_b74[161];
volatile gpio_clock_gate_reg_t clock_gate;
volatile gpio_date_reg_t date;
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0xe00, "Invalid size of gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of apm_region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** apm_region_filter_en : R/W; bitpos: [15:0]; default: 1;
* Configure bit $n (0-15) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t apm_region_filter_en:16;
uint32_t reserved_16:16;
};
uint32_t val;
} hp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of apm_regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** apm_regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n.
*/
uint32_t apm_regionn_addr_start:32;
};
uint32_t val;
} hp_apm_regionn_addr_start_reg_t;
/** Type of apm_regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** apm_regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n.
*/
uint32_t apm_regionn_addr_end:32;
};
uint32_t val;
} hp_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of apm_regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** apm_regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_x:1;
/** apm_regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_w:1;
/** apm_regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t apm_regionn_r0_r:1;
uint32_t reserved_3:1;
/** apm_regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_x:1;
/** apm_regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_w:1;
/** apm_regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t apm_regionn_r1_r:1;
uint32_t reserved_7:1;
/** apm_regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_x:1;
/** apm_regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_w:1;
/** apm_regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t apm_regionn_r2_r:1;
/** apm_regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t apm_regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} hp_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of apm_func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** apm_m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t apm_m0_func_en:1;
/** apm_m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t apm_m1_func_en:1;
/** apm_m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t apm_m2_func_en:1;
/** apm_m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t apm_m3_func_en:1;
/** apm_m4_func_en : R/W; bitpos: [4]; default: 1;
* PMS M4 function enable
*/
uint32_t apm_m4_func_en:1;
uint32_t reserved_5:27;
};
uint32_t val;
} hp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of apm_m0_status register
* M0 status register
*/
typedef union {
struct {
/** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of apm_m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** apm_m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of apm_m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** apm_m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m0_exception_region:16;
/** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m0_exception_mode:2;
/** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of apm_m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m0_exception_addr:32;
};
uint32_t val;
} hp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of apm_m1_status register
* M1 status register
*/
typedef union {
struct {
/** apm_m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of apm_m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** apm_m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of apm_m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** apm_m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m1_exception_region:16;
/** apm_m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m1_exception_mode:2;
/** apm_m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of apm_m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** apm_m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m1_exception_addr:32;
};
uint32_t val;
} hp_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of apm_m2_status register
* M2 status register
*/
typedef union {
struct {
/** apm_m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of apm_m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** apm_m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of apm_m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** apm_m2_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m2_exception_region:16;
/** apm_m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m2_exception_mode:2;
/** apm_m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m2_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of apm_m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** apm_m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m2_exception_addr:32;
};
uint32_t val;
} hp_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of apm_m3_status register
* M3 status register
*/
typedef union {
struct {
/** apm_m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of apm_m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** apm_m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of apm_m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** apm_m3_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m3_exception_region:16;
/** apm_m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m3_exception_mode:2;
/** apm_m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m3_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of apm_m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** apm_m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m3_exception_addr:32;
};
uint32_t val;
} hp_apm_m3_exception_info1_reg_t;
/** Group: M4 status register */
/** Type of apm_m4_status register
* M4 status register
*/
typedef union {
struct {
/** apm_m4_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t apm_m4_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m4_status_reg_t;
/** Group: M4 status clear register */
/** Type of apm_m4_status_clr register
* M4 status clear register
*/
typedef union {
struct {
/** apm_m4_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t apm_m4_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m4_status_clr_reg_t;
/** Group: M4 exception_info0 register */
/** Type of apm_m4_exception_info0 register
* M4 exception_info0 register
*/
typedef union {
struct {
/** apm_m4_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t apm_m4_exception_region:16;
/** apm_m4_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t apm_m4_exception_mode:2;
/** apm_m4_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t apm_m4_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m4_exception_info0_reg_t;
/** Group: M4 exception_info1 register */
/** Type of apm_m4_exception_info1 register
* M4 exception_info1 register
*/
typedef union {
struct {
/** apm_m4_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t apm_m4_exception_addr:32;
};
uint32_t val;
} hp_apm_m4_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of apm_int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m0_apm_int_en:1;
/** apm_m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m1_apm_int_en:1;
/** apm_m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m2_apm_int_en:1;
/** apm_m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m3_apm_int_en:1;
/** apm_m4_apm_int_en : R/W; bitpos: [4]; default: 0;
* Configures to enable APM M4 interrupt.
* 0: disable
* 1: enable
*/
uint32_t apm_m4_apm_int_en:1;
uint32_t reserved_5:27;
};
uint32_t val;
} hp_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Type of apm_clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** apm_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t apm_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of apm_date register
* Version control register
*/
typedef union {
struct {
/** apm_date : R/W; bitpos: [27:0]; default: 36773904;
* Version control register.
*/
uint32_t apm_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_apm_date_reg_t;
typedef struct {
volatile hp_apm_region_filter_en_reg_t apm_region_filter_en;
volatile hp_apm_regionn_addr_start_reg_t apm_region0_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region0_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region0_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region1_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region1_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region1_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region2_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region2_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region2_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region3_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region3_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region3_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region4_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region4_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region4_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region5_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region5_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region5_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region6_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region6_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region6_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region7_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region7_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region7_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region8_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region8_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region8_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region9_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region9_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region9_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region10_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region10_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region10_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region11_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region11_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region11_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region12_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region12_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region12_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region13_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region13_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region13_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region14_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region14_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region14_attr;
volatile hp_apm_regionn_addr_start_reg_t apm_region15_addr_start;
volatile hp_apm_regionn_addr_end_reg_t apm_region15_addr_end;
volatile hp_apm_regionn_attr_reg_t apm_region15_attr;
volatile hp_apm_func_ctrl_reg_t apm_func_ctrl;
volatile hp_apm_m0_status_reg_t apm_m0_status;
volatile hp_apm_m0_status_clr_reg_t apm_m0_status_clr;
volatile hp_apm_m0_exception_info0_reg_t apm_m0_exception_info0;
volatile hp_apm_m0_exception_info1_reg_t apm_m0_exception_info1;
volatile hp_apm_m1_status_reg_t apm_m1_status;
volatile hp_apm_m1_status_clr_reg_t apm_m1_status_clr;
volatile hp_apm_m1_exception_info0_reg_t apm_m1_exception_info0;
volatile hp_apm_m1_exception_info1_reg_t apm_m1_exception_info1;
volatile hp_apm_m2_status_reg_t apm_m2_status;
volatile hp_apm_m2_status_clr_reg_t apm_m2_status_clr;
volatile hp_apm_m2_exception_info0_reg_t apm_m2_exception_info0;
volatile hp_apm_m2_exception_info1_reg_t apm_m2_exception_info1;
volatile hp_apm_m3_status_reg_t apm_m3_status;
volatile hp_apm_m3_status_clr_reg_t apm_m3_status_clr;
volatile hp_apm_m3_exception_info0_reg_t apm_m3_exception_info0;
volatile hp_apm_m3_exception_info1_reg_t apm_m3_exception_info1;
volatile hp_apm_m4_status_reg_t apm_m4_status;
volatile hp_apm_m4_status_clr_reg_t apm_m4_status_clr;
volatile hp_apm_m4_exception_info0_reg_t apm_m4_exception_info0;
volatile hp_apm_m4_exception_info1_reg_t apm_m4_exception_info1;
volatile hp_apm_int_en_reg_t apm_int_en;
uint32_t reserved_11c[439];
volatile hp_apm_clock_gate_reg_t apm_clock_gate;
volatile hp_apm_date_reg_t apm_date;
} hp_dev_t;
extern hp_dev_t HP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_dev_t) == 0x800, "Invalid size of hp_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/hp_system_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
* External device encryption/decryption configuration register
*/
#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
* CPU_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_BASE + 0xc)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing CPU peripheral
* register in the number of clock cycles of the clock domain.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Write 1 to clear timeout interrupt.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
* CPU_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_BASE + 0x10)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
* CPU_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_BASE + 0x14)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
* HP_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_BASE + 0x18)
/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing HP peripheral
* register, corresponding to the number of clock cycles of the clock domain.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.
* 0: No effect
* 1: Clear timeout interrupt
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
* HP_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_BASE + 0x1c)
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
* HP_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_BASE + 0x20)
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_SDIO_CTRL_REG register
* SDIO Control configuration register
*/
#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_BASE + 0x30)
/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
#define HP_SYSTEM_DIS_SDIO_PROB (BIT(0))
#define HP_SYSTEM_DIS_SDIO_PROB_M (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S)
#define HP_SYSTEM_DIS_SDIO_PROB_V 0x00000001U
#define HP_SYSTEM_DIS_SDIO_PROB_S 0
/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN (BIT(1))
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S)
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V 0x00000001U
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S 1
/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
* ROM-Table lock register
*/
#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_BASE + 0x38)
/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE.
* 0: Unlock
* 1: Lock
*/
#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0))
#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U
#define HP_SYSTEM_ROM_TABLE_LOCK_S 0
/** HP_SYSTEM_ROM_TABLE_REG register
* ROM-Table register
*/
#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_BASE + 0x3c)
/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
* Software ROM-Table register, whose content can be modified only when
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
*/
#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_M (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_S 0
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
* Core Debug RunStall configurion register
*/
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_BASE + 0x40)
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable debug RunStall functionality between HP CPU and
* LP CPU.
* 0: Disable
* 1: Enable
*/
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0))
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S 0
/** HP_SYSTEM_CORE0_RUNSTALLED : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core0. 1: stalled, 0:
* not stalled.
*/
#define HP_SYSTEM_CORE0_RUNSTALLED (BIT(1))
#define HP_SYSTEM_CORE0_RUNSTALLED_M (HP_SYSTEM_CORE0_RUNSTALLED_V << HP_SYSTEM_CORE0_RUNSTALLED_S)
#define HP_SYSTEM_CORE0_RUNSTALLED_V 0x00000001U
#define HP_SYSTEM_CORE0_RUNSTALLED_S 1
/** HP_SYSTEM_CORE1_RUNSTALLED : RO; bitpos: [2]; default: 0;
* Software can read this field to get the runstall status of hp-core1. 1: stalled, 0:
* not stalled.
*/
#define HP_SYSTEM_CORE1_RUNSTALLED (BIT(2))
#define HP_SYSTEM_CORE1_RUNSTALLED_M (HP_SYSTEM_CORE1_RUNSTALLED_V << HP_SYSTEM_CORE1_RUNSTALLED_S)
#define HP_SYSTEM_CORE1_RUNSTALLED_V 0x00000001U
#define HP_SYSTEM_CORE1_RUNSTALLED_S 2
/** HP_SYSTEM_SPROM_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SPROM_CTRL_REG (DR_REG_HP_BASE + 0x70)
/** HP_SYSTEM_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 80;
* reserved
*/
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_M (HP_SYSTEM_SPROM_MEM_AUX_CTRL_V << HP_SYSTEM_SPROM_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_SPRAM_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SPRAM_CTRL_REG (DR_REG_HP_BASE + 0x74)
/** HP_SYSTEM_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 10320;
* reserved
*/
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_M (HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V << HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_SPRF_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SPRF_CTRL_REG (DR_REG_HP_BASE + 0x78)
/** HP_SYSTEM_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 10320;
* reserved
*/
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SPRF_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register
* reserved
*/
#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_BASE + 0x80)
/** HP_SYSTEM_BITSCRAMBLER_RX_SEL : R/W; bitpos: [3:0]; default: 0;
* select peri that will be connected to bitscrambler,dir : receive data from bs
*/
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL_M (HP_SYSTEM_BITSCRAMBLER_RX_SEL_V << HP_SYSTEM_BITSCRAMBLER_RX_SEL_S)
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL_V 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL_S 0
/** HP_SYSTEM_BITSCRAMBLER_TX_SEL : R/W; bitpos: [7:4]; default: 0;
* select peri that will be connected to bitscrambler,dir : transfer data to peri
*/
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_M (HP_SYSTEM_BITSCRAMBLER_TX_SEL_V << HP_SYSTEM_BITSCRAMBLER_TX_SEL_S)
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_V 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_S 4
/** HP_SYSTEM_APPCPU_BOOT_ADDR_REG register
* reserved
*/
#define HP_SYSTEM_APPCPU_BOOT_ADDR_REG (DR_REG_HP_BASE + 0x84)
/** HP_SYSTEM_APPCPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_SYSTEM_APPCPU_BOOT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_APPCPU_BOOT_ADDR_M (HP_SYSTEM_APPCPU_BOOT_ADDR_V << HP_SYSTEM_APPCPU_BOOT_ADDR_S)
#define HP_SYSTEM_APPCPU_BOOT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_APPCPU_BOOT_ADDR_S 0
/** HP_SYSTEM_AXI_MST_PRI_REG register
* AXI mst priority configuration register
*/
#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_BASE + 0x88)
/** HP_SYSTEM_DMA_PRIORITY : R/W; bitpos: [0]; default: 0;
* AHB-DMA arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
#define HP_SYSTEM_DMA_PRIORITY (BIT(0))
#define HP_SYSTEM_DMA_PRIORITY_M (HP_SYSTEM_DMA_PRIORITY_V << HP_SYSTEM_DMA_PRIORITY_S)
#define HP_SYSTEM_DMA_PRIORITY_V 0x00000001U
#define HP_SYSTEM_DMA_PRIORITY_S 0
/** HP_SYSTEM_CACHE_PRIORITY : R/W; bitpos: [1]; default: 0;
* CACHE arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
#define HP_SYSTEM_CACHE_PRIORITY (BIT(1))
#define HP_SYSTEM_CACHE_PRIORITY_M (HP_SYSTEM_CACHE_PRIORITY_V << HP_SYSTEM_CACHE_PRIORITY_S)
#define HP_SYSTEM_CACHE_PRIORITY_V 0x00000001U
#define HP_SYSTEM_CACHE_PRIORITY_S 1
/** HP_SYSTEM_CPU_PERI_PMS_CONF_REG register
* CPU Peripherals PMS configuration register
*/
#define HP_SYSTEM_CPU_PERI_PMS_CONF_REG (DR_REG_HP_BASE + 0x90)
/** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear cpu peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR (BIT(0))
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR_M (HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR_V << HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR_S)
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_CLR_S 0
/** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_INFO_REG register
* CPU Peripherals PMS exception info record register
*/
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_BASE + 0x94)
/** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0;
* Represents whether the cpu peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET (BIT(0))
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET_M (HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET_V << HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET_S)
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_DET_S 0
/** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ID : RO; bitpos: [5:1]; default: 0;
* Represents the master id when cpu peripheral pms has been triggered.
*/
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ID 0x0000001FU
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ID_M (HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ID_V << HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ID_S)
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ID_V 0x0000001FU
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ID_S 1
/** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_MODE : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when cpu peripheral pms has been triggered.
*/
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_MODE 0x00000003U
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_MODE_M (HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_MODE_V << HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_MODE_S)
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_MODE_V 0x00000003U
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_MODE_S 6
/** HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ADDR : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when cpu peripheral pms has been
* triggered.
*/
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ADDR 0x00FFFFFFU
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ADDR_M (HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ADDR_V << HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ADDR_S)
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU
#define HP_SYSTEM_CPU_PERI_PMS_EXCEPTION_ADDR_S 8
/** HP_SYSTEM_HP_PERI_PMS_CONF_REG register
* HP Peripherals PMS configuration register
*/
#define HP_SYSTEM_HP_PERI_PMS_CONF_REG (DR_REG_HP_BASE + 0x98)
/** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear hp peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR (BIT(0))
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR_M (HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR_V << HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR_S)
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR_V 0x00000001U
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_CLR_S 0
/** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_INFO_REG register
* HP Peripherals PMS exception info record register
*/
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_BASE + 0x9c)
/** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0;
* Represents whether the hp peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET (BIT(0))
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET_M (HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET_V << HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET_S)
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET_V 0x00000001U
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_DET_S 0
/** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ID : RO; bitpos: [5:1]; default: 0;
* Represents the master id when hp peripheral pms has been triggered.
*/
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ID 0x0000001FU
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ID_M (HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ID_V << HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ID_S)
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ID_V 0x0000001FU
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ID_S 1
/** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_MODE : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when hp peripheral pms has been triggered.
*/
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_MODE 0x00000003U
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_MODE_M (HP_SYSTEM_HP_PERI_PMS_EXCEPTION_MODE_V << HP_SYSTEM_HP_PERI_PMS_EXCEPTION_MODE_S)
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_MODE_V 0x00000003U
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_MODE_S 6
/** HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ADDR : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when hp peripheral pms has been
* triggered.
*/
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ADDR 0x00FFFFFFU
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ADDR_M (HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ADDR_V << HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ADDR_S)
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU
#define HP_SYSTEM_HP_PERI_PMS_EXCEPTION_ADDR_S 8
/** HP_SYSTEM_MODEM_PERI_PMS_CONF_REG register
* MODEM Peripherals PMS configuration register
*/
#define HP_SYSTEM_MODEM_PERI_PMS_CONF_REG (DR_REG_HP_BASE + 0xa0)
/** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear modem peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR (BIT(0))
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR_M (HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR_V << HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR_S)
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_CLR_S 0
/** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_INFO_REG register
* MODEM Peripherals PMS exception info record register
*/
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_HP_BASE + 0xa4)
/** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0;
* Represents whether the modem peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET (BIT(0))
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET_M (HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET_V << HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET_S)
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_DET_S 0
/** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ID : RO; bitpos: [5:1]; default: 0;
* Represents the master id when modem peripheral pms has been triggered.
*/
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ID 0x0000001FU
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ID_M (HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ID_V << HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ID_S)
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ID_V 0x0000001FU
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ID_S 1
/** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_MODE : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when modem peripheral pms has been triggered.
*/
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_MODE 0x00000003U
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_MODE_M (HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_MODE_V << HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_MODE_S)
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_MODE_V 0x00000003U
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_MODE_S 6
/** HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when modem peripheral pms has been
* triggered.
*/
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR 0x00FFFFFFU
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_M (HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_V << HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_S)
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_S 8
/** HP_SYSTEM_ID_REG register
* ID register
*/
#define HP_SYSTEM_ID_REG (DR_REG_HP_BASE + 0x3dc)
/** HP_SYSTEM_ROM_ID : RO; bitpos: [27:12]; default: 0;
* Represents the ROM ID of chip
*/
#define HP_SYSTEM_ROM_ID 0x0000FFFFU
#define HP_SYSTEM_ROM_ID_M (HP_SYSTEM_ROM_ID_V << HP_SYSTEM_ROM_ID_S)
#define HP_SYSTEM_ROM_ID_V 0x0000FFFFU
#define HP_SYSTEM_ROM_ID_S 12
/** HP_SYSTEM_RST_EN_REG register
* PCR clock gating configure register
*/
#define HP_SYSTEM_RST_EN_REG (DR_REG_HP_BASE + 0x3f0)
/** HP_SYSTEM_HPSYSREG_RST_EN : R/W; bitpos: [0]; default: 0;
* Set 0 to reset hp_system_reg module
*/
#define HP_SYSTEM_HPSYSREG_RST_EN (BIT(0))
#define HP_SYSTEM_HPSYSREG_RST_EN_M (HP_SYSTEM_HPSYSREG_RST_EN_V << HP_SYSTEM_HPSYSREG_RST_EN_S)
#define HP_SYSTEM_HPSYSREG_RST_EN_V 0x00000001U
#define HP_SYSTEM_HPSYSREG_RST_EN_S 0
/** HP_SYSTEM_DATE_REG register
* Date control and version control register
*/
#define HP_SYSTEM_DATE_REG (DR_REG_HP_BASE + 0x3fc)
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37823056;
* Version control register.
*/
#define HP_SYSTEM_DATE 0x0FFFFFFFU
#define HP_SYSTEM_DATE_M (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
#define HP_SYSTEM_DATE_V 0x0FFFFFFFU
#define HP_SYSTEM_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/hp_system_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of system_external_device_encrypt_decrypt_control register
* External device encryption/decryption configuration register
*/
typedef union {
struct {
/** system_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t system_enable_spi_manual_encrypt:1;
/** system_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t system_enable_download_db_encrypt:1;
/** system_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t system_enable_download_g0cb_decrypt:1;
/** system_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode.
* 0: Disable
* 1: Enable
*/
uint32_t system_enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_system_external_device_encrypt_decrypt_control_reg_t;
/** Type of system_sdio_ctrl register
* SDIO Control configuration register
*/
typedef union {
struct {
/** system_dis_sdio_prob : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
uint32_t system_dis_sdio_prob:1;
/** system_sdio_win_access_en : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
uint32_t system_sdio_win_access_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_sdio_ctrl_reg_t;
/** Type of system_rom_table_lock register
* ROM-Table lock register
*/
typedef union {
struct {
/** system_rom_table_lock : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE.
* 0: Unlock
* 1: Lock
*/
uint32_t system_rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_rom_table_lock_reg_t;
/** Type of system_rom_table register
* ROM-Table register
*/
typedef union {
struct {
/** system_rom_table : R/W; bitpos: [31:0]; default: 0;
* Software ROM-Table register, whose content can be modified only when
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
*/
uint32_t system_rom_table:32;
};
uint32_t val;
} hp_system_rom_table_reg_t;
/** Type of system_core_debug_runstall_conf register
* Core Debug RunStall configurion register
*/
typedef union {
struct {
/** system_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable debug RunStall functionality between HP CPU and
* LP CPU.
* 0: Disable
* 1: Enable
*/
uint32_t system_core_debug_runstall_enable:1;
/** system_core0_runstalled : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core0. 1: stalled, 0:
* not stalled.
*/
uint32_t system_core0_runstalled:1;
/** system_core1_runstalled : RO; bitpos: [2]; default: 0;
* Software can read this field to get the runstall status of hp-core1. 1: stalled, 0:
* not stalled.
*/
uint32_t system_core1_runstalled:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_system_core_debug_runstall_conf_reg_t;
/** Type of system_sprom_ctrl register
* reserved
*/
typedef union {
struct {
/** system_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 80;
* reserved
*/
uint32_t system_sprom_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprom_ctrl_reg_t;
/** Type of system_spram_ctrl register
* reserved
*/
typedef union {
struct {
/** system_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;
* reserved
*/
uint32_t system_spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_spram_ctrl_reg_t;
/** Type of system_sprf_ctrl register
* reserved
*/
typedef union {
struct {
/** system_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;
* reserved
*/
uint32_t system_sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprf_ctrl_reg_t;
/** Type of system_bitscrambler_peri_sel register
* reserved
*/
typedef union {
struct {
/** system_bitscrambler_rx_sel : R/W; bitpos: [3:0]; default: 0;
* select peri that will be connected to bitscrambler,dir : receive data from bs
*/
uint32_t system_bitscrambler_rx_sel:4;
/** system_bitscrambler_tx_sel : R/W; bitpos: [7:4]; default: 0;
* select peri that will be connected to bitscrambler,dir : transfer data to peri
*/
uint32_t system_bitscrambler_tx_sel:4;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_system_bitscrambler_peri_sel_reg_t;
/** Type of system_appcpu_boot_addr register
* reserved
*/
typedef union {
struct {
/** system_appcpu_boot_addr : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t system_appcpu_boot_addr:32;
};
uint32_t val;
} hp_system_appcpu_boot_addr_reg_t;
/** Type of system_axi_mst_pri register
* AXI mst priority configuration register
*/
typedef union {
struct {
/** system_dma_priority : R/W; bitpos: [0]; default: 0;
* AHB-DMA arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t system_dma_priority:1;
/** system_cache_priority : R/W; bitpos: [1]; default: 0;
* CACHE arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t system_cache_priority:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_axi_mst_pri_reg_t;
/** Type of system_rst_en register
* PCR clock gating configure register
*/
typedef union {
struct {
/** system_hpsysreg_rst_en : R/W; bitpos: [0]; default: 0;
* Set 0 to reset hp_system_reg module
*/
uint32_t system_hpsysreg_rst_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_rst_en_reg_t;
/** Group: Timeout Register */
/** Type of system_cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** system_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing CPU peripheral
* register in the number of clock cycles of the clock domain.
*/
uint32_t system_cpu_peri_timeout_thres:16;
/** system_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Write 1 to clear timeout interrupt.
*/
uint32_t system_cpu_peri_timeout_int_clear:1;
/** system_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t system_cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_cpu_peri_timeout_conf_reg_t;
/** Type of system_cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** system_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t system_cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_cpu_peri_timeout_addr_reg_t;
/** Type of system_cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** system_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t system_cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_cpu_peri_timeout_uid_reg_t;
/** Type of system_hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** system_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing HP peripheral
* register, corresponding to the number of clock cycles of the clock domain.
*/
uint32_t system_hp_peri_timeout_thres:16;
/** system_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.
* 0: No effect
* 1: Clear timeout interrupt
*/
uint32_t system_hp_peri_timeout_int_clear:1;
/** system_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t system_hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_hp_peri_timeout_conf_reg_t;
/** Type of system_hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** system_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t system_hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_hp_peri_timeout_addr_reg_t;
/** Type of system_hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** system_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t system_hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_hp_peri_timeout_uid_reg_t;
/** Group: PMS Register */
/** Type of system_cpu_peri_pms_conf register
* CPU Peripherals PMS configuration register
*/
typedef union {
struct {
/** system_cpu_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear cpu peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
uint32_t system_cpu_peri_pms_exception_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_cpu_peri_pms_conf_reg_t;
/** Type of system_cpu_peri_pms_exception_info register
* CPU Peripherals PMS exception info record register
*/
typedef union {
struct {
/** system_cpu_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
* Represents whether the cpu peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
uint32_t system_cpu_peri_pms_exception_det:1;
/** system_cpu_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
* Represents the master id when cpu peripheral pms has been triggered.
*/
uint32_t system_cpu_peri_pms_exception_id:5;
/** system_cpu_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when cpu peripheral pms has been triggered.
*/
uint32_t system_cpu_peri_pms_exception_mode:2;
/** system_cpu_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when cpu peripheral pms has been
* triggered.
*/
uint32_t system_cpu_peri_pms_exception_addr:24;
};
uint32_t val;
} hp_system_cpu_peri_pms_exception_info_reg_t;
/** Type of system_hp_peri_pms_conf register
* HP Peripherals PMS configuration register
*/
typedef union {
struct {
/** system_hp_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear hp peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
uint32_t system_hp_peri_pms_exception_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_hp_peri_pms_conf_reg_t;
/** Type of system_hp_peri_pms_exception_info register
* HP Peripherals PMS exception info record register
*/
typedef union {
struct {
/** system_hp_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
* Represents whether the hp peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
uint32_t system_hp_peri_pms_exception_det:1;
/** system_hp_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
* Represents the master id when hp peripheral pms has been triggered.
*/
uint32_t system_hp_peri_pms_exception_id:5;
/** system_hp_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when hp peripheral pms has been triggered.
*/
uint32_t system_hp_peri_pms_exception_mode:2;
/** system_hp_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when hp peripheral pms has been
* triggered.
*/
uint32_t system_hp_peri_pms_exception_addr:24;
};
uint32_t val;
} hp_system_hp_peri_pms_exception_info_reg_t;
/** Type of system_modem_peri_pms_conf register
* MODEM Peripherals PMS configuration register
*/
typedef union {
struct {
/** system_modem_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear modem peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
uint32_t system_modem_peri_pms_exception_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_modem_peri_pms_conf_reg_t;
/** Type of system_modem_peri_pms_exception_info register
* MODEM Peripherals PMS exception info record register
*/
typedef union {
struct {
/** system_modem_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
* Represents whether the modem peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
uint32_t system_modem_peri_pms_exception_det:1;
/** system_modem_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
* Represents the master id when modem peripheral pms has been triggered.
*/
uint32_t system_modem_peri_pms_exception_id:5;
/** system_modem_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when modem peripheral pms has been triggered.
*/
uint32_t system_modem_peri_pms_exception_mode:2;
/** system_modem_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when modem peripheral pms has been
* triggered.
*/
uint32_t system_modem_peri_pms_exception_addr:24;
};
uint32_t val;
} hp_system_modem_peri_pms_exception_info_reg_t;
/** Group: ID Register */
/** Type of system_id register
* ID register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** system_rom_id : RO; bitpos: [27:12]; default: 0;
* Represents the ROM ID of chip
*/
uint32_t system_rom_id:16;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_system_id_reg_t;
/** Group: Version Register */
/** Type of system_date register
* Date control and version control register
*/
typedef union {
struct {
/** system_date : R/W; bitpos: [27:0]; default: 37823056;
* Version control register.
*/
uint32_t system_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_system_date_reg_t;
typedef struct {
volatile hp_system_external_device_encrypt_decrypt_control_reg_t system_external_device_encrypt_decrypt_control;
uint32_t reserved_004[2];
volatile hp_system_cpu_peri_timeout_conf_reg_t system_cpu_peri_timeout_conf;
volatile hp_system_cpu_peri_timeout_addr_reg_t system_cpu_peri_timeout_addr;
volatile hp_system_cpu_peri_timeout_uid_reg_t system_cpu_peri_timeout_uid;
volatile hp_system_hp_peri_timeout_conf_reg_t system_hp_peri_timeout_conf;
volatile hp_system_hp_peri_timeout_addr_reg_t system_hp_peri_timeout_addr;
volatile hp_system_hp_peri_timeout_uid_reg_t system_hp_peri_timeout_uid;
uint32_t reserved_024[3];
volatile hp_system_sdio_ctrl_reg_t system_sdio_ctrl;
uint32_t reserved_034;
volatile hp_system_rom_table_lock_reg_t system_rom_table_lock;
volatile hp_system_rom_table_reg_t system_rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t system_core_debug_runstall_conf;
uint32_t reserved_044[11];
volatile hp_system_sprom_ctrl_reg_t system_sprom_ctrl;
volatile hp_system_spram_ctrl_reg_t system_spram_ctrl;
volatile hp_system_sprf_ctrl_reg_t system_sprf_ctrl;
uint32_t reserved_07c;
volatile hp_system_bitscrambler_peri_sel_reg_t system_bitscrambler_peri_sel;
volatile hp_system_appcpu_boot_addr_reg_t system_appcpu_boot_addr;
volatile hp_system_axi_mst_pri_reg_t system_axi_mst_pri;
uint32_t reserved_08c;
volatile hp_system_cpu_peri_pms_conf_reg_t system_cpu_peri_pms_conf;
volatile hp_system_cpu_peri_pms_exception_info_reg_t system_cpu_peri_pms_exception_info;
volatile hp_system_hp_peri_pms_conf_reg_t system_hp_peri_pms_conf;
volatile hp_system_hp_peri_pms_exception_info_reg_t system_hp_peri_pms_exception_info;
volatile hp_system_modem_peri_pms_conf_reg_t system_modem_peri_pms_conf;
volatile hp_system_modem_peri_pms_exception_info_reg_t system_modem_peri_pms_exception_info;
uint32_t reserved_0a8[205];
volatile hp_system_id_reg_t system_id;
uint32_t reserved_3e0[4];
volatile hp_system_rst_en_reg_t system_rst_en;
uint32_t reserved_3f4[2];
volatile hp_system_date_reg_t system_date;
} hp_dev_t;
extern hp_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_dev_t) == 0x400, "Invalid size of hp_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
* CPU_INTR_FROM_CPU_0 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_0 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
* CPU_INTR_FROM_CPU_1 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_1 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
* CPU_INTR_FROM_CPU_2 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_2 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
* CPU_INTR_FROM_CPU_3 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_3 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
/** INTPRI_DATE_REG register
* Version control register
*/
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784;
* Version control register.
*/
#define INTPRI_DATE 0x0FFFFFFFU
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
#define INTPRI_DATE_V 0x0FFFFFFFU
#define INTPRI_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_n register
* CPU_INTR_FROM_CPU_n mapping register
*/
typedef union {
struct {
/** cpu_intr_from_cpu_n : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_n mapping register.
*/
uint32_t cpu_intr_from_cpu_n:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_n_reg_t;
/** Group: Version Registers */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36712784;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} intpri_date_reg_t;
typedef struct {
uint32_t reserved_000[36];
volatile intpri_cpu_intr_from_cpu_n_reg_t cpu_intr_from_cpu_n[4];
volatile intpri_date_reg_t date;
} intpri_dev_t;
extern intpri_dev_t INTPRI;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0xa4, "Invalid size of intpri_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of mux_gpion register
* IO MUX configuration register for GPIOn
*/
typedef union {
struct {
/** mux_gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_oe:1;
/** mux_gpion_slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for GPIOn.
* 0: Not enter
* 1: Enter
*/
uint32_t mux_gpion_slp_sel:1;
/** mux_gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_wpd:1;
/** mux_gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_wpu:1;
/** mux_gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_ie:1;
/** mux_gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of GPIOn during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t mux_gpion_mcu_drv:2;
/** mux_gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_wpd:1;
/** mux_gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_wpu:1;
/** mux_gpion_fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_ie:1;
/** mux_gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of GPIOn.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t mux_gpion_fun_drv:2;
/** mux_gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
uint32_t mux_gpion_mcu_sel:3;
/** mux_gpion_filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_filter_en:1;
/** mux_gpion_hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_GPIOn_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_hys_en:1;
/** mux_gpion_hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for GPIOn.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN
*/
uint32_t mux_gpion_hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} io_mux_gpion_reg_t;
/** Group: Version Register */
/** Type of mux_date register
* Version control register
*/
typedef union {
struct {
/** mux_reg_date : R/W; bitpos: [27:0]; default: 37822816;
* Version control register
*/
uint32_t mux_reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} io_mux_date_reg_t;
typedef struct {
volatile io_mux_gpion_reg_t mux_gpion[40];
uint32_t reserved_0a0[87];
volatile io_mux_date_reg_t mux_date;
} io_dev_t;
extern io_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_dev_t) == 0x200, "Invalid size of io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* Bus access logging configuration register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
* Configures monitoring modes.bit[0]: Configures write monitoring.
* 0: Disable
* 1: Enable
* bit[1]: Configures word monitoring.
* 0: Disable
* 1: Enable
* bit[2]: Configures halfword monitoring.
* 0: Disable
* 1: Enable
* bit[3]: Configures byte monitoring.
* 0: Disable
* 1: Enable
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 0
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
* Configures the writing mode for recorded data.1: Loop mode
* 0: Non-loop mode
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
* enable HP CPU bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_S 8
/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
* to enable DMA_0 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
* to enable DMA_1 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
#define MEM_MONITOR_LOG_DMA_1_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_S 24
/** MEM_MONITOR_LOG_SETTING1_REG register
* Bus access logging configuration register
*/
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_BASE + 0x4)
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
* to enable DMA_2 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
* to enable DMA_3 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
#define MEM_MONITOR_LOG_DMA_3_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_S 8
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* Configures monitored data in Bus access logging
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_BASE + 0x8)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* Configures the data to be monitored during bus accessing.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* Configures masked data in Bus access logging
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_BASE + 0xc)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
* Configures whether to mask the least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[1]: Configures whether to mask the second least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[2]: Configures whether to mask the second most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[3]: Configures whether to mask the most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* Configures monitored address space in Bus access logging
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_BASE + 0x10)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of the monitored address space.
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* Configures monitored address space in Bus access logging
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_BASE + 0x14)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of the monitored address space.
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_BASE + 0x18)
/** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the HP CPU bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0
/** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0;
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update
* 0: Not update
*/
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31))
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S 31
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_BASE + 0x1c)
/** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_0 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S 0
/** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_1 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S 8
/** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_2 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S 16
/** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_3 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S 24
/** MEM_MONITOR_LOG_MEM_START_REG register
* Configures the starting address of the storage memory for recorded data
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* Configures the starting address of the storage space for recorded data.
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* Configures the end address of the storage memory for recorded data
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* Configures the ending address of the storage space for recorded data.
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* Represents the address for the next write
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_BASE + 0x28)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the address of the next write.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* Updates the address for the next write with the starting address for the recorded
* data
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_BASE + 0x2c)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update
* 0: Not update (default)
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* Logging overflow status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_BASE + 0x30)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* Represents whether data overflows the storage space.0: Not Overflow
* 1: Overflow
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not clear
* 1: Clear
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* Register clock control
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_BASE + 0x34)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the register clock gating.0: Disable
* 1: Enable
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* Version control register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36733248;
* Version control register.
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of monitor_log_setting register
* Bus access logging configuration register
*/
typedef union {
struct {
/** monitor_log_mode : R/W; bitpos: [3:0]; default: 0;
* Configures monitoring modes.bit[0]: Configures write monitoring.
* 0: Disable
* 1: Enable
* bit[1]: Configures word monitoring.
* 0: Disable
* 1: Enable
* bit[2]: Configures halfword monitoring.
* 0: Disable
* 1: Enable
* bit[3]: Configures byte monitoring.
* 0: Disable
* 1: Enable
*/
uint32_t monitor_log_mode:4;
/** monitor_log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
* Configures the writing mode for recorded data.1: Loop mode
* 0: Non-loop mode
*/
uint32_t monitor_log_mem_loop_enable:1;
uint32_t reserved_5:3;
/** monitor_log_core_ena : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
* enable HP CPU bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_core_ena:8;
/** monitor_log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
* to enable DMA_0 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_dma_0_ena:8;
/** monitor_log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
* to enable DMA_1 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_dma_1_ena:8;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of monitor_log_setting1 register
* Bus access logging configuration register
*/
typedef union {
struct {
/** monitor_log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
* to enable DMA_2 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_dma_2_ena:8;
/** monitor_log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
* to enable DMA_3 bus access logging.
* 0: Disable
* 1: Enable
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_dma_3_ena:8;
uint32_t reserved_16:16;
};
uint32_t val;
} mem_monitor_log_setting1_reg_t;
/** Type of monitor_log_check_data register
* Configures monitored data in Bus access logging
*/
typedef union {
struct {
/** monitor_log_check_data : R/W; bitpos: [31:0]; default: 0;
* Configures the data to be monitored during bus accessing.
*/
uint32_t monitor_log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of monitor_log_data_mask register
* Configures masked data in Bus access logging
*/
typedef union {
struct {
/** monitor_log_data_mask : R/W; bitpos: [3:0]; default: 0;
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
* Configures whether to mask the least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[1]: Configures whether to mask the second least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[2]: Configures whether to mask the second most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
* bit[3]: Configures whether to mask the most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.
* 0: Not mask
* 1: Mask
*/
uint32_t monitor_log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of monitor_log_min register
* Configures monitored address space in Bus access logging
*/
typedef union {
struct {
/** monitor_log_min : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of the monitored address space.
*/
uint32_t monitor_log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of monitor_log_max register
* Configures monitored address space in Bus access logging
*/
typedef union {
struct {
/** monitor_log_max : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of the monitored address space.
*/
uint32_t monitor_log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of monitor_log_mon_addr_update_0 register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
typedef union {
struct {
/** monitor_log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the HP CPU bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_mon_addr_core_update:8;
uint32_t reserved_8:23;
/** monitor_log_mon_addr_all_update : WT; bitpos: [31]; default: 0;
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update
* 0: Not update
*/
uint32_t monitor_log_mon_addr_all_update:1;
};
uint32_t val;
} mem_monitor_log_mon_addr_update_0_reg_t;
/** Type of monitor_log_mon_addr_update_1 register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
typedef union {
struct {
/** monitor_log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_0 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_mon_addr_dma_0_update:8;
/** monitor_log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_1 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_mon_addr_dma_1_update:8;
/** monitor_log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_2 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_mon_addr_dma_2_update:8;
/** monitor_log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_3 bus.1: Update
* 0: Not update
* Bit[7:1]: Reserved
*/
uint32_t monitor_log_mon_addr_dma_3_update:8;
};
uint32_t val;
} mem_monitor_log_mon_addr_update_1_reg_t;
/** Type of monitor_log_mem_start register
* Configures the starting address of the storage memory for recorded data
*/
typedef union {
struct {
/** monitor_log_mem_start : R/W; bitpos: [31:0]; default: 0;
* Configures the starting address of the storage space for recorded data.
*/
uint32_t monitor_log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of monitor_log_mem_end register
* Configures the end address of the storage memory for recorded data
*/
typedef union {
struct {
/** monitor_log_mem_end : R/W; bitpos: [31:0]; default: 0;
* Configures the ending address of the storage space for recorded data.
*/
uint32_t monitor_log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of monitor_log_mem_current_addr register
* Represents the address for the next write
*/
typedef union {
struct {
/** monitor_log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address of the next write.
*/
uint32_t monitor_log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of monitor_log_mem_addr_update register
* Updates the address for the next write with the starting address for the recorded
* data
*/
typedef union {
struct {
/** monitor_log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update
* 0: Not update (default)
*/
uint32_t monitor_log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of monitor_log_mem_full_flag register
* Logging overflow status register
*/
typedef union {
struct {
/** monitor_log_mem_full_flag : RO; bitpos: [0]; default: 0;
* Represents whether data overflows the storage space.0: Not Overflow
* 1: Overflow
*/
uint32_t monitor_log_mem_full_flag:1;
/** monitor_clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not clear
* 1: Clear
*/
uint32_t monitor_clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of monitor_clock_gate register
* Register clock control
*/
typedef union {
struct {
/** monitor_clk_en : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the register clock gating.0: Disable
* 1: Enable
*/
uint32_t monitor_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of monitor_date register
* Version control register
*/
typedef union {
struct {
/** monitor_date : R/W; bitpos: [27:0]; default: 36733248;
* Version control register.
*/
uint32_t monitor_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct {
volatile mem_monitor_log_setting_reg_t monitor_log_setting;
volatile mem_monitor_log_setting1_reg_t monitor_log_setting1;
volatile mem_monitor_log_check_data_reg_t monitor_log_check_data;
volatile mem_monitor_log_data_mask_reg_t monitor_log_data_mask;
volatile mem_monitor_log_min_reg_t monitor_log_min;
volatile mem_monitor_log_max_reg_t monitor_log_max;
volatile mem_monitor_log_mon_addr_update_0_reg_t monitor_log_mon_addr_update_0;
volatile mem_monitor_log_mon_addr_update_1_reg_t monitor_log_mon_addr_update_1;
volatile mem_monitor_log_mem_start_reg_t monitor_log_mem_start;
volatile mem_monitor_log_mem_end_reg_t monitor_log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t monitor_log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t monitor_log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t monitor_log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t monitor_clock_gate;
uint32_t reserved_038[241];
volatile mem_monitor_date_reg_t monitor_date;
} mem_dev_t;
extern mem_dev_t MEM_MONITOR;
#ifndef __cplusplus
_Static_assert(sizeof(mem_dev_t) == 0x400, "Invalid size of mem_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PARL_IO_RX_MODE_CFG_REG register
* Parallel RX Sampling mode configuration register.
*/
#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_BASE + 0x0)
/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_S 21
/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
* Write 1 to enable data sampling by software.
*/
#define PARL_IO_RX_SW_EN (BIT(25))
#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
#define PARL_IO_RX_SW_EN_V 0x00000001U
#define PARL_IO_RX_SW_EN_S 25
/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
* Write 1 to invert the external enable signal.
*/
#define PARL_IO_RX_EXT_EN_INV (BIT(26))
#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U
#define PARL_IO_RX_EXT_EN_INV_S 26
/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 0: positive pulse start(data bit included) && positive pulse end(data bit included)
* 1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
* 2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
* 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
* 4: positive pulse start(data bit included) && length end
* 5: positive pulse start(data bit excluded) && length end
*/
#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27
/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 0: external level enable mode
* 1: external pulse enable mode
* 2: internal software enable mode
*/
#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_S 30
/** PARL_IO_RX_DATA_CFG_REG register
* Parallel RX data configuration register.
*/
#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x4)
/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
#define PARL_IO_RX_BITLEN 0x0007FFFFU
#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
#define PARL_IO_RX_BITLEN_V 0x0007FFFFU
#define PARL_IO_RX_BITLEN_S 9
/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
*/
#define PARL_IO_RX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_RX_DATA_ORDER_INV_S 28
/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
#define PARL_IO_RX_BUS_WID_SEL 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_S 29
/** PARL_IO_RX_GENRL_CFG_REG register
* Parallel RX general configuration register.
*/
#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x8)
/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
#define PARL_IO_RX_GATING_EN (BIT(12))
#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
#define PARL_IO_RX_GATING_EN_V 0x00000001U
#define PARL_IO_RX_GATING_EN_S 12
/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_S 13
/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
* Write 1 to enable timeout function to generate error eof.
*/
#define PARL_IO_RX_TIMEOUT_EN (BIT(29))
#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U
#define PARL_IO_RX_TIMEOUT_EN_S 29
/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
#define PARL_IO_RX_EOF_GEN_SEL (BIT(30))
#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_RX_EOF_GEN_SEL_S 30
/** PARL_IO_RX_START_CFG_REG register
* Parallel RX Start configuration register.
*/
#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_BASE + 0xc)
/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
#define PARL_IO_RX_START (BIT(31))
#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
#define PARL_IO_RX_START_V 0x00000001U
#define PARL_IO_RX_START_S 31
/** PARL_IO_TX_DATA_CFG_REG register
* Parallel TX data configuration register.
*/
#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x10)
/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
#define PARL_IO_TX_BITLEN 0x0007FFFFU
#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
#define PARL_IO_TX_BITLEN_V 0x0007FFFFU
#define PARL_IO_TX_BITLEN_S 9
/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
*/
#define PARL_IO_TX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_TX_DATA_ORDER_INV_S 28
/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
#define PARL_IO_TX_BUS_WID_SEL 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_S 29
/** PARL_IO_TX_START_CFG_REG register
* Parallel TX Start configuration register.
*/
#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_BASE + 0x14)
/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
#define PARL_IO_TX_START (BIT(31))
#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
#define PARL_IO_TX_START_V 0x00000001U
#define PARL_IO_TX_START_S 31
/** PARL_IO_TX_GENRL_CFG_REG register
* Parallel TX general configuration register.
*/
#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x18)
/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
#define PARL_IO_TX_EOF_GEN_SEL (BIT(13))
#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_TX_EOF_GEN_SEL_S 13
/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_S 14
/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
* Write 1 to enable the clock gating of output tx clock.
*/
#define PARL_IO_TX_GATING_EN (BIT(30))
#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
#define PARL_IO_TX_GATING_EN_V 0x00000001U
#define PARL_IO_TX_GATING_EN_S 30
/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
* Write 1 to enable the output of tx data valid signal.
*/
#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31))
#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U
#define PARL_IO_TX_VALID_OUTPUT_EN_S 31
/** PARL_IO_FIFO_CFG_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_BASE + 0x1c)
/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
#define PARL_IO_TX_FIFO_SRST (BIT(30))
#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
#define PARL_IO_TX_FIFO_SRST_V 0x00000001U
#define PARL_IO_TX_FIFO_SRST_S 30
/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
* Write 1 to reset async fifo in rx module.
*/
#define PARL_IO_RX_FIFO_SRST (BIT(31))
#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
#define PARL_IO_RX_FIFO_SRST_V 0x00000001U
#define PARL_IO_RX_FIFO_SRST_S 31
/** PARL_IO_REG_UPDATE_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_BASE + 0x20)
/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
#define PARL_IO_RX_REG_UPDATE (BIT(31))
#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
#define PARL_IO_RX_REG_UPDATE_V 0x00000001U
#define PARL_IO_RX_REG_UPDATE_S 31
/** PARL_IO_ST_REG register
* Parallel IO module status register0.
*/
#define PARL_IO_ST_REG (DR_REG_PARL_BASE + 0x24)
/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
#define PARL_IO_TX_READY (BIT(31))
#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
#define PARL_IO_TX_READY_V 0x00000001U
#define PARL_IO_TX_READY_S 31
/** PARL_IO_INT_ENA_REG register
* Parallel IO interrupt enable signal configuration register.
*/
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_BASE + 0x28)
/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1
/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ENA (BIT(2))
#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ENA_S 2
/** PARL_IO_INT_RAW_REG register
* Parallel IO interrupt raw signal status register.
*/
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_BASE + 0x2c)
/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1
/** PARL_IO_TX_EOF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_RAW (BIT(2))
#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U
#define PARL_IO_TX_EOF_INT_RAW_S 2
/** PARL_IO_INT_ST_REG register
* Parallel IO interrupt signal status register.
*/
#define PARL_IO_INT_ST_REG (DR_REG_PARL_BASE + 0x30)
/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1
/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ST (BIT(2))
#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ST_S 2
/** PARL_IO_INT_CLR_REG register
* Parallel IO interrupt clear signal configuration register.
*/
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_BASE + 0x34)
/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1
/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_CLR (BIT(2))
#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U
#define PARL_IO_TX_EOF_INT_CLR_S 2
/** PARL_IO_RX_ST0_REG register
* Parallel IO RX status register0
*/
#define PARL_IO_RX_ST0_REG (DR_REG_PARL_BASE + 0x38)
/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
#define PARL_IO_RX_CNT 0x0000001FU
#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
#define PARL_IO_RX_CNT_V 0x0000001FU
#define PARL_IO_RX_CNT_S 8
/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13
/** PARL_IO_RX_ST1_REG register
* Parallel IO RX status register1
*/
#define PARL_IO_RX_ST1_REG (DR_REG_PARL_BASE + 0x3c)
/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_TX_ST0_REG register
* Parallel IO TX status register0
*/
#define PARL_IO_TX_ST0_REG (DR_REG_PARL_BASE + 0x40)
/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
#define PARL_IO_TX_CNT 0x0000007FU
#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
#define PARL_IO_TX_CNT_V 0x0000007FU
#define PARL_IO_TX_CNT_S 6
/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_RX_CLK_CFG_REG register
* Parallel IO RX clk configuration register
*/
#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x44)
/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
#define PARL_IO_RX_CLK_I_INV (BIT(30))
#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
#define PARL_IO_RX_CLK_I_INV_V 0x00000001U
#define PARL_IO_RX_CLK_I_INV_S 30
/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Rx core clock.
*/
#define PARL_IO_RX_CLK_O_INV (BIT(31))
#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
#define PARL_IO_RX_CLK_O_INV_V 0x00000001U
#define PARL_IO_RX_CLK_O_INV_S 31
/** PARL_IO_TX_CLK_CFG_REG register
* Parallel IO TX clk configuration register
*/
#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x48)
/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
#define PARL_IO_TX_CLK_I_INV (BIT(30))
#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
#define PARL_IO_TX_CLK_I_INV_V 0x00000001U
#define PARL_IO_TX_CLK_I_INV_S 30
/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Tx core clock.
*/
#define PARL_IO_TX_CLK_O_INV (BIT(31))
#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
#define PARL_IO_TX_CLK_O_INV_V 0x00000001U
#define PARL_IO_TX_CLK_O_INV_S 31
/** PARL_IO_TX_CS_CFG_REG register
* Parallel IO tx_cs_o generate configuration
*/
#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_BASE + 0x4c)
/** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0;
* configure the delay between data tx end and tx_cs_o posedge
*/
#define PARL_IO_TX_CS_STOP_DELAY 0x0000FFFFU
#define PARL_IO_TX_CS_STOP_DELAY_M (PARL_IO_TX_CS_STOP_DELAY_V << PARL_IO_TX_CS_STOP_DELAY_S)
#define PARL_IO_TX_CS_STOP_DELAY_V 0x0000FFFFU
#define PARL_IO_TX_CS_STOP_DELAY_S 0
/** PARL_IO_TX_CS_START_DELAY : R/W; bitpos: [31:16]; default: 0;
* configure the delay between tx_cs_o negedge and data tx start
*/
#define PARL_IO_TX_CS_START_DELAY 0x0000FFFFU
#define PARL_IO_TX_CS_START_DELAY_M (PARL_IO_TX_CS_START_DELAY_V << PARL_IO_TX_CS_START_DELAY_S)
#define PARL_IO_TX_CS_START_DELAY_V 0x0000FFFFU
#define PARL_IO_TX_CS_START_DELAY_S 16
/** PARL_IO_CLK_REG register
* Parallel IO clk configuration register
*/
#define PARL_IO_CLK_REG (DR_REG_PARL_BASE + 0x120)
/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
#define PARL_IO_CLK_EN (BIT(31))
#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
#define PARL_IO_CLK_EN_V 0x00000001U
#define PARL_IO_CLK_EN_S 31
/** PARL_IO_VERSION_REG register
* Version register.
*/
#define PARL_IO_VERSION_REG (DR_REG_PARL_BASE + 0x3fc)
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160;
* Version of this register file
*/
#define PARL_IO_DATE 0x0FFFFFFFU
#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S)
#define PARL_IO_DATE_V 0x0FFFFFFFU
#define PARL_IO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/parl_io_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: PARL_IO RX Mode Configuration */
/** Type of io_rx_mode_cfg register
* Parallel RX Sampling mode configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** io_rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
uint32_t io_rx_ext_en_sel:4;
/** io_rx_sw_en : R/W; bitpos: [25]; default: 0;
* Write 1 to enable data sampling by software.
*/
uint32_t io_rx_sw_en:1;
/** io_rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
* Write 1 to invert the external enable signal.
*/
uint32_t io_rx_ext_en_inv:1;
/** io_rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 0: positive pulse start(data bit included) && positive pulse end(data bit included)
* 1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
* 2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
* 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
* 4: positive pulse start(data bit included) && length end
* 5: positive pulse start(data bit excluded) && length end
*/
uint32_t io_rx_pulse_submode_sel:3;
/** io_rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 0: external level enable mode
* 1: external pulse enable mode
* 2: internal software enable mode
*/
uint32_t io_rx_smp_mode_sel:2;
};
uint32_t val;
} parl_io_rx_mode_cfg_reg_t;
/** Group: PARL_IO RX Data Configuration */
/** Type of io_rx_data_cfg register
* Parallel RX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** io_rx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
uint32_t io_rx_bitlen:19;
/** io_rx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
*/
uint32_t io_rx_data_order_inv:1;
/** io_rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t io_rx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_rx_data_cfg_reg_t;
/** Group: PARL_IO RX General Configuration */
/** Type of io_rx_genrl_cfg register
* Parallel RX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** io_rx_gating_en : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
uint32_t io_rx_gating_en:1;
/** io_rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
uint32_t io_rx_timeout_thres:16;
/** io_rx_timeout_en : R/W; bitpos: [29]; default: 1;
* Write 1 to enable timeout function to generate error eof.
*/
uint32_t io_rx_timeout_en:1;
/** io_rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
uint32_t io_rx_eof_gen_sel:1;
uint32_t reserved_31:1;
};
uint32_t val;
} parl_io_rx_genrl_cfg_reg_t;
/** Group: PARL_IO RX Start Configuration */
/** Type of io_rx_start_cfg register
* Parallel RX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_rx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
uint32_t io_rx_start:1;
};
uint32_t val;
} parl_io_rx_start_cfg_reg_t;
/** Group: PARL_IO TX Data Configuration */
/** Type of io_tx_data_cfg register
* Parallel TX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** io_tx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
uint32_t io_tx_bitlen:19;
/** io_tx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
*/
uint32_t io_tx_data_order_inv:1;
/** io_tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t io_tx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_tx_data_cfg_reg_t;
/** Group: PARL_IO TX Start Configuration */
/** Type of io_tx_start_cfg register
* Parallel TX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_tx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
uint32_t io_tx_start:1;
};
uint32_t val;
} parl_io_tx_start_cfg_reg_t;
/** Group: PARL_IO TX General Configuration */
/** Type of io_tx_genrl_cfg register
* Parallel TX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** io_tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
uint32_t io_tx_eof_gen_sel:1;
/** io_tx_idle_value : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
uint32_t io_tx_idle_value:16;
/** io_tx_gating_en : R/W; bitpos: [30]; default: 0;
* Write 1 to enable the clock gating of output tx clock.
*/
uint32_t io_tx_gating_en:1;
/** io_tx_valid_output_en : R/W; bitpos: [31]; default: 0;
* Write 1 to enable the output of tx data valid signal.
*/
uint32_t io_tx_valid_output_en:1;
};
uint32_t val;
} parl_io_tx_genrl_cfg_reg_t;
/** Group: PARL_IO FIFO Configuration */
/** Type of io_fifo_cfg register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_tx_fifo_srst : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
uint32_t io_tx_fifo_srst:1;
/** io_rx_fifo_srst : R/W; bitpos: [31]; default: 0;
* Write 1 to reset async fifo in rx module.
*/
uint32_t io_rx_fifo_srst:1;
};
uint32_t val;
} parl_io_fifo_cfg_reg_t;
/** Group: PARL_IO Register Update Configuration */
/** Type of io_reg_update register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_rx_reg_update : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
uint32_t io_rx_reg_update:1;
};
uint32_t val;
} parl_io_reg_update_reg_t;
/** Group: PARL_IO Status */
/** Type of io_st register
* Parallel IO module status register0.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_tx_ready : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
uint32_t io_tx_ready:1;
};
uint32_t val;
} parl_io_st_reg_t;
/** Group: PARL_IO Interrupt Configuration and Status */
/** Type of io_int_ena register
* Parallel IO interrupt enable signal configuration register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_ena:1;
/** io_rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_ena:1;
/** io_tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INT.
*/
uint32_t io_tx_eof_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_ena_reg_t;
/** Type of io_int_raw register
* Parallel IO interrupt raw signal status register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_raw:1;
/** io_rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_raw:1;
/** io_tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
uint32_t io_tx_eof_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_raw_reg_t;
/** Type of io_int_st register
* Parallel IO interrupt signal status register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_st:1;
/** io_rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_st:1;
/** io_tx_eof_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
uint32_t io_tx_eof_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_st_reg_t;
/** Type of io_int_clr register
* Parallel IO interrupt clear signal configuration register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_clr:1;
/** io_rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_clr:1;
/** io_tx_eof_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INT.
*/
uint32_t io_tx_eof_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_clr_reg_t;
/** Group: PARL_IO Rx Status0 */
/** Type of io_rx_st0 register
* Parallel IO RX status register0
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** io_rx_cnt : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
uint32_t io_rx_cnt:5;
/** io_rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
uint32_t io_rx_fifo_wr_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st0_reg_t;
/** Group: PARL_IO Rx Status1 */
/** Type of io_rx_st1 register
* Parallel IO RX status register1
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** io_rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
uint32_t io_rx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st1_reg_t;
/** Group: PARL_IO Tx Status0 */
/** Type of io_tx_st0 register
* Parallel IO TX status register0
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** io_tx_cnt : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
uint32_t io_tx_cnt:7;
/** io_tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
uint32_t io_tx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_tx_st0_reg_t;
/** Group: PARL_IO Rx Clock Configuration */
/** Type of io_rx_clk_cfg register
* Parallel IO RX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
uint32_t io_rx_clk_i_inv:1;
/** io_rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Rx core clock.
*/
uint32_t io_rx_clk_o_inv:1;
};
uint32_t val;
} parl_io_rx_clk_cfg_reg_t;
/** Group: PARL_IO Tx Clock Configuration */
/** Type of io_tx_clk_cfg register
* Parallel IO TX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
uint32_t io_tx_clk_i_inv:1;
/** io_tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Tx core clock.
*/
uint32_t io_tx_clk_o_inv:1;
};
uint32_t val;
} parl_io_tx_clk_cfg_reg_t;
/** Group: PARL_TX_CS Configuration */
/** Type of io_tx_cs_cfg register
* Parallel IO tx_cs_o generate configuration
*/
typedef union {
struct {
/** io_tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0;
* configure the delay between data tx end and tx_cs_o posedge
*/
uint32_t io_tx_cs_stop_delay:16;
/** io_tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0;
* configure the delay between tx_cs_o negedge and data tx start
*/
uint32_t io_tx_cs_start_delay:16;
};
uint32_t val;
} parl_io_tx_cs_cfg_reg_t;
/** Group: PARL_IO Clock Configuration */
/** Type of io_clk register
* Parallel IO clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_clk_en : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
uint32_t io_clk_en:1;
};
uint32_t val;
} parl_io_clk_reg_t;
/** Group: PARL_IO Version Register */
/** Type of io_version register
* Version register.
*/
typedef union {
struct {
/** io_date : R/W; bitpos: [27:0]; default: 37786160;
* Version of this register file
*/
uint32_t io_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} parl_io_version_reg_t;
typedef struct {
volatile parl_io_rx_mode_cfg_reg_t io_rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t io_rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t io_rx_genrl_cfg;
volatile parl_io_rx_start_cfg_reg_t io_rx_start_cfg;
volatile parl_io_tx_data_cfg_reg_t io_tx_data_cfg;
volatile parl_io_tx_start_cfg_reg_t io_tx_start_cfg;
volatile parl_io_tx_genrl_cfg_reg_t io_tx_genrl_cfg;
volatile parl_io_fifo_cfg_reg_t io_fifo_cfg;
volatile parl_io_reg_update_reg_t io_reg_update;
volatile parl_io_st_reg_t io_st;
volatile parl_io_int_ena_reg_t io_int_ena;
volatile parl_io_int_raw_reg_t io_int_raw;
volatile parl_io_int_st_reg_t io_int_st;
volatile parl_io_int_clr_reg_t io_int_clr;
volatile parl_io_rx_st0_reg_t io_rx_st0;
volatile parl_io_rx_st1_reg_t io_rx_st1;
volatile parl_io_tx_st0_reg_t io_tx_st0;
volatile parl_io_rx_clk_cfg_reg_t io_rx_clk_cfg;
volatile parl_io_tx_clk_cfg_reg_t io_tx_clk_cfg;
volatile parl_io_tx_cs_cfg_reg_t io_tx_cs_cfg;
uint32_t reserved_050[52];
volatile parl_io_clk_reg_t io_clk;
uint32_t reserved_124[182];
volatile parl_io_version_reg_t io_version;
} parl_dev_t;
extern parl_dev_t PARL_IO;
#ifndef __cplusplus
_Static_assert(sizeof(parl_dev_t) == 0x400, "Invalid size of parl_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/pau_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
* Peri backup control register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_START : WT; bitpos: [3]; default: 0;
* backup start signal
*/
#define PAU_START (BIT(3))
#define PAU_START_M (PAU_START_V << PAU_START_S)
#define PAU_START_V 0x00000001U
#define PAU_START_S 3
/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM (BIT(4))
#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
#define PAU_TO_MEM_V 0x00000001U
#define PAU_TO_MEM_S 4
/** PAU_LINK_SEL : R/W; bitpos: [8:5]; default: 0;
* Link select
*/
#define PAU_LINK_SEL 0x0000000FU
#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
#define PAU_LINK_SEL_V 0x0000000FU
#define PAU_LINK_SEL_S 5
/** PAU_SW_RETRY_EN : R/W; bitpos: [9]; default: 0;
* sw_retry_en
*/
#define PAU_SW_RETRY_EN (BIT(9))
#define PAU_SW_RETRY_EN_M (PAU_SW_RETRY_EN_V << PAU_SW_RETRY_EN_S)
#define PAU_SW_RETRY_EN_V 0x00000001U
#define PAU_SW_RETRY_EN_S 9
/** PAU_PAUDMA_BUSY : RO; bitpos: [10]; default: 0;
* regdma_busy
*/
#define PAU_PAUDMA_BUSY (BIT(10))
#define PAU_PAUDMA_BUSY_M (PAU_PAUDMA_BUSY_V << PAU_PAUDMA_BUSY_S)
#define PAU_PAUDMA_BUSY_V 0x00000001U
#define PAU_PAUDMA_BUSY_S 10
/** PAU_FIX_PRI_EN : R/W; bitpos: [11]; default: 0;
* fix_pri_en
*/
#define PAU_FIX_PRI_EN (BIT(11))
#define PAU_FIX_PRI_EN_M (PAU_FIX_PRI_EN_V << PAU_FIX_PRI_EN_S)
#define PAU_FIX_PRI_EN_V 0x00000001U
#define PAU_FIX_PRI_EN_S 11
/** PAU_REGDMA_CLK_CONF_REG register
* Clock control register
*/
#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
* clock enable
*/
#define PAU_CLK_EN (BIT(0))
#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
#define PAU_CLK_EN_V 0x00000001U
#define PAU_CLK_EN_S 0
/** PAU_REGDMA_ETM_CTRL_REG register
* ETM start ctrl reg
*/
#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
#define PAU_ETM_START_0 (BIT(0))
#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
#define PAU_ETM_START_0_V 0x00000001U
#define PAU_ETM_START_0_S 0
/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
#define PAU_ETM_START_1 (BIT(1))
#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
#define PAU_ETM_START_1_V 0x00000001U
#define PAU_ETM_START_1_S 1
/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
#define PAU_ETM_START_2 (BIT(2))
#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
#define PAU_ETM_START_2_V 0x00000001U
#define PAU_ETM_START_2_S 2
/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
#define PAU_ETM_START_3 (BIT(3))
#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
#define PAU_ETM_START_3_V 0x00000001U
#define PAU_ETM_START_3_S 3
/** PAU_ETM_LINK_SEL_0 : R/W; bitpos: [8:4]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_0 0x0000001FU
#define PAU_ETM_LINK_SEL_0_M (PAU_ETM_LINK_SEL_0_V << PAU_ETM_LINK_SEL_0_S)
#define PAU_ETM_LINK_SEL_0_V 0x0000001FU
#define PAU_ETM_LINK_SEL_0_S 4
/** PAU_ETM_LINK_SEL_1 : R/W; bitpos: [13:9]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_1 0x0000001FU
#define PAU_ETM_LINK_SEL_1_M (PAU_ETM_LINK_SEL_1_V << PAU_ETM_LINK_SEL_1_S)
#define PAU_ETM_LINK_SEL_1_V 0x0000001FU
#define PAU_ETM_LINK_SEL_1_S 9
/** PAU_ETM_LINK_SEL_2 : R/W; bitpos: [18:14]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_2 0x0000001FU
#define PAU_ETM_LINK_SEL_2_M (PAU_ETM_LINK_SEL_2_V << PAU_ETM_LINK_SEL_2_S)
#define PAU_ETM_LINK_SEL_2_V 0x0000001FU
#define PAU_ETM_LINK_SEL_2_S 14
/** PAU_ETM_LINK_SEL_3 : R/W; bitpos: [23:19]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_3 0x0000001FU
#define PAU_ETM_LINK_SEL_3_M (PAU_ETM_LINK_SEL_3_V << PAU_ETM_LINK_SEL_3_S)
#define PAU_ETM_LINK_SEL_3_V 0x0000001FU
#define PAU_ETM_LINK_SEL_3_S 19
/** PAU_ETM_RETRY_EN_0 : R/W; bitpos: [24]; default: 0;
* etm_retry
*/
#define PAU_ETM_RETRY_EN_0 (BIT(24))
#define PAU_ETM_RETRY_EN_0_M (PAU_ETM_RETRY_EN_0_V << PAU_ETM_RETRY_EN_0_S)
#define PAU_ETM_RETRY_EN_0_V 0x00000001U
#define PAU_ETM_RETRY_EN_0_S 24
/** PAU_ETM_RETRY_EN_1 : R/W; bitpos: [25]; default: 0;
* etm_retry
*/
#define PAU_ETM_RETRY_EN_1 (BIT(25))
#define PAU_ETM_RETRY_EN_1_M (PAU_ETM_RETRY_EN_1_V << PAU_ETM_RETRY_EN_1_S)
#define PAU_ETM_RETRY_EN_1_V 0x00000001U
#define PAU_ETM_RETRY_EN_1_S 25
/** PAU_ETM_RETRY_EN_2 : R/W; bitpos: [26]; default: 0;
* etm_retry
*/
#define PAU_ETM_RETRY_EN_2 (BIT(26))
#define PAU_ETM_RETRY_EN_2_M (PAU_ETM_RETRY_EN_2_V << PAU_ETM_RETRY_EN_2_S)
#define PAU_ETM_RETRY_EN_2_V 0x00000001U
#define PAU_ETM_RETRY_EN_2_S 26
/** PAU_ETM_RETRY_EN_3 : R/W; bitpos: [27]; default: 0;
* etm_retry
*/
#define PAU_ETM_RETRY_EN_3 (BIT(27))
#define PAU_ETM_RETRY_EN_3_M (PAU_ETM_RETRY_EN_3_V << PAU_ETM_RETRY_EN_3_S)
#define PAU_ETM_RETRY_EN_3_V 0x00000001U
#define PAU_ETM_RETRY_EN_3_S 27
/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
* current link addr
*/
#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0xc)
/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_S 0
/** PAU_REGDMA_PERI_ADDR_REG register
* Backup addr
*/
#define PAU_REGDMA_PERI_ADDR_REG (DR_REG_PAU_BASE + 0x10)
/** PAU_PERI_ADDR : RO; bitpos: [31:0]; default: 0;
* peri addr reg
*/
#define PAU_PERI_ADDR 0xFFFFFFFFU
#define PAU_PERI_ADDR_M (PAU_PERI_ADDR_V << PAU_PERI_ADDR_S)
#define PAU_PERI_ADDR_V 0xFFFFFFFFU
#define PAU_PERI_ADDR_S 0
/** PAU_REGDMA_MEM_ADDR_REG register
* mem addr
*/
#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x14)
/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
#define PAU_MEM_ADDR 0xFFFFFFFFU
#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
#define PAU_MEM_ADDR_V 0xFFFFFFFFU
#define PAU_MEM_ADDR_S 0
/** PAU_INT_ENA_REG register
* Read only register for error and done
*/
#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x18)
/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ENA (BIT(0))
#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
#define PAU_DONE_INT_ENA_V 0x00000001U
#define PAU_DONE_INT_ENA_S 0
/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ENA (BIT(1))
#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
#define PAU_ERROR_INT_ENA_V 0x00000001U
#define PAU_ERROR_INT_ENA_S 1
/** PAU_INT_RAW_REG register
* Read only register for error and done
*/
#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x1c)
/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_RAW (BIT(0))
#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
#define PAU_DONE_INT_RAW_V 0x00000001U
#define PAU_DONE_INT_RAW_S 0
/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_RAW (BIT(1))
#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
#define PAU_ERROR_INT_RAW_V 0x00000001U
#define PAU_ERROR_INT_RAW_S 1
/** PAU_INT_CLR_REG register
* Read only register for error and done
*/
#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x20)
/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_CLR (BIT(0))
#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
#define PAU_DONE_INT_CLR_V 0x00000001U
#define PAU_DONE_INT_CLR_S 0
/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_CLR (BIT(1))
#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
#define PAU_ERROR_INT_CLR_V 0x00000001U
#define PAU_ERROR_INT_CLR_S 1
/** PAU_INT_ST_REG register
* Read only register for error and done
*/
#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x24)
/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ST (BIT(0))
#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
#define PAU_DONE_INT_ST_V 0x00000001U
#define PAU_DONE_INT_ST_S 0
/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ST (BIT(1))
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
#define PAU_ERROR_INT_ST_V 0x00000001U
#define PAU_ERROR_INT_ST_S 1
/** PAU_REGDMA_GRANT_RESULT_REG register
* Read only register for error and done
*/
#define PAU_REGDMA_GRANT_RESULT_REG (DR_REG_PAU_BASE + 0x28)
/** PAU_GRANT_START_RESULT : RO; bitpos: [6:0]; default: 0;
* Grant start result
*/
#define PAU_GRANT_START_RESULT 0x0000007FU
#define PAU_GRANT_START_RESULT_M (PAU_GRANT_START_RESULT_V << PAU_GRANT_START_RESULT_S)
#define PAU_GRANT_START_RESULT_V 0x0000007FU
#define PAU_GRANT_START_RESULT_S 0
/** PAU_GRANT_DONE_RESULT : RO; bitpos: [13:7]; default: 0;
* Grant done result
*/
#define PAU_GRANT_DONE_RESULT 0x0000007FU
#define PAU_GRANT_DONE_RESULT_M (PAU_GRANT_DONE_RESULT_V << PAU_GRANT_DONE_RESULT_S)
#define PAU_GRANT_DONE_RESULT_V 0x0000007FU
#define PAU_GRANT_DONE_RESULT_S 7
/** PAU_GRANT_RESULT_CLR : WT; bitpos: [14]; default: 0;
* Grant result clear
*/
#define PAU_GRANT_RESULT_CLR (BIT(14))
#define PAU_GRANT_RESULT_CLR_M (PAU_GRANT_RESULT_CLR_V << PAU_GRANT_RESULT_CLR_S)
#define PAU_GRANT_RESULT_CLR_V 0x00000001U
#define PAU_GRANT_RESULT_CLR_S 14
/** PAU_DATE_REG register
* Date register.
*/
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
/** PAU_DATE : R/W; bitpos: [27:0]; default: 37765760;
* REGDMA date information/ REGDMA version information.
*/
#define PAU_DATE 0x0FFFFFFFU
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
#define PAU_DATE_V 0x0FFFFFFFU
#define PAU_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
* Peri backup control register
*/
typedef union {
struct {
uint32_t reserved_0:3;
/** start : WT; bitpos: [3]; default: 0;
* backup start signal
*/
uint32_t start:1;
/** to_mem : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem:1;
/** link_sel : R/W; bitpos: [8:5]; default: 0;
* Link select
*/
uint32_t link_sel:4;
/** sw_retry_en : R/W; bitpos: [9]; default: 0;
* sw_retry_en
*/
uint32_t sw_retry_en:1;
/** paudma_busy : RO; bitpos: [10]; default: 0;
* regdma_busy
*/
uint32_t paudma_busy:1;
/** fix_pri_en : R/W; bitpos: [11]; default: 0;
* fix_pri_en
*/
uint32_t fix_pri_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} pau_regdma_conf_reg_t;
/** Type of regdma_clk_conf register
* Clock control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pau_regdma_clk_conf_reg_t;
/** Type of regdma_etm_ctrl register
* ETM start ctrl reg
*/
typedef union {
struct {
/** etm_start_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
uint32_t etm_start_0:1;
/** etm_start_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
uint32_t etm_start_1:1;
/** etm_start_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
uint32_t etm_start_2:1;
/** etm_start_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
uint32_t etm_start_3:1;
/** etm_link_sel_0 : R/W; bitpos: [8:4]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_0:5;
/** etm_link_sel_1 : R/W; bitpos: [13:9]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_1:5;
/** etm_link_sel_2 : R/W; bitpos: [18:14]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_2:5;
/** etm_link_sel_3 : R/W; bitpos: [23:19]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_3:5;
/** etm_retry_en_0 : R/W; bitpos: [24]; default: 0;
* etm_retry
*/
uint32_t etm_retry_en_0:1;
/** etm_retry_en_1 : R/W; bitpos: [25]; default: 0;
* etm_retry
*/
uint32_t etm_retry_en_1:1;
/** etm_retry_en_2 : R/W; bitpos: [26]; default: 0;
* etm_retry
*/
uint32_t etm_retry_en_2:1;
/** etm_retry_en_3 : R/W; bitpos: [27]; default: 0;
* etm_retry
*/
uint32_t etm_retry_en_3:1;
uint32_t reserved_28:4;
};
uint32_t val;
} pau_regdma_etm_ctrl_reg_t;
/** Type of regdma_current_link_addr register
* current link addr
*/
typedef union {
struct {
/** current_link_addr : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
uint32_t current_link_addr:32;
};
uint32_t val;
} pau_regdma_current_link_addr_reg_t;
/** Type of regdma_peri_addr register
* Backup addr
*/
typedef union {
struct {
/** peri_addr : RO; bitpos: [31:0]; default: 0;
* peri addr reg
*/
uint32_t peri_addr:32;
};
uint32_t val;
} pau_regdma_peri_addr_reg_t;
/** Type of regdma_mem_addr register
* mem addr
*/
typedef union {
struct {
/** mem_addr : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
uint32_t mem_addr:32;
};
uint32_t val;
} pau_regdma_mem_addr_reg_t;
/** Type of int_ena register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_ena : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_ena:1;
/** error_int_ena : R/W; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_ena_reg_t;
/** Type of int_raw register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_raw:1;
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_raw_reg_t;
/** Type of int_clr register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_clr : WT; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_clr:1;
/** error_int_clr : WT; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_clr_reg_t;
/** Type of int_st register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_st : RO; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_st:1;
/** error_int_st : RO; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_st_reg_t;
/** Type of regdma_grant_result register
* Read only register for error and done
*/
typedef union {
struct {
/** grant_start_result : RO; bitpos: [6:0]; default: 0;
* Grant start result
*/
uint32_t grant_start_result:7;
/** grant_done_result : RO; bitpos: [13:7]; default: 0;
* Grant done result
*/
uint32_t grant_done_result:7;
/** grant_result_clr : WT; bitpos: [14]; default: 0;
* Grant result clear
*/
uint32_t grant_result_clr:1;
uint32_t reserved_15:17;
};
uint32_t val;
} pau_regdma_grant_result_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37765760;
* REGDMA date information/ REGDMA version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} pau_date_reg_t;
typedef struct {
volatile pau_regdma_conf_reg_t regdma_conf;
volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
volatile pau_regdma_peri_addr_reg_t regdma_peri_addr;
volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
volatile pau_int_ena_reg_t int_ena;
volatile pau_int_raw_reg_t int_raw;
volatile pau_int_clr_reg_t int_clr;
volatile pau_int_st_reg_t int_st;
volatile pau_regdma_grant_result_reg_t regdma_grant_result;
uint32_t reserved_02c[244];
volatile pau_date_reg_t date;
} pau_dev_t;
extern pau_dev_t PAU;
#ifndef __cplusplus
_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit n
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
* Configures the maximum threshold for the filter. Any pulses with width less than
* this will be ignored when the filter is enabled.
* Measurement unit: APB_CLK cycles.
*/
uint32_t filter_thres_un:10;
/** filter_en_un : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en_un:1;
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en_un:1;
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
* the high limit interrupt.
*/
uint32_t thr_h_lim_en_un:1;
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
* the low limit interrupt.
*/
uint32_t thr_l_lim_en_un:1;
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en_un:1;
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en_un:1;
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a negative edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch0_neg_mode_un:2;
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a positive edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch0_pos_mode_un:2;
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch0_hctrl_mode_un:2;
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch0_lctrl_mode_un:2;
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a negative edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch1_neg_mode_un:2;
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a positive edge.
* 1: Increment the counter
* 2: Decrement the counter
* 0, 3: No effect
*/
uint32_t ch1_pos_mode_un:2;
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch1_hctrl_mode_un:2;
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low.
* 0: No modification
* 1: Invert behavior (increase -> decrease, decrease -> increase)
* 2, 3: Inhibit counter modification
*/
uint32_t ch1_lctrl_mode_un:2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit n
*/
typedef union {
struct {
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thres0 value for unit n.
*/
uint32_t cnt_thres0_un:16;
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thres1 value for unit n.
*/
uint32_t cnt_thres1_un:16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit n
*/
typedef union {
struct {
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thr_h_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_h_lim_un:16;
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thr_l_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_l_lim_un:16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of u0_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 0.
*/
uint32_t cnt_h_step_u0:16;
/** cnt_l_step_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 0.
*/
uint32_t cnt_l_step_u0:16;
};
uint32_t val;
} pcnt_u0_conf3_reg_t;
/** Type of u1_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 1.
*/
uint32_t cnt_h_step_u1:16;
/** cnt_l_step_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 1.
*/
uint32_t cnt_l_step_u1:16;
};
uint32_t val;
} pcnt_u1_conf3_reg_t;
/** Type of u2_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 2.
*/
uint32_t cnt_h_step_u2:16;
/** cnt_l_step_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 2.
*/
uint32_t cnt_l_step_u2:16;
};
uint32_t val;
} pcnt_u2_conf3_reg_t;
/** Type of u3_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u3 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 3.
*/
uint32_t cnt_h_step_u3:16;
/** cnt_l_step_u3 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 3.
*/
uint32_t cnt_l_step_u3:16;
};
uint32_t val;
} pcnt_u3_conf3_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0:1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0:1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1:1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1:1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2:1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2:1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3:1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3:1;
/** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
* Configures this bit to enable unit 0's step comparator.
*/
uint32_t dalta_change_en_u0:1;
/** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
* Configures this bit to enable unit 1's step comparator.
*/
uint32_t dalta_change_en_u1:1;
/** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
* Configures this bit to enable unit 2's step comparator.
*/
uint32_t dalta_change_en_u2:1;
/** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
* Configures this bit to enable unit 3's step comparator.
*/
uint32_t dalta_change_en_u3:1;
uint32_t reserved_12:4;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit n
*/
typedef union {
struct {
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
* Represents the current pulse count value for unit n.
*/
uint32_t pulse_cnt_un:16;
uint32_t reserved_16:16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNITn status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
* Represents the pulse counter status of PCNT_Un corresponding to 0.
* 0: pulse counter decreases from positive to 0
* 1: pulse counter increases from negative to 0
* 2: pulse counter is negative
* 3: pulse counter is positive
*/
uint32_t cnt_thr_zero_mode_un:2;
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
* Represents the latched value of thres1 event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thres1 and thres1 event is valid
*/
uint32_t cnt_thr_thres1_lat_un:1;
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
* Represents the latched value of thres0 event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thres0 and thres0 event is valid
*/
uint32_t cnt_thr_thres0_lat_un:1;
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
* Represents the latched value of low limit event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thr_l_lim and low limit event is valid.
*/
uint32_t cnt_thr_l_lim_lat_un:1;
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
* Represents the latched value of high limit event of PCNT_Un when threshold event
* interrupt is valid.
* 0: others
* 1: the current pulse counter equals to thr_h_lim and high limit event is valid.
*/
uint32_t cnt_thr_h_lim_lat_un:1;
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
* Represents the latched value of zero threshold event of PCNT_Un when threshold
* event interrupt is valid.
* 0: others
* 1: the current pulse counter equals to 0 and zero threshold event is valid.
*/
uint32_t cnt_thr_zero_lat_un:1;
/** cnt_thr_h_step_lat_un : RO; bitpos: [7]; default: 0;
* Represents the latched value of step counter event of PCNT_Un when step counter
* event interrupt is valid. 1: the current pulse counter decrement equals to
* reg_cnt_step and step counter event is valid. 0: others
*/
uint32_t cnt_thr_h_step_lat_un:1;
/** cnt_thr_l_step_lat_un : RO; bitpos: [8]; default: 0;
* Represents the latched value of step counter event of PCNT_Un when step counter
* event interrupt is valid. 1: the current pulse counter increment equals to
* reg_cnt_step and step counter event is valid. 0: others
*/
uint32_t cnt_thr_l_step_lat_un:1;
uint32_t reserved_9:23;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw:1;
/** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw:1;
/** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw:1;
/** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st:1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st:1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st:1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena:1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena:1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena:1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr:1;
/** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr:1;
/** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr:1;
/** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 37778192;
* Version control register.
*/
uint32_t date:32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_u0_conf3_reg_t u0_conf3;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_u1_conf3_reg_t u1_conf3;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_u2_conf3_reg_t u2_conf3;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
volatile pcnt_u3_conf3_reg_t u3_conf3;
volatile pcnt_un_cnt_reg_t un_cnt[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_ctrl_reg_t ctrl;
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: FIFO R/W registers */
/** Type of chndata register
* The read and write data register for channel n by APB FIFO access.
*/
typedef union {
struct {
/** chndata : HRO; bitpos: [31:0]; default: 0;
* Read and write data for channel n via APB FIFO.
*/
uint32_t chndata:32;
};
uint32_t val;
} rmt_chndata_reg_t;
/** Group: Configuration registers */
/** Type of chnconf0 register
* Configuration register 0 for channel n
*/
typedef union {
struct {
/** tx_start_chn : WT; bitpos: [0]; default: 0;
* Configures whether to enable sending data in channel n.
* 0: No effect
* 1: Enable
*/
uint32_t tx_start_chn:1;
/** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
* Configures whether to reset RAM read address accessed by the transmitter for
* channel n.
* 0: No effect
* 1: Reset
*/
uint32_t mem_rd_rst_chn:1;
/** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
* Configures whether to reset RAM W/R address accessed by APB FIFO for channel n.
* 0: No effect
* 1: Reset
*/
uint32_t apb_mem_rst_chn:1;
/** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
* Configures whether to enable continuous TX mode for channel n.
* 0: No Effect
* 1: Enable
* In this mode, the transmitter starts transmission from the first data. If an
* end-marker is encountered, the transmitter starts transmitting data from the first
* data again. if no end-marker is encountered, the transmitter starts transmitting
* the first data again when the last data is transmitted.
*/
uint32_t tx_conti_mode_chn:1;
/** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
* Configures whether to enable wrap TX mode for channel n.
* 0: No effect
* 1: Enable
* In this mode, if the TX data size is larger than the channel's RAM block size, the
* transmitter continues transmitting the first data to the last data in loops.
*/
uint32_t mem_tx_wrap_en_chn:1;
/** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
* Configures the level of output signal for channel n when the transmitter is in idle
* state.
*/
uint32_t idle_out_lv_chn:1;
/** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
* Configures whether to enable the output for channel n in idle state.
* 0: No effect
* 1: Enable
*/
uint32_t idle_out_en_chn:1;
/** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
* Configures whether to stop the transmitter of channel n sending data out.
* 0: No effect
* 1: Stop
*/
uint32_t tx_stop_chn:1;
/** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
* Configures the divider for clock of channel n.
* Measurement unit: rmt_sclk
*/
uint32_t div_cnt_chn:8;
/** mem_size_chn : R/W; bitpos: [18:16]; default: 1;
* Configures the maximum number of memory blocks allocated to channel n.
*/
uint32_t mem_size_chn:3;
uint32_t reserved_19:1;
/** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
* Configures whether to add carrier modulation on the output signal only at
* data-sending state for channel n.
* 0: Add carrier modulation on the output signal at data-sending state and idle state
* for channel n
* 1: Add carrier modulation on the output signal only at data-sending state for
* channel n
* Only valid when RMT_CARRIER_EN_CHn is 1.
*/
uint32_t carrier_eff_en_chn:1;
/** carrier_en_chn : R/W; bitpos: [21]; default: 1;
* Configures whether to enable the carrier modulation on output signal for channel n.
* 0: Disable
* 1: Enable
*/
uint32_t carrier_en_chn:1;
/** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
* Configures the position of carrier wave for channel n.
* 0: Add carrier wave on low level
* 1: Add carrier wave on high level
*/
uint32_t carrier_out_lv_chn:1;
uint32_t reserved_23:1;
/** conf_update_chn : WT; bitpos: [24]; default: 0;
* Synchronization bit for channel n.
*/
uint32_t conf_update_chn:1;
uint32_t reserved_25:7;
};
uint32_t val;
} rmt_chnconf0_reg_t;
/** Type of chmconf0 register
* Configuration register 0 for channel m
*/
typedef union {
struct {
/** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
* Configures the clock divider of channel m.
* Measurement unit: rmt_sclk
*/
uint32_t div_cnt_chm:8;
/** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
* Configures RX threshold.
* When no edge is detected on the input signal for continuous clock cycles longer
* than this field value, the receiver stops receiving data.
* Measurement unit: clk_div
*/
uint32_t idle_thres_chm:15;
/** mem_size_chm : R/W; bitpos: [25:23]; default: 1;
* Configures the maximum number of memory blocks allocated to channel m.
*/
uint32_t mem_size_chm:3;
uint32_t reserved_26:2;
/** carrier_en_chm : R/W; bitpos: [28]; default: 1;
* Configures whether to enable carrier modulation on output signal for channel m.
* 0: Disable
* 1: Enable
*/
uint32_t carrier_en_chm:1;
/** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
* Configures the position of carrier wave for channel m.
* 0: Add carrier wave on low level
* 1: Add carrier wave on high level
*/
uint32_t carrier_out_lv_chm:1;
uint32_t reserved_30:2;
};
uint32_t val;
} rmt_chmconf0_reg_t;
/** Type of chmconf1 register
* Configuration register 1 for channel m
*/
typedef union {
struct {
/** rx_en_chm : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the receiver to start receiving data in channel m.
* 0: Disable
* 1: Enable
*/
uint32_t rx_en_chm:1;
/** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
* Configures whether to reset RAM write address accessed by the receiver for channel
* m.
* 0: No effect
* 1: Reset
*/
uint32_t mem_wr_rst_chm:1;
/** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
* Configures whether to reset RAM W/R address accessed by APB FIFO for channel m.
* 0: No effect
* 1: Reset
*/
uint32_t apb_mem_rst_chm:1;
/** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
* Configures the ownership of channel m's RAM block.
* 0: APB bus is using the RAM
* 1: Receiver is using the RAM
*/
uint32_t mem_owner_chm:1;
/** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
* Configures whether to enable the receiver's filter for channel m.
* 0: Disable
* 1: Enable
*/
uint32_t rx_filter_en_chm:1;
/** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
* Configures whether the receiver, when receiving data, ignores the input pulse when
* its width is shorter than this register value in units of rmt_sclk cycles.
* 0: No effect
* 1: Reset
*/
uint32_t rx_filter_thres_chm:8;
/** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
* Configures whether to enable wrap RX mode for channel m.
* 0: Disable
* 1: Enable
* In this mode, if the RX data size is larger than channel m's RAM block size, the
* receiver stores the RX data from the first address to the last address in loops.
*/
uint32_t mem_rx_wrap_en_chm:1;
uint32_t reserved_14:1;
/** conf_update_chm : WT; bitpos: [15]; default: 0;
* Synchronization bit for channel m.
*/
uint32_t conf_update_chm:1;
uint32_t reserved_16:16;
};
uint32_t val;
} rmt_chmconf1_reg_t;
/** Type of sys_conf register
* Configuration register for RMT APB
*/
typedef union {
struct {
/** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
* Configures the memory access mode.
* 0: Access memory by FIFO
* 1: Access memory directly
*/
uint32_t apb_fifo_mask:1;
uint32_t reserved_1:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Configures whether to enable signal of RMT register clock gate.
* 0: Power down the drive clock of registers
* 1: Power up the drive clock of registers
*/
uint32_t clk_en:1;
};
uint32_t val;
} rmt_sys_conf_reg_t;
/** Type of ref_cnt_rst register
* RMT clock divider reset register
*/
typedef union {
struct {
/** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
* This register is used to reset the clock divider of CHANNEL0.
*/
uint32_t ref_cnt_rst_ch0:1;
/** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
* This register is used to reset the clock divider of CHANNEL1.
*/
uint32_t ref_cnt_rst_ch1:1;
/** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
* This register is used to reset the clock divider of CHANNEL2.
*/
uint32_t ref_cnt_rst_ch2:1;
/** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
* This register is used to reset the clock divider of CHANNEL3.
*/
uint32_t ref_cnt_rst_ch3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} rmt_ref_cnt_rst_reg_t;
/** Group: Status registers */
/** Type of chnstatus register
* Channel n status register
*/
typedef union {
struct {
/** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0;
* Represents the memory address offset when transmitter of channel n is using the RAM.
*/
uint32_t mem_raddr_ex_chn:9;
/** state_chn : RO; bitpos: [11:9]; default: 0;
* Represents the FSM status of channel n.
*/
uint32_t state_chn:3;
/** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0;
* Represents the memory address offset when writes RAM over APB bus.
*/
uint32_t apb_mem_waddr_chn:9;
/** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0;
* Represents whether the offset address exceeds memory size when reading via APB bus.
* 0: Not exceed
* 1: Exceed
*/
uint32_t apb_mem_rd_err_chn:1;
/** mem_empty_chn : RO; bitpos: [22]; default: 0;
* Represents whether the TX data size exceeds the memory size and the wrap TX mode is
* disabled.
* 0: Not exceed
* 1: Exceed
*/
uint32_t mem_empty_chn:1;
/** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0;
* Represents whether the offset address exceeds memory size (overflows) when writes
* via APB bus.
* 0: Not exceed
* 1: Exceed
*/
uint32_t apb_mem_wr_err_chn:1;
/** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0;
* Represents the memory address offset when reading RAM over APB bus.
*/
uint32_t apb_mem_raddr_chn:8;
};
uint32_t val;
} rmt_chnstatus_reg_t;
/** Type of chmstatus register
* Channel m status register
*/
typedef union {
struct {
/** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0;
* Represents the memory address offset when receiver of channel m is using the RAM.
*/
uint32_t mem_waddr_ex_chm:9;
uint32_t reserved_9:3;
/** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0;
* Represents the memory address offset when reads RAM over APB bus.
*/
uint32_t apb_mem_raddr_chm:9;
uint32_t reserved_21:1;
/** state_chm : RO; bitpos: [24:22]; default: 0;
* Represents the FSM status of channel m.
*/
uint32_t state_chm:3;
/** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
* Represents whether the ownership of memory block is wrong.
* 0: The ownership of memory block is correct
* 1: The ownership of memory block is wrong
*/
uint32_t mem_owner_err_chm:1;
/** mem_full_chm : RO; bitpos: [26]; default: 0;
* Represents whether the receiver receives more data than the memory can fit.
* 0: The receiver does not receive more data than the memory can fit
* 1: The receiver receives more data than the memory can fit
*/
uint32_t mem_full_chm:1;
/** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
* Represents whether the offset address exceeds memory size (overflows) when reads
* RAM via APB bus.
* 0: Not exceed
* 1: Exceed
*/
uint32_t apb_mem_rd_err_chm:1;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_chmstatus_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmission done.
*/
uint32_t ch0_tx_end_int_raw:1;
/** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmission done.
*/
uint32_t ch1_tx_end_int_raw:1;
/** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when reception done.
*/
uint32_t ch2_rx_end_int_raw:1;
/** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when reception done.
*/
uint32_t ch3_rx_end_int_raw:1;
/** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch0_err_int_raw:1;
/** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch1_err_int_raw:1;
/** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch2_err_int_raw:1;
/** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch3_err_int_raw:1;
/** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch0_tx_thr_event_int_raw:1;
/** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch1_tx_thr_event_int_raw:1;
/** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch2_rx_thr_event_int_raw:1;
/** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch3_rx_thr_event_int_raw:1;
/** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch0_tx_loop_int_raw:1;
/** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch1_tx_loop_int_raw:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_raw_reg_t;
/** Type of int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_st:1;
/** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_st:1;
/** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_st:1;
/** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_st:1;
/** ch0_err_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_st:1;
/** ch1_err_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_st:1;
/** ch2_err_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_st:1;
/** ch3_err_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_st:1;
/** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
* The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_st:1;
/** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
* The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_st:1;
/** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0;
* The masked interrupt status bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_st:1;
/** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0;
* The masked interrupt status bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_st:1;
/** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
* The masked interrupt status bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_st:1;
/** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
* The masked interrupt status bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_st:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_ena:1;
/** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_ena:1;
/** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_ena:1;
/** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_ena:1;
/** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_ena:1;
/** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_ena:1;
/** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_ena:1;
/** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_ena:1;
/** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_ena:1;
/** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_ena:1;
/** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_ena:1;
/** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_ena:1;
/** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_ena:1;
/** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_ena:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear theCH0_TX_END_INT interrupt.
*/
uint32_t ch0_tx_end_int_clr:1;
/** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear theCH1_TX_END_INT interrupt.
*/
uint32_t ch1_tx_end_int_clr:1;
/** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear theCH2_RX_END_INT interrupt.
*/
uint32_t ch2_rx_end_int_clr:1;
/** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear theCH3_RX_END_INT interrupt.
*/
uint32_t ch3_rx_end_int_clr:1;
/** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch0_err_int_clr:1;
/** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch1_err_int_clr:1;
/** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch2_err_int_clr:1;
/** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch3_err_int_clr:1;
/** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch0_tx_thr_event_int_clr:1;
/** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch1_tx_thr_event_int_clr:1;
/** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch2_rx_thr_event_int_clr:1;
/** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch3_rx_thr_event_int_clr:1;
/** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear theCH0_TX_LOOP_INT interrupt.
*/
uint32_t ch0_tx_loop_int_clr:1;
/** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear theCH1_TX_LOOP_INT interrupt.
*/
uint32_t ch1_tx_loop_int_clr:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_clr_reg_t;
/** Group: Carrier wave duty cycle registers */
/** Type of chncarrier_duty register
* Duty cycle configuration register for channel n
*/
typedef union {
struct {
/** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
* Configures carrier wave's low level clock period for channel n.
* Measurement unit: rmt_sclk
*/
uint32_t carrier_low_chn:16;
/** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
* Configures carrier wave's high level clock period for channel n.
* Measurement unit: rmt_sclk
*/
uint32_t carrier_high_chn:16;
};
uint32_t val;
} rmt_chncarrier_duty_reg_t;
/** Type of chm_rx_carrier_rm register
* Carrier remove register for channel m
*/
typedef union {
struct {
/** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
* Configures the low level period in a carrier modulation mode for channel m.
* The low level period in a carrier modulation mode is (RMT_CARRIER_LOW_THRES_CHm +
* 1) for channel m.
* Measurement unit: clk_div
*/
uint32_t carrier_low_thres_chm:16;
/** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
* Configures the high level period in a carrier modulation mode for channel m.
* The high level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.
* Measurement unit: clk_div
*/
uint32_t carrier_high_thres_chm:16;
};
uint32_t val;
} rmt_chm_rx_carrier_rm_reg_t;
/** Group: Tx event configuration registers */
/** Type of chn_tx_lim register
* Configuration register for channel n TX event
*/
typedef union {
struct {
/** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
* Configures the maximum entries that channel n can send out.
*/
uint32_t tx_lim_chn:9;
/** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
* Configures the maximum loop count when Continuous TX mode is valid.
*/
uint32_t tx_loop_num_chn:10;
/** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
* Configures whether to enable loop count.
* 0: No effect
* 1: Enable
*/
uint32_t tx_loop_cnt_en_chn:1;
/** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
* Configures whether to reset the loop count when tx_conti_mode is valid.
* 0: No effect
* 1: Reset
*/
uint32_t loop_count_reset_chn:1;
/** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
* Configures whether to enable the loop send stop function after the loop counter
* counts to loop number for channel n.
* 0: No effect
* 1: Enable
*/
uint32_t loop_stop_en_chn:1;
uint32_t reserved_22:10;
};
uint32_t val;
} rmt_chn_tx_lim_reg_t;
/** Type of tx_sim register
* RMT TX synchronous register
*/
typedef union {
struct {
/** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
* Set this bit to enable CHANNEL0 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch0:1;
/** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
* Set this bit to enable CHANNEL1 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch1:1;
/** tx_sim_en : R/W; bitpos: [2]; default: 0;
* This register is used to enable multiple of channels to start sending data
* synchronously.
*/
uint32_t tx_sim_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} rmt_tx_sim_reg_t;
/** Group: Rx event configuration registers */
/** Type of chm_rx_lim register
* Configuration register for channel m RX event
*/
typedef union {
struct {
/** rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELm can receive.
*/
uint32_t rx_lim_chm:9;
uint32_t reserved_9:23;
};
uint32_t val;
} rmt_chm_rx_lim_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 34636307;
* This is the version register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_date_reg_t;
typedef struct {
volatile rmt_chndata_reg_t chndata[4];
volatile rmt_chnconf0_reg_t chnconf0[2];
volatile rmt_chmconf0_reg_t ch2conf0;
volatile rmt_chmconf1_reg_t ch2conf1;
volatile rmt_chmconf0_reg_t ch3conf0;
volatile rmt_chmconf1_reg_t ch3conf1;
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;
volatile rmt_int_st_reg_t int_st;
volatile rmt_int_ena_reg_t int_ena;
volatile rmt_int_clr_reg_t int_clr;
volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2];
volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2];
volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2];
volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2];
volatile rmt_sys_conf_reg_t sys_conf;
volatile rmt_tx_sim_reg_t tx_sim;
volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
uint32_t reserved_074[22];
volatile rmt_date_reg_t date;
} rmt_dev_t;
extern rmt_dev_t RMT;
#ifndef __cplusplus
_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SYSTIMER_CONF_REG register
* Configure system timer clock
*/
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enable generation of ETM events.
* 0: Disable
* 1: Enable
*/
#define SYSTIMER_ETM_EN (BIT(1))
#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
#define SYSTIMER_ETM_EN_V 0x00000001U
#define SYSTIMER_ETM_EN_S 1
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable COMP2.
* 0: Disable
* 1: Enable
*/
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET2_WORK_EN_S 22
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable COMP1. See details in SYSTIMER_TARGET2_WORK_EN.
*/
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET1_WORK_EN_S 23
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable COMP0. See details in SYSTIMER_TARGET2_WORK_EN.
*/
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U
#define SYSTIMER_TARGET0_WORK_EN_S 24
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
* Configures whether or not UNIT1 is stalled when CORE1 is stalled.
* 0: UNIT1 is not stalled.
* 1: UNIT1 is stalled.
*/
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
* Configures whether or not UNIT1 is stalled when CORE0 is stalled. See details in
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
*/
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
* Configures whether or not UNIT0 is stalled when CORE1 is stalled. See details in
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
*/
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
* Configures whether or not UNIT0 is stalled when CORE0 is stalled. See details in
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
*/
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable UNIT1.
* 0: Disable
* 1: Enable
*/
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
* Configures whether or not to enable UNIT0.
* 0: Disable
* 1: Enable
*/
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* Configures register clock gating.
* 0: Only enable needed clock for register read or write operations.
* 1: Register clock is always enabled for read and write operations.
*/
#define SYSTIMER_CLK_EN (BIT(31))
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
#define SYSTIMER_CLK_EN_V 0x00000001U
#define SYSTIMER_CLK_EN_S 31
/** SYSTIMER_UNIT0_OP_REG register
* Read UNIT0 value to registers
*/
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* Represents UNIT0 value is synchronized and valid.
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
* Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value
* to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO.
* 0: No effect
* 1: Update timer UNIT0
*/
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
/** SYSTIMER_UNIT1_OP_REG register
* Read UNIT1 value to registers
*/
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* Represents UNIT1 value is synchronized and valid.
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
* Configures whether or not to update timer UNIT1, i.e., reads the UNIT1 count value
* to SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO.
* 0: No effect
* 1: Update timer UNIT1
*/
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
/** SYSTIMER_UNIT0_LOAD_HI_REG register
* High 20 bits to be loaded to UNIT0
*/
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* Configures the value to be loaded to UNIT0, high 20 bits.
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
/** SYSTIMER_UNIT0_LOAD_LO_REG register
* Low 32 bits to be loaded to UNIT0
*/
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the value to be loaded to UNIT0, low 32 bits.
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
/** SYSTIMER_UNIT1_LOAD_HI_REG register
* High 20 bits to be loaded to UNIT1
*/
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* Configures the value to be loaded to UNIT1, high 20 bits.
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
/** SYSTIMER_UNIT1_LOAD_LO_REG register
* Low 32 bits to be loaded to UNIT1
*/
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the value to be loaded to UNIT1, low 32 bits.
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
/** SYSTIMER_TARGET0_HI_REG register
* Alarm value to be loaded to COMP0, high 20 bits
*/
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
* Configures the alarm value to be loaded to COMP0, high 20 bits.
*/
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET0_HI_S 0
/** SYSTIMER_TARGET0_LO_REG register
* Alarm value to be loaded to COMP0, low 32 bits
*/
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the alarm value to be loaded to COMP0, low 32 bits.
*/
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET0_LO_S 0
/** SYSTIMER_TARGET1_HI_REG register
* Alarm value to be loaded to COMP1, high 20 bits
*/
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
* Configures the alarm value to be loaded to COMP1, high 20 bits.
*/
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET1_HI_S 0
/** SYSTIMER_TARGET1_LO_REG register
* Alarm value to be loaded to COMP1, low 32 bits
*/
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the alarm value to be loaded to COMP1, low 32 bits.
*/
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET1_LO_S 0
/** SYSTIMER_TARGET2_HI_REG register
* Alarm value to be loaded to COMP2, high 20 bits
*/
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
* Configures the alarm value to be loaded to COMP2, high 20 bits.
*/
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_TARGET2_HI_S 0
/** SYSTIMER_TARGET2_LO_REG register
* Alarm value to be loaded to COMP2, low 32 bits
*/
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the alarm value to be loaded to COMP2, low 32 bits.
*/
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_TARGET2_LO_S 0
/** SYSTIMER_TARGET0_CONF_REG register
* Configure COMP0 alarm mode
*/
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
* Configures COMP0 alarm period.
*/
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET0_PERIOD_S 0
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Selects the two alarm modes for COMP0.
* 0: Target mode
* 1: Period mode
*/
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* Chooses the counter value for comparison with COMP0.
* 0: Use the count value from UNIT$0
* 1: Use the count value from UNIT$1
*/
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
/** SYSTIMER_TARGET1_CONF_REG register
* Configure COMP1 alarm mode
*/
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
* Configures COMP1 alarm period.
*/
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET1_PERIOD_S 0
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Selects the two alarm modes for COMP1. See details in SYSTIMER_TARGET0_PERIOD_MODE.
*/
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* Chooses the counter value for comparison with COMP1. See details in
* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
*/
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
/** SYSTIMER_TARGET2_CONF_REG register
* Configure COMP2 alarm mode
*/
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
* Configures COMP2 alarm period.
*/
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU
#define SYSTIMER_TARGET2_PERIOD_S 0
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Configures Configures the two alarm modes for COMP2. See details in
* SYSTIMER_TARGET0_PERIOD_MODE.
*/
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* Chooses the counter value for comparison with COMP2. See details in
* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
*/
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
/** SYSTIMER_UNIT0_VALUE_HI_REG register
* UNIT0 value, high 20 bits
*/
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* Represents UNIT0 read value, high 20 bits.
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
/** SYSTIMER_UNIT0_VALUE_LO_REG register
* UNIT0 value, low 32 bits
*/
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* Represents UNIT0 read value, low 32 bits.
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
/** SYSTIMER_UNIT1_VALUE_HI_REG register
* UNIT1 value, high 20 bits
*/
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* Represents UNIT1 read value, high 20 bits.
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
/** SYSTIMER_UNIT1_VALUE_LO_REG register
* UNIT1 value, low 32 bits
*/
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* Represents UNIT1 read value, low 32 bits.
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
/** SYSTIMER_COMP0_LOAD_REG register
* COMP0 synchronization register
*/
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
* Configures whether or not to enable COMP0 synchronization, i.e., reload the alarm
* value/period to COMP0.
* 0: No effect
* 1: Enable COMP0 synchronization
*/
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
/** SYSTIMER_COMP1_LOAD_REG register
* COMP1 synchronization register
*/
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
* Configures whether or not to enable COMP1 synchronization, i.e., reload the alarm
* value/period to COMP1.
* 0: No effect
* 1: Enable COMP1 synchronization
*/
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
/** SYSTIMER_COMP2_LOAD_REG register
* COMP2 synchronization register
*/
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
* Configures whether or not to enable COMP2 synchronization, i.e., reload the alarm
* value/period to COMP2.
* 0: No effect
* 1: Enable COMP2 synchronization
*/
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
/** SYSTIMER_UNIT0_LOAD_REG register
* UNIT0 synchronization register
*/
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
* Configures whether or not to reload the value of UNIT0, i.e., reloads the values of
* SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO to UNIT0.
* 0: No effect
* 1: Reload the value of UNIT0
*/
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
/** SYSTIMER_UNIT1_LOAD_REG register
* UNIT1 synchronization register
*/
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
* Configures whether or not to reload the value of UNIT1, i.e., reload the values of
* SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO to UNIT1.
* 0: No effect
* 1: Reload the value of UNIT1
*/
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
/** SYSTIMER_INT_ENA_REG register
* Interrupt enable register of system timer
*/
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable SYSTIMER_TARGET0_INT.
*/
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET0_INT_ENA_S 0
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable SYSTIMER_TARGET1_INT.
*/
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET1_INT_ENA_S 1
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable SYSTIMER_TARGET2_INT.
*/
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U
#define SYSTIMER_TARGET2_INT_ENA_S 2
/** SYSTIMER_INT_RAW_REG register
* Interrupt raw register of system timer
*/
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of SYSTIMER_TARGET0_INT.
*/
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET0_INT_RAW_S 0
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status of SYSTIMER_TARGET1_INT.
*/
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET1_INT_RAW_S 1
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status of SYSTIMER_TARGET2_INT.
*/
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U
#define SYSTIMER_TARGET2_INT_RAW_S 2
/** SYSTIMER_INT_CLR_REG register
* Interrupt clear register of system timer
*/
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear SYSTIMER_TARGET0_INT.
*/
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET0_INT_CLR_S 0
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear SYSTIMER_TARGET1_INT.
*/
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET1_INT_CLR_S 1
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear SYSTIMER_TARGET2_INT.
*/
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U
#define SYSTIMER_TARGET2_INT_CLR_S 2
/** SYSTIMER_INT_ST_REG register
* Interrupt status register of system timer
*/
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
* The interrupt status of SYSTIMER_TARGET0_INT.
*/
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET0_INT_ST_S 0
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
* The interrupt status of SYSTIMER_TARGET1_INT.
*/
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET1_INT_ST_S 1
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
* The interrupt status of SYSTIMER_TARGET2_INT.
*/
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U
#define SYSTIMER_TARGET2_INT_ST_S 2
/** SYSTIMER_REAL_TARGET0_LO_REG register
* Actual target value of COMP0, low 32 bits
*/
#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
* Represents the actual target value of COMP0, low 32 bits.
*/
#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET0_LO_RO_S 0
/** SYSTIMER_REAL_TARGET0_HI_REG register
* Actual target value of COMP0, high 20 bits
*/
#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
* Represents the actual target value of COMP0, high 20 bits.
*/
#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET0_HI_RO_S 0
/** SYSTIMER_REAL_TARGET1_LO_REG register
* Actual target value of COMP1, low 32 bits
*/
#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
* Represents the actual target value of COMP1, low 32 bits.
*/
#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET1_LO_RO_S 0
/** SYSTIMER_REAL_TARGET1_HI_REG register
* Actual target value of COMP1, high 20 bits
*/
#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
* Represents the actual target value of COMP1, high 20 bits.
*/
#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET1_HI_RO_S 0
/** SYSTIMER_REAL_TARGET2_LO_REG register
* Actual target value of COMP2, low 32 bits
*/
#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
* Represents the actual target value of COMP2, low 32 bits.
*/
#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU
#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU
#define SYSTIMER_TARGET2_LO_RO_S 0
/** SYSTIMER_REAL_TARGET2_HI_REG register
* Actual target value of COMP2, high 20 bits
*/
#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
* Represents the actual target value of COMP2, high 20 bits.
*/
#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU
#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU
#define SYSTIMER_TARGET2_HI_RO_S 0
/** SYSTIMER_DATE_REG register
* Version control register
*/
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 36774432;
* Version control register.
*/
#define SYSTIMER_DATE 0xFFFFFFFFU
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
#define SYSTIMER_DATE_V 0xFFFFFFFFU
#define SYSTIMER_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
* Configure system timer clock
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** etm_en : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enable generation of ETM events.
* 0: Disable
* 1: Enable
*/
uint32_t etm_en:1;
uint32_t reserved_2:20;
/** target2_work_en : R/W; bitpos: [22]; default: 0;
* Configures whether or not to enable COMP2.
* 0: Disable
* 1: Enable
*/
uint32_t target2_work_en:1;
/** target1_work_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable COMP1. See details in SYSTIMER_TARGET2_WORK_EN.
*/
uint32_t target1_work_en:1;
/** target0_work_en : R/W; bitpos: [24]; default: 0;
* Configures whether or not to enable COMP0. See details in SYSTIMER_TARGET2_WORK_EN.
*/
uint32_t target0_work_en:1;
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
* Configures whether or not UNIT1 is stalled when CORE1 is stalled.
* 0: UNIT1 is not stalled.
* 1: UNIT1 is stalled.
*/
uint32_t timer_unit1_core1_stall_en:1;
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
* Configures whether or not UNIT1 is stalled when CORE0 is stalled. See details in
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
*/
uint32_t timer_unit1_core0_stall_en:1;
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
* Configures whether or not UNIT0 is stalled when CORE1 is stalled. See details in
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
*/
uint32_t timer_unit0_core1_stall_en:1;
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
* Configures whether or not UNIT0 is stalled when CORE0 is stalled. See details in
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
*/
uint32_t timer_unit0_core0_stall_en:1;
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable UNIT1.
* 0: Disable
* 1: Enable
*/
uint32_t timer_unit1_work_en:1;
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
* Configures whether or not to enable UNIT0.
* 0: Disable
* 1: Enable
*/
uint32_t timer_unit0_work_en:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Configures register clock gating.
* 0: Only enable needed clock for register read or write operations.
* 1: Register clock is always enabled for read and write operations.
*/
uint32_t clk_en:1;
};
uint32_t val;
} systimer_conf_reg_t;
/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */
/** Type of unit_op register
* Read unit value to registers
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* Represents UNIT value is synchronized and valid.
*/
uint32_t timer_unit_value_valid:1;
/** timer_unit_update : WT; bitpos: [30]; default: 0;
* Configures whether or not to update timer UNIT, i.e., reads the UNIT count value
* to SYSTIMER_TIMER_UNIT_VALUE_HI and SYSTIMER_TIMER_UNIT_VALUE_LO.
* 0: No effect
* 1: Update timer UNIT
*/
uint32_t timer_unit_update:1;
uint32_t reserved_31:1;
};
uint32_t val;
} systimer_unit_op_reg_t;
/** Type of unit_load_hi register
* High 20 bits to be loaded to UNIT
*/
typedef union {
struct {
/** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
* Configures the value to be loaded to UNIT, high 20 bits.
*/
uint32_t timer_unit_load_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit_load_hi_reg_t;
/** Type of unit_load_lo register
* Low 32 bits to be loaded to UNIT
*/
typedef union {
struct {
/** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
* Configures the value to be loaded to UNIT, low 32 bits.
*/
uint32_t timer_unit_load_lo:32;
};
uint32_t val;
} systimer_unit_load_lo_reg_t;
/** Type of unit_value_hi register
* UNIT value, high 20 bits
*/
typedef union {
struct {
/** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
* Represents UNIT read value, high 20 bits.
*/
uint32_t timer_unit_value_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_unit_value_hi_reg_t;
/** Type of unit_value_lo register
* UNIT value, low 32 bits
*/
typedef union {
struct {
/** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
* Represents UNIT read value, low 32 bits.
*/
uint32_t timer_unit_value_lo:32;
};
uint32_t val;
} systimer_unit_value_lo_reg_t;
/** Type of unit_load register
* UNIT synchronization register
*/
typedef union {
struct {
/** timer_unit_load : WT; bitpos: [0]; default: 0;
* Configures whether or not to reload the value of UNIT, i.e., reloads the values of
* SYSTIMER_TIMER_UNIT_VALUE_HI and SYSTIMER_TIMER_UNIT_VALUE_LO to UNIT.
* 0: No effect
* 1: Reload the value of UNIT
*/
uint32_t timer_unit_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_unit_load_reg_t;
/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */
/** Type of target0_hi register
* Alarm value to be loaded to COMP0, high 20 bits
*/
typedef union {
struct {
/** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
* Configures the alarm value to be loaded to COMP0, high 20 bits.
*/
uint32_t timer_target_hi:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_target_hi_reg_t;
/** Type of target0_lo register
* Alarm value to be loaded to COMP0, low 32 bits
*/
typedef union {
struct {
/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
* Configures the alarm value to be loaded to COMP0, low 32 bits.
*/
uint32_t timer_target_lo:32;
};
uint32_t val;
} systimer_target_lo_reg_t;
/** Type of target0_conf register
* Configure COMP0 alarm mode
*/
typedef union {
struct {
/** target_period : R/W; bitpos: [25:0]; default: 0;
* Configures COMP0 alarm period.
*/
uint32_t target_period:26;
uint32_t reserved_26:4;
/** target_period_mode : R/W; bitpos: [30]; default: 0;
* Selects the two alarm modes for COMP0.
* 0: Target mode
* 1: Period mode
*/
uint32_t target_period_mode:1;
/** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* Chooses the counter value for comparison with COMP0.
* 0: Use the count value from UNIT$0
* 1: Use the count value from UNIT$1
*/
uint32_t target_timer_unit_sel:1;
};
uint32_t val;
} systimer_target_conf_reg_t;
/** Type of comp0_load register
* COMP0 synchronization register
*/
typedef union {
struct {
/** timer_comp0_load : WT; bitpos: [0]; default: 0;
* Configures whether or not to enable COMP0 synchronization, i.e., reload the alarm
* value/period to COMP0.
* 0: No effect
* 1: Enable COMP0 synchronization
*/
uint32_t timer_comp0_load:1;
uint32_t reserved_1:31;
};
uint32_t val;
} systimer_comp_load_reg_t;
/** Group: SYSTEM TIMER INTERRUPT REGISTER */
/** Type of int_ena register
* Interrupt enable register of system timer
*/
typedef union {
struct {
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable SYSTIMER_TARGET0_INT.
*/
uint32_t target0_int_ena:1;
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable SYSTIMER_TARGET1_INT.
*/
uint32_t target1_int_ena:1;
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable SYSTIMER_TARGET2_INT.
*/
uint32_t target2_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_ena_reg_t;
/** Type of int_raw register
* Interrupt raw register of system timer
*/
typedef union {
struct {
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of SYSTIMER_TARGET0_INT.
*/
uint32_t target0_int_raw:1;
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status of SYSTIMER_TARGET1_INT.
*/
uint32_t target1_int_raw:1;
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status of SYSTIMER_TARGET2_INT.
*/
uint32_t target2_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_raw_reg_t;
/** Type of int_clr register
* Interrupt clear register of system timer
*/
typedef union {
struct {
/** target0_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear SYSTIMER_TARGET0_INT.
*/
uint32_t target0_int_clr:1;
/** target1_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear SYSTIMER_TARGET1_INT.
*/
uint32_t target1_int_clr:1;
/** target2_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear SYSTIMER_TARGET2_INT.
*/
uint32_t target2_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_clr_reg_t;
/** Type of int_st register
* Interrupt status register of system timer
*/
typedef union {
struct {
/** target0_int_st : RO; bitpos: [0]; default: 0;
* The interrupt status of SYSTIMER_TARGET0_INT.
*/
uint32_t target0_int_st:1;
/** target1_int_st : RO; bitpos: [1]; default: 0;
* The interrupt status of SYSTIMER_TARGET1_INT.
*/
uint32_t target1_int_st:1;
/** target2_int_st : RO; bitpos: [2]; default: 0;
* The interrupt status of SYSTIMER_TARGET2_INT.
*/
uint32_t target2_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} systimer_int_st_reg_t;
/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */
/** Type of real_target0_lo register
* Actual target value of COMP0, low 32 bits
*/
typedef union {
struct {
/** target0_lo_ro : RO; bitpos: [31:0]; default: 0;
* Represents the actual target value of COMP0, low 32 bits.
*/
uint32_t target0_lo_ro:32;
};
uint32_t val;
} systimer_real_target_lo_reg_t;
/** Type of real_target0_hi register
* Actual target value of COMP0, high 20 bits
*/
typedef union {
struct {
/** target0_hi_ro : RO; bitpos: [19:0]; default: 0;
* Represents the actual target value of COMP0, high 20 bits.
*/
uint32_t target0_hi_ro:20;
uint32_t reserved_20:12;
};
uint32_t val;
} systimer_real_target_hi_reg_t;
/** Group: VERSION REGISTER */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36774432;
* Version control register.
*/
uint32_t date:32;
};
uint32_t val;
} systimer_date_reg_t;
typedef struct {
volatile systimer_unit_load_hi_reg_t hi;
volatile systimer_unit_load_lo_reg_t lo;
} systimer_unit_load_val_reg_t;
typedef struct {
volatile systimer_target_hi_reg_t hi;
volatile systimer_target_lo_reg_t lo;
} systimer_target_val_reg_t;
typedef struct {
volatile systimer_unit_value_hi_reg_t hi;
volatile systimer_unit_value_lo_reg_t lo;
} systimer_unit_value_reg_t;
typedef struct {
volatile systimer_real_target_hi_reg_t hi;
volatile systimer_real_target_lo_reg_t lo;
} systimer_real_target_reg_t;
typedef struct systimer_dev_t{
volatile systimer_conf_reg_t conf;
volatile systimer_unit_op_reg_t unit_op[2];
volatile systimer_unit_load_val_reg_t unit_load_val[2];
volatile systimer_target_val_reg_t target_val[3];
volatile systimer_target_conf_reg_t target_conf[3];
volatile systimer_unit_value_reg_t unit_val[2];
volatile systimer_comp_load_reg_t comp_load[3];
volatile systimer_unit_load_reg_t unit_load[2];
volatile systimer_int_ena_reg_t int_ena;
volatile systimer_int_raw_reg_t int_raw;
volatile systimer_int_clr_reg_t int_clr;
volatile systimer_int_st_reg_t int_st;
volatile systimer_real_target_reg_t real_target[3];
uint32_t reserved_08c[28];
volatile systimer_date_reg_t date;
} systimer_dev_t;
extern systimer_dev_t SYSTIMER;
#ifndef __cplusplus
_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* Configures whether or not to enable the timer 0 alarm function. This bit will be
* automatically cleared once an alarm occurs.
* 0: Disable
* 1: Enable
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* Configures whether or not to reset the timer 0 's clock divider counter.
* 0: No effect
* 1: Reset
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Represents the timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* Configures whether or not to enable the timer 0 auto-reload function at the time of
* alarm.
* 0: No effect
* 1: Enable
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* Configures the counting direction of the timer 0 time-base counter.
* 0: Decrement
* 1: Increment
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* Configures whether or not to enable the timer 0 time-base counter.
* 0: Disable
* 1: Enable
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
#define TIMG_T0_EN_V 0x00000001U
#define TIMG_T0_EN_S 31
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* Represents the low 32 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
#define TIMG_T0_LO_V 0xFFFFFFFFU
#define TIMG_T0_LO_S 0
/** TIMG_T0HI_REG register
* Timer 0 current value, high 22 bits
*/
#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* Represents the high 22 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
#define TIMG_T0_HI_V 0x003FFFFFU
#define TIMG_T0_HI_S 0
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG
*/
#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* Configures to latch the counter value.
* 0: Latch
* 1: Latch
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
#define TIMG_T0_UPDATE_V 0x00000001U
#define TIMG_T0_UPDATE_S 31
/** TIMG_T0ALARMLO_REG register
* Timer 0 alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_S 0
/** TIMG_T0ALARMHI_REG register
* Timer 0 alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
#define TIMG_T0_ALARM_HI_S 0
/** TIMG_T0LOADLO_REG register
* Timer 0 reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Configures low 32 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_S 0
/** TIMG_T0LOADHI_REG register
* Timer 0 reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* Configures high 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
#define TIMG_T0_LOAD_HI_S 0
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG
*/
#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
* Write any value to trigger a timer 0 time-base counter reload.
*
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* Configures whether to enable flash boot protection.
* 0: Disable
* 1: Enable
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* Configures the system reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* Configures the CPU reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* Configures to update the WDT configuration registers.
* 0: No effect
* 1: Update
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Configures the timeout action of stage 0. Valid only when write protection is
* disabled.
* 0: No effect
* 1: Interrupt
* 2: Reset CPU
* 3: Reset system
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* Configures whether or not to enable the MWDT. Valid only when write protection is
* disabled.
* 0: Disable
* 1: Enable
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
#define TIMG_WDT_EN_V 0x00000001U
#define TIMG_WDT_EN_S 31
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* Configures whether to reset WDT 's clock divider counter.
* 0: No effect
* 1: Reset
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* Configures MWDT clock prescaler value. Valid only when write protection is
* disabled.
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_S 16
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Configures the stage 0 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_S 0
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Configures the stage 1 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_S 0
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 2 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_S 0
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 3 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_S 0
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. Valid only when write protection is disabled.
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
#define TIMG_WDT_FEED_S 0
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* Configures a different value than its reset value to enable write protection.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
#define TIMG_WDT_WKEY_S 0
/** TIMG_RTCCALICFG_REG register
* RTC frequency calculation configuration register 0
*/
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* Configures the frequency calculation mode.
* 0: one-shot frequency calculation
* 1: periodic frequency calculation
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* Represents whether one-shot frequency calculation is done.
* 0: Not done
* 1: Done
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Configures the time to calculate RTC slow clock's frequency.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Configures whether to enable one-shot frequency calculation.
* 0: Disable
* 1: Enable
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
#define TIMG_RTC_CALI_START_V 0x00000001U
#define TIMG_RTC_CALI_START_S 31
/** TIMG_RTCCALICFG1_REG register
* RTC frequency calculation configuration register 1
*/
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* Represents whether periodic frequency calculation is done.
* 0: Not done
* 1: Done
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* Represents the value countered by XTAL_CLK when one-shot or periodic frequency
* calculation is done. It is used to calculate RTC slow clock's frequency.
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_S 7
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(2))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
#define TIMG_WDT_INT_ENA_V 0x00000001U
#define TIMG_WDT_INT_ENA_S 2
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit of the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit of the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(2))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
#define TIMG_WDT_INT_RAW_V 0x00000001U
#define TIMG_WDT_INT_RAW_S 2
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit of the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit of the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(2))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
#define TIMG_WDT_INT_ST_V 0x00000001U
#define TIMG_WDT_INT_ST_S 2
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the TIMG_T0_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(2))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
#define TIMG_WDT_INT_CLR_V 0x00000001U
#define TIMG_WDT_INT_CLR_S 2
/** TIMG_RTCCALICFG2_REG register
* RTC frequency calculation configuration register 2
*/
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* Represents whether RTC frequency calculation is timeout.
* 0: No timeout
* 1: Timeout
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Configures the cycles that reset frequency calculation timeout.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Configures the threshold value for the RTC frequency calculation timer. If the
* timer's value exceeds this threshold, a timeout is triggered.
* Measurement unit: XTAL_CLK
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
* Version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_S 0
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
* Configures whether to enable timer's ETM task and event.
* 0: Disable
* 1: Enable
*/
#define TIMG_ETM_EN (BIT(28))
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
#define TIMG_ETM_EN_V 0x00000001U
#define TIMG_ETM_EN_S 28
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Configures whether to enable gate clock signal for registers.
* 0: Force clock on for registers
* 1: Support clock only when registers are read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
#define TIMG_CLK_EN_V 0x00000001U
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer 0 configuration register
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* Configures whether or not to enable the timer 0 alarm function. This bit will be
* automatically cleared once an alarm occurs.
* 0: Disable
* 1: Enable
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* Configures whether or not to reset the timer 0 's clock divider counter.
* 0: No effect
* 1: Reset
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Represents the timer 0 clock (T0_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* Configures whether or not to enable the timer 0 auto-reload function at the time of
* alarm.
* 0: No effect
* 1: Enable
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* Configures the counting direction of the timer 0 time-base counter.
* 0: Decrement
* 1: Increment
*/
uint32_t tx_increase:1;
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
* Configures whether or not to enable the timer 0 time-base counter.
* 0: Disable
* 1: Enable
*/
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer 0 current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* Represents the low 32 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer 0 current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* Represents the high 22 bits of the time-base counter of timer 0. Valid only after
* writing to TIMG_T0UPDATE_REG.
* Measurement unit: T0_clk
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* Configures to latch the counter value.
* 0: Latch
* 1: Latch
*/
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer 0 alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer 0 alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid
* only when TIMG_T0_ALARM_EN is 1.
* Measurement unit: T0_clk
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer 0 reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Configures low 32 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer 0 reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* Configures high 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
* Measurement unit: T0_clk
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
* Write any value to trigger a timer 0 time-base counter reload.
*
*/
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
/** Group: WDT Control and configuration registers */
/** Type of wdtconfig0 register
* Watchdog timer configuration register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* Configures whether to mask the CPU reset generated by MWDT. Valid only when write
* protection is disabled.
* 0: Mask
* 1: Unmask
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* Configures whether to enable flash boot protection.
* 0: Disable
* 1: Enable
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* Configures the system reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* Configures the CPU reset signal length. Valid only when write protection is
* disabled.
* Measurement unit: mwdt_clk
* \begin{multicols}{2}
* 0: 8
* 1: 16
* 2: 24
* 3: 32
* 4: 40
* 5: 64
* 6: 128
* 7: 256
* \end{multicols}
*/
uint32_t wdt_cpu_reset_length:3;
uint32_t reserved_21:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* Configures to update the WDT configuration registers.
* 0: No effect
* 1: Update
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only
* when write protection is disabled.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Configures the timeout action of stage 0. Valid only when write protection is
* disabled.
* 0: No effect
* 1: Interrupt
* 2: Reset CPU
* 3: Reset system
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* Configures whether or not to enable the MWDT. Valid only when write protection is
* disabled.
* 0: Disable
* 1: Enable
*/
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
/** Type of wdtconfig1 register
* Watchdog timer prescaler register
*/
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* Configures whether to reset WDT 's clock divider counter.
* 0: No effect
* 1: Reset
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* Configures MWDT clock prescaler value. Valid only when write protection is
* disabled.
* MWDT clock period = MWDT's clock source period * TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
/** Type of wdtconfig2 register
* Watchdog timer stage 0 timeout value
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Configures the stage 0 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
/** Type of wdtconfig3 register
* Watchdog timer stage 1 timeout value
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Configures the stage 1 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
/** Type of wdtconfig4 register
* Watchdog timer stage 2 timeout value
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 2 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
/** Type of wdtconfig5 register
* Watchdog timer stage 3 timeout value
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Configures the stage 3 timeout value. Valid only when write protection is disabled.
* Measurement unit: mwdt_clk
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
/** Type of wdtfeed register
* Write to feed the watchdog timer
*/
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. Valid only when write protection is disabled.
*/
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
/** Type of wdtwprotect register
* Watchdog write protect register
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* Configures a different value than its reset value to enable write protection.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC frequency calculation configuration register 0
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* Configures the frequency calculation mode.
* 0: one-shot frequency calculation
* 1: periodic frequency calculation
*/
uint32_t rtc_cali_start_cycling:1;
uint32_t reserved_13:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* Represents whether one-shot frequency calculation is done.
* 0: Not done
* 1: Done
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Configures the time to calculate RTC slow clock's frequency.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Configures whether to enable one-shot frequency calculation.
* 0: Disable
* 1: Enable
*/
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC frequency calculation configuration register 1
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* Represents whether periodic frequency calculation is done.
* 0: Not done
* 1: Done
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* Represents the value countered by XTAL_CLK when one-shot or periodic frequency
* calculation is done. It is used to calculate RTC slow clock's frequency.
*/
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* RTC frequency calculation configuration register 2
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* Represents whether RTC frequency calculation is timeout.
* 0: No timeout
* 1: Timeout
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Configures the cycles that reset frequency calculation timeout.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Configures the threshold value for the RTC frequency calculation timer. If the
* timer's value exceeds this threshold, a timeout is triggered.
* Measurement unit: XTAL_CLK
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena_timers register
* Interrupt enable bits
*/
typedef union {
struct {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_ena:1;
uint32_t reserved_1:1;
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
/** Type of int_raw_timers register
* Raw interrupt status
*/
typedef union {
struct {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit of the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_raw:1;
uint32_t reserved_1:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit of the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
/** Type of int_st_timers register
* Masked interrupt status
*/
typedef union {
struct {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit of the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_st:1;
uint32_t reserved_1:1;
/** wdt_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit of the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_st_timers_reg_t;
/** Type of int_clr_timers register
* Interrupt clear bits
*/
typedef union {
struct {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_clr:1;
uint32_t reserved_1:1;
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
/** Group: Version register */
/** Type of ntimers_date register
* Timer version control register
*/
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
* Version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
/** Group: Clock configuration registers */
/** Type of regclk register
* Timer group clock gate register
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** etm_en : R/W; bitpos: [28]; default: 1;
* Configures whether to enable timer's ETM task and event.
* 0: Disable
* 1: Enable
*/
uint32_t etm_en:1;
uint32_t reserved_29:2;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Configures whether to enable gate clock signal for registers.
* 0: Force clock on for registers
* 1: Support clock only when registers are read or written to by software.
*/
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t config;
volatile timg_txlo_reg_t lo;
volatile timg_txhi_reg_t hi;
volatile timg_txupdate_reg_t update;
volatile timg_txalarmlo_reg_t alarmlo;
volatile timg_txalarmhi_reg_t alarmhi;
volatile timg_txloadlo_reg_t loadlo;
volatile timg_txloadhi_reg_t loadhi;
volatile timg_txload_reg_t load;
} timg_hwtimer_reg_t;
typedef struct {
volatile timg_hwtimer_reg_t hw_timer[1];
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;
volatile timg_wdtconfig3_reg_t wdtconfig3;
volatile timg_wdtconfig4_reg_t wdtconfig4;
volatile timg_wdtconfig5_reg_t wdtconfig5;
volatile timg_wdtfeed_reg_t wdtfeed;
volatile timg_wdtwprotect_reg_t wdtwprotect;
volatile timg_rtccalicfg_reg_t rtccalicfg;
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
volatile timg_int_ena_timers_reg_t int_ena_timers;
volatile timg_int_raw_timers_reg_t int_raw_timers;
volatile timg_int_st_timers_reg_t int_st_timers;
volatile timg_int_clr_timers_reg_t int_clr_timers;
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
uint32_t reserved_084[29];
volatile timg_ntimers_date_reg_t ntimers_date;
volatile timg_regclk_reg_t regclk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#ifndef __cplusplus
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TOUCH_INT_RAW_REG register
* need_des
*/
#define TOUCH_INT_RAW_REG (DR_REG_TOUCH_BASE + 0x0)
/** TOUCH_SCAN_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* need_des
*/
#define TOUCH_SCAN_DONE_INT_RAW (BIT(0))
#define TOUCH_SCAN_DONE_INT_RAW_M (TOUCH_SCAN_DONE_INT_RAW_V << TOUCH_SCAN_DONE_INT_RAW_S)
#define TOUCH_SCAN_DONE_INT_RAW_V 0x00000001U
#define TOUCH_SCAN_DONE_INT_RAW_S 0
/** TOUCH_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define TOUCH_DONE_INT_RAW (BIT(1))
#define TOUCH_DONE_INT_RAW_M (TOUCH_DONE_INT_RAW_V << TOUCH_DONE_INT_RAW_S)
#define TOUCH_DONE_INT_RAW_V 0x00000001U
#define TOUCH_DONE_INT_RAW_S 1
/** TOUCH_ACTIVE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* need_des
*/
#define TOUCH_ACTIVE_INT_RAW (BIT(2))
#define TOUCH_ACTIVE_INT_RAW_M (TOUCH_ACTIVE_INT_RAW_V << TOUCH_ACTIVE_INT_RAW_S)
#define TOUCH_ACTIVE_INT_RAW_V 0x00000001U
#define TOUCH_ACTIVE_INT_RAW_S 2
/** TOUCH_INACTIVE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* need_des
*/
#define TOUCH_INACTIVE_INT_RAW (BIT(3))
#define TOUCH_INACTIVE_INT_RAW_M (TOUCH_INACTIVE_INT_RAW_V << TOUCH_INACTIVE_INT_RAW_S)
#define TOUCH_INACTIVE_INT_RAW_V 0x00000001U
#define TOUCH_INACTIVE_INT_RAW_S 3
/** TOUCH_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* need_des
*/
#define TOUCH_TIMEOUT_INT_RAW (BIT(4))
#define TOUCH_TIMEOUT_INT_RAW_M (TOUCH_TIMEOUT_INT_RAW_V << TOUCH_TIMEOUT_INT_RAW_S)
#define TOUCH_TIMEOUT_INT_RAW_V 0x00000001U
#define TOUCH_TIMEOUT_INT_RAW_S 4
/** TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* need_des
*/
#define TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(5))
#define TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << TOUCH_APPROACH_LOOP_DONE_INT_RAW_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 5
/** TOUCH_INT_ST_REG register
* need_des
*/
#define TOUCH_INT_ST_REG (DR_REG_TOUCH_BASE + 0x4)
/** TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* need_des
*/
#define TOUCH_SCAN_DONE_INT_ST (BIT(0))
#define TOUCH_SCAN_DONE_INT_ST_M (TOUCH_SCAN_DONE_INT_ST_V << TOUCH_SCAN_DONE_INT_ST_S)
#define TOUCH_SCAN_DONE_INT_ST_V 0x00000001U
#define TOUCH_SCAN_DONE_INT_ST_S 0
/** TOUCH_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* need_des
*/
#define TOUCH_DONE_INT_ST (BIT(1))
#define TOUCH_DONE_INT_ST_M (TOUCH_DONE_INT_ST_V << TOUCH_DONE_INT_ST_S)
#define TOUCH_DONE_INT_ST_V 0x00000001U
#define TOUCH_DONE_INT_ST_S 1
/** TOUCH_ACTIVE_INT_ST : RO; bitpos: [2]; default: 0;
* need_des
*/
#define TOUCH_ACTIVE_INT_ST (BIT(2))
#define TOUCH_ACTIVE_INT_ST_M (TOUCH_ACTIVE_INT_ST_V << TOUCH_ACTIVE_INT_ST_S)
#define TOUCH_ACTIVE_INT_ST_V 0x00000001U
#define TOUCH_ACTIVE_INT_ST_S 2
/** TOUCH_INACTIVE_INT_ST : RO; bitpos: [3]; default: 0;
* need_des
*/
#define TOUCH_INACTIVE_INT_ST (BIT(3))
#define TOUCH_INACTIVE_INT_ST_M (TOUCH_INACTIVE_INT_ST_V << TOUCH_INACTIVE_INT_ST_S)
#define TOUCH_INACTIVE_INT_ST_V 0x00000001U
#define TOUCH_INACTIVE_INT_ST_S 3
/** TOUCH_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
* need_des
*/
#define TOUCH_TIMEOUT_INT_ST (BIT(4))
#define TOUCH_TIMEOUT_INT_ST_M (TOUCH_TIMEOUT_INT_ST_V << TOUCH_TIMEOUT_INT_ST_S)
#define TOUCH_TIMEOUT_INT_ST_V 0x00000001U
#define TOUCH_TIMEOUT_INT_ST_S 4
/** TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [5]; default: 0;
* need_des
*/
#define TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(5))
#define TOUCH_APPROACH_LOOP_DONE_INT_ST_M (TOUCH_APPROACH_LOOP_DONE_INT_ST_V << TOUCH_APPROACH_LOOP_DONE_INT_ST_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_ST_S 5
/** TOUCH_INT_ENA_REG register
* need_des
*/
#define TOUCH_INT_ENA_REG (DR_REG_TOUCH_BASE + 0x8)
/** TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define TOUCH_SCAN_DONE_INT_ENA (BIT(0))
#define TOUCH_SCAN_DONE_INT_ENA_M (TOUCH_SCAN_DONE_INT_ENA_V << TOUCH_SCAN_DONE_INT_ENA_S)
#define TOUCH_SCAN_DONE_INT_ENA_V 0x00000001U
#define TOUCH_SCAN_DONE_INT_ENA_S 0
/** TOUCH_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define TOUCH_DONE_INT_ENA (BIT(1))
#define TOUCH_DONE_INT_ENA_M (TOUCH_DONE_INT_ENA_V << TOUCH_DONE_INT_ENA_S)
#define TOUCH_DONE_INT_ENA_V 0x00000001U
#define TOUCH_DONE_INT_ENA_S 1
/** TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define TOUCH_ACTIVE_INT_ENA (BIT(2))
#define TOUCH_ACTIVE_INT_ENA_M (TOUCH_ACTIVE_INT_ENA_V << TOUCH_ACTIVE_INT_ENA_S)
#define TOUCH_ACTIVE_INT_ENA_V 0x00000001U
#define TOUCH_ACTIVE_INT_ENA_S 2
/** TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [3]; default: 0;
* need_des
*/
#define TOUCH_INACTIVE_INT_ENA (BIT(3))
#define TOUCH_INACTIVE_INT_ENA_M (TOUCH_INACTIVE_INT_ENA_V << TOUCH_INACTIVE_INT_ENA_S)
#define TOUCH_INACTIVE_INT_ENA_V 0x00000001U
#define TOUCH_INACTIVE_INT_ENA_S 3
/** TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
* need_des
*/
#define TOUCH_TIMEOUT_INT_ENA (BIT(4))
#define TOUCH_TIMEOUT_INT_ENA_M (TOUCH_TIMEOUT_INT_ENA_V << TOUCH_TIMEOUT_INT_ENA_S)
#define TOUCH_TIMEOUT_INT_ENA_V 0x00000001U
#define TOUCH_TIMEOUT_INT_ENA_S 4
/** TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
* need_des
*/
#define TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(5))
#define TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << TOUCH_APPROACH_LOOP_DONE_INT_ENA_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 5
/** TOUCH_INT_CLR_REG register
* need_des
*/
#define TOUCH_INT_CLR_REG (DR_REG_TOUCH_BASE + 0xc)
/** TOUCH_SCAN_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define TOUCH_SCAN_DONE_INT_CLR (BIT(0))
#define TOUCH_SCAN_DONE_INT_CLR_M (TOUCH_SCAN_DONE_INT_CLR_V << TOUCH_SCAN_DONE_INT_CLR_S)
#define TOUCH_SCAN_DONE_INT_CLR_V 0x00000001U
#define TOUCH_SCAN_DONE_INT_CLR_S 0
/** TOUCH_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* need_des
*/
#define TOUCH_DONE_INT_CLR (BIT(1))
#define TOUCH_DONE_INT_CLR_M (TOUCH_DONE_INT_CLR_V << TOUCH_DONE_INT_CLR_S)
#define TOUCH_DONE_INT_CLR_V 0x00000001U
#define TOUCH_DONE_INT_CLR_S 1
/** TOUCH_ACTIVE_INT_CLR : WT; bitpos: [2]; default: 0;
* need_des
*/
#define TOUCH_ACTIVE_INT_CLR (BIT(2))
#define TOUCH_ACTIVE_INT_CLR_M (TOUCH_ACTIVE_INT_CLR_V << TOUCH_ACTIVE_INT_CLR_S)
#define TOUCH_ACTIVE_INT_CLR_V 0x00000001U
#define TOUCH_ACTIVE_INT_CLR_S 2
/** TOUCH_INACTIVE_INT_CLR : WT; bitpos: [3]; default: 0;
* need_des
*/
#define TOUCH_INACTIVE_INT_CLR (BIT(3))
#define TOUCH_INACTIVE_INT_CLR_M (TOUCH_INACTIVE_INT_CLR_V << TOUCH_INACTIVE_INT_CLR_S)
#define TOUCH_INACTIVE_INT_CLR_V 0x00000001U
#define TOUCH_INACTIVE_INT_CLR_S 3
/** TOUCH_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
* need_des
*/
#define TOUCH_TIMEOUT_INT_CLR (BIT(4))
#define TOUCH_TIMEOUT_INT_CLR_M (TOUCH_TIMEOUT_INT_CLR_V << TOUCH_TIMEOUT_INT_CLR_S)
#define TOUCH_TIMEOUT_INT_CLR_V 0x00000001U
#define TOUCH_TIMEOUT_INT_CLR_S 4
/** TOUCH_APPROACH_LOOP_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
* need_des
*/
#define TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(5))
#define TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << TOUCH_APPROACH_LOOP_DONE_INT_CLR_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 5
/** TOUCH_CHN_STATUS_REG register
* need_des
*/
#define TOUCH_CHN_STATUS_REG (DR_REG_TOUCH_BASE + 0x10)
/** TOUCH_PAD_ACTIVE : RO; bitpos: [14:0]; default: 0;
* need_des
*/
#define TOUCH_PAD_ACTIVE 0x00007FFFU
#define TOUCH_PAD_ACTIVE_M (TOUCH_PAD_ACTIVE_V << TOUCH_PAD_ACTIVE_S)
#define TOUCH_PAD_ACTIVE_V 0x00007FFFU
#define TOUCH_PAD_ACTIVE_S 0
/** TOUCH_MEAS_DONE : RO; bitpos: [15]; default: 0;
* need_des
*/
#define TOUCH_MEAS_DONE (BIT(15))
#define TOUCH_MEAS_DONE_M (TOUCH_MEAS_DONE_V << TOUCH_MEAS_DONE_S)
#define TOUCH_MEAS_DONE_V 0x00000001U
#define TOUCH_MEAS_DONE_S 15
/** TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 15;
* need_des
*/
#define TOUCH_SCAN_CURR 0x0000000FU
#define TOUCH_SCAN_CURR_M (TOUCH_SCAN_CURR_V << TOUCH_SCAN_CURR_S)
#define TOUCH_SCAN_CURR_V 0x0000000FU
#define TOUCH_SCAN_CURR_S 16
/** TOUCH_STATUS_0_REG register
* need_des
*/
#define TOUCH_STATUS_0_REG (DR_REG_TOUCH_BASE + 0x14)
/** TOUCH_PAD0_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD0_DATA 0x0000FFFFU
#define TOUCH_PAD0_DATA_M (TOUCH_PAD0_DATA_V << TOUCH_PAD0_DATA_S)
#define TOUCH_PAD0_DATA_V 0x0000FFFFU
#define TOUCH_PAD0_DATA_S 0
/** TOUCH_PAD0_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD0_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD0_DEBOUNCE_CNT_M (TOUCH_PAD0_DEBOUNCE_CNT_V << TOUCH_PAD0_DEBOUNCE_CNT_S)
#define TOUCH_PAD0_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD0_DEBOUNCE_CNT_S 16
/** TOUCH_PAD0_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD0_NN_CNT 0x0000000FU
#define TOUCH_PAD0_NN_CNT_M (TOUCH_PAD0_NN_CNT_V << TOUCH_PAD0_NN_CNT_S)
#define TOUCH_PAD0_NN_CNT_V 0x0000000FU
#define TOUCH_PAD0_NN_CNT_S 19
/** TOUCH_STATUS_1_REG register
* need_des
*/
#define TOUCH_STATUS_1_REG (DR_REG_TOUCH_BASE + 0x18)
/** TOUCH_PAD1_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD1_DATA 0x0000FFFFU
#define TOUCH_PAD1_DATA_M (TOUCH_PAD1_DATA_V << TOUCH_PAD1_DATA_S)
#define TOUCH_PAD1_DATA_V 0x0000FFFFU
#define TOUCH_PAD1_DATA_S 0
/** TOUCH_PAD1_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD1_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD1_DEBOUNCE_CNT_M (TOUCH_PAD1_DEBOUNCE_CNT_V << TOUCH_PAD1_DEBOUNCE_CNT_S)
#define TOUCH_PAD1_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD1_DEBOUNCE_CNT_S 16
/** TOUCH_PAD1_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD1_NN_CNT 0x0000000FU
#define TOUCH_PAD1_NN_CNT_M (TOUCH_PAD1_NN_CNT_V << TOUCH_PAD1_NN_CNT_S)
#define TOUCH_PAD1_NN_CNT_V 0x0000000FU
#define TOUCH_PAD1_NN_CNT_S 19
/** TOUCH_STATUS_2_REG register
* need_des
*/
#define TOUCH_STATUS_2_REG (DR_REG_TOUCH_BASE + 0x1c)
/** TOUCH_PAD2_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD2_DATA 0x0000FFFFU
#define TOUCH_PAD2_DATA_M (TOUCH_PAD2_DATA_V << TOUCH_PAD2_DATA_S)
#define TOUCH_PAD2_DATA_V 0x0000FFFFU
#define TOUCH_PAD2_DATA_S 0
/** TOUCH_PAD2_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD2_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD2_DEBOUNCE_CNT_M (TOUCH_PAD2_DEBOUNCE_CNT_V << TOUCH_PAD2_DEBOUNCE_CNT_S)
#define TOUCH_PAD2_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD2_DEBOUNCE_CNT_S 16
/** TOUCH_PAD2_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD2_NN_CNT 0x0000000FU
#define TOUCH_PAD2_NN_CNT_M (TOUCH_PAD2_NN_CNT_V << TOUCH_PAD2_NN_CNT_S)
#define TOUCH_PAD2_NN_CNT_V 0x0000000FU
#define TOUCH_PAD2_NN_CNT_S 19
/** TOUCH_STATUS_3_REG register
* need_des
*/
#define TOUCH_STATUS_3_REG (DR_REG_TOUCH_BASE + 0x20)
/** TOUCH_PAD3_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD3_DATA 0x0000FFFFU
#define TOUCH_PAD3_DATA_M (TOUCH_PAD3_DATA_V << TOUCH_PAD3_DATA_S)
#define TOUCH_PAD3_DATA_V 0x0000FFFFU
#define TOUCH_PAD3_DATA_S 0
/** TOUCH_PAD3_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD3_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD3_DEBOUNCE_CNT_M (TOUCH_PAD3_DEBOUNCE_CNT_V << TOUCH_PAD3_DEBOUNCE_CNT_S)
#define TOUCH_PAD3_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD3_DEBOUNCE_CNT_S 16
/** TOUCH_PAD3_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD3_NN_CNT 0x0000000FU
#define TOUCH_PAD3_NN_CNT_M (TOUCH_PAD3_NN_CNT_V << TOUCH_PAD3_NN_CNT_S)
#define TOUCH_PAD3_NN_CNT_V 0x0000000FU
#define TOUCH_PAD3_NN_CNT_S 19
/** TOUCH_STATUS_4_REG register
* need_des
*/
#define TOUCH_STATUS_4_REG (DR_REG_TOUCH_BASE + 0x24)
/** TOUCH_PAD4_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD4_DATA 0x0000FFFFU
#define TOUCH_PAD4_DATA_M (TOUCH_PAD4_DATA_V << TOUCH_PAD4_DATA_S)
#define TOUCH_PAD4_DATA_V 0x0000FFFFU
#define TOUCH_PAD4_DATA_S 0
/** TOUCH_PAD4_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD4_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD4_DEBOUNCE_CNT_M (TOUCH_PAD4_DEBOUNCE_CNT_V << TOUCH_PAD4_DEBOUNCE_CNT_S)
#define TOUCH_PAD4_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD4_DEBOUNCE_CNT_S 16
/** TOUCH_PAD4_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD4_NN_CNT 0x0000000FU
#define TOUCH_PAD4_NN_CNT_M (TOUCH_PAD4_NN_CNT_V << TOUCH_PAD4_NN_CNT_S)
#define TOUCH_PAD4_NN_CNT_V 0x0000000FU
#define TOUCH_PAD4_NN_CNT_S 19
/** TOUCH_STATUS_5_REG register
* need_des
*/
#define TOUCH_STATUS_5_REG (DR_REG_TOUCH_BASE + 0x28)
/** TOUCH_PAD5_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD5_DATA 0x0000FFFFU
#define TOUCH_PAD5_DATA_M (TOUCH_PAD5_DATA_V << TOUCH_PAD5_DATA_S)
#define TOUCH_PAD5_DATA_V 0x0000FFFFU
#define TOUCH_PAD5_DATA_S 0
/** TOUCH_PAD5_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD5_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD5_DEBOUNCE_CNT_M (TOUCH_PAD5_DEBOUNCE_CNT_V << TOUCH_PAD5_DEBOUNCE_CNT_S)
#define TOUCH_PAD5_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD5_DEBOUNCE_CNT_S 16
/** TOUCH_PAD5_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD5_NN_CNT 0x0000000FU
#define TOUCH_PAD5_NN_CNT_M (TOUCH_PAD5_NN_CNT_V << TOUCH_PAD5_NN_CNT_S)
#define TOUCH_PAD5_NN_CNT_V 0x0000000FU
#define TOUCH_PAD5_NN_CNT_S 19
/** TOUCH_STATUS_6_REG register
* need_des
*/
#define TOUCH_STATUS_6_REG (DR_REG_TOUCH_BASE + 0x2c)
/** TOUCH_PAD6_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD6_DATA 0x0000FFFFU
#define TOUCH_PAD6_DATA_M (TOUCH_PAD6_DATA_V << TOUCH_PAD6_DATA_S)
#define TOUCH_PAD6_DATA_V 0x0000FFFFU
#define TOUCH_PAD6_DATA_S 0
/** TOUCH_PAD6_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD6_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD6_DEBOUNCE_CNT_M (TOUCH_PAD6_DEBOUNCE_CNT_V << TOUCH_PAD6_DEBOUNCE_CNT_S)
#define TOUCH_PAD6_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD6_DEBOUNCE_CNT_S 16
/** TOUCH_PAD6_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD6_NN_CNT 0x0000000FU
#define TOUCH_PAD6_NN_CNT_M (TOUCH_PAD6_NN_CNT_V << TOUCH_PAD6_NN_CNT_S)
#define TOUCH_PAD6_NN_CNT_V 0x0000000FU
#define TOUCH_PAD6_NN_CNT_S 19
/** TOUCH_STATUS_7_REG register
* need_des
*/
#define TOUCH_STATUS_7_REG (DR_REG_TOUCH_BASE + 0x30)
/** TOUCH_PAD7_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD7_DATA 0x0000FFFFU
#define TOUCH_PAD7_DATA_M (TOUCH_PAD7_DATA_V << TOUCH_PAD7_DATA_S)
#define TOUCH_PAD7_DATA_V 0x0000FFFFU
#define TOUCH_PAD7_DATA_S 0
/** TOUCH_PAD7_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD7_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD7_DEBOUNCE_CNT_M (TOUCH_PAD7_DEBOUNCE_CNT_V << TOUCH_PAD7_DEBOUNCE_CNT_S)
#define TOUCH_PAD7_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD7_DEBOUNCE_CNT_S 16
/** TOUCH_PAD7_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD7_NN_CNT 0x0000000FU
#define TOUCH_PAD7_NN_CNT_M (TOUCH_PAD7_NN_CNT_V << TOUCH_PAD7_NN_CNT_S)
#define TOUCH_PAD7_NN_CNT_V 0x0000000FU
#define TOUCH_PAD7_NN_CNT_S 19
/** TOUCH_STATUS_8_REG register
* need_des
*/
#define TOUCH_STATUS_8_REG (DR_REG_TOUCH_BASE + 0x34)
/** TOUCH_PAD8_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD8_DATA 0x0000FFFFU
#define TOUCH_PAD8_DATA_M (TOUCH_PAD8_DATA_V << TOUCH_PAD8_DATA_S)
#define TOUCH_PAD8_DATA_V 0x0000FFFFU
#define TOUCH_PAD8_DATA_S 0
/** TOUCH_PAD8_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD8_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD8_DEBOUNCE_CNT_M (TOUCH_PAD8_DEBOUNCE_CNT_V << TOUCH_PAD8_DEBOUNCE_CNT_S)
#define TOUCH_PAD8_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD8_DEBOUNCE_CNT_S 16
/** TOUCH_PAD8_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD8_NN_CNT 0x0000000FU
#define TOUCH_PAD8_NN_CNT_M (TOUCH_PAD8_NN_CNT_V << TOUCH_PAD8_NN_CNT_S)
#define TOUCH_PAD8_NN_CNT_V 0x0000000FU
#define TOUCH_PAD8_NN_CNT_S 19
/** TOUCH_STATUS_9_REG register
* need_des
*/
#define TOUCH_STATUS_9_REG (DR_REG_TOUCH_BASE + 0x38)
/** TOUCH_PAD9_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD9_DATA 0x0000FFFFU
#define TOUCH_PAD9_DATA_M (TOUCH_PAD9_DATA_V << TOUCH_PAD9_DATA_S)
#define TOUCH_PAD9_DATA_V 0x0000FFFFU
#define TOUCH_PAD9_DATA_S 0
/** TOUCH_PAD9_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD9_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD9_DEBOUNCE_CNT_M (TOUCH_PAD9_DEBOUNCE_CNT_V << TOUCH_PAD9_DEBOUNCE_CNT_S)
#define TOUCH_PAD9_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD9_DEBOUNCE_CNT_S 16
/** TOUCH_PAD9_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD9_NN_CNT 0x0000000FU
#define TOUCH_PAD9_NN_CNT_M (TOUCH_PAD9_NN_CNT_V << TOUCH_PAD9_NN_CNT_S)
#define TOUCH_PAD9_NN_CNT_V 0x0000000FU
#define TOUCH_PAD9_NN_CNT_S 19
/** TOUCH_STATUS_10_REG register
* need_des
*/
#define TOUCH_STATUS_10_REG (DR_REG_TOUCH_BASE + 0x3c)
/** TOUCH_PAD10_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD10_DATA 0x0000FFFFU
#define TOUCH_PAD10_DATA_M (TOUCH_PAD10_DATA_V << TOUCH_PAD10_DATA_S)
#define TOUCH_PAD10_DATA_V 0x0000FFFFU
#define TOUCH_PAD10_DATA_S 0
/** TOUCH_PAD10_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD10_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD10_DEBOUNCE_CNT_M (TOUCH_PAD10_DEBOUNCE_CNT_V << TOUCH_PAD10_DEBOUNCE_CNT_S)
#define TOUCH_PAD10_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD10_DEBOUNCE_CNT_S 16
/** TOUCH_PAD10_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD10_NN_CNT 0x0000000FU
#define TOUCH_PAD10_NN_CNT_M (TOUCH_PAD10_NN_CNT_V << TOUCH_PAD10_NN_CNT_S)
#define TOUCH_PAD10_NN_CNT_V 0x0000000FU
#define TOUCH_PAD10_NN_CNT_S 19
/** TOUCH_STATUS_11_REG register
* need_des
*/
#define TOUCH_STATUS_11_REG (DR_REG_TOUCH_BASE + 0x40)
/** TOUCH_PAD11_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD11_DATA 0x0000FFFFU
#define TOUCH_PAD11_DATA_M (TOUCH_PAD11_DATA_V << TOUCH_PAD11_DATA_S)
#define TOUCH_PAD11_DATA_V 0x0000FFFFU
#define TOUCH_PAD11_DATA_S 0
/** TOUCH_PAD11_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD11_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD11_DEBOUNCE_CNT_M (TOUCH_PAD11_DEBOUNCE_CNT_V << TOUCH_PAD11_DEBOUNCE_CNT_S)
#define TOUCH_PAD11_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD11_DEBOUNCE_CNT_S 16
/** TOUCH_PAD11_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD11_NN_CNT 0x0000000FU
#define TOUCH_PAD11_NN_CNT_M (TOUCH_PAD11_NN_CNT_V << TOUCH_PAD11_NN_CNT_S)
#define TOUCH_PAD11_NN_CNT_V 0x0000000FU
#define TOUCH_PAD11_NN_CNT_S 19
/** TOUCH_STATUS_12_REG register
* need_des
*/
#define TOUCH_STATUS_12_REG (DR_REG_TOUCH_BASE + 0x44)
/** TOUCH_PAD12_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD12_DATA 0x0000FFFFU
#define TOUCH_PAD12_DATA_M (TOUCH_PAD12_DATA_V << TOUCH_PAD12_DATA_S)
#define TOUCH_PAD12_DATA_V 0x0000FFFFU
#define TOUCH_PAD12_DATA_S 0
/** TOUCH_PAD12_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD12_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD12_DEBOUNCE_CNT_M (TOUCH_PAD12_DEBOUNCE_CNT_V << TOUCH_PAD12_DEBOUNCE_CNT_S)
#define TOUCH_PAD12_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD12_DEBOUNCE_CNT_S 16
/** TOUCH_PAD12_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD12_NN_CNT 0x0000000FU
#define TOUCH_PAD12_NN_CNT_M (TOUCH_PAD12_NN_CNT_V << TOUCH_PAD12_NN_CNT_S)
#define TOUCH_PAD12_NN_CNT_V 0x0000000FU
#define TOUCH_PAD12_NN_CNT_S 19
/** TOUCH_STATUS_13_REG register
* need_des
*/
#define TOUCH_STATUS_13_REG (DR_REG_TOUCH_BASE + 0x48)
/** TOUCH_PAD13_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD13_DATA 0x0000FFFFU
#define TOUCH_PAD13_DATA_M (TOUCH_PAD13_DATA_V << TOUCH_PAD13_DATA_S)
#define TOUCH_PAD13_DATA_V 0x0000FFFFU
#define TOUCH_PAD13_DATA_S 0
/** TOUCH_PAD13_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD13_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD13_DEBOUNCE_CNT_M (TOUCH_PAD13_DEBOUNCE_CNT_V << TOUCH_PAD13_DEBOUNCE_CNT_S)
#define TOUCH_PAD13_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD13_DEBOUNCE_CNT_S 16
/** TOUCH_PAD13_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD13_NN_CNT 0x0000000FU
#define TOUCH_PAD13_NN_CNT_M (TOUCH_PAD13_NN_CNT_V << TOUCH_PAD13_NN_CNT_S)
#define TOUCH_PAD13_NN_CNT_V 0x0000000FU
#define TOUCH_PAD13_NN_CNT_S 19
/** TOUCH_STATUS_14_REG register
* need_des
*/
#define TOUCH_STATUS_14_REG (DR_REG_TOUCH_BASE + 0x4c)
/** TOUCH_PAD14_DATA : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define TOUCH_PAD14_DATA 0x0000FFFFU
#define TOUCH_PAD14_DATA_M (TOUCH_PAD14_DATA_V << TOUCH_PAD14_DATA_S)
#define TOUCH_PAD14_DATA_V 0x0000FFFFU
#define TOUCH_PAD14_DATA_S 0
/** TOUCH_PAD14_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_PAD14_DEBOUNCE_CNT 0x00000007U
#define TOUCH_PAD14_DEBOUNCE_CNT_M (TOUCH_PAD14_DEBOUNCE_CNT_V << TOUCH_PAD14_DEBOUNCE_CNT_S)
#define TOUCH_PAD14_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_PAD14_DEBOUNCE_CNT_S 16
/** TOUCH_PAD14_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_PAD14_NN_CNT 0x0000000FU
#define TOUCH_PAD14_NN_CNT_M (TOUCH_PAD14_NN_CNT_V << TOUCH_PAD14_NN_CNT_S)
#define TOUCH_PAD14_NN_CNT_V 0x0000000FU
#define TOUCH_PAD14_NN_CNT_S 19
/** TOUCH_STATUS_15_REG register
* need_des
*/
#define TOUCH_STATUS_15_REG (DR_REG_TOUCH_BASE + 0x50)
/** TOUCH_SLP_DATA : RO; bitpos: [15:0]; default: 65535;
* need_des
*/
#define TOUCH_SLP_DATA 0x0000FFFFU
#define TOUCH_SLP_DATA_M (TOUCH_SLP_DATA_V << TOUCH_SLP_DATA_S)
#define TOUCH_SLP_DATA_V 0x0000FFFFU
#define TOUCH_SLP_DATA_S 0
/** TOUCH_SLP_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
* need_des
*/
#define TOUCH_SLP_DEBOUNCE_CNT 0x00000007U
#define TOUCH_SLP_DEBOUNCE_CNT_M (TOUCH_SLP_DEBOUNCE_CNT_V << TOUCH_SLP_DEBOUNCE_CNT_S)
#define TOUCH_SLP_DEBOUNCE_CNT_V 0x00000007U
#define TOUCH_SLP_DEBOUNCE_CNT_S 16
/** TOUCH_SLP_NN_CNT : RO; bitpos: [22:19]; default: 0;
* need_des
*/
#define TOUCH_SLP_NN_CNT 0x0000000FU
#define TOUCH_SLP_NN_CNT_M (TOUCH_SLP_NN_CNT_V << TOUCH_SLP_NN_CNT_S)
#define TOUCH_SLP_NN_CNT_V 0x0000000FU
#define TOUCH_SLP_NN_CNT_S 19
/** TOUCH_STATUS_16_REG register
* need_des
*/
#define TOUCH_STATUS_16_REG (DR_REG_TOUCH_BASE + 0x54)
/** TOUCH_APPROACH_PAD2_CNT : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define TOUCH_APPROACH_PAD2_CNT 0x000000FFU
#define TOUCH_APPROACH_PAD2_CNT_M (TOUCH_APPROACH_PAD2_CNT_V << TOUCH_APPROACH_PAD2_CNT_S)
#define TOUCH_APPROACH_PAD2_CNT_V 0x000000FFU
#define TOUCH_APPROACH_PAD2_CNT_S 0
/** TOUCH_APPROACH_PAD1_CNT : RO; bitpos: [15:8]; default: 0;
* need_des
*/
#define TOUCH_APPROACH_PAD1_CNT 0x000000FFU
#define TOUCH_APPROACH_PAD1_CNT_M (TOUCH_APPROACH_PAD1_CNT_V << TOUCH_APPROACH_PAD1_CNT_S)
#define TOUCH_APPROACH_PAD1_CNT_V 0x000000FFU
#define TOUCH_APPROACH_PAD1_CNT_S 8
/** TOUCH_APPROACH_PAD0_CNT : RO; bitpos: [23:16]; default: 0;
* need_des
*/
#define TOUCH_APPROACH_PAD0_CNT 0x000000FFU
#define TOUCH_APPROACH_PAD0_CNT_M (TOUCH_APPROACH_PAD0_CNT_V << TOUCH_APPROACH_PAD0_CNT_S)
#define TOUCH_APPROACH_PAD0_CNT_V 0x000000FFU
#define TOUCH_APPROACH_PAD0_CNT_S 16
/** TOUCH_SLP_APPROACH_CNT : RO; bitpos: [31:24]; default: 0;
* need_des
*/
#define TOUCH_SLP_APPROACH_CNT 0x000000FFU
#define TOUCH_SLP_APPROACH_CNT_M (TOUCH_SLP_APPROACH_CNT_V << TOUCH_SLP_APPROACH_CNT_S)
#define TOUCH_SLP_APPROACH_CNT_V 0x000000FFU
#define TOUCH_SLP_APPROACH_CNT_S 24
/** TOUCH_STATUS_17_REG register
* need_des
*/
#define TOUCH_STATUS_17_REG (DR_REG_TOUCH_BASE + 0x58)
/** TOUCH_DCAP_LPF : RO; bitpos: [6:0]; default: 0;
* Reserved
*/
#define TOUCH_DCAP_LPF 0x0000007FU
#define TOUCH_DCAP_LPF_M (TOUCH_DCAP_LPF_V << TOUCH_DCAP_LPF_S)
#define TOUCH_DCAP_LPF_V 0x0000007FU
#define TOUCH_DCAP_LPF_S 0
/** TOUCH_DRES_LPF : RO; bitpos: [8:7]; default: 0;
* need_des
*/
#define TOUCH_DRES_LPF 0x00000003U
#define TOUCH_DRES_LPF_M (TOUCH_DRES_LPF_V << TOUCH_DRES_LPF_S)
#define TOUCH_DRES_LPF_V 0x00000003U
#define TOUCH_DRES_LPF_S 7
/** TOUCH_DRV_LS : RO; bitpos: [12:9]; default: 0;
* need_des
*/
#define TOUCH_DRV_LS 0x0000000FU
#define TOUCH_DRV_LS_M (TOUCH_DRV_LS_V << TOUCH_DRV_LS_S)
#define TOUCH_DRV_LS_V 0x0000000FU
#define TOUCH_DRV_LS_S 9
/** TOUCH_DRV_HS : RO; bitpos: [17:13]; default: 0;
* need_des
*/
#define TOUCH_DRV_HS 0x0000001FU
#define TOUCH_DRV_HS_M (TOUCH_DRV_HS_V << TOUCH_DRV_HS_S)
#define TOUCH_DRV_HS_V 0x0000001FU
#define TOUCH_DRV_HS_S 13
/** TOUCH_DBIAS : RO; bitpos: [22:18]; default: 0;
* need_des
*/
#define TOUCH_DBIAS 0x0000001FU
#define TOUCH_DBIAS_M (TOUCH_DBIAS_V << TOUCH_DBIAS_S)
#define TOUCH_DBIAS_V 0x0000001FU
#define TOUCH_DBIAS_S 18
/** TOUCH_FREQ_SCAN_CNT : RO; bitpos: [24:23]; default: 0;
* need_des
*/
#define TOUCH_FREQ_SCAN_CNT 0x00000003U
#define TOUCH_FREQ_SCAN_CNT_M (TOUCH_FREQ_SCAN_CNT_V << TOUCH_FREQ_SCAN_CNT_S)
#define TOUCH_FREQ_SCAN_CNT_V 0x00000003U
#define TOUCH_FREQ_SCAN_CNT_S 23
/** TOUCH_CHN_TMP_STATUS_REG register
* need_des
*/
#define TOUCH_CHN_TMP_STATUS_REG (DR_REG_TOUCH_BASE + 0x5c)
/** TOUCH_PAD_INACTIVE_STATUS : RO; bitpos: [14:0]; default: 0;
* need_des
*/
#define TOUCH_PAD_INACTIVE_STATUS 0x00007FFFU
#define TOUCH_PAD_INACTIVE_STATUS_M (TOUCH_PAD_INACTIVE_STATUS_V << TOUCH_PAD_INACTIVE_STATUS_S)
#define TOUCH_PAD_INACTIVE_STATUS_V 0x00007FFFU
#define TOUCH_PAD_INACTIVE_STATUS_S 0
/** TOUCH_PAD_ACTIVE_STATUS : RO; bitpos: [29:15]; default: 0;
* need_des
*/
#define TOUCH_PAD_ACTIVE_STATUS 0x00007FFFU
#define TOUCH_PAD_ACTIVE_STATUS_M (TOUCH_PAD_ACTIVE_STATUS_V << TOUCH_PAD_ACTIVE_STATUS_S)
#define TOUCH_PAD_ACTIVE_STATUS_V 0x00007FFFU
#define TOUCH_PAD_ACTIVE_STATUS_S 15
/** TOUCH_DATE_REG register
* need_des
*/
#define TOUCH_DATE_REG (DR_REG_TOUCH_BASE + 0x100)
/** TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define TOUCH_CLK_EN (BIT(31))
#define TOUCH_CLK_EN_M (TOUCH_CLK_EN_V << TOUCH_CLK_EN_S)
#define TOUCH_CLK_EN_V 0x00000001U
#define TOUCH_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/touch_struct.h Normal file
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@ -0,0 +1,655 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
/** scan_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* need_des
*/
uint32_t scan_done_int_raw:1;
/** done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t done_int_raw:1;
/** active_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* need_des
*/
uint32_t active_int_raw:1;
/** inactive_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* need_des
*/
uint32_t inactive_int_raw:1;
/** timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* need_des
*/
uint32_t timeout_int_raw:1;
/** approach_loop_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* need_des
*/
uint32_t approach_loop_done_int_raw:1;
uint32_t reserved_6:26;
};
uint32_t val;
} touch_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
/** scan_done_int_st : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t scan_done_int_st:1;
/** done_int_st : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t done_int_st:1;
/** active_int_st : RO; bitpos: [2]; default: 0;
* need_des
*/
uint32_t active_int_st:1;
/** inactive_int_st : RO; bitpos: [3]; default: 0;
* need_des
*/
uint32_t inactive_int_st:1;
/** timeout_int_st : RO; bitpos: [4]; default: 0;
* need_des
*/
uint32_t timeout_int_st:1;
/** approach_loop_done_int_st : RO; bitpos: [5]; default: 0;
* need_des
*/
uint32_t approach_loop_done_int_st:1;
uint32_t reserved_6:26;
};
uint32_t val;
} touch_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
/** scan_done_int_ena : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t scan_done_int_ena:1;
/** done_int_ena : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t done_int_ena:1;
/** active_int_ena : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t active_int_ena:1;
/** inactive_int_ena : R/W; bitpos: [3]; default: 0;
* need_des
*/
uint32_t inactive_int_ena:1;
/** timeout_int_ena : R/W; bitpos: [4]; default: 0;
* need_des
*/
uint32_t timeout_int_ena:1;
/** approach_loop_done_int_ena : R/W; bitpos: [5]; default: 0;
* need_des
*/
uint32_t approach_loop_done_int_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} touch_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
/** scan_done_int_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t scan_done_int_clr:1;
/** done_int_clr : WT; bitpos: [1]; default: 0;
* need_des
*/
uint32_t done_int_clr:1;
/** active_int_clr : WT; bitpos: [2]; default: 0;
* need_des
*/
uint32_t active_int_clr:1;
/** inactive_int_clr : WT; bitpos: [3]; default: 0;
* need_des
*/
uint32_t inactive_int_clr:1;
/** timeout_int_clr : WT; bitpos: [4]; default: 0;
* need_des
*/
uint32_t timeout_int_clr:1;
/** approach_loop_done_int_clr : WT; bitpos: [5]; default: 0;
* need_des
*/
uint32_t approach_loop_done_int_clr:1;
uint32_t reserved_6:26;
};
uint32_t val;
} touch_int_clr_reg_t;
/** Type of chn_status register
* need_des
*/
typedef union {
struct {
/** pad_active : RO; bitpos: [14:0]; default: 0;
* need_des
*/
uint32_t pad_active:15;
/** meas_done : RO; bitpos: [15]; default: 0;
* need_des
*/
uint32_t meas_done:1;
/** scan_curr : RO; bitpos: [19:16]; default: 15;
* need_des
*/
uint32_t scan_curr:4;
uint32_t reserved_20:12;
};
uint32_t val;
} touch_chn_status_reg_t;
/** Type of status_0 register
* need_des
*/
typedef union {
struct {
/** pad0_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad0_data:16;
/** pad0_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad0_debounce_cnt:3;
/** pad0_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad0_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_0_reg_t;
/** Type of status_1 register
* need_des
*/
typedef union {
struct {
/** pad1_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad1_data:16;
/** pad1_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad1_debounce_cnt:3;
/** pad1_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad1_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_1_reg_t;
/** Type of status_2 register
* need_des
*/
typedef union {
struct {
/** pad2_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad2_data:16;
/** pad2_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad2_debounce_cnt:3;
/** pad2_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad2_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_2_reg_t;
/** Type of status_3 register
* need_des
*/
typedef union {
struct {
/** pad3_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad3_data:16;
/** pad3_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad3_debounce_cnt:3;
/** pad3_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad3_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_3_reg_t;
/** Type of status_4 register
* need_des
*/
typedef union {
struct {
/** pad4_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad4_data:16;
/** pad4_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad4_debounce_cnt:3;
/** pad4_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad4_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_4_reg_t;
/** Type of status_5 register
* need_des
*/
typedef union {
struct {
/** pad5_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad5_data:16;
/** pad5_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad5_debounce_cnt:3;
/** pad5_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad5_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_5_reg_t;
/** Type of status_6 register
* need_des
*/
typedef union {
struct {
/** pad6_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad6_data:16;
/** pad6_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad6_debounce_cnt:3;
/** pad6_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad6_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_6_reg_t;
/** Type of status_7 register
* need_des
*/
typedef union {
struct {
/** pad7_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad7_data:16;
/** pad7_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad7_debounce_cnt:3;
/** pad7_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad7_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_7_reg_t;
/** Type of status_8 register
* need_des
*/
typedef union {
struct {
/** pad8_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad8_data:16;
/** pad8_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad8_debounce_cnt:3;
/** pad8_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad8_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_8_reg_t;
/** Type of status_9 register
* need_des
*/
typedef union {
struct {
/** pad9_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad9_data:16;
/** pad9_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad9_debounce_cnt:3;
/** pad9_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad9_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_9_reg_t;
/** Type of status_10 register
* need_des
*/
typedef union {
struct {
/** pad10_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad10_data:16;
/** pad10_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad10_debounce_cnt:3;
/** pad10_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad10_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_10_reg_t;
/** Type of status_11 register
* need_des
*/
typedef union {
struct {
/** pad11_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad11_data:16;
/** pad11_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad11_debounce_cnt:3;
/** pad11_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad11_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_11_reg_t;
/** Type of status_12 register
* need_des
*/
typedef union {
struct {
/** pad12_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad12_data:16;
/** pad12_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad12_debounce_cnt:3;
/** pad12_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad12_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_12_reg_t;
/** Type of status_13 register
* need_des
*/
typedef union {
struct {
/** pad13_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad13_data:16;
/** pad13_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad13_debounce_cnt:3;
/** pad13_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad13_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_13_reg_t;
/** Type of status_14 register
* need_des
*/
typedef union {
struct {
/** pad14_data : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t pad14_data:16;
/** pad14_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t pad14_debounce_cnt:3;
/** pad14_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t pad14_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_14_reg_t;
/** Type of status_15 register
* need_des
*/
typedef union {
struct {
/** slp_data : RO; bitpos: [15:0]; default: 65535;
* need_des
*/
uint32_t slp_data:16;
/** slp_debounce_cnt : RO; bitpos: [18:16]; default: 0;
* need_des
*/
uint32_t slp_debounce_cnt:3;
/** slp_nn_cnt : RO; bitpos: [22:19]; default: 0;
* need_des
*/
uint32_t slp_nn_cnt:4;
uint32_t reserved_23:9;
};
uint32_t val;
} touch_status_15_reg_t;
/** Type of status_16 register
* need_des
*/
typedef union {
struct {
/** approach_pad2_cnt : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t approach_pad2_cnt:8;
/** approach_pad1_cnt : RO; bitpos: [15:8]; default: 0;
* need_des
*/
uint32_t approach_pad1_cnt:8;
/** approach_pad0_cnt : RO; bitpos: [23:16]; default: 0;
* need_des
*/
uint32_t approach_pad0_cnt:8;
/** slp_approach_cnt : RO; bitpos: [31:24]; default: 0;
* need_des
*/
uint32_t slp_approach_cnt:8;
};
uint32_t val;
} touch_status_16_reg_t;
/** Type of status_17 register
* need_des
*/
typedef union {
struct {
/** dcap_lpf : RO; bitpos: [6:0]; default: 0;
* Reserved
*/
uint32_t dcap_lpf:7;
/** dres_lpf : RO; bitpos: [8:7]; default: 0;
* need_des
*/
uint32_t dres_lpf:2;
/** drv_ls : RO; bitpos: [12:9]; default: 0;
* need_des
*/
uint32_t drv_ls:4;
/** drv_hs : RO; bitpos: [17:13]; default: 0;
* need_des
*/
uint32_t drv_hs:5;
/** dbias : RO; bitpos: [22:18]; default: 0;
* need_des
*/
uint32_t dbias:5;
/** freq_scan_cnt : RO; bitpos: [24:23]; default: 0;
* need_des
*/
uint32_t freq_scan_cnt:2;
uint32_t reserved_25:7;
};
uint32_t val;
} touch_status_17_reg_t;
/** Type of chn_tmp_status register
* need_des
*/
typedef union {
struct {
/** pad_inactive_status : RO; bitpos: [14:0]; default: 0;
* need_des
*/
uint32_t pad_inactive_status:15;
/** pad_active_status : RO; bitpos: [29:15]; default: 0;
* need_des
*/
uint32_t pad_active_status:15;
uint32_t reserved_30:2;
};
uint32_t val;
} touch_chn_tmp_status_reg_t;
/** Group: Version */
/** Type of date register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} touch_date_reg_t;
typedef struct {
volatile touch_int_raw_reg_t int_raw;
volatile touch_int_st_reg_t int_st;
volatile touch_int_ena_reg_t int_ena;
volatile touch_int_clr_reg_t int_clr;
volatile touch_chn_status_reg_t chn_status;
volatile touch_status_0_reg_t status_0;
volatile touch_status_1_reg_t status_1;
volatile touch_status_2_reg_t status_2;
volatile touch_status_3_reg_t status_3;
volatile touch_status_4_reg_t status_4;
volatile touch_status_5_reg_t status_5;
volatile touch_status_6_reg_t status_6;
volatile touch_status_7_reg_t status_7;
volatile touch_status_8_reg_t status_8;
volatile touch_status_9_reg_t status_9;
volatile touch_status_10_reg_t status_10;
volatile touch_status_11_reg_t status_11;
volatile touch_status_12_reg_t status_12;
volatile touch_status_13_reg_t status_13;
volatile touch_status_14_reg_t status_14;
volatile touch_status_15_reg_t status_15;
volatile touch_status_16_reg_t status_16;
volatile touch_status_17_reg_t status_17;
volatile touch_chn_tmp_status_reg_t chn_tmp_status;
uint32_t reserved_060[40];
volatile touch_date_reg_t date;
} touch_dev_t;
extern touch_dev_t TOUCH_SENS;
#ifndef __cplusplus
_Static_assert(sizeof(touch_dev_t) == 0x104, "Invalid size of touch_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/trace_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TRACE_MEM_START_ADDR_REG register
* Memory start address
*/
#define TRACE_MEM_START_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x0)
/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
* Configures the start address of the trace memory
*/
#define TRACE_MEM_START_ADDR 0xFFFFFFFFU
#define TRACE_MEM_START_ADDR_M (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
#define TRACE_MEM_START_ADDR_V 0xFFFFFFFFU
#define TRACE_MEM_START_ADDR_S 0
/** TRACE_MEM_END_ADDR_REG register
* Memory end address
*/
#define TRACE_MEM_END_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x4)
/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the end address of the trace memory.
*/
#define TRACE_MEM_END_ADDR 0xFFFFFFFFU
#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU
#define TRACE_MEM_END_ADDR_S 0
/** TRACE_MEM_CURRENT_ADDR_REG register
* Memory current addr
*/
#define TRACE_MEM_CURRENT_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x8)
/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the current memory address for writing.
*/
#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define TRACE_MEM_CURRENT_ADDR_S 0
/** TRACE_MEM_ADDR_UPDATE_REG register
* Memory address update
*/
#define TRACE_MEM_ADDR_UPDATE_REG(i) (DR_REG_TRACE_BASE(i) + 0xc)
/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Configures whether to update the value of
* \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
* 0: Not update
* 1: Update
*/
#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0))
#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U
#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0
/** TRACE_FIFO_STATUS_REG register
* FIFO status register
*/
#define TRACE_FIFO_STATUS_REG(i) (DR_REG_TRACE_BASE(i) + 0x10)
/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
* Represent whether the FIFO is empty.
* 1: Empty
* 0: Not empty
*/
#define TRACE_FIFO_EMPTY (BIT(0))
#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
#define TRACE_FIFO_EMPTY_V 0x00000001U
#define TRACE_FIFO_EMPTY_S 0
/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
* Represent the state of the encoder:
* 0: Idle state
* 1: Working state
* 2: Wait state because hart is halted or in reset
* 3: Lost state
*/
#define TRACE_WORK_STATUS 0x00000003U
#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
#define TRACE_WORK_STATUS_V 0x00000003U
#define TRACE_WORK_STATUS_S 1
/** TRACE_INTR_ENA_REG register
* Interrupt enable register
*/
#define TRACE_INTR_ENA_REG(i) (DR_REG_TRACE_BASE(i) + 0x14)
/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TRACE_FIFO_OVERFLOW_INTR
*/
#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0))
#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U
#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0
/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable TRACE_MEM_FULL_INTR
*/
#define TRACE_MEM_FULL_INTR_ENA (BIT(1))
#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U
#define TRACE_MEM_FULL_INTR_ENA_S 1
/** TRACE_INTR_RAW_REG register
* Interrupt raw status register
*/
#define TRACE_INTR_RAW_REG(i) (DR_REG_TRACE_BASE(i) + 0x18)
/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
* The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.
*/
#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0))
#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U
#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0
/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
* The raw interrupt status of TRACE_MEM_FULL_INTR
*/
#define TRACE_MEM_FULL_INTR_RAW (BIT(1))
#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U
#define TRACE_MEM_FULL_INTR_RAW_S 1
/** TRACE_INTR_CLR_REG register
* Interrupt clear register
*/
#define TRACE_INTR_CLR_REG(i) (DR_REG_TRACE_BASE(i) + 0x1c)
/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear TRACE_FIFO_OVERFLOW_INTR
*/
#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0))
#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U
#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0
/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear TRACE_MEM_FULL_INTR
*/
#define TRACE_MEM_FULL_INTR_CLR (BIT(1))
#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U
#define TRACE_MEM_FULL_INTR_CLR_S 1
/** TRACE_TRIGGER_REG register
* Trace enable register
*/
#define TRACE_TRIGGER_REG(i) (DR_REG_TRACE_BASE(i) + 0x20)
/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
* Configure whether to enable the encoder.
* 0: Invalid
* 1: Enable
*/
#define TRACE_TRIGGER_ON (BIT(0))
#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
#define TRACE_TRIGGER_ON_V 0x00000001U
#define TRACE_TRIGGER_ON_S 0
/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
* Configure whether to disable the encoder.
* 0: Invalid
* 1: Disable
*/
#define TRACE_TRIGGER_OFF (BIT(1))
#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
#define TRACE_TRIGGER_OFF_V 0x00000001U
#define TRACE_TRIGGER_OFF_S 1
/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
* Configure the memory writing mode.
* 0: Non-loop mode.
* 1: Loop mode
*/
#define TRACE_MEM_LOOP (BIT(2))
#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
#define TRACE_MEM_LOOP_V 0x00000001U
#define TRACE_MEM_LOOP_S 2
/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
* Configure whether or not enable automatic restart function for the encoder.
* 0: Disable
* 1: Enable
*/
#define TRACE_RESTART_ENA (BIT(3))
#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
#define TRACE_RESTART_ENA_V 0x00000001U
#define TRACE_RESTART_ENA_S 3
/** TRACE_CONFIG_REG register
* trace configuration register
*/
#define TRACE_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x24)
/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
* Configure whether to enable the trigger signal.
* 0: Disable
* 1:enable
*/
#define TRACE_DM_TRIGGER_ENA (BIT(0))
#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
#define TRACE_DM_TRIGGER_ENA_V 0x00000001U
#define TRACE_DM_TRIGGER_ENA_S 0
/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
* Configure whether to reset, when enabled, if cpu have reset, the encoder will
* output a packet to report the address of the last instruction, and upon reset
* deassertion, the encoder start again.
* 0: Disable
* 0: Enable
*/
#define TRACE_RESET_ENA (BIT(1))
#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
#define TRACE_RESET_ENA_V 0x00000001U
#define TRACE_RESET_ENA_S 1
/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the halt signal.
* 1: Disable
* 1: Enable
*/
#define TRACE_HALT_ENA (BIT(2))
#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
#define TRACE_HALT_ENA_V 0x00000001U
#define TRACE_HALT_ENA_S 2
/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
* Configure whether to enable the stall signal.
* 0: Disable.
* 1: Enable
*/
#define TRACE_STALL_ENA (BIT(3))
#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
#define TRACE_STALL_ENA_V 0x00000001U
#define TRACE_STALL_ENA_S 3
/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
* Configure the address mode.
* 0: Delta address mode.
* 1: Full address mode.
*/
#define TRACE_FULL_ADDRESS (BIT(4))
#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
#define TRACE_FULL_ADDRESS_V 0x00000001U
#define TRACE_FULL_ADDRESS_S 4
/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
* Configure whether or not enable implicit exception mode. When enabled,, do not sent
* exception address, only exception cause in exception packets.
* 1: enabled
* 0: disabled
*/
#define TRACE_IMPLICIT_EXCEPT (BIT(5))
#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
#define TRACE_IMPLICIT_EXCEPT_V 0x00000001U
#define TRACE_IMPLICIT_EXCEPT_S 5
/** TRACE_FILTER_CONTROL_REG register
* filter control register
*/
#define TRACE_FILTER_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x28)
/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
* Configure whether to enable filtering.
* 0: Disable, always match.
* 1: Enable
*/
#define TRACE_FILTER_EN (BIT(0))
#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
#define TRACE_FILTER_EN_V 0x00000001U
#define TRACE_FILTER_EN_S 0
/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
* Configure whether to enable the comparator match mode.
* 0: Disable
* 1: Enable, the comparator must be high in order for the filter to match
*/
#define TRACE_MATCH_COMP (BIT(1))
#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
#define TRACE_MATCH_COMP_V 0x00000001U
#define TRACE_MATCH_COMP_S 1
/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the privilege match mode.
* 0: Disable
* 1: Enable, match privilege levels specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
*/
#define TRACE_MATCH_PRIVILEGE (BIT(2))
#define TRACE_MATCH_PRIVILEGE_M (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
#define TRACE_MATCH_PRIVILEGE_V 0x00000001U
#define TRACE_MATCH_PRIVILEGE_S 2
/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
* Configure whether to enable ecause match mode.
* 0: Disable
* 1: Enable, start matching from exception cause codes specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
* matching upon return from the 1st matching exception.
*/
#define TRACE_MATCH_ECAUSE (BIT(3))
#define TRACE_MATCH_ECAUSE_M (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
#define TRACE_MATCH_ECAUSE_V 0x00000001U
#define TRACE_MATCH_ECAUSE_S 3
/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
* Configure whether to enable the interrupt match mode.
* 0: Disable
* 1: Enable, start matching from a trap with the interrupt level codes specified by
* \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
* stop matching upon return from the 1st matching trap.
*/
#define TRACE_MATCH_INTERRUPT (BIT(4))
#define TRACE_MATCH_INTERRUPT_M (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
#define TRACE_MATCH_INTERRUPT_V 0x00000001U
#define TRACE_MATCH_INTERRUPT_S 4
/** TRACE_FILTER_MATCH_CONTROL_REG register
* filter match control register
*/
#define TRACE_FILTER_MATCH_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x2c)
/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
* Configures the privilege level for matching. Valid only when
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
* 0: User mode.
* 1: Machine mode
*/
#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0))
#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
#define TRACE_MATCH_CHOICE_PRIVILEGE_V 0x00000001U
#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0
/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
* Configures the interrupt level for match. Valid only when when
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
* 0: itype=2.
* 0: itype=2.
*/
#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1))
#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
#define TRACE_MATCH_VALUE_INTERRUPT_V 0x00000001U
#define TRACE_MATCH_VALUE_INTERRUPT_S 1
/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
* Configures the ecause code for matching.
*/
#define TRACE_MATCH_CHOICE_ECAUSE 0x0000003FU
#define TRACE_MATCH_CHOICE_ECAUSE_M (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
#define TRACE_MATCH_CHOICE_ECAUSE_V 0x0000003FU
#define TRACE_MATCH_CHOICE_ECAUSE_S 2
/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
* filter comparator match control register
*/
#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x30)
/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
* Configures the input of the primary comparator for matching:
* 0: iaddr
* 1: tval
*/
#define TRACE_P_INPUT (BIT(0))
#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
#define TRACE_P_INPUT_V 0x00000001U
#define TRACE_P_INPUT_S 0
/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
* Configures the function for the primary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
#define TRACE_P_FUNCTION 0x00000007U
#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
#define TRACE_P_FUNCTION_V 0x00000007U
#define TRACE_P_FUNCTION_S 2
/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
* Configure whether to explicitly report an instruction address matched against the
* primary comparator.
* 0:Not report
* 1:Report
*/
#define TRACE_P_NOTIFY (BIT(5))
#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
#define TRACE_P_NOTIFY_V 0x00000001U
#define TRACE_P_NOTIFY_S 5
/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
* Configures the input of the secondary comparator for matching:
* 0: iaddr
* 1: tval
*/
#define TRACE_S_INPUT (BIT(8))
#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
#define TRACE_S_INPUT_V 0x00000001U
#define TRACE_S_INPUT_S 8
/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
* Configures the function for the secondary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
#define TRACE_S_FUNCTION 0x00000007U
#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
#define TRACE_S_FUNCTION_V 0x00000007U
#define TRACE_S_FUNCTION_S 10
/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
* Generate a trace packet explicitly reporting the address that cause the secondary
* match
*/
#define TRACE_S_NOTIFY (BIT(13))
#define TRACE_S_NOTIFY_M (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
#define TRACE_S_NOTIFY_V 0x00000001U
#define TRACE_S_NOTIFY_S 13
/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
* Configures the comparator match mode:
* 0: Only the primary comparator matches
* 1: Both primary and secondary comparator matches(P\&\&S)
* 2:Neither primary or secondary comparator matches !(P\&\&S)
* 3: Start filtering when the primary comparator matches and stop filtering when the
* secondary comparator matches
*/
#define TRACE_MATCH_MODE 0x00000003U
#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
#define TRACE_MATCH_MODE_V 0x00000003U
#define TRACE_MATCH_MODE_S 16
/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
* primary comparator match value
*/
#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x34)
/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
* Configures the match value for the primary comparator
*/
#define TRACE_P_MATCH 0xFFFFFFFFU
#define TRACE_P_MATCH_M (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
#define TRACE_P_MATCH_V 0xFFFFFFFFU
#define TRACE_P_MATCH_S 0
/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
* secondary comparator match value
*/
#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x38)
/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
* Configures the match value for the secondary comparator
*/
#define TRACE_S_MATCH 0xFFFFFFFFU
#define TRACE_S_MATCH_M (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
#define TRACE_S_MATCH_V 0xFFFFFFFFU
#define TRACE_S_MATCH_S 0
/** TRACE_RESYNC_PROLONGED_REG register
* Resync configuration register
*/
#define TRACE_RESYNC_PROLONGED_REG(i) (DR_REG_TRACE_BASE(i) + 0x3c)
/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
* Configures the threshold for synchronization counter
*/
#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU
#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU
#define TRACE_RESYNC_PROLONGED_S 0
/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
* Configures the synchronization mode:
* 0: Disable the synchronization counter
* 1: Invalid
* 2: Synchronization counter counts by packet
* 3: Synchronization counter counts by cycle
*/
#define TRACE_RESYNC_MODE 0x00000003U
#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
#define TRACE_RESYNC_MODE_V 0x00000003U
#define TRACE_RESYNC_MODE_S 24
/** TRACE_AHB_CONFIG_REG register
* AHB config register
*/
#define TRACE_AHB_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x40)
/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
* Configures the AHB burst mode.
* 0: SINGLE
* 1: INCR(length not defined)
* 2:INCR4
* 4:INCR8
* Others:Invalid
*/
#define TRACE_HBURST 0x00000007U
#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S)
#define TRACE_HBURST_V 0x00000007U
#define TRACE_HBURST_S 0
/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
* Configures the maximum burst length for INCR mode
*/
#define TRACE_MAX_INCR 0x00000007U
#define TRACE_MAX_INCR_M (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
#define TRACE_MAX_INCR_V 0x00000007U
#define TRACE_MAX_INCR_S 3
/** TRACE_CLOCK_GATE_REG register
* Clock gate control register
*/
#define TRACE_CLOCK_GATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x44)
/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures register clock gating.
* 0: Support clock only when the application writes registers to save power.
* 1:Always force the clock on for registers
* This bit doesn't affect register access.
*/
#define TRACE_CLK_EN (BIT(0))
#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
#define TRACE_CLK_EN_V 0x00000001U
#define TRACE_CLK_EN_S 0
/** TRACE_DATE_REG register
* Version control register
*/
#define TRACE_DATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x3fc)
/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
* Version control register.
*/
#define TRACE_DATE 0x0FFFFFFFU
#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S)
#define TRACE_DATE_V 0x0FFFFFFFU
#define TRACE_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/trace_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory configuration registers */
/** Type of mem_start_addr register
* Memory start address
*/
typedef union {
struct {
/** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
* Configures the start address of the trace memory
*/
uint32_t mem_start_addr:32;
};
uint32_t val;
} trace_mem_start_addr_reg_t;
/** Type of mem_end_addr register
* Memory end address
*/
typedef union {
struct {
/** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the end address of the trace memory.
*/
uint32_t mem_end_addr:32;
};
uint32_t val;
} trace_mem_end_addr_reg_t;
/** Type of mem_current_addr register
* Memory current addr
*/
typedef union {
struct {
/** mem_current_addr : RO; bitpos: [31:0]; default: 0;
* Represents the current memory address for writing.
*/
uint32_t mem_current_addr:32;
};
uint32_t val;
} trace_mem_current_addr_reg_t;
/** Type of mem_addr_update register
* Memory address update
*/
typedef union {
struct {
/** mem_current_addr_update : WT; bitpos: [0]; default: 0;
* Configures whether to update the value of
* \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
* \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
* 0: Not update
* 1: Update
*/
uint32_t mem_current_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} trace_mem_addr_update_reg_t;
/** Group: Trace fifo status register */
/** Type of fifo_status register
* FIFO status register
*/
typedef union {
struct {
/** fifo_empty : RO; bitpos: [0]; default: 1;
* Represent whether the FIFO is empty.
* 1: Empty
* 0: Not empty
*/
uint32_t fifo_empty:1;
/** work_status : RO; bitpos: [2:1]; default: 0;
* Represent the state of the encoder:
* 0: Idle state
* 1: Working state
* 2: Wait state because hart is halted or in reset
* 3: Lost state
*/
uint32_t work_status:2;
uint32_t reserved_3:29;
};
uint32_t val;
} trace_fifo_status_reg_t;
/** Group: Interrupt registers */
/** Type of intr_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TRACE_FIFO_OVERFLOW_INTR
*/
uint32_t fifo_overflow_intr_ena:1;
/** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable TRACE_MEM_FULL_INTR
*/
uint32_t mem_full_intr_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} trace_intr_ena_reg_t;
/** Type of intr_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
* The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.
*/
uint32_t fifo_overflow_intr_raw:1;
/** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
* The raw interrupt status of TRACE_MEM_FULL_INTR
*/
uint32_t mem_full_intr_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} trace_intr_raw_reg_t;
/** Type of intr_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear TRACE_FIFO_OVERFLOW_INTR
*/
uint32_t fifo_overflow_intr_clr:1;
/** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear TRACE_MEM_FULL_INTR
*/
uint32_t mem_full_intr_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} trace_intr_clr_reg_t;
/** Group: Trace configuration register */
/** Type of trigger register
* Trace enable register
*/
typedef union {
struct {
/** trigger_on : WT; bitpos: [0]; default: 0;
* Configure whether to enable the encoder.
* 0: Invalid
* 1: Enable
*/
uint32_t trigger_on:1;
/** trigger_off : WT; bitpos: [1]; default: 0;
* Configure whether to disable the encoder.
* 0: Invalid
* 1: Disable
*/
uint32_t trigger_off:1;
/** mem_loop : R/W; bitpos: [2]; default: 1;
* Configure the memory writing mode.
* 0: Non-loop mode.
* 1: Loop mode
*/
uint32_t mem_loop:1;
/** restart_ena : R/W; bitpos: [3]; default: 1;
* Configure whether or not enable automatic restart function for the encoder.
* 0: Disable
* 1: Enable
*/
uint32_t restart_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} trace_trigger_reg_t;
/** Type of config register
* trace configuration register
*/
typedef union {
struct {
/** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
* Configure whether to enable the trigger signal.
* 0: Disable
* 1:enable
*/
uint32_t dm_trigger_ena:1;
/** reset_ena : R/W; bitpos: [1]; default: 0;
* Configure whether to reset, when enabled, if cpu have reset, the encoder will
* output a packet to report the address of the last instruction, and upon reset
* deassertion, the encoder start again.
* 0: Disable
* 0: Enable
*/
uint32_t reset_ena:1;
/** halt_ena : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the halt signal.
* 1: Disable
* 1: Enable
*/
uint32_t halt_ena:1;
/** stall_ena : R/W; bitpos: [3]; default: 0;
* Configure whether to enable the stall signal.
* 0: Disable.
* 1: Enable
*/
uint32_t stall_ena:1;
/** full_address : R/W; bitpos: [4]; default: 0;
* Configure the address mode.
* 0: Delta address mode.
* 1: Full address mode.
*/
uint32_t full_address:1;
/** implicit_except : R/W; bitpos: [5]; default: 0;
* Configure whether or not enable implicit exception mode. When enabled,, do not sent
* exception address, only exception cause in exception packets.
* 1: enabled
* 0: disabled
*/
uint32_t implicit_except:1;
uint32_t reserved_6:26;
};
uint32_t val;
} trace_config_reg_t;
/** Type of filter_control register
* filter control register
*/
typedef union {
struct {
/** filter_en : R/W; bitpos: [0]; default: 0;
* Configure whether to enable filtering.
* 0: Disable, always match.
* 1: Enable
*/
uint32_t filter_en:1;
/** match_comp : R/W; bitpos: [1]; default: 0;
* Configure whether to enable the comparator match mode.
* 0: Disable
* 1: Enable, the comparator must be high in order for the filter to match
*/
uint32_t match_comp:1;
/** match_privilege : R/W; bitpos: [2]; default: 0;
* Configure whether to enable the privilege match mode.
* 0: Disable
* 1: Enable, match privilege levels specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
*/
uint32_t match_privilege:1;
/** match_ecause : R/W; bitpos: [3]; default: 0;
* Configure whether to enable ecause match mode.
* 0: Disable
* 1: Enable, start matching from exception cause codes specified by
* \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
* matching upon return from the 1st matching exception.
*/
uint32_t match_ecause:1;
/** match_interrupt : R/W; bitpos: [4]; default: 0;
* Configure whether to enable the interrupt match mode.
* 0: Disable
* 1: Enable, start matching from a trap with the interrupt level codes specified by
* \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
* stop matching upon return from the 1st matching trap.
*/
uint32_t match_interrupt:1;
uint32_t reserved_5:27;
};
uint32_t val;
} trace_filter_control_reg_t;
/** Type of filter_match_control register
* filter match control register
*/
typedef union {
struct {
/** match_choice_privilege : R/W; bitpos: [0]; default: 0;
* Configures the privilege level for matching. Valid only when
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
* 0: User mode.
* 1: Machine mode
*/
uint32_t match_choice_privilege:1;
/** match_value_interrupt : R/W; bitpos: [1]; default: 0;
* Configures the interrupt level for match. Valid only when when
* \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
* 0: itype=2.
* 0: itype=2.
*/
uint32_t match_value_interrupt:1;
/** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
* Configures the ecause code for matching.
*/
uint32_t match_choice_ecause:6;
uint32_t reserved_8:24;
};
uint32_t val;
} trace_filter_match_control_reg_t;
/** Type of filter_comparator_control register
* filter comparator match control register
*/
typedef union {
struct {
/** p_input : R/W; bitpos: [0]; default: 0;
* Configures the input of the primary comparator for matching:
* 0: iaddr
* 1: tval
*/
uint32_t p_input:1;
uint32_t reserved_1:1;
/** p_function : R/W; bitpos: [4:2]; default: 0;
* Configures the function for the primary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
uint32_t p_function:3;
/** p_notify : R/W; bitpos: [5]; default: 0;
* Configure whether to explicitly report an instruction address matched against the
* primary comparator.
* 0:Not report
* 1:Report
*/
uint32_t p_notify:1;
uint32_t reserved_6:2;
/** s_input : R/W; bitpos: [8]; default: 0;
* Configures the input of the secondary comparator for matching:
* 0: iaddr
* 1: tval
*/
uint32_t s_input:1;
uint32_t reserved_9:1;
/** s_function : R/W; bitpos: [12:10]; default: 0;
* Configures the function for the secondary comparator.
* 0: Equal,
* 1: Not equal,
* 2: Less than,
* 3: Less than or equal,
* 4: Greater than,
* 5: Greater than or equal,
* Other: Always match
*/
uint32_t s_function:3;
/** s_notify : R/W; bitpos: [13]; default: 0;
* Generate a trace packet explicitly reporting the address that cause the secondary
* match
*/
uint32_t s_notify:1;
uint32_t reserved_14:2;
/** match_mode : R/W; bitpos: [17:16]; default: 0;
* Configures the comparator match mode:
* 0: Only the primary comparator matches
* 1: Both primary and secondary comparator matches(P\&\&S)
* 2:Neither primary or secondary comparator matches !(P\&\&S)
* 3: Start filtering when the primary comparator matches and stop filtering when the
* secondary comparator matches
*/
uint32_t match_mode:2;
uint32_t reserved_18:14;
};
uint32_t val;
} trace_filter_comparator_control_reg_t;
/** Type of filter_p_comparator_match register
* primary comparator match value
*/
typedef union {
struct {
/** p_match : R/W; bitpos: [31:0]; default: 0;
* Configures the match value for the primary comparator
*/
uint32_t p_match:32;
};
uint32_t val;
} trace_filter_p_comparator_match_reg_t;
/** Type of filter_s_comparator_match register
* secondary comparator match value
*/
typedef union {
struct {
/** s_match : R/W; bitpos: [31:0]; default: 0;
* Configures the match value for the secondary comparator
*/
uint32_t s_match:32;
};
uint32_t val;
} trace_filter_s_comparator_match_reg_t;
/** Type of resync_prolonged register
* Resync configuration register
*/
typedef union {
struct {
/** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
* Configures the threshold for synchronization counter
*/
uint32_t resync_prolonged:24;
/** resync_mode : R/W; bitpos: [25:24]; default: 0;
* Configures the synchronization mode:
* 0: Disable the synchronization counter
* 1: Invalid
* 2: Synchronization counter counts by packet
* 3: Synchronization counter counts by cycle
*/
uint32_t resync_mode:2;
uint32_t reserved_26:6;
};
uint32_t val;
} trace_resync_prolonged_reg_t;
/** Type of ahb_config register
* AHB config register
*/
typedef union {
struct {
/** hburst : R/W; bitpos: [2:0]; default: 0;
* Configures the AHB burst mode.
* 0: SINGLE
* 1: INCR(length not defined)
* 2:INCR4
* 4:INCR8
* Others:Invalid
*/
uint32_t hburst:3;
/** max_incr : R/W; bitpos: [5:3]; default: 0;
* Configures the maximum burst length for INCR mode
*/
uint32_t max_incr:3;
uint32_t reserved_6:26;
};
uint32_t val;
} trace_ahb_config_reg_t;
/** Group: Clock Gate Control and configuration register */
/** Type of clock_gate register
* Clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures register clock gating.
* 0: Support clock only when the application writes registers to save power.
* 1:Always force the clock on for registers
* This bit doesn't affect register access.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} trace_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35721984;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} trace_date_reg_t;
typedef struct {
volatile trace_mem_start_addr_reg_t mem_start_addr;
volatile trace_mem_end_addr_reg_t mem_end_addr;
volatile trace_mem_current_addr_reg_t mem_current_addr;
volatile trace_mem_addr_update_reg_t mem_addr_update;
volatile trace_fifo_status_reg_t fifo_status;
volatile trace_intr_ena_reg_t intr_ena;
volatile trace_intr_raw_reg_t intr_raw;
volatile trace_intr_clr_reg_t intr_clr;
volatile trace_trigger_reg_t trigger;
volatile trace_config_reg_t config;
volatile trace_filter_control_reg_t filter_control;
volatile trace_filter_match_control_reg_t filter_match_control;
volatile trace_filter_comparator_control_reg_t filter_comparator_control;
volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
volatile trace_resync_prolonged_reg_t resync_prolonged;
volatile trace_ahb_config_reg_t ahb_config;
volatile trace_clock_gate_reg_t clock_gate;
uint32_t reserved_048[237];
volatile trace_date_reg_t date;
} trace_dev_t;
extern trace_dev_t TRACE0;
extern trace_dev_t TRACE1;
#ifndef __cplusplus
_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of conf0 register
* UHCI configuration register
*/
typedef union {
struct {
/** tx_rst : R/W; bitpos: [0]; default: 0;
* Write 1 and then write 0 to reset the decoder state machine.
*/
uint32_t tx_rst:1;
/** rx_rst : R/W; bitpos: [1]; default: 0;
* Write 1 and then write 0 to reset the encoder state machine.
*/
uint32_t rx_rst:1;
/** uart_sel : R/W; bitpos: [4:2]; default: 7;
* Configures to select which uart to connect with UHCI.
* 0: UART0
* 1: UART1
*/
uint32_t uart_sel:3;
/** seper_en : R/W; bitpos: [5]; default: 1;
* Configures whether or not to separate the data frame with a special character.
* 0: Not separate
* 1: Separate
*/
uint32_t seper_en:1;
/** head_en : R/W; bitpos: [6]; default: 1;
* Configures whether or not to encode the data packet with a formatting header.
* 0: Not use formatting header
* 1: Use formatting header
*/
uint32_t head_en:1;
/** crc_rec_en : R/W; bitpos: [7]; default: 1;
* Configures whether or not to enable the reception of the 16-bit CRC.
* 0: Disable
* 1: Enable
*/
uint32_t crc_rec_en:1;
/** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
* Configures whether or not to stop receiving data when UART is idle.
* 0: Not stop
* 1: Stop
*/
uint32_t uart_idle_eof_en:1;
/** len_eof_en : R/W; bitpos: [9]; default: 1;
* Configures when the UHCI decoder stops receiving data.
* 0: Stops after receiving 0xC0
* 1: Stops when the number of received data bytes reach the specified value. When
* UHCI_HEAD_EN is 1, the specified value is the data length indicated by the UHCI
* packet header. when UHCI_HEAD_EN is 0, the specified value is the configured value.
*/
uint32_t len_eof_en:1;
/** encode_crc_en : R/W; bitpos: [10]; default: 1;
* Configures whether or not to enable data integrity check by appending a 16 bit
* CCITT-CRC to the end of the data.
* 0: Disable
* 1: Enable
*/
uint32_t encode_crc_en:1;
/** clk_en : R/W; bitpos: [11]; default: 0;
* Configures clock gating.
* 0: Support clock only when the application writes registers.
* 1: Always force the clock on for registers.
*/
uint32_t clk_en:1;
/** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
* Configures whether or not to stop UHCI from receiving data after UART has received
* a NULL frame.
* 0: Not stop
* 1: Stop
*/
uint32_t uart_rx_brk_eof_en:1;
uint32_t reserved_13:19;
};
uint32_t val;
} uhci_conf0_reg_t;
/** Type of conf1 register
* UHCI configuration register
*/
typedef union {
struct {
/** check_sum_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable header checksum validation when UHCI receives a
* data packet.
* 0: Disable
* 1: Enable
*/
uint32_t check_sum_en:1;
/** check_seq_en : R/W; bitpos: [1]; default: 1;
* Configures whether or not to enable the sequence number check when UHCI receives a
* data packet.
* 0: Disable
* 1: Enable
*/
uint32_t check_seq_en:1;
/** crc_disable : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable CRC calculation.
* 0: Disable
* 1: Enable
* Valid only when the Data Integrity Check Present bit in UHCI packet is 1.
*/
uint32_t crc_disable:1;
/** save_head : R/W; bitpos: [3]; default: 0;
* Configures whether or not to save the packet header when UHCI receives a data
* packet.
* 0: Not save
* 1: Save
*/
uint32_t save_head:1;
/** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
* Configures whether or not to encode the data packet with a checksum.
* 0: Not use checksum
* 1: Use checksum
*/
uint32_t tx_check_sum_re:1;
/** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
* Configures whether or not to encode the data packet with an acknowledgment when a
* reliable packet is to be transmitted.
* 0: Not use acknowledgement
* 1: Use acknowledgement
*/
uint32_t tx_ack_num_re:1;
uint32_t reserved_6:1;
/** wait_sw_start : R/W; bitpos: [7]; default: 0;
* Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT state.
* 0: No
* 1: Yes
*/
uint32_t wait_sw_start:1;
/** sw_start : WT; bitpos: [8]; default: 0;
* Write 1 to send data packets when the encoder state machine is in ST_SW_WAIT state.
*/
uint32_t sw_start:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_conf1_reg_t;
/** Type of escape_conf register
* Escape character configuration
*/
typedef union {
struct {
/** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to decode character 0xC0 when DMA receives data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_c0_esc_en:1;
/** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
* Configures whether or not to decode character 0xDB when DMA receives data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_db_esc_en:1;
/** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
* Configures whether or not to decode flow control character 0x11 when DMA receives
* data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_11_esc_en:1;
/** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
* Configures whether or not to decode flow control character 0x13 when DMA receives
* data.
* 0: Not decode
* 1: Decode
*/
uint32_t tx_13_esc_en:1;
/** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
* Configures whether or not to replace 0xC0 by special characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_c0_esc_en:1;
/** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
* Configures whether or not to replace 0xDB by special characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_db_esc_en:1;
/** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
* Configures whether or not to replace flow control character 0x11 by special
* characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_11_esc_en:1;
/** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to replace flow control character 0x13 by special
* characters when DMA sends data.
* 0: Not replace
* 1: Replace
*/
uint32_t rx_13_esc_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} uhci_escape_conf_reg_t;
/** Type of hung_conf register
* Timeout configuration
*/
typedef union {
struct {
/** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
* Configures the timeout value for DMA data reception.
* Measurement unit: ms.
*/
uint32_t txfifo_timeout:8;
/** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
* Configures the upper limit of the timeout counter for TX FIFO.
*/
uint32_t txfifo_timeout_shift:3;
/** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
* Configures whether or not to enable the data reception timeout for TX FIFO.
* 0: Disable
* 1: Enable
*/
uint32_t txfifo_timeout_ena:1;
/** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
* Configures the timeout value for DMA to read data from RAM.
* Measurement unit: ms.
*/
uint32_t rxfifo_timeout:8;
/** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
* Configures the upper limit of the timeout counter for RX FIFO.
*/
uint32_t rxfifo_timeout_shift:3;
/** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
* Configures whether or not to enable the DMA data transmission timeout.
* 0: Disable
* 1: Enable
*/
uint32_t rxfifo_timeout_ena:1;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_hung_conf_reg_t;
/** Type of ack_num register
* UHCI ACK number configuration
*/
typedef union {
struct {
/** ack_num : R/W; bitpos: [2:0]; default: 0;
* Configures the number of acknowledgements used in software flow control.
*/
uint32_t ack_num:3;
/** ack_num_load : WT; bitpos: [3]; default: 0;
* Configures whether or not load acknowledgements.
* 0: Not load
* 1: Load
*/
uint32_t ack_num_load:1;
uint32_t reserved_4:28;
};
uint32_t val;
} uhci_ack_num_reg_t;
/** Type of quick_sent register
* UHCI quick send configuration register
*/
typedef union {
struct {
/** single_send_num : R/W; bitpos: [2:0]; default: 0;
* Configures the source of data to be transmitted in single_send mode.
* 0: Q0 register
* 1: Q1 register
* 2: Q2 register
* 3: Q3 register
* 4: Q4 register
* 5: Q5 register
* 6: Q6 register
* 7: Invalid. No effect
*/
uint32_t single_send_num:3;
/** single_send_en : WT; bitpos: [3]; default: 0;
* Write 1 to enable single_send mode.
*/
uint32_t single_send_en:1;
/** always_send_num : R/W; bitpos: [6:4]; default: 0;
* Configures the source of data to be transmitted in always_send mode.
* 0: Q0 register
* 1: Q1 register
* 2: Q2 register
* 3: Q3 register
* 4: Q4 register
* 5: Q5 register
* 6: Q6 register
* 7: Invalid. No effect
*/
uint32_t always_send_num:3;
/** always_send_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable always_send mode.
* 0: Disable
* 1: Enable
*/
uint32_t always_send_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} uhci_quick_sent_reg_t;
/** Type of reg_q0_word0 register
* Q0 WORD0 quick send register
*/
typedef union {
struct {
/** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q0 register.
*/
uint32_t send_q0_word0:32;
};
uint32_t val;
} uhci_reg_q0_word0_reg_t;
/** Type of reg_q0_word1 register
* Q0 WORD1 quick send register
*/
typedef union {
struct {
/** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q0 register.
*/
uint32_t send_q0_word1:32;
};
uint32_t val;
} uhci_reg_q0_word1_reg_t;
/** Type of reg_q1_word0 register
* Q1 WORD0 quick send register
*/
typedef union {
struct {
/** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q1 register.
*/
uint32_t send_q1_word0:32;
};
uint32_t val;
} uhci_reg_q1_word0_reg_t;
/** Type of reg_q1_word1 register
* Q1 WORD1 quick send register
*/
typedef union {
struct {
/** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q1 register.
*/
uint32_t send_q1_word1:32;
};
uint32_t val;
} uhci_reg_q1_word1_reg_t;
/** Type of reg_q2_word0 register
* Q2 WORD0 quick send register
*/
typedef union {
struct {
/** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q2 register.
*/
uint32_t send_q2_word0:32;
};
uint32_t val;
} uhci_reg_q2_word0_reg_t;
/** Type of reg_q2_word1 register
* Q2 WORD1 quick send register
*/
typedef union {
struct {
/** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q2 register.
*/
uint32_t send_q2_word1:32;
};
uint32_t val;
} uhci_reg_q2_word1_reg_t;
/** Type of reg_q3_word0 register
* Q3 WORD0 quick send register
*/
typedef union {
struct {
/** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q3 register.
*/
uint32_t send_q3_word0:32;
};
uint32_t val;
} uhci_reg_q3_word0_reg_t;
/** Type of reg_q3_word1 register
* Q3 WORD1 quick send register
*/
typedef union {
struct {
/** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q3 register.
*/
uint32_t send_q3_word1:32;
};
uint32_t val;
} uhci_reg_q3_word1_reg_t;
/** Type of reg_q4_word0 register
* Q4 WORD0 quick send register
*/
typedef union {
struct {
/** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q4 register.
*/
uint32_t send_q4_word0:32;
};
uint32_t val;
} uhci_reg_q4_word0_reg_t;
/** Type of reg_q4_word1 register
* Q4 WORD1 quick send register
*/
typedef union {
struct {
/** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q4 register.
*/
uint32_t send_q4_word1:32;
};
uint32_t val;
} uhci_reg_q4_word1_reg_t;
/** Type of reg_q5_word0 register
* Q5 WORD0 quick send register
*/
typedef union {
struct {
/** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q5 register.
*/
uint32_t send_q5_word0:32;
};
uint32_t val;
} uhci_reg_q5_word0_reg_t;
/** Type of reg_q5_word1 register
* Q5 WORD1 quick send register
*/
typedef union {
struct {
/** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q5 register.
*/
uint32_t send_q5_word1:32;
};
uint32_t val;
} uhci_reg_q5_word1_reg_t;
/** Type of reg_q6_word0 register
* Q6 WORD0 quick send register
*/
typedef union {
struct {
/** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q6 register.
*/
uint32_t send_q6_word0:32;
};
uint32_t val;
} uhci_reg_q6_word0_reg_t;
/** Type of reg_q6_word1 register
* Q6 WORD1 quick register
*/
typedef union {
struct {
/** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q6 register.
*/
uint32_t send_q6_word1:32;
};
uint32_t val;
} uhci_reg_q6_word1_reg_t;
/** Type of esc_conf0 register
* Escape sequence configuration register 0
*/
typedef union {
struct {
/** seper_char : R/W; bitpos: [7:0]; default: 192;
* Configures separators to encode data packets. The default value is 0xC0.
*/
uint32_t seper_char:8;
/** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
* Configures the first character of SLIP escape sequence. The default value is 0xDB.
*/
uint32_t seper_esc_char0:8;
/** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
* Configures the second character of SLIP escape sequence. The default value is 0xDC.
*/
uint32_t seper_esc_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf0_reg_t;
/** Type of esc_conf1 register
* Escape sequence configuration register 1
*/
typedef union {
struct {
/** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
* Configures the character that needs to be encoded. The default value is 0xDB used
* as the first character of SLIP escape sequence.
*/
uint32_t esc_seq0:8;
/** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
* Configures the first character of SLIP escape sequence. The default value is 0xDB.
*/
uint32_t esc_seq0_char0:8;
/** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
* Configures the second character of SLIP escape sequence. The default value is 0xDD.
*/
uint32_t esc_seq0_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf1_reg_t;
/** Type of esc_conf2 register
* Escape sequence configuration register 2
*/
typedef union {
struct {
/** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
* Configures a character that need to be encoded. The default value is 0x11 used as a
* flow control character.
*/
uint32_t esc_seq1:8;
/** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
* Configures the first character of SLIP escape sequence. The default value is 0xDB.
*/
uint32_t esc_seq1_char0:8;
/** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
* Configures the second character of SLIP escape sequence. The default value is 0xDE.
*/
uint32_t esc_seq1_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf2_reg_t;
/** Type of esc_conf3 register
* Escape sequence configuration register 3
*/
typedef union {
struct {
/** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
* Configures the character that needs to be decoded. The default value is 0x13 used
* as a flow control character.
*/
uint32_t esc_seq2:8;
/** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
* Configures the first character of SLIP escape sequence. The default value is 0xDB.
*/
uint32_t esc_seq2_char0:8;
/** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
* Configures the second character of SLIP escape sequence. The default value is 0xDF.
*/
uint32_t esc_seq2_char1:8;
uint32_t reserved_24:8;
};
uint32_t val;
} uhci_esc_conf3_reg_t;
/** Type of pkt_thres register
* Configuration register for packet length
*/
typedef union {
struct {
/** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
* Configures the maximum value of the packet length.
* Measurement unit: byte.
* Valid only when UHCI_HEAD_EN is 0.
*/
uint32_t pkt_thrs:13;
uint32_t reserved_13:19;
};
uint32_t val;
} uhci_pkt_thres_reg_t;
/** Group: UHCI Interrupt Register */
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of UHCI_RX_START_INT.
*/
uint32_t rx_start_int_raw:1;
/** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status of UHCI_TX_START_INT.
*/
uint32_t tx_start_int_raw:1;
/** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status of UHCI_RX_HUNG_INT.
*/
uint32_t rx_hung_int_raw:1;
/** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status of UHCI_TX_HUNG_INT.
*/
uint32_t tx_hung_int_raw:1;
/** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt status of UHCI_SEND_S_REG_Q_INT.
*/
uint32_t send_s_reg_q_int_raw:1;
/** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt status of UHCI_SEND_A_REG_Q_INT.
*/
uint32_t send_a_reg_q_int_raw:1;
/** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt status of UHCI_OUT_EOF_INT.
*/
uint32_t out_eof_int_raw:1;
/** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
* The raw interrupt status of UHCI_APP_CTRL0_INT.
*/
uint32_t app_ctrl0_int_raw:1;
/** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
* The raw interrupt status of UHCI_APP_CTRL1_INT.
*/
uint32_t app_ctrl1_int_raw:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_raw_reg_t;
/** Type of int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** rx_start_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of UHCI_RX_START_INT.
*/
uint32_t rx_start_int_st:1;
/** tx_start_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of UHCI_TX_START_INT.
*/
uint32_t tx_start_int_st:1;
/** rx_hung_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of UHCI_RX_HUNG_INT.
*/
uint32_t rx_hung_int_st:1;
/** tx_hung_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status of UHCI_TX_HUNG_INT.
*/
uint32_t tx_hung_int_st:1;
/** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status of UHCI_SEND_S_REG_Q_INT.
*/
uint32_t send_s_reg_q_int_st:1;
/** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status of UHCI_SEND_A_REG_Q_INT.
*/
uint32_t send_a_reg_q_int_st:1;
/** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status of UHCI_OUTLINK_EOF_ERR_INT.
*/
uint32_t outlink_eof_err_int_st:1;
/** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status of UHCI_APP_CTRL0_INT.
*/
uint32_t app_ctrl0_int_st:1;
/** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
* The masked interrupt status of UHCI_APP_CTRL1_INT.
*/
uint32_t app_ctrl1_int_st:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable UHCI_RX_START_INT.
*/
uint32_t rx_start_int_ena:1;
/** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable UHCI_TX_START_INT.
*/
uint32_t tx_start_int_ena:1;
/** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable UHCI_RX_HUNG_INT.
*/
uint32_t rx_hung_int_ena:1;
/** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
* Write 1 to enable UHCI_TX_HUNG_INT.
*/
uint32_t tx_hung_int_ena:1;
/** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
* Write 1 to enable UHCI_SEND_S_REG_Q_INT.
*/
uint32_t send_s_reg_q_int_ena:1;
/** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
* Write 1 to enable UHCI_SEND_A_REG_Q_INT.
*/
uint32_t send_a_reg_q_int_ena:1;
/** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
* Write 1 to enable UHCI_OUTLINK_EOF_ERR_INT.
*/
uint32_t outlink_eof_err_int_ena:1;
/** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
* Write 1 to enable UHCI_APP_CTRL0_INT.
*/
uint32_t app_ctrl0_int_ena:1;
/** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
* Write 1 to enable UHCI_APP_CTRL1_INT.
*/
uint32_t app_ctrl1_int_ena:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** rx_start_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear UHCI_RX_START_INT.
*/
uint32_t rx_start_int_clr:1;
/** tx_start_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear UHCI_TX_START_INT.
*/
uint32_t tx_start_int_clr:1;
/** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear UHCI_RX_HUNG_INT.
*/
uint32_t rx_hung_int_clr:1;
/** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
* Write 1 to clear UHCI_TX_HUNG_INT.
*/
uint32_t tx_hung_int_clr:1;
/** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
* Write 1 to clear UHCI_SEND_S_REG_Q_INT.
*/
uint32_t send_s_reg_q_int_clr:1;
/** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
* Write 1 to clear UHCI_SEND_A_REG_Q_INT.
*/
uint32_t send_a_reg_q_int_clr:1;
/** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
* Write 1 to clear UHCI_OUTLINK_EOF_ERR_INT.
*/
uint32_t outlink_eof_err_int_clr:1;
/** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
* Write 1 to clear UHCI_APP_CTRL0_INT.
*/
uint32_t app_ctrl0_int_clr:1;
/** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
* Write 1 to clear UHCI_APP_CTRL1_INT.
*/
uint32_t app_ctrl1_int_clr:1;
uint32_t reserved_9:23;
};
uint32_t val;
} uhci_int_clr_reg_t;
/** Group: UHCI Status Register */
/** Type of state0 register
* UHCI receive status
*/
typedef union {
struct {
/** rx_err_cause : RO; bitpos: [2:0]; default: 0;
* Represents the error type when DMA has received a packet with error.
* 0: Invalid. No effect
* 1: Checksum error in the HCI packet
* 2: Sequence number error in the HCI packet
* 3: CRC bit error in the HCI packet
* 4: 0xC0 is found but the received HCI packet is not complete\
* 5: 0xC0 is not found when the HCI packet has been received
* 6: CRC check error
* 7: Invalid. No effect
*/
uint32_t rx_err_cause:3;
/** decode_state : RO; bitpos: [5:3]; default: 0;
* Represents the UHCI decoder status.
*/
uint32_t decode_state:3;
uint32_t reserved_6:26;
};
uint32_t val;
} uhci_state0_reg_t;
/** Type of state1 register
* UHCI transmit status
*/
typedef union {
struct {
/** encode_state : RO; bitpos: [2:0]; default: 0;
* Represents the UHCI encoder status.
*/
uint32_t encode_state:3;
uint32_t reserved_3:29;
};
uint32_t val;
} uhci_state1_reg_t;
/** Type of rx_head register
* UHCI packet header register
*/
typedef union {
struct {
/** rx_head : RO; bitpos: [31:0]; default: 0;
* Represents the header of the current received packet.
*/
uint32_t rx_head:32;
};
uint32_t val;
} uhci_rx_head_reg_t;
/** Group: Version Register */
/** Type of date register
* UHCI version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 35655936;
* Version control register.
*/
uint32_t date:32;
};
uint32_t val;
} uhci_date_reg_t;
typedef struct {
volatile uhci_conf0_reg_t conf0;
volatile uhci_int_raw_reg_t int_raw;
volatile uhci_int_st_reg_t int_st;
volatile uhci_int_ena_reg_t int_ena;
volatile uhci_int_clr_reg_t int_clr;
volatile uhci_conf1_reg_t conf1;
volatile uhci_state0_reg_t state0;
volatile uhci_state1_reg_t state1;
volatile uhci_escape_conf_reg_t escape_conf;
volatile uhci_hung_conf_reg_t hung_conf;
volatile uhci_ack_num_reg_t ack_num;
volatile uhci_rx_head_reg_t rx_head;
volatile uhci_quick_sent_reg_t quick_sent;
volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
volatile uhci_esc_conf0_reg_t esc_conf0;
volatile uhci_esc_conf1_reg_t esc_conf1;
volatile uhci_esc_conf2_reg_t esc_conf2;
volatile uhci_esc_conf3_reg_t esc_conf3;
volatile uhci_pkt_thres_reg_t pkt_thres;
volatile uhci_date_reg_t date;
} uhci_dev_t;
extern uhci_dev_t UHCI0;
#ifndef __cplusplus
_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/zero_det_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ZERO_DET_CONF_REG register
* zero det cfg reg
*/
#define ZERO_DET_CONF_REG (DR_REG_ZERO_BASE + 0x0)
/** ZERO_DET_VREF_CHANNEL_SEL : R/W; bitpos: [3:0]; default: 8;
* vref pad sel,one hot code and cannot set the same bit with other channels
*/
#define ZERO_DET_VREF_CHANNEL_SEL 0x0000000FU
#define ZERO_DET_VREF_CHANNEL_SEL_M (ZERO_DET_VREF_CHANNEL_SEL_V << ZERO_DET_VREF_CHANNEL_SEL_S)
#define ZERO_DET_VREF_CHANNEL_SEL_V 0x0000000FU
#define ZERO_DET_VREF_CHANNEL_SEL_S 0
/** ZERO_DET_COMP_CHANNEL_3_SEL : R/W; bitpos: [7:4]; default: 4;
* Channel 3 comp pad sel,one hot code and cannot set the same bit with other channels
*/
#define ZERO_DET_COMP_CHANNEL_3_SEL 0x0000000FU
#define ZERO_DET_COMP_CHANNEL_3_SEL_M (ZERO_DET_COMP_CHANNEL_3_SEL_V << ZERO_DET_COMP_CHANNEL_3_SEL_S)
#define ZERO_DET_COMP_CHANNEL_3_SEL_V 0x0000000FU
#define ZERO_DET_COMP_CHANNEL_3_SEL_S 4
/** ZERO_DET_COMP_CHANNEL_2_SEL : R/W; bitpos: [11:8]; default: 2;
* Channel 2 comp pad sel,one hot code and cannot set the same bit with other channels
*/
#define ZERO_DET_COMP_CHANNEL_2_SEL 0x0000000FU
#define ZERO_DET_COMP_CHANNEL_2_SEL_M (ZERO_DET_COMP_CHANNEL_2_SEL_V << ZERO_DET_COMP_CHANNEL_2_SEL_S)
#define ZERO_DET_COMP_CHANNEL_2_SEL_V 0x0000000FU
#define ZERO_DET_COMP_CHANNEL_2_SEL_S 8
/** ZERO_DET_COMP_CHANNEL_1_SEL : R/W; bitpos: [15:12]; default: 1;
* Channel 1 comp pad sel,one hot code and cannot set the same bit with other channels
*/
#define ZERO_DET_COMP_CHANNEL_1_SEL 0x0000000FU
#define ZERO_DET_COMP_CHANNEL_1_SEL_M (ZERO_DET_COMP_CHANNEL_1_SEL_V << ZERO_DET_COMP_CHANNEL_1_SEL_S)
#define ZERO_DET_COMP_CHANNEL_1_SEL_V 0x0000000FU
#define ZERO_DET_COMP_CHANNEL_1_SEL_S 12
/** ZERO_DET_CHANNEL_3_EVENT_TIMER_EN : R/W; bitpos: [16]; default: 0;
* enable channel 3 event timer to trigger channel 1 event after
* pad_comp_channel_3_int
*/
#define ZERO_DET_CHANNEL_3_EVENT_TIMER_EN (BIT(16))
#define ZERO_DET_CHANNEL_3_EVENT_TIMER_EN_M (ZERO_DET_CHANNEL_3_EVENT_TIMER_EN_V << ZERO_DET_CHANNEL_3_EVENT_TIMER_EN_S)
#define ZERO_DET_CHANNEL_3_EVENT_TIMER_EN_V 0x00000001U
#define ZERO_DET_CHANNEL_3_EVENT_TIMER_EN_S 16
/** ZERO_DET_CHANNEL_2_EVENT_TIMER_EN : R/W; bitpos: [17]; default: 0;
* enable channel 2 event timer to trigger channel 1 event after
* pad_comp_channel_2_int
*/
#define ZERO_DET_CHANNEL_2_EVENT_TIMER_EN (BIT(17))
#define ZERO_DET_CHANNEL_2_EVENT_TIMER_EN_M (ZERO_DET_CHANNEL_2_EVENT_TIMER_EN_V << ZERO_DET_CHANNEL_2_EVENT_TIMER_EN_S)
#define ZERO_DET_CHANNEL_2_EVENT_TIMER_EN_V 0x00000001U
#define ZERO_DET_CHANNEL_2_EVENT_TIMER_EN_S 17
/** ZERO_DET_CHANNEL_1_EVENT_TIMER_EN : R/W; bitpos: [18]; default: 0;
* enable channel 1 event timer to trigger channel 1 event after
* pad_comp_channel_1_int
*/
#define ZERO_DET_CHANNEL_1_EVENT_TIMER_EN (BIT(18))
#define ZERO_DET_CHANNEL_1_EVENT_TIMER_EN_M (ZERO_DET_CHANNEL_1_EVENT_TIMER_EN_V << ZERO_DET_CHANNEL_1_EVENT_TIMER_EN_S)
#define ZERO_DET_CHANNEL_1_EVENT_TIMER_EN_V 0x00000001U
#define ZERO_DET_CHANNEL_1_EVENT_TIMER_EN_S 18
/** ZERO_DET_CHANNEL_TIMER_EN : R/W; bitpos: [19]; default: 0;
* enable timer to record the time between two continuous zero det int in each channel
*/
#define ZERO_DET_CHANNEL_TIMER_EN (BIT(19))
#define ZERO_DET_CHANNEL_TIMER_EN_M (ZERO_DET_CHANNEL_TIMER_EN_V << ZERO_DET_CHANNEL_TIMER_EN_S)
#define ZERO_DET_CHANNEL_TIMER_EN_V 0x00000001U
#define ZERO_DET_CHANNEL_TIMER_EN_S 19
/** ZERO_DET_LIMIT_CNT : R/W; bitpos: [27:20]; default: 5;
* cfg continuous zero det num to change zero det result
*/
#define ZERO_DET_LIMIT_CNT 0x000000FFU
#define ZERO_DET_LIMIT_CNT_M (ZERO_DET_LIMIT_CNT_V << ZERO_DET_LIMIT_CNT_S)
#define ZERO_DET_LIMIT_CNT_V 0x000000FFU
#define ZERO_DET_LIMIT_CNT_S 20
/** ZERO_DET_COMP_POLL_MASK : R/W; bitpos: [30:28]; default: 0;
* mask channel to do pad compare and zero det
*/
#define ZERO_DET_COMP_POLL_MASK 0x00000007U
#define ZERO_DET_COMP_POLL_MASK_M (ZERO_DET_COMP_POLL_MASK_V << ZERO_DET_COMP_POLL_MASK_S)
#define ZERO_DET_COMP_POLL_MASK_V 0x00000007U
#define ZERO_DET_COMP_POLL_MASK_S 28
/** ZERO_DET_COMP_POLL_MODE : R/W; bitpos: [31]; default: 0;
* cfg channel scan mode ,0 means one trigger scan all mask channel, 1 means one
* trigger scan one mask channel
*/
#define ZERO_DET_COMP_POLL_MODE (BIT(31))
#define ZERO_DET_COMP_POLL_MODE_M (ZERO_DET_COMP_POLL_MODE_V << ZERO_DET_COMP_POLL_MODE_S)
#define ZERO_DET_COMP_POLL_MODE_V 0x00000001U
#define ZERO_DET_COMP_POLL_MODE_S 31
/** ZERO_DET_FILTER_CNT_REG register
* protect time reg
*/
#define ZERO_DET_FILTER_CNT_REG (DR_REG_ZERO_BASE + 0x4)
/** ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 255;
* protect time after det the first zero det int
*/
#define ZERO_DET_FILTER_CNT 0xFFFFFFFFU
#define ZERO_DET_FILTER_CNT_M (ZERO_DET_FILTER_CNT_V << ZERO_DET_FILTER_CNT_S)
#define ZERO_DET_FILTER_CNT_V 0xFFFFFFFFU
#define ZERO_DET_FILTER_CNT_S 0
/** ZERO_DET_POLL_PERIOD_REG register
* poll period time reg
*/
#define ZERO_DET_POLL_PERIOD_REG (DR_REG_ZERO_BASE + 0x8)
/** ZERO_DET_COMP_POLL_PERIOD : R/W; bitpos: [15:0]; default: 15;
* poll period time for each channel
*/
#define ZERO_DET_COMP_POLL_PERIOD 0x0000FFFFU
#define ZERO_DET_COMP_POLL_PERIOD_M (ZERO_DET_COMP_POLL_PERIOD_V << ZERO_DET_COMP_POLL_PERIOD_S)
#define ZERO_DET_COMP_POLL_PERIOD_V 0x0000FFFFU
#define ZERO_DET_COMP_POLL_PERIOD_S 0
/** ZERO_DET_DELAY_EVENT_TIME_REG register
* delay time reg
*/
#define ZERO_DET_DELAY_EVENT_TIME_REG (DR_REG_ZERO_BASE + 0xc)
/** ZERO_DET_DELAY_EVENT_TIME : R/W; bitpos: [15:0]; default: 15;
* delay time after zero det int to trigger event for each channel
*/
#define ZERO_DET_DELAY_EVENT_TIME 0x0000FFFFU
#define ZERO_DET_DELAY_EVENT_TIME_M (ZERO_DET_DELAY_EVENT_TIME_V << ZERO_DET_DELAY_EVENT_TIME_S)
#define ZERO_DET_DELAY_EVENT_TIME_V 0x0000FFFFU
#define ZERO_DET_DELAY_EVENT_TIME_S 0
/** ZERO_DET_INT_ENA_REG register
* zero det int ena
*/
#define ZERO_DET_INT_ENA_REG (DR_REG_ZERO_BASE + 0x10)
/** ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ENA : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ENA (BIT(0))
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ENA_S 0
/** ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ENA : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ENA (BIT(1))
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ENA_S 1
/** ZERO_DET_PAD_COMP_CHANNEL_3_INT_ENA : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ENA (BIT(2))
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_3_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_3_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ENA_S 2
/** ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ENA : R/W; bitpos: [3]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ENA (BIT(3))
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ENA_S 3
/** ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ENA : R/W; bitpos: [4]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ENA (BIT(4))
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ENA_S 4
/** ZERO_DET_PAD_COMP_CHANNEL_2_INT_ENA : R/W; bitpos: [5]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ENA (BIT(5))
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_2_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_2_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ENA_S 5
/** ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ENA : R/W; bitpos: [6]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ENA (BIT(6))
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ENA_S 6
/** ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ENA : R/W; bitpos: [7]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ENA (BIT(7))
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ENA_S 7
/** ZERO_DET_PAD_COMP_CHANNEL_1_INT_ENA : R/W; bitpos: [8]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ENA (BIT(8))
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ENA_M (ZERO_DET_PAD_COMP_CHANNEL_1_INT_ENA_V << ZERO_DET_PAD_COMP_CHANNEL_1_INT_ENA_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ENA_S 8
/** ZERO_DET_PAD_COMP_NEG_INT_ENA : R/W; bitpos: [9]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_NEG_INT_ENA (BIT(9))
#define ZERO_DET_PAD_COMP_NEG_INT_ENA_M (ZERO_DET_PAD_COMP_NEG_INT_ENA_V << ZERO_DET_PAD_COMP_NEG_INT_ENA_S)
#define ZERO_DET_PAD_COMP_NEG_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_NEG_INT_ENA_S 9
/** ZERO_DET_PAD_COMP_POS_INT_ENA : R/W; bitpos: [10]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_POS_INT_ENA (BIT(10))
#define ZERO_DET_PAD_COMP_POS_INT_ENA_M (ZERO_DET_PAD_COMP_POS_INT_ENA_V << ZERO_DET_PAD_COMP_POS_INT_ENA_S)
#define ZERO_DET_PAD_COMP_POS_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_POS_INT_ENA_S 10
/** ZERO_DET_PAD_COMP_INT_ENA : R/W; bitpos: [11]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_INT_ENA (BIT(11))
#define ZERO_DET_PAD_COMP_INT_ENA_M (ZERO_DET_PAD_COMP_INT_ENA_V << ZERO_DET_PAD_COMP_INT_ENA_S)
#define ZERO_DET_PAD_COMP_INT_ENA_V 0x00000001U
#define ZERO_DET_PAD_COMP_INT_ENA_S 11
/** ZERO_DET_INT_RAW_REG register
* zero det int raw
*/
#define ZERO_DET_INT_RAW_REG (DR_REG_ZERO_BASE + 0x14)
/** ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_RAW (BIT(0))
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_RAW_S 0
/** ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_RAW (BIT(1))
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_RAW_S 1
/** ZERO_DET_PAD_COMP_CHANNEL_3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_RAW (BIT(2))
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_3_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_3_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_RAW_S 2
/** ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_RAW (BIT(3))
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_RAW_S 3
/** ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_RAW (BIT(4))
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_RAW_S 4
/** ZERO_DET_PAD_COMP_CHANNEL_2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_RAW (BIT(5))
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_2_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_2_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_RAW_S 5
/** ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_RAW (BIT(6))
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_RAW_S 6
/** ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_RAW (BIT(7))
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_RAW_S 7
/** ZERO_DET_PAD_COMP_CHANNEL_1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_RAW (BIT(8))
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_RAW_M (ZERO_DET_PAD_COMP_CHANNEL_1_INT_RAW_V << ZERO_DET_PAD_COMP_CHANNEL_1_INT_RAW_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_RAW_S 8
/** ZERO_DET_PAD_COMP_NEG_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_NEG_INT_RAW (BIT(9))
#define ZERO_DET_PAD_COMP_NEG_INT_RAW_M (ZERO_DET_PAD_COMP_NEG_INT_RAW_V << ZERO_DET_PAD_COMP_NEG_INT_RAW_S)
#define ZERO_DET_PAD_COMP_NEG_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_NEG_INT_RAW_S 9
/** ZERO_DET_PAD_COMP_POS_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_POS_INT_RAW (BIT(10))
#define ZERO_DET_PAD_COMP_POS_INT_RAW_M (ZERO_DET_PAD_COMP_POS_INT_RAW_V << ZERO_DET_PAD_COMP_POS_INT_RAW_S)
#define ZERO_DET_PAD_COMP_POS_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_POS_INT_RAW_S 10
/** ZERO_DET_PAD_COMP_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_INT_RAW (BIT(11))
#define ZERO_DET_PAD_COMP_INT_RAW_M (ZERO_DET_PAD_COMP_INT_RAW_V << ZERO_DET_PAD_COMP_INT_RAW_S)
#define ZERO_DET_PAD_COMP_INT_RAW_V 0x00000001U
#define ZERO_DET_PAD_COMP_INT_RAW_S 11
/** ZERO_DET_INT_CLR_REG register
* zero det int clr
*/
#define ZERO_DET_INT_CLR_REG (DR_REG_ZERO_BASE + 0x18)
/** ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_CLR : WT; bitpos: [0]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_CLR (BIT(0))
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_CLR_S 0
/** ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_CLR : WT; bitpos: [1]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_CLR (BIT(1))
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_CLR_S 1
/** ZERO_DET_PAD_COMP_CHANNEL_3_INT_CLR : WT; bitpos: [2]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_CLR (BIT(2))
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_3_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_3_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_CLR_S 2
/** ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_CLR : WT; bitpos: [3]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_CLR (BIT(3))
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_CLR_S 3
/** ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_CLR : WT; bitpos: [4]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_CLR (BIT(4))
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_CLR_S 4
/** ZERO_DET_PAD_COMP_CHANNEL_2_INT_CLR : WT; bitpos: [5]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_CLR (BIT(5))
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_2_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_2_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_CLR_S 5
/** ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_CLR : WT; bitpos: [6]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_CLR (BIT(6))
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_CLR_S 6
/** ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_CLR : WT; bitpos: [7]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_CLR (BIT(7))
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_CLR_S 7
/** ZERO_DET_PAD_COMP_CHANNEL_1_INT_CLR : WT; bitpos: [8]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_CLR (BIT(8))
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_CLR_M (ZERO_DET_PAD_COMP_CHANNEL_1_INT_CLR_V << ZERO_DET_PAD_COMP_CHANNEL_1_INT_CLR_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_CLR_S 8
/** ZERO_DET_PAD_COMP_NEG_INT_CLR : WT; bitpos: [9]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_NEG_INT_CLR (BIT(9))
#define ZERO_DET_PAD_COMP_NEG_INT_CLR_M (ZERO_DET_PAD_COMP_NEG_INT_CLR_V << ZERO_DET_PAD_COMP_NEG_INT_CLR_S)
#define ZERO_DET_PAD_COMP_NEG_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_NEG_INT_CLR_S 9
/** ZERO_DET_PAD_COMP_POS_INT_CLR : WT; bitpos: [10]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_POS_INT_CLR (BIT(10))
#define ZERO_DET_PAD_COMP_POS_INT_CLR_M (ZERO_DET_PAD_COMP_POS_INT_CLR_V << ZERO_DET_PAD_COMP_POS_INT_CLR_S)
#define ZERO_DET_PAD_COMP_POS_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_POS_INT_CLR_S 10
/** ZERO_DET_PAD_COMP_INT_CLR : WT; bitpos: [11]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_INT_CLR (BIT(11))
#define ZERO_DET_PAD_COMP_INT_CLR_M (ZERO_DET_PAD_COMP_INT_CLR_V << ZERO_DET_PAD_COMP_INT_CLR_S)
#define ZERO_DET_PAD_COMP_INT_CLR_V 0x00000001U
#define ZERO_DET_PAD_COMP_INT_CLR_S 11
/** ZERO_DET_INT_ST_REG register
* zero det int st
*/
#define ZERO_DET_INT_ST_REG (DR_REG_ZERO_BASE + 0x1c)
/** ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ST : RO; bitpos: [0]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ST (BIT(0))
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_NEG_INT_ST_S 0
/** ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ST : RO; bitpos: [1]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ST (BIT(1))
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_POS_INT_ST_S 1
/** ZERO_DET_PAD_COMP_CHANNEL_3_INT_ST : RO; bitpos: [2]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ST (BIT(2))
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_3_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_3_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_3_INT_ST_S 2
/** ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ST : RO; bitpos: [3]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ST (BIT(3))
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_NEG_INT_ST_S 3
/** ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ST : RO; bitpos: [4]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ST (BIT(4))
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_POS_INT_ST_S 4
/** ZERO_DET_PAD_COMP_CHANNEL_2_INT_ST : RO; bitpos: [5]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ST (BIT(5))
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_2_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_2_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_2_INT_ST_S 5
/** ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ST : RO; bitpos: [6]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ST (BIT(6))
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_NEG_INT_ST_S 6
/** ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ST : RO; bitpos: [7]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ST (BIT(7))
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_POS_INT_ST_S 7
/** ZERO_DET_PAD_COMP_CHANNEL_1_INT_ST : RO; bitpos: [8]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ST (BIT(8))
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ST_M (ZERO_DET_PAD_COMP_CHANNEL_1_INT_ST_V << ZERO_DET_PAD_COMP_CHANNEL_1_INT_ST_S)
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_CHANNEL_1_INT_ST_S 8
/** ZERO_DET_PAD_COMP_NEG_INT_ST : RO; bitpos: [9]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_NEG_INT_ST (BIT(9))
#define ZERO_DET_PAD_COMP_NEG_INT_ST_M (ZERO_DET_PAD_COMP_NEG_INT_ST_V << ZERO_DET_PAD_COMP_NEG_INT_ST_S)
#define ZERO_DET_PAD_COMP_NEG_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_NEG_INT_ST_S 9
/** ZERO_DET_PAD_COMP_POS_INT_ST : RO; bitpos: [10]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_POS_INT_ST (BIT(10))
#define ZERO_DET_PAD_COMP_POS_INT_ST_M (ZERO_DET_PAD_COMP_POS_INT_ST_V << ZERO_DET_PAD_COMP_POS_INT_ST_S)
#define ZERO_DET_PAD_COMP_POS_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_POS_INT_ST_S 10
/** ZERO_DET_PAD_COMP_INT_ST : RO; bitpos: [11]; default: 0;
* reserved
*/
#define ZERO_DET_PAD_COMP_INT_ST (BIT(11))
#define ZERO_DET_PAD_COMP_INT_ST_M (ZERO_DET_PAD_COMP_INT_ST_V << ZERO_DET_PAD_COMP_INT_ST_S)
#define ZERO_DET_PAD_COMP_INT_ST_V 0x00000001U
#define ZERO_DET_PAD_COMP_INT_ST_S 11
/** ZERO_DET_CHANNEL_1_TIMER0_REG register
* record timer reg
*/
#define ZERO_DET_CHANNEL_1_TIMER0_REG (DR_REG_ZERO_BASE + 0x20)
/** ZERO_DET_CHANNEL_1_TIMER0 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the first zero det int in channel 1
*/
#define ZERO_DET_CHANNEL_1_TIMER0 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_1_TIMER0_M (ZERO_DET_CHANNEL_1_TIMER0_V << ZERO_DET_CHANNEL_1_TIMER0_S)
#define ZERO_DET_CHANNEL_1_TIMER0_V 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_1_TIMER0_S 0
/** ZERO_DET_CHANNEL_1_TIMER1_REG register
* record timer reg
*/
#define ZERO_DET_CHANNEL_1_TIMER1_REG (DR_REG_ZERO_BASE + 0x24)
/** ZERO_DET_CHANNEL_1_TIMER1 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the second zero det int in channel 1
*/
#define ZERO_DET_CHANNEL_1_TIMER1 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_1_TIMER1_M (ZERO_DET_CHANNEL_1_TIMER1_V << ZERO_DET_CHANNEL_1_TIMER1_S)
#define ZERO_DET_CHANNEL_1_TIMER1_V 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_1_TIMER1_S 0
/** ZERO_DET_CHANNEL_2_TIMER0_REG register
* record timer reg
*/
#define ZERO_DET_CHANNEL_2_TIMER0_REG (DR_REG_ZERO_BASE + 0x28)
/** ZERO_DET_CHANNEL_2_TIMER0 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the first zero det int in channel 2
*/
#define ZERO_DET_CHANNEL_2_TIMER0 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_2_TIMER0_M (ZERO_DET_CHANNEL_2_TIMER0_V << ZERO_DET_CHANNEL_2_TIMER0_S)
#define ZERO_DET_CHANNEL_2_TIMER0_V 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_2_TIMER0_S 0
/** ZERO_DET_CHANNEL_2_TIMER1_REG register
* record timer reg
*/
#define ZERO_DET_CHANNEL_2_TIMER1_REG (DR_REG_ZERO_BASE + 0x2c)
/** ZERO_DET_CHANNEL_2_TIMER1 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the second zero det int in channel 2
*/
#define ZERO_DET_CHANNEL_2_TIMER1 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_2_TIMER1_M (ZERO_DET_CHANNEL_2_TIMER1_V << ZERO_DET_CHANNEL_2_TIMER1_S)
#define ZERO_DET_CHANNEL_2_TIMER1_V 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_2_TIMER1_S 0
/** ZERO_DET_CHANNEL_3_TIMER0_REG register
* record timer reg
*/
#define ZERO_DET_CHANNEL_3_TIMER0_REG (DR_REG_ZERO_BASE + 0x30)
/** ZERO_DET_CHANNEL_3_TIMER0 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the first zero det int in channel 3
*/
#define ZERO_DET_CHANNEL_3_TIMER0 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_3_TIMER0_M (ZERO_DET_CHANNEL_3_TIMER0_V << ZERO_DET_CHANNEL_3_TIMER0_S)
#define ZERO_DET_CHANNEL_3_TIMER0_V 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_3_TIMER0_S 0
/** ZERO_DET_CHANNEL_3_TIMER1_REG register
* record timer reg
*/
#define ZERO_DET_CHANNEL_3_TIMER1_REG (DR_REG_ZERO_BASE + 0x34)
/** ZERO_DET_CHANNEL_3_TIMER1 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the second zero det int in channel 3
*/
#define ZERO_DET_CHANNEL_3_TIMER1 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_3_TIMER1_M (ZERO_DET_CHANNEL_3_TIMER1_V << ZERO_DET_CHANNEL_3_TIMER1_S)
#define ZERO_DET_CHANNEL_3_TIMER1_V 0xFFFFFFFFU
#define ZERO_DET_CHANNEL_3_TIMER1_S 0
/** ZERO_DET_CHANNEL_STATUS_REG register
* pad comp status reg
*/
#define ZERO_DET_CHANNEL_STATUS_REG (DR_REG_ZERO_BASE + 0x38)
/** ZERO_DET_CHANNEL_3_PAD_COMP_STATUS : RO; bitpos: [0]; default: 0;
* record the pad comp status for channel 3, 0 means now is neg int , 1 means now is
* pos int
*/
#define ZERO_DET_CHANNEL_3_PAD_COMP_STATUS (BIT(0))
#define ZERO_DET_CHANNEL_3_PAD_COMP_STATUS_M (ZERO_DET_CHANNEL_3_PAD_COMP_STATUS_V << ZERO_DET_CHANNEL_3_PAD_COMP_STATUS_S)
#define ZERO_DET_CHANNEL_3_PAD_COMP_STATUS_V 0x00000001U
#define ZERO_DET_CHANNEL_3_PAD_COMP_STATUS_S 0
/** ZERO_DET_CHANNEL_2_PAD_COMP_STATUS : RO; bitpos: [1]; default: 0;
* record the pad comp status for channel 2, 0 means now is neg int , 1 means now is
* pos int
*/
#define ZERO_DET_CHANNEL_2_PAD_COMP_STATUS (BIT(1))
#define ZERO_DET_CHANNEL_2_PAD_COMP_STATUS_M (ZERO_DET_CHANNEL_2_PAD_COMP_STATUS_V << ZERO_DET_CHANNEL_2_PAD_COMP_STATUS_S)
#define ZERO_DET_CHANNEL_2_PAD_COMP_STATUS_V 0x00000001U
#define ZERO_DET_CHANNEL_2_PAD_COMP_STATUS_S 1
/** ZERO_DET_CHANNEL_1_PAD_COMP_STATUS : RO; bitpos: [2]; default: 0;
* record the pad comp status for channel 1, 0 means now is neg int , 1 means now is
* pos int
*/
#define ZERO_DET_CHANNEL_1_PAD_COMP_STATUS (BIT(2))
#define ZERO_DET_CHANNEL_1_PAD_COMP_STATUS_M (ZERO_DET_CHANNEL_1_PAD_COMP_STATUS_V << ZERO_DET_CHANNEL_1_PAD_COMP_STATUS_S)
#define ZERO_DET_CHANNEL_1_PAD_COMP_STATUS_V 0x00000001U
#define ZERO_DET_CHANNEL_1_PAD_COMP_STATUS_S 2
/** ZERO_DET_PAD_COMP_CFG_REG register
* pad comp cfg reg
*/
#define ZERO_DET_PAD_COMP_CFG_REG (DR_REG_ZERO_BASE + 0x3c)
/** ZERO_DET_PAD_COMP_HYS : R/W; bitpos: [2:0]; default: 0;
* hys cfg signal
*/
#define ZERO_DET_PAD_COMP_HYS 0x00000007U
#define ZERO_DET_PAD_COMP_HYS_M (ZERO_DET_PAD_COMP_HYS_V << ZERO_DET_PAD_COMP_HYS_S)
#define ZERO_DET_PAD_COMP_HYS_V 0x00000007U
#define ZERO_DET_PAD_COMP_HYS_S 0
/** ZERO_DET_PAD_COMP_HYS_EN : R/W; bitpos: [3]; default: 0;
* enable hys function,only works while pad comp mode = 0
*/
#define ZERO_DET_PAD_COMP_HYS_EN (BIT(3))
#define ZERO_DET_PAD_COMP_HYS_EN_M (ZERO_DET_PAD_COMP_HYS_EN_V << ZERO_DET_PAD_COMP_HYS_EN_S)
#define ZERO_DET_PAD_COMP_HYS_EN_V 0x00000001U
#define ZERO_DET_PAD_COMP_HYS_EN_S 3
/** ZERO_DET_PAD_COMP_DREF : R/W; bitpos: [6:4]; default: 0;
* internal vref cfg signal,0~2.3v step is 330mv
*/
#define ZERO_DET_PAD_COMP_DREF 0x00000007U
#define ZERO_DET_PAD_COMP_DREF_M (ZERO_DET_PAD_COMP_DREF_V << ZERO_DET_PAD_COMP_DREF_S)
#define ZERO_DET_PAD_COMP_DREF_V 0x00000007U
#define ZERO_DET_PAD_COMP_DREF_S 4
/** ZERO_DET_PAD_COMP_MODE : R/W; bitpos: [7]; default: 0;
* pad comp mode cfg 1:external pad 0:internal vref
*/
#define ZERO_DET_PAD_COMP_MODE (BIT(7))
#define ZERO_DET_PAD_COMP_MODE_M (ZERO_DET_PAD_COMP_MODE_V << ZERO_DET_PAD_COMP_MODE_S)
#define ZERO_DET_PAD_COMP_MODE_V 0x00000001U
#define ZERO_DET_PAD_COMP_MODE_S 7
/** ZERO_DET_PAD_COMP_XPD : R/W; bitpos: [8]; default: 0;
* pad comp xpd
*/
#define ZERO_DET_PAD_COMP_XPD (BIT(8))
#define ZERO_DET_PAD_COMP_XPD_M (ZERO_DET_PAD_COMP_XPD_V << ZERO_DET_PAD_COMP_XPD_S)
#define ZERO_DET_PAD_COMP_XPD_V 0x00000001U
#define ZERO_DET_PAD_COMP_XPD_S 8
/** ZERO_DET_DATE_REG register
* date reg
*/
#define ZERO_DET_DATE_REG (DR_REG_ZERO_BASE + 0x40)
/** ZERO_DET_DATE : R/W; bitpos: [27:0]; default: 37773696;
* zero det reg change date
*/
#define ZERO_DET_DATE 0x0FFFFFFFU
#define ZERO_DET_DATE_M (ZERO_DET_DATE_V << ZERO_DET_DATE_S)
#define ZERO_DET_DATE_V 0x0FFFFFFFU
#define ZERO_DET_DATE_S 0
/** ZERO_DET_CLK_EN : R/W; bitpos: [28]; default: 0;
* reg clk en
*/
#define ZERO_DET_CLK_EN (BIT(28))
#define ZERO_DET_CLK_EN_M (ZERO_DET_CLK_EN_V << ZERO_DET_CLK_EN_S)
#define ZERO_DET_CLK_EN_V 0x00000001U
#define ZERO_DET_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/zero_det_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of det_conf register
* zero det cfg reg
*/
typedef union {
struct {
/** det_vref_channel_sel : R/W; bitpos: [3:0]; default: 8;
* vref pad sel,one hot code and cannot set the same bit with other channels
*/
uint32_t det_vref_channel_sel:4;
/** det_comp_channel_3_sel : R/W; bitpos: [7:4]; default: 4;
* Channel 3 comp pad sel,one hot code and cannot set the same bit with other channels
*/
uint32_t det_comp_channel_3_sel:4;
/** det_comp_channel_2_sel : R/W; bitpos: [11:8]; default: 2;
* Channel 2 comp pad sel,one hot code and cannot set the same bit with other channels
*/
uint32_t det_comp_channel_2_sel:4;
/** det_comp_channel_1_sel : R/W; bitpos: [15:12]; default: 1;
* Channel 1 comp pad sel,one hot code and cannot set the same bit with other channels
*/
uint32_t det_comp_channel_1_sel:4;
/** det_channel_3_event_timer_en : R/W; bitpos: [16]; default: 0;
* enable channel 3 event timer to trigger channel 1 event after
* pad_comp_channel_3_int
*/
uint32_t det_channel_3_event_timer_en:1;
/** det_channel_2_event_timer_en : R/W; bitpos: [17]; default: 0;
* enable channel 2 event timer to trigger channel 1 event after
* pad_comp_channel_2_int
*/
uint32_t det_channel_2_event_timer_en:1;
/** det_channel_1_event_timer_en : R/W; bitpos: [18]; default: 0;
* enable channel 1 event timer to trigger channel 1 event after
* pad_comp_channel_1_int
*/
uint32_t det_channel_1_event_timer_en:1;
/** det_channel_timer_en : R/W; bitpos: [19]; default: 0;
* enable timer to record the time between two continuous zero det int in each channel
*/
uint32_t det_channel_timer_en:1;
/** det_limit_cnt : R/W; bitpos: [27:20]; default: 5;
* cfg continuous zero det num to change zero det result
*/
uint32_t det_limit_cnt:8;
/** det_comp_poll_mask : R/W; bitpos: [30:28]; default: 0;
* mask channel to do pad compare and zero det
*/
uint32_t det_comp_poll_mask:3;
/** det_comp_poll_mode : R/W; bitpos: [31]; default: 0;
* cfg channel scan mode ,0 means one trigger scan all mask channel, 1 means one
* trigger scan one mask channel
*/
uint32_t det_comp_poll_mode:1;
};
uint32_t val;
} zero_det_conf_reg_t;
/** Type of det_filter_cnt register
* protect time reg
*/
typedef union {
struct {
/** det_filter_cnt : R/W; bitpos: [31:0]; default: 255;
* protect time after det the first zero det int
*/
uint32_t det_filter_cnt:32;
};
uint32_t val;
} zero_det_filter_cnt_reg_t;
/** Type of det_poll_period register
* poll period time reg
*/
typedef union {
struct {
/** det_comp_poll_period : R/W; bitpos: [15:0]; default: 15;
* poll period time for each channel
*/
uint32_t det_comp_poll_period:16;
uint32_t reserved_16:16;
};
uint32_t val;
} zero_det_poll_period_reg_t;
/** Type of det_delay_event_time register
* delay time reg
*/
typedef union {
struct {
/** det_delay_event_time : R/W; bitpos: [15:0]; default: 15;
* delay time after zero det int to trigger event for each channel
*/
uint32_t det_delay_event_time:16;
uint32_t reserved_16:16;
};
uint32_t val;
} zero_det_delay_event_time_reg_t;
/** Type of det_int_ena register
* zero det int ena
*/
typedef union {
struct {
/** det_pad_comp_channel_3_neg_int_ena : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_neg_int_ena:1;
/** det_pad_comp_channel_3_pos_int_ena : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_pos_int_ena:1;
/** det_pad_comp_channel_3_int_ena : R/W; bitpos: [2]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_int_ena:1;
/** det_pad_comp_channel_2_neg_int_ena : R/W; bitpos: [3]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_neg_int_ena:1;
/** det_pad_comp_channel_2_pos_int_ena : R/W; bitpos: [4]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_pos_int_ena:1;
/** det_pad_comp_channel_2_int_ena : R/W; bitpos: [5]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_int_ena:1;
/** det_pad_comp_channel_1_neg_int_ena : R/W; bitpos: [6]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_neg_int_ena:1;
/** det_pad_comp_channel_1_pos_int_ena : R/W; bitpos: [7]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_pos_int_ena:1;
/** det_pad_comp_channel_1_int_ena : R/W; bitpos: [8]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_int_ena:1;
/** det_pad_comp_neg_int_ena : R/W; bitpos: [9]; default: 0;
* reserved
*/
uint32_t det_pad_comp_neg_int_ena:1;
/** det_pad_comp_pos_int_ena : R/W; bitpos: [10]; default: 0;
* reserved
*/
uint32_t det_pad_comp_pos_int_ena:1;
/** det_pad_comp_int_ena : R/W; bitpos: [11]; default: 0;
* reserved
*/
uint32_t det_pad_comp_int_ena:1;
uint32_t reserved_12:20;
};
uint32_t val;
} zero_det_int_ena_reg_t;
/** Type of det_int_raw register
* zero det int raw
*/
typedef union {
struct {
/** det_pad_comp_channel_3_neg_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_neg_int_raw:1;
/** det_pad_comp_channel_3_pos_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_pos_int_raw:1;
/** det_pad_comp_channel_3_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_int_raw:1;
/** det_pad_comp_channel_2_neg_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_neg_int_raw:1;
/** det_pad_comp_channel_2_pos_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_pos_int_raw:1;
/** det_pad_comp_channel_2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_int_raw:1;
/** det_pad_comp_channel_1_neg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_neg_int_raw:1;
/** det_pad_comp_channel_1_pos_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_pos_int_raw:1;
/** det_pad_comp_channel_1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_int_raw:1;
/** det_pad_comp_neg_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* reserved
*/
uint32_t det_pad_comp_neg_int_raw:1;
/** det_pad_comp_pos_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* reserved
*/
uint32_t det_pad_comp_pos_int_raw:1;
/** det_pad_comp_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* reserved
*/
uint32_t det_pad_comp_int_raw:1;
uint32_t reserved_12:20;
};
uint32_t val;
} zero_det_int_raw_reg_t;
/** Type of det_int_clr register
* zero det int clr
*/
typedef union {
struct {
/** det_pad_comp_channel_3_neg_int_clr : WT; bitpos: [0]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_neg_int_clr:1;
/** det_pad_comp_channel_3_pos_int_clr : WT; bitpos: [1]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_pos_int_clr:1;
/** det_pad_comp_channel_3_int_clr : WT; bitpos: [2]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_int_clr:1;
/** det_pad_comp_channel_2_neg_int_clr : WT; bitpos: [3]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_neg_int_clr:1;
/** det_pad_comp_channel_2_pos_int_clr : WT; bitpos: [4]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_pos_int_clr:1;
/** det_pad_comp_channel_2_int_clr : WT; bitpos: [5]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_int_clr:1;
/** det_pad_comp_channel_1_neg_int_clr : WT; bitpos: [6]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_neg_int_clr:1;
/** det_pad_comp_channel_1_pos_int_clr : WT; bitpos: [7]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_pos_int_clr:1;
/** det_pad_comp_channel_1_int_clr : WT; bitpos: [8]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_int_clr:1;
/** det_pad_comp_neg_int_clr : WT; bitpos: [9]; default: 0;
* reserved
*/
uint32_t det_pad_comp_neg_int_clr:1;
/** det_pad_comp_pos_int_clr : WT; bitpos: [10]; default: 0;
* reserved
*/
uint32_t det_pad_comp_pos_int_clr:1;
/** det_pad_comp_int_clr : WT; bitpos: [11]; default: 0;
* reserved
*/
uint32_t det_pad_comp_int_clr:1;
uint32_t reserved_12:20;
};
uint32_t val;
} zero_det_int_clr_reg_t;
/** Type of det_int_st register
* zero det int st
*/
typedef union {
struct {
/** det_pad_comp_channel_3_neg_int_st : RO; bitpos: [0]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_neg_int_st:1;
/** det_pad_comp_channel_3_pos_int_st : RO; bitpos: [1]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_pos_int_st:1;
/** det_pad_comp_channel_3_int_st : RO; bitpos: [2]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_3_int_st:1;
/** det_pad_comp_channel_2_neg_int_st : RO; bitpos: [3]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_neg_int_st:1;
/** det_pad_comp_channel_2_pos_int_st : RO; bitpos: [4]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_pos_int_st:1;
/** det_pad_comp_channel_2_int_st : RO; bitpos: [5]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_2_int_st:1;
/** det_pad_comp_channel_1_neg_int_st : RO; bitpos: [6]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_neg_int_st:1;
/** det_pad_comp_channel_1_pos_int_st : RO; bitpos: [7]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_pos_int_st:1;
/** det_pad_comp_channel_1_int_st : RO; bitpos: [8]; default: 0;
* reserved
*/
uint32_t det_pad_comp_channel_1_int_st:1;
/** det_pad_comp_neg_int_st : RO; bitpos: [9]; default: 0;
* reserved
*/
uint32_t det_pad_comp_neg_int_st:1;
/** det_pad_comp_pos_int_st : RO; bitpos: [10]; default: 0;
* reserved
*/
uint32_t det_pad_comp_pos_int_st:1;
/** det_pad_comp_int_st : RO; bitpos: [11]; default: 0;
* reserved
*/
uint32_t det_pad_comp_int_st:1;
uint32_t reserved_12:20;
};
uint32_t val;
} zero_det_int_st_reg_t;
/** Type of det_channel_1_timer0 register
* record timer reg
*/
typedef union {
struct {
/** det_channel_1_timer0 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the first zero det int in channel 1
*/
uint32_t det_channel_1_timer0:32;
};
uint32_t val;
} zero_det_channel_1_timer0_reg_t;
/** Type of det_channel_1_timer1 register
* record timer reg
*/
typedef union {
struct {
/** det_channel_1_timer1 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the second zero det int in channel 1
*/
uint32_t det_channel_1_timer1:32;
};
uint32_t val;
} zero_det_channel_1_timer1_reg_t;
/** Type of det_channel_2_timer0 register
* record timer reg
*/
typedef union {
struct {
/** det_channel_2_timer0 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the first zero det int in channel 2
*/
uint32_t det_channel_2_timer0:32;
};
uint32_t val;
} zero_det_channel_2_timer0_reg_t;
/** Type of det_channel_2_timer1 register
* record timer reg
*/
typedef union {
struct {
/** det_channel_2_timer1 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the second zero det int in channel 2
*/
uint32_t det_channel_2_timer1:32;
};
uint32_t val;
} zero_det_channel_2_timer1_reg_t;
/** Type of det_channel_3_timer0 register
* record timer reg
*/
typedef union {
struct {
/** det_channel_3_timer0 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the first zero det int in channel 3
*/
uint32_t det_channel_3_timer0:32;
};
uint32_t val;
} zero_det_channel_3_timer0_reg_t;
/** Type of det_channel_3_timer1 register
* record timer reg
*/
typedef union {
struct {
/** det_channel_3_timer1 : RO; bitpos: [31:0]; default: 0;
* record the time while detect the second zero det int in channel 3
*/
uint32_t det_channel_3_timer1:32;
};
uint32_t val;
} zero_det_channel_3_timer1_reg_t;
/** Type of det_channel_status register
* pad comp status reg
*/
typedef union {
struct {
/** det_channel_3_pad_comp_status : RO; bitpos: [0]; default: 0;
* record the pad comp status for channel 3, 0 means now is neg int , 1 means now is
* pos int
*/
uint32_t det_channel_3_pad_comp_status:1;
/** det_channel_2_pad_comp_status : RO; bitpos: [1]; default: 0;
* record the pad comp status for channel 2, 0 means now is neg int , 1 means now is
* pos int
*/
uint32_t det_channel_2_pad_comp_status:1;
/** det_channel_1_pad_comp_status : RO; bitpos: [2]; default: 0;
* record the pad comp status for channel 1, 0 means now is neg int , 1 means now is
* pos int
*/
uint32_t det_channel_1_pad_comp_status:1;
uint32_t reserved_3:29;
};
uint32_t val;
} zero_det_channel_status_reg_t;
/** Type of det_pad_comp_cfg register
* pad comp cfg reg
*/
typedef union {
struct {
/** det_pad_comp_hys : R/W; bitpos: [2:0]; default: 0;
* hys cfg signal
*/
uint32_t det_pad_comp_hys:3;
/** det_pad_comp_hys_en : R/W; bitpos: [3]; default: 0;
* enable hys function,only works while pad comp mode = 0
*/
uint32_t det_pad_comp_hys_en:1;
/** det_pad_comp_dref : R/W; bitpos: [6:4]; default: 0;
* internal vref cfg signal,0~2.3v step is 330mv
*/
uint32_t det_pad_comp_dref:3;
/** det_pad_comp_mode : R/W; bitpos: [7]; default: 0;
* pad comp mode cfg 1:external pad 0:internal vref
*/
uint32_t det_pad_comp_mode:1;
/** det_pad_comp_xpd : R/W; bitpos: [8]; default: 0;
* pad comp xpd
*/
uint32_t det_pad_comp_xpd:1;
uint32_t reserved_9:23;
};
uint32_t val;
} zero_det_pad_comp_cfg_reg_t;
/** Group: Version Register */
/** Type of det_date register
* date reg
*/
typedef union {
struct {
/** det_date : R/W; bitpos: [27:0]; default: 37773696;
* zero det reg change date
*/
uint32_t det_date:28;
/** det_clk_en : R/W; bitpos: [28]; default: 0;
* reg clk en
*/
uint32_t det_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} zero_det_date_reg_t;
typedef struct {
volatile zero_det_conf_reg_t det_conf;
volatile zero_det_filter_cnt_reg_t det_filter_cnt;
volatile zero_det_poll_period_reg_t det_poll_period;
volatile zero_det_delay_event_time_reg_t det_delay_event_time;
volatile zero_det_int_ena_reg_t det_int_ena;
volatile zero_det_int_raw_reg_t det_int_raw;
volatile zero_det_int_clr_reg_t det_int_clr;
volatile zero_det_int_st_reg_t det_int_st;
volatile zero_det_channel_1_timer0_reg_t det_channel_1_timer0;
volatile zero_det_channel_1_timer1_reg_t det_channel_1_timer1;
volatile zero_det_channel_2_timer0_reg_t det_channel_2_timer0;
volatile zero_det_channel_2_timer1_reg_t det_channel_2_timer1;
volatile zero_det_channel_3_timer0_reg_t det_channel_3_timer0;
volatile zero_det_channel_3_timer1_reg_t det_channel_3_timer1;
volatile zero_det_channel_status_reg_t det_channel_status;
volatile zero_det_pad_comp_cfg_reg_t det_pad_comp_cfg;
volatile zero_det_date_reg_t det_date;
} zero_dev_t;
extern zero_dev_t ZERO_DET;
#ifndef __cplusplus
_Static_assert(sizeof(zero_dev_t) == 0x44, "Invalid size of zero_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif