Merge branch 'bugfix/cpu_utils_watchpoint_num' into 'master'

xtensa: fix swapped breakpoint and watchpoint numbers

Closes IDFCI-1315

See merge request espressif/esp-idf!19213
This commit is contained in:
Ivan Grokhotkov
2022-07-26 20:31:10 +08:00

View File

@@ -116,7 +116,7 @@ FORCE_INLINE_ATTR uint32_t xt_utils_intr_get_enabled_mask(void)
FORCE_INLINE_ATTR void xt_utils_set_breakpoint(int bp_num, uint32_t bp_addr)
{
//Set the breakpoint's address
if (bp_num == 0) {
if (bp_num == 1) {
WSR(IBREAKA_1, bp_addr);
} else {
WSR(IBREAKA_0, bp_addr);
@@ -137,7 +137,7 @@ FORCE_INLINE_ATTR void xt_utils_clear_breakpoint(int bp_num)
WSR(IBREAKENABLE, bp_en);
// Zero the break address register
uint32_t bp_addr = 0;
if (bp_num == 0) {
if (bp_num == 1) {
WSR(IBREAKA_1, bp_addr);
} else {
WSR(IBREAKA_0, bp_addr);
@@ -161,7 +161,7 @@ FORCE_INLINE_ATTR void xt_utils_set_watchpoint(int wp_num,
dbreakc_reg |= BIT(31);
}
// Enable break address and break control register
if (wp_num == 0) {
if (wp_num == 1) {
WSR(DBREAKA_1, (uint32_t) wp_addr);
WSR(DBREAKC_1, dbreakc_reg);
} else {
@@ -173,7 +173,7 @@ FORCE_INLINE_ATTR void xt_utils_set_watchpoint(int wp_num,
FORCE_INLINE_ATTR void xt_utils_clear_watchpoint(int wp_num)
{
// Clear both break control and break address register
if (wp_num == 0) {
if (wp_num == 1) {
WSR(DBREAKC_1, 0);
WSR(DBREAKA_1, 0);
} else {