feedc0de/esp-idf
1
0
Fork 0
forked from espressif/esp-idf
Code Pull Requests Activity

Merge branch 'bugfix/fix_tbtt_interrupt_timing_error' into 'master'

Browse Source 
fix(pm): fix tbtt interrupt timing error when BLE RTC is configured to use...

Closes WIFIBUG-1151

See merge request espressif/esp-idf!38771
This commit is contained in:
Jiang Jiang Jian
2025-04-29 11:12:30 +08:00
parent 8d8bf19395 26d6f0fc13
commit c508207349
7 changed files with 15 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
components/esp_hw_support/include/esp_private/esp_pmu.h
View File

@ -332,15 +332,6 @@ bool pmu_sleep_finish(bool dslp);
*/
void pmu_init(void);
/**
* @brief Enable or disable system clock in PMU HP sleep state
*
* This API only used for fix BLE 40 MHz low power clock source issue
*
* @param enable true to enable, false to disable
*/
void pmu_sleep_enable_hp_sleep_sysclk(bool enable);
/**
* Get the time overhead used by regdma to work on the retention link during the hardware wake-up process
* @return regdma time cost during hardware wake-up stage in microseconds

3
components/esp_hw_support/include/esp_private/esp_sleep_internal.h
View File

@ -94,6 +94,9 @@ typedef enum {
ESP_SLEEP_CLOCK_UART1, //!< The clock ICG cell mapping of UART1
#if SOC_UART_HP_NUM > 2
ESP_SLEEP_CLOCK_UART2, //!< The clock ICG cell mapping of UART2
#endif
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK, //!< The clock ICG cell remapping of RETENTION
#endif
ESP_SLEEP_CLOCK_MAX //!< Number of ICG cells
} esp_sleep_clock_t;

5
components/esp_hw_support/modem_clock.c
View File

@ -13,6 +13,7 @@
#include "soc/soc_caps.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/esp_modem_clock.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/esp_pmu.h"
#include "esp_sleep.h"
#include "hal/efuse_hal.h"
@ -408,7 +409,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
if (efuse_hal_chip_revision() != 0) {
if (src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
pmu_sleep_enable_hp_sleep_sysclk(true);
esp_sleep_clock_config(ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK, ESP_SLEEP_CLOCK_OPTION_UNGATE);
modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, true);
modem_clock_domain_clk_gate_disable(MODEM_CLOCK_DOMAIN_WIFIPWR, PMU_HP_ICG_MODEM_CODE_SLEEP);
}
@ -481,7 +482,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module)
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND && SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643
if (efuse_hal_chip_revision() != 0) {
if (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
pmu_sleep_enable_hp_sleep_sysclk(false);
esp_sleep_clock_config(ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK, ESP_SLEEP_CLOCK_OPTION_GATE);
modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, false);
modem_clock_domain_clk_gate_enable(MODEM_CLOCK_DOMAIN_WIFIPWR, PMU_HP_ICG_MODEM_CODE_SLEEP);
}

5
components/esp_hw_support/port/esp32c5/pmu_sleep.c
View File

@ -328,11 +328,6 @@ bool pmu_sleep_finish(bool dslp)
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}
void pmu_sleep_enable_hp_sleep_sysclk(bool enable)
{
pmu_ll_hp_set_icg_sysclk_enable(PMU_instance()->hal->dev, HP(SLEEP), enable);
}
uint32_t pmu_sleep_get_wakup_retention_cost(void)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;

5
components/esp_hw_support/port/esp32c6/pmu_sleep.c
View File

@ -391,11 +391,6 @@ bool pmu_sleep_finish(bool dslp)
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}
void pmu_sleep_enable_hp_sleep_sysclk(bool enable)
{
pmu_ll_hp_set_icg_sysclk_enable(PMU_instance()->hal->dev, HP(SLEEP), enable);
}
uint32_t pmu_sleep_get_wakup_retention_cost(void)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;

5
components/esp_hw_support/port/esp32c61/pmu_sleep.c
View File

@ -327,11 +327,6 @@ bool pmu_sleep_finish(bool dslp)
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}
void pmu_sleep_enable_hp_sleep_sysclk(bool enable)
{
pmu_ll_hp_set_icg_sysclk_enable(PMU_instance()->hal->dev, HP(SLEEP), enable);
}
uint32_t pmu_sleep_get_wakup_retention_cost(void)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;

9
components/esp_hw_support/sleep_modes.c
View File

@ -2646,6 +2646,15 @@ static SLEEP_FN_ATTR uint32_t get_sleep_clock_icg_flags(void)
clk_flags |= BIT(PMU_ICG_FUNC_ENA_UART2);
}
#endif
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
/* Starting from C6ECO1 and later versions, when BLE RTC is configured to use
* MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL,the actual slow clock source is the WiFi power clock.
* As all 32 bits of ICG_FUNC are occupied, the ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK
* has been remapped to PMU_ICG_FUNC_ENA_RETENTION.*/
if (s_config.clock_icg_refs[ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK] > 0) {
clk_flags |= BIT(PMU_ICG_FUNC_ENA_RETENTION);
}
#endif
#endif /* SOC_PM_SUPPORT_PMU_CLK_ICG */
return clk_flags;
}