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Merge branch 'bugfix/keep_rtc8m_in_lightsleep' into 'master'

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pm: fixed RTC8M domain power down issue when used as RTC source

See merge request espressif/esp-idf!17612
This commit is contained in:
Michael (XIAO Xufeng)
2022-05-12 10:25:35 +08:00
parent 2e506bd93e 36074b9812
commit cc37f63e14
29 changed files with 126 additions and 32 deletions
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5
components/esp_hw_support/port/esp32/rtc_clk.c
View File

@@ -847,6 +847,11 @@ void rtc_dig_clk8m_disable(void)
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
bool rtc_dig_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/

9
components/esp_hw_support/port/esp32/rtc_sleep.c
View File

@@ -180,14 +180,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == RTC_SLOW_FREQ_8MD256) {
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
}
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
if (!cfg.int_8m_pd_en) {
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);

5
components/esp_hw_support/port/esp32c2/rtc_clk.c
View File

@@ -386,6 +386,11 @@ void rtc_dig_clk8m_disable(void)
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
bool rtc_dig_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/

4
components/esp_hw_support/port/esp32c2/rtc_sleep.c
View File

@@ -85,9 +85,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP);
}
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
if (!cfg.int_8m_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
} else {

5
components/esp_hw_support/port/esp32c3/rtc_clk.c
View File

@@ -509,6 +509,11 @@ void rtc_dig_clk8m_disable(void)
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
bool rtc_dig_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
static bool rtc_clk_set_bbpll_always_on(void)
{
/* We just keep the rtc bbpll clock on just under the case that

4
components/esp_hw_support/port/esp32c3/rtc_sleep.c
View File

@@ -113,9 +113,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP);
}
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
if (!cfg.int_8m_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
} else {

5
components/esp_hw_support/port/esp32h2/rtc_clk.c
View File

@@ -405,6 +405,11 @@ void rtc_dig_clk8m_disable(void)
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
bool rtc_dig_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
uint32_t read_spll_freq(void)
{
return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SPLL_FREQ);

8
components/esp_hw_support/port/esp32h2/rtc_sleep.c
View File

@@ -217,6 +217,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}
if (!cfg.int_8m_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
}
/* enable VDDSDIO control by state machine */
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);

5
components/esp_hw_support/port/esp32s2/rtc_clk.c
View File

@@ -572,6 +572,11 @@ void rtc_dig_clk8m_disable(void)
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
bool rtc_dig_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/

4
components/esp_hw_support/port/esp32s2/rtc_sleep.c
View File

@@ -111,9 +111,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP);
}
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
if (!cfg.int_8m_pd_en) {
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);

5
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@@ -555,6 +555,11 @@ void rtc_dig_clk8m_disable(void)
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
bool rtc_dig_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
}
static bool rtc_clk_set_bbpll_always_on(void)
{
/* We just keep the rtc bbpll clock on just under the case that

4
components/esp_hw_support/port/esp32s3/rtc_sleep.c
View File

@@ -122,9 +122,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
/* mem pd */
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
if (!cfg.int_8m_pd_en) {
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);

17
components/esp_hw_support/sleep_modes.c
View File

@@ -385,6 +385,20 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
suspend_uarts();
}
#if SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
//Keep the RTC8M_CLK on if RTC clock is 8MD256.
bool rtc_using_8md256 = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_8MD256);
#else
bool rtc_using_8md256 = false;
#endif
//Keep the RTC8M_CLK on if the ledc low-speed channel is clocked by RTC8M_CLK in lightsleep mode
bool dig_8m_enabled = !deep_sleep && rtc_dig_8m_enabled();
//Override user-configured power modes.
if (rtc_using_8md256 || dig_8m_enabled) {
pd_flags &= ~RTC_SLEEP_PD_INT_8M;
}
// Save current frequency and switch to XTAL
rtc_cpu_freq_config_t cpu_freq_config;
rtc_clk_cpu_freq_get_config(&cpu_freq_config);
@@ -437,6 +451,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
}
}
#endif
uint32_t reject_triggers = 0;
if ((pd_flags & RTC_SLEEP_PD_DIG) == 0 && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
/* Light sleep, enable sleep reject for faster return from this function,
@@ -558,7 +573,7 @@ void IRAM_ATTR esp_deep_sleep_start(void)
// Correct the sleep time
s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US;
uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO;
uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL;
#if SOC_PM_SUPPORT_WIFI_PD
force_pd_flags |= RTC_SLEEP_PD_WIFI;

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@@ -171,6 +171,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
bool
default y
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y

7
components/soc/esp32/include/soc/rtc.h
View File

@@ -485,6 +485,11 @@ void rtc_dig_clk8m_enable(void);
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Get whether the rtc digital 8M clock is enabled
*/
bool rtc_dig_8m_enabled(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
@@ -534,7 +539,7 @@ typedef struct rtc_sleep_config_s {
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.rom_mem_pd_en = 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \

1
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -120,6 +120,7 @@
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (9)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@@ -123,6 +123,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y

9
components/soc/esp32c2/include/soc/rtc.h
View File

@@ -504,6 +504,11 @@ void rtc_dig_clk8m_enable(void);
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Get whether the rtc digital 8M clock is enabled
*/
bool rtc_dig_8m_enabled(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
@@ -571,7 +576,7 @@ typedef struct {
#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG)
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 1, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
@@ -583,7 +588,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};

1
components/soc/esp32c2/include/soc/soc_caps.h
View File

@@ -65,6 +65,7 @@
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@@ -439,6 +439,10 @@ config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 0

9
components/soc/esp32c3/include/soc/rtc.h
View File

@@ -564,6 +564,11 @@ void rtc_dig_clk8m_enable(void);
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Get whether the rtc digital 8M clock is enabled
*/
bool rtc_dig_8m_enabled(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
@@ -648,7 +653,7 @@ typedef struct {
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
@@ -661,7 +666,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};

2
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -209,6 +209,8 @@
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */

9
components/soc/esp32h2/include/soc/rtc.h
View File

@@ -580,6 +580,11 @@ void rtc_dig_clk8m_enable(void);
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Get whether the rtc digital 8M clock is enabled
*/
bool rtc_dig_8m_enabled(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
@@ -664,7 +669,7 @@ typedef struct {
.dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, \
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
@@ -677,7 +682,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@@ -191,6 +191,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
int
default 13
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
bool
default y
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y

9
components/soc/esp32s2/include/soc/rtc.h
View File

@@ -628,6 +628,11 @@ void rtc_dig_clk8m_enable(void);
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Get whether the rtc digital 8M clock is enabled
*/
bool rtc_dig_8m_enabled(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
@@ -703,7 +708,7 @@ typedef struct {
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
@@ -717,7 +722,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_1V00, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};

1
components/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -96,6 +96,7 @@
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (13)
#define SOC_ADC_RTC_MAX_BITWIDTH (13)
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@@ -275,6 +275,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
bool
default y
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y

9
components/soc/esp32s3/include/soc/rtc.h
View File

@@ -571,6 +571,11 @@ void rtc_dig_clk8m_enable(void);
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Get whether the rtc digital 8M clock is enabled
*/
bool rtc_dig_8m_enabled(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
@@ -655,7 +660,7 @@ typedef struct {
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
@@ -668,7 +673,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};

1
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -90,6 +90,7 @@
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/