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fix(examples): Enable ipc_isr tests on CI

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This commit is contained in:
KonstantinKondrashov
2023-10-02 22:50:33 +08:00
parent aa3b9df318
commit ccb90e3d4a
3 changed files with 5 additions and 8 deletions
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8
examples/system/.build-test-rules.yml
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@@ -82,17 +82,13 @@ examples/system/himem:
examples/system/ipc/ipc_isr/riscv: examples/system/ipc/ipc_isr/riscv:
enable: enable:
- if: IDF_TARGET_ARCH_RISCV == 1 and ESP_IPC_ISR_ENABLE == 1 - if: IDF_TARGET in ["esp32p4"]
temporary: true temporary: true
reason: The test is intended only for multi-core chips reason: The test is intended only for multi-core chips
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: lack of runners
examples/system/ipc/ipc_isr/xtensa: examples/system/ipc/ipc_isr/xtensa:
enable: enable:
- if: IDF_TARGET_ARCH_XTENSA == 1 and ESP_IPC_ISR_ENABLE == 1 - if: IDF_TARGET in ["esp32", "esp32s3"]
temporary: true temporary: true
reason: The test is intended only for multi-core chips reason: The test is intended only for multi-core chips

4
examples/system/ipc/ipc_isr/riscv/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32P4 | | Supported Targets | ESP32-P4 |
| ----------------- | ------- | | ----------------- | -------- |
# IPC ISR Example # IPC ISR Example

1
examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
View File

@@ -7,6 +7,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32p4 @pytest.mark.esp32p4
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='lack of runner')
def test_ipc_isr(dut: Dut) -> None: def test_ipc_isr(dut: Dut) -> None:
dut.expect_exact('example: Start') dut.expect_exact('example: Start')
dut.expect_exact('example: MSTATUS = 0x3880') dut.expect_exact('example: MSTATUS = 0x3880')