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Merge branch 'feature/esp32c5_clock_preliminary_support' into 'master'

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Feature/esp32c5 clock preliminary support

See merge request espressif/esp-idf!28808
This commit is contained in:
Song Ruo Jing
2024-02-08 11:54:35 +08:00
parent ae31dfe4b8 95133c179f
commit d556fee5c4
16 changed files with 512 additions and 242 deletions
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components/esp_system/port/soc/esp32c5/Kconfig.cpu
-4
View File
@@ -10,8 +10,6 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
depends on IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_80
bool "80 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_120
bool "120 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_160
bool "160 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_240
@@ -21,8 +19,6 @@ endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
default 60 if ESP_DEFAULT_CPU_FREQ_MHZ_60
default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80
default 120 if ESP_DEFAULT_CPU_FREQ_MHZ_120
default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160
default 240 if ESP_DEFAULT_CPU_FREQ_MHZ_240
components/esp_system/port/soc/esp32c5/system_internal.c
+1 -1
View File
@@ -39,7 +39,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
modem_lpcon_ll_reset_all(&MODEM_LPCON);
// Set SPI Flash Freq to 40M
clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_XTAL);
clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
clk_ll_mspi_fast_set_divider(1);
// Set Peripheral clk rst