Merge branch 'bugfix/hal_coverity_fix' into 'master'

fix(hal): integer overflow found by coverity

Closes IDF-11747, IDF-11746, IDF-11733, IDF-11744, IDF-11721, IDF-11715, IDF-11731, IDF-11737, IDF-9831, IDF-9830, IDF-9424, and IDF-10650

See merge request espressif/esp-idf!35183

components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c

@@ -44,8 +44,10 @@ static void IRAM_ATTR esp_cam_ctlr_dvp_config_dma_desc(esp_cam_ctlr_dvp_dma_desc
         n++;
     }
 
+    if (n > 0) {
         desc[n - 1].next = NULL;
     }
+}
 
 /**
  * @brief Initialize DVP DMA object

components/esp_driver_jpeg/jpeg_parse_marker.c

@@ -130,10 +130,10 @@ esp_err_t jpeg_parse_sof_marker(jpeg_dec_header_info_t *header_info)
 
     // The vertical and horizontal in process must be divided by mcu block.
     if (header_info->origin_v % header_info->mcuy != 0) {
-        header_info->process_v = (uint32_t)(ceil(header_info->origin_v / header_info->mcuy) + 1) * header_info->mcuy;
+        header_info->process_v = ((header_info->origin_v / header_info->mcuy) + 1) * header_info->mcuy;
     }
     if (header_info->origin_h % header_info->mcux != 0) {
-        header_info->process_h = (uint32_t)(ceil(header_info->origin_h / header_info->mcux) + 1) * header_info->mcux;
+        header_info->process_h = ((header_info->origin_h / header_info->mcux) + 1) * header_info->mcux;
     }
 
     return ESP_OK;

components/esp_driver_parlio/src/parlio_rx.c

@@ -138,7 +138,9 @@ static IRAM_ATTR size_t s_parlio_mount_transaction_buffer(parlio_rx_unit_handle_
     /* Update the current transaction to the next one, and declare the delimiter is under using of the rx unit */
     memcpy(&rx_unit->curr_trans, trans, sizeof(parlio_rx_transaction_t));
     portENTER_CRITICAL_SAFE(&s_rx_spinlock);
+    if (trans->delimiter) {
         trans->delimiter->under_using = true;
+    }
     portEXIT_CRITICAL_SAFE(&s_rx_spinlock);
 
     uint32_t desc_num = trans->size / PARLIO_MAX_ALIGNED_DMA_BUF_SIZE;

components/esp_driver_uart/src/uart_vfs.c

@@ -215,7 +215,7 @@ static int uart_rx_char(int fd)
 static int uart_rx_char_via_driver(int fd)
 {
     uint8_t c;
-    int timeout = s_ctx[fd]->non_blocking ? 0 : portMAX_DELAY;
+    TickType_t timeout = s_ctx[fd]->non_blocking ? 0 : portMAX_DELAY;
     int n = uart_read_bytes(fd, &c, 1, timeout);
     if (n <= 0) {
         return NONE;

components/esp_hw_support/debug_probe/debug_probe.c

@@ -15,10 +15,12 @@
 #include "esp_heap_caps.h"
 #include "soc/soc_caps.h"
 #include "soc/debug_probe_periph.h"
+#include "soc/io_mux_reg.h"
 #include "hal/debug_probe_ll.h"
 #include "esp_private/debug_probe.h"
+#include "esp_private/gpio.h"
+#include "esp_private/esp_gpio_reserve.h"
 #include "esp_rom_gpio.h"
-#include "driver/gpio.h"
 
 static const char *TAG = "dbg_probe";
 
@@ -28,6 +30,7 @@ typedef struct debug_probe_channel_t debug_probe_channel_t;
 struct debug_probe_unit_t {
     int unit_id; // unit id
     debug_probe_channel_t *channels[DEBUG_PROBE_LL_CHANNELS_PER_UNIT]; // channels installed in this unit
+    uint64_t pin_bit_mask; // bit-mask of the GPIOs used by this unit
 };
 
 struct debug_probe_channel_t {
@@ -53,6 +56,7 @@ static esp_err_t debug_probe_unit_destroy(debug_probe_unit_t *unit)
 
     // disable the probe output
     debug_probe_ll_enable_unit(unit_id, false);
+    esp_gpio_revoke(unit->pin_bit_mask);
     // free the memory
     free(unit);
     return ESP_OK;
@@ -60,7 +64,6 @@ static esp_err_t debug_probe_unit_destroy(debug_probe_unit_t *unit)
 
 esp_err_t debug_probe_new_unit(const debug_probe_unit_config_t *config, debug_probe_unit_handle_t *out_handle)
 {
-    esp_err_t ret = ESP_OK;
     debug_probe_unit_t *unit = NULL;
     int unit_id = -1;
     ESP_RETURN_ON_FALSE(config && out_handle, ESP_ERR_INVALID_ARG, TAG, "invalid args");
@@ -80,43 +83,35 @@ esp_err_t debug_probe_new_unit(const debug_probe_unit_config_t *config, debug_pr
     ESP_RETURN_ON_FALSE(unit, ESP_ERR_NO_MEM, TAG, "no mem for unit");
     unit->unit_id = unit_id;
 
-    // configure the GPIOs
+    uint64_t pin_bit_mask = 0;
-    gpio_config_t monitor_io_conf = {
-        .mode = GPIO_MODE_OUTPUT,
-        .pin_bit_mask = 0,
-    };
     for (int i = 0; i < SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH; i++) {
-        // skip unused IOs
+        if (config->probe_out_gpio_nums[i] >= 0) {
-        if (config->probe_out_gpio_nums[i] < 0) {
+            pin_bit_mask |= BIT64(config->probe_out_gpio_nums[i]);
-            continue;
         }
-        monitor_io_conf.pin_bit_mask |= (1ULL << config->probe_out_gpio_nums[i]);
     }
-    if (monitor_io_conf.pin_bit_mask) {
+    // reserve the GPIO output path, because we don't expect another peripheral to signal to the same GPIO
-        ESP_GOTO_ON_ERROR(gpio_config(&monitor_io_conf), err, TAG, "gpio_config failed");
+    uint64_t old_gpio_rsv_mask = esp_gpio_reserve(pin_bit_mask);
+    // check if the GPIO is already used by others, RMT TX channel only uses the output path of the GPIO
+    if (old_gpio_rsv_mask & pin_bit_mask) {
+        ESP_LOGW(TAG, "GPIO conflict with others");
     }
 
     // connect the probe output signals to the GPIOs
     for (int i = 0; i < SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH; i++) {
-        if (config->probe_out_gpio_nums[i] < 0) {
+        if (config->probe_out_gpio_nums[i] >= 0) {
-            continue;
+            gpio_func_sel(config->probe_out_gpio_nums[i], PIN_FUNC_GPIO);
-        }
             esp_rom_gpio_connect_out_signal(config->probe_out_gpio_nums[i],
                                             debug_probe_periph_signals.units[unit_id].out_sig[i],
                                             false, false);
         }
+    }
+    unit->pin_bit_mask = pin_bit_mask;
 
     // enable the probe unit
     debug_probe_ll_enable_unit(unit_id, true);
 
     *out_handle = unit;
     return ESP_OK;
-
-err:
-    if (unit) {
-        debug_probe_unit_destroy(unit);
-    }
-    return ret;
 }
 
 esp_err_t debug_probe_del_unit(debug_probe_unit_handle_t unit)

components/hal/esp32/include/hal/spi_ll.h

@@ -63,10 +63,10 @@ typedef spi_dev_t spi_dma_dev_t;
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    if (enable) {
-        switch (host_id)
 {
+    if (enable) {
+        switch (host_id) {
         case SPI1_HOST:
             DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
             break;
@@ -79,8 +79,7 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
         default: HAL_ASSERT(false);
         }
     } else {
-        switch (host_id)
+        switch (host_id) {
-        {
         case SPI1_HOST:
             DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
             break;
@@ -104,9 +103,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
         DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
@@ -793,8 +792,10 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set the delay of SPI clocks before the CS inactive edge after the last SPI clock.
@@ -1061,7 +1062,8 @@ static inline void spi_ll_enable_int(spi_dev_t *hw)
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
+{
     (void)host_id; // has only one spi_dma
     if (enable) {
         DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_DMA_CLK_EN);
@@ -1080,7 +1082,8 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
 __attribute__((always_inline))
-static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_dma_ll_reset_register(spi_host_device_t host_id)
+{
     (void)host_id; // has only one spi_dma
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);

components/hal/esp32c2/include/hal/gpspi_flash_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -362,8 +362,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -387,15 +389,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32c2/include/hal/spi_ll.h

@@ -97,9 +97,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         SYSTEM.perip_clk_en0.spi01_clk_en = enable;
         break;
@@ -119,9 +119,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         SYSTEM.perip_rst_en0.spi01_rst = 1;
         SYSTEM.perip_rst_en0.spi01_rst = 0;
@@ -158,9 +158,9 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
  * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t`
  */
 __attribute__((always_inline))
-static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source){
+static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
-    switch (clk_source)
 {
+    switch (clk_source) {
     case SPI_CLK_SRC_XTAL:
         hw->clk_gate.mst_clk_sel = 0;
         break;
@@ -1018,8 +1018,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1181,8 +1183,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;
@@ -1344,22 +1345,19 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
     conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK;
     conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK;
 
-    switch (line_mode.cmd_lines)
+    switch (line_mode.cmd_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break;
     default: break;
     }
 
-    switch (line_mode.addr_lines)
+    switch (line_mode.addr_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break;
     default: break;
     }
 
-    switch (line_mode.data_lines)
+    switch (line_mode.data_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M);
         SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
         break;

components/hal/esp32c2/include/hal/spimem_flash_ll.h

@@ -582,8 +582,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set D/Q output level during dummy phase

components/hal/esp32c3/include/hal/gpspi_flash_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -363,8 +363,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -388,15 +390,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32c3/include/hal/spi_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -99,9 +99,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         SYSTEM.perip_clk_en0.reg_spi01_clk_en = enable;
         break;
@@ -121,9 +121,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         SYSTEM.perip_rst_en0.reg_spi01_rst = 1;
         SYSTEM.perip_rst_en0.reg_spi01_rst = 0;
@@ -160,9 +160,9 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
  * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t`
  */
 __attribute__((always_inline))
-static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source){
+static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
-    switch (clk_source)
 {
+    switch (clk_source) {
     case SPI_CLK_SRC_XTAL:
         hw->clk_gate.mst_clk_sel = 0;
         break;
@@ -1020,8 +1020,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1257,22 +1259,19 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
     conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK;
     conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK;
 
-    switch (line_mode.cmd_lines)
+    switch (line_mode.cmd_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break;
     default: break;
     }
 
-    switch (line_mode.addr_lines)
+    switch (line_mode.addr_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break;
     default: break;
     }
 
-    switch (line_mode.data_lines)
+    switch (line_mode.data_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M);
         SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
         break;
@@ -1511,8 +1510,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32c3/include/hal/spimem_flash_ll.h

@@ -584,8 +584,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set D/Q output level during dummy phase

components/hal/esp32c5/include/hal/gpspi_flash_ll.h

@@ -363,8 +363,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -388,15 +390,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32c5/include/hal/spi_ll.h

@@ -99,9 +99,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI2_HOST:
         PCR.spi2_conf.spi2_clk_en = enable;
         break;
@@ -115,9 +115,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI2_HOST:
         PCR.spi2_conf.spi2_rst_en = 1;
         PCR.spi2_conf.spi2_rst_en = 0;
@@ -1028,8 +1028,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1194,8 +1196,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32c5/include/hal/spimem_flash_ll.h

@@ -606,8 +606,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set CS hold time.
@@ -648,8 +650,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
 {
     int source_clk_mhz = 0;
 
-    switch (PCR.mspi_clk_conf.mspi_func_clk_sel)
+    switch (PCR.mspi_clk_conf.mspi_func_clk_sel) {
-    {
     case 0:
         source_clk_mhz = clk_ll_xtal_get_freq_mhz();
         break;

components/hal/esp32c6/include/hal/gpspi_flash_ll.h

@@ -363,8 +363,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -388,15 +390,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32c6/include/hal/spi_ll.h

@@ -97,9 +97,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         PCR.mspi_conf.mspi_clk_en = enable;
         break;
@@ -115,9 +115,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         PCR.mspi_conf.mspi_rst_en = 1;
         PCR.mspi_conf.mspi_rst_en = 0;
@@ -151,8 +151,7 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
 __attribute__((always_inline))
 static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
 {
-    switch (clk_source)
+    switch (clk_source) {
-    {
     case SPI_CLK_SRC_RC_FAST:
         PCR.spi2_clkm_conf.spi2_clkm_sel = 2;
         break;
@@ -1012,8 +1011,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1250,22 +1251,19 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
     conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK;
     conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK;
 
-    switch (line_mode.cmd_lines)
+    switch (line_mode.cmd_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break;
     default: break;
     }
 
-    switch (line_mode.addr_lines)
+    switch (line_mode.addr_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break;
     default: break;
     }
 
-    switch (line_mode.data_lines)
+    switch (line_mode.data_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M);
         SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
         break;
@@ -1504,8 +1502,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32c6/include/hal/spimem_flash_ll.h

@@ -597,8 +597,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set CS hold time.

components/hal/esp32c61/include/hal/gpspi_flash_ll.h

@@ -363,8 +363,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -388,15 +390,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32c61/include/hal/spi_ll.h

@@ -99,9 +99,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         PCR.mspi_conf.mspi_clk_en = enable;
         break;
@@ -117,9 +117,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         PCR.mspi_conf.mspi_rst_en = 1;
         PCR.mspi_conf.mspi_rst_en = 0;
@@ -153,8 +153,7 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
 __attribute__((always_inline))
 static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
 {
-    switch (clk_source)
+    switch (clk_source) {
-    {
     case SPI_CLK_SRC_RC_FAST:
         PCR.spi2_clkm_conf.spi2_clkm_sel = 2;
         break;
@@ -1032,8 +1031,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1198,8 +1199,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32c61/include/hal/spimem_flash_ll.h

@@ -599,8 +599,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set CS hold time.
@@ -630,8 +632,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
 {
     int source_clk_mhz = 0;
 
-    switch (PCR.mspi_clk_conf.mspi_func_clk_sel)
+    switch (PCR.mspi_clk_conf.mspi_func_clk_sel) {
-    {
     case 0:
         source_clk_mhz = clk_ll_xtal_get_freq_mhz();
         break;

components/hal/esp32h2/include/hal/gpspi_flash_ll.h

@@ -363,8 +363,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -388,15 +390,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32h2/include/hal/spi_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -96,9 +96,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         PCR.mspi_conf.mspi_clk_en = enable;
         break;
@@ -114,9 +114,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         PCR.mspi_conf.mspi_rst_en = 1;
         PCR.mspi_conf.mspi_rst_en = 0;
@@ -150,8 +150,7 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
 __attribute__((always_inline))
 static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
 {
-    switch (clk_source)
+    switch (clk_source) {
-    {
     case SPI_CLK_SRC_RC_FAST:
         PCR.spi2_clkm_conf.spi2_clkm_sel = 2;
         break;
@@ -1011,8 +1010,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1249,24 +1250,21 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
     conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK;
     conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK;
 
-    switch (line_mode.cmd_lines)
+    switch (line_mode.cmd_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break;
     case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M); break;
     default: break;
     }
 
-    switch (line_mode.addr_lines)
+    switch (line_mode.addr_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break;
     case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M); break;
     default: break;
     }
 
-    switch (line_mode.data_lines)
+    switch (line_mode.data_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M);
         SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
         break;
@@ -1509,8 +1507,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32h2/include/hal/spimem_flash_ll.h

@@ -618,8 +618,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set CS hold time.

components/hal/esp32p4/include/hal/gpspi_flash_ll.h

@@ -363,8 +363,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -388,15 +390,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32p4/include/hal/lcd_ll.h

@@ -363,9 +363,13 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl
     dev->lcd_user.lcd_dummy = (dummy_cycles > 0);
     dev->lcd_user.lcd_dout = (data_cycles > 0);
     dev->lcd_user.lcd_cmd_2_cycle_en = cmd_cycles > 1;
+    if (dummy_cycles > 0) {
         dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1;
+    }
+    if (data_cycles > 0) {
         dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1;
     }
+}
 
 /**
  * @brief Set clock cycles of blank phases
@@ -377,9 +381,13 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl
 static inline void lcd_ll_set_blank_cycles(lcd_cam_dev_t *dev, uint32_t fk_cycles, uint32_t bk_cycles)
 {
     dev->lcd_misc.lcd_bk_en = (fk_cycles || bk_cycles);
+    if (fk_cycles > 0) {
         dev->lcd_misc.lcd_vfk_cyclelen = fk_cycles - 1;
+    }
+    if (bk_cycles > 0) {
         dev->lcd_misc.lcd_vbk_cyclelen = bk_cycles - 1;
     }
+}
 
 /**
  * @brief Set data read stride, i.e., number of bytes the LCD reads from the DMA in each step

components/hal/esp32p4/include/hal/spi_ll.h

@@ -98,9 +98,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI2_HOST:
         HP_SYS_CLKRST.soc_clk_ctrl1.reg_gpspi2_sys_clk_en = enable;
         HP_SYS_CLKRST.soc_clk_ctrl2.reg_gpspi2_apb_clk_en = enable;
@@ -122,9 +122,9 @@ static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enab
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI2_HOST:
         HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_spi2 = 1;
         HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_spi2 = 0;
@@ -149,8 +149,7 @@ static inline void spi_ll_reset_register(spi_host_device_t host_id) {
  */
 static inline void _spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
 {
-    switch (host_id)
+    switch (host_id) {
-    {
     case SPI2_HOST:
         HP_SYS_CLKRST.peri_clk_ctrl116.reg_gpspi2_hs_clk_en = enable;
         HP_SYS_CLKRST.peri_clk_ctrl116.reg_gpspi2_mst_clk_en = enable;
@@ -1078,8 +1077,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1244,8 +1245,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32p4/include/hal/spimem_flash_ll.h

@@ -611,8 +611,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set CS hold time.
@@ -654,8 +656,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
     // return 80;
     int source_clk_mhz = 0;
 
-    switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel)
+    switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel) {
-    {
     case 0:
         source_clk_mhz = clk_ll_xtal_load_freq_mhz();
         break;

components/hal/esp32s2/include/hal/gpspi_flash_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -357,8 +357,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -374,17 +376,33 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
     dev->ctrl.d_pol = out_lev;
 }
 
+/**
+ * Set extra hold time of CS after the clocks.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param hold_n Cycles of clocks before CS is inactive
+ */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->ctrl2.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->ctrl2.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->ctrl2.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32s2/include/hal/spi_ll.h

@@ -112,10 +112,10 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    if (enable) {
-        switch (host_id)
 {
+    if (enable) {
+        switch (host_id) {
         case SPI1_HOST:
             DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
             break;
@@ -128,8 +128,7 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
         default: HAL_ASSERT(false);
         }
     } else {
-        switch (host_id)
+        switch (host_id) {
-        {
         case SPI1_HOST:
             DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
             break;
@@ -153,9 +152,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
         DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
@@ -853,8 +852,10 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set the delay of SPI clocks before the CS inactive edge after the last SPI clock.
@@ -1207,10 +1208,10 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    if (enable) {
-        switch (host_id)
 {
+    if (enable) {
+        switch (host_id) {
         case SPI2_HOST:
             DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_DMA_CLK_EN);
             break;
@@ -1221,8 +1222,7 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e
             HAL_ASSERT(false);
         }
     } else {
-        switch (host_id)
+        switch (host_id) {
-        {
         case SPI2_HOST:
             DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_DMA_CLK_EN);
             break;
@@ -1244,9 +1244,9 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_dma_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI2_HOST:
         DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST);
         DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST);
@@ -1592,24 +1592,21 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
     conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK;
     conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK;
 
-    switch (line_mode.cmd_lines)
+    switch (line_mode.cmd_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break;
     case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M); break;
     default: break;
     }
 
-    switch (line_mode.addr_lines)
+    switch (line_mode.addr_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break;
     case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M); break;
     default: break;
     }
 
-    switch (line_mode.data_lines)
+    switch (line_mode.data_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M);
         SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
         break;
@@ -1856,8 +1853,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32s2/include/hal/spimem_flash_ll.h

@@ -524,8 +524,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Set D/Q output level during dummy phase

components/hal/esp32s3/include/hal/gpspi_flash_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -369,8 +369,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1)
     }
+}
 
 /**
  * Set D/Q output level during dummy phase
@@ -394,15 +396,25 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
  */
 static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
 {
-    dev->user1.cs_hold_time = hold_n - 1;
     dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
+    if (hold_n > 0) {
+        dev->user1.cs_hold_time = hold_n - 1;
+    }
 }
 
+/**
+ * Set the delay of SPI clocks before the first SPI clock after the CS active edge.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
+ */
 static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
 {
     dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    if (cs_setup_time > 0) {
         dev->user1.cs_setup_time = cs_setup_time - 1;
     }
+}
 
 /**
  * Calculate spi_flash clock frequency division parameters for register.

components/hal/esp32s3/include/hal/lcd_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -347,9 +347,13 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl
     dev->lcd_user.lcd_dummy = (dummy_cycles > 0);
     dev->lcd_user.lcd_dout = (data_cycles > 0);
     dev->lcd_user.lcd_cmd_2_cycle_en = cmd_cycles > 1;
+    if (dummy_cycles > 0) {
         dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1;
+    }
+    if (data_cycles > 0) {
         dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1;
     }
+}
 
 /**
  * @brief Set clock cycles of blank phases
@@ -361,9 +365,13 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl
 static inline void lcd_ll_set_blank_cycles(lcd_cam_dev_t *dev, uint32_t fk_cycles, uint32_t bk_cycles)
 {
     dev->lcd_misc.lcd_bk_en = (fk_cycles || bk_cycles);
+    if (fk_cycles > 0) {
         dev->lcd_misc.lcd_vfk_cyclelen = fk_cycles - 1;
+    }
+    if (bk_cycles > 0) {
         dev->lcd_misc.lcd_vbk_cyclelen = bk_cycles - 1;
     }
+}
 
 /**
  * @brief Set data read stride, i.e., number of bytes the LCD reads from the DMA in each step
@@ -571,7 +579,7 @@ static inline void lcd_ll_set_command(lcd_cam_dev_t *dev, uint32_t data_width, u
 }
 
 /**
- * @brief Wether to enable RGB interface
+ * @brief Whether to enable RGB interface
  *
  * @param dev LCD register base address
  * @param en True to enable RGB interface, False to disable RGB interface
@@ -594,7 +602,7 @@ static inline void lcd_ll_enable_auto_next_frame(lcd_cam_dev_t *dev, bool en)
 }
 
 /**
- * @brief Wether to output HSYNC signal in porch resion
+ * @brief Whether to output HSYNC signal in porch region
  *
  * @param dev LCD register base address
  * @param en True to enable, False to disable
@@ -726,7 +734,7 @@ static inline uint32_t lcd_ll_get_interrupt_status(lcd_cam_dev_t *dev)
  * @brief Clear interrupt status by mask
  *
  * @param dev LCD register base address
- * @param mask Interupt status mask
+ * @param mask Interrupt status mask
  */
 __attribute__((always_inline))
 static inline void lcd_ll_clear_interrupt_status(lcd_cam_dev_t *dev, uint32_t mask)

components/hal/esp32s3/include/hal/spi_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -99,9 +99,9 @@ typedef enum {
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  * @param enable    Enable/Disable
  */
-static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
+static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         SYSTEM.perip_clk_en0.spi01_clk_en = enable;
         break;
@@ -124,9 +124,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
  *
  * @param host_id   Peripheral index number, see `spi_host_device_t`
  */
-static inline void spi_ll_reset_register(spi_host_device_t host_id) {
+static inline void spi_ll_reset_register(spi_host_device_t host_id)
-    switch (host_id)
 {
+    switch (host_id) {
     case SPI1_HOST:
         SYSTEM.perip_rst_en0.spi01_rst = 1;
         SYSTEM.perip_rst_en0.spi01_rst = 0;
@@ -167,9 +167,9 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
  * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t`
  */
 __attribute__((always_inline))
-static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source){
+static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
-    switch (clk_source)
 {
+    switch (clk_source) {
     case SPI_CLK_SRC_XTAL:
         hw->clk_gate.mst_clk_sel = 0;
         break;
@@ -1040,8 +1040,10 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
     }
+}
 
 /**
  * Enable/disable the RX data phase.
@@ -1279,24 +1281,21 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
     conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK;
     conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK;
 
-    switch (line_mode.cmd_lines)
+    switch (line_mode.cmd_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break;
     case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M); break;
     default: break;
     }
 
-    switch (line_mode.addr_lines)
+    switch (line_mode.addr_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break;
     case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break;
     case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M); break;
     default: break;
     }
 
-    switch (line_mode.data_lines)
+    switch (line_mode.data_lines) {
-    {
     case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M);
         SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
         break;
@@ -1538,8 +1537,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
 static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
 {
     uint8_t cmd_base = 0x00;
-    switch (cmd_t)
+    switch (cmd_t) {
-    {
     case SPI_CMD_HD_WRBUF:
         cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
         break;

components/hal/esp32s3/include/hal/spimem_flash_ll.h

@@ -604,8 +604,10 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
+    if (dummy_n > 0) {
         dev->user1.usr_dummy_cyclelen = dummy_n - 1;
     }
+}
 
 /**
  * Set D/Q output level during dummy phase