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Merge branch 'refactor/remove_legacy_i2s_driver' into 'master'

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remove(legacy_i2s): remove legacy i2s driver in IDF v6.0

Closes IDF-13170

See merge request espressif/esp-idf!39681
This commit is contained in:
Kevin (Lao Kaiyao)
2025-06-10 18:49:55 +08:00
parent 443e8718b8 6eb5bfe587
commit e71e7552ef
32 changed files with 23 additions and 9305 deletions
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5
components/driver/CMakeLists.txt
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@@ -36,11 +36,6 @@ if(CONFIG_SOC_I2C_SUPPORTED)
list(APPEND srcs "i2c/i2c.c")
endif()
# I2S related source files
if(CONFIG_SOC_I2S_SUPPORTED)
list(APPEND srcs "deprecated/i2s_legacy.c")
endif()
# MCPWM legacy driver
if(CONFIG_SOC_MCPWM_SUPPORTED)
list(APPEND srcs "deprecated/mcpwm_legacy.c")

17
components/driver/Kconfig
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@@ -119,23 +119,6 @@ menu "Driver Configurations"
This configuration option allows the user to bypass the conflict check mechanism with legacy code.
endmenu # Legacy RMT Driver Configurations
menu "Legacy I2S Driver Configurations"
depends on SOC_I2S_SUPPORTED
config I2S_SUPPRESS_DEPRECATE_WARN
bool "Suppress legacy driver deprecated warning"
default n
help
Whether to suppress the deprecation warnings when using legacy i2s driver (driver/i2s.h).
If you want to continue using the legacy driver, and don't want to see related deprecation warnings,
you can enable this option.
config I2S_SKIP_LEGACY_CONFLICT_CHECK
bool "Skip legacy conflict check"
default n
help
This configuration option allows the user to bypass the conflict check mechanism with legacy code.
endmenu # Legacy I2S Driver Configurationss
menu "Legacy I2C Driver Configurations"
depends on SOC_I2C_SUPPORTED
config I2C_SKIP_LEGACY_CONFLICT_CHECK

383
components/driver/deprecated/driver/i2s.h
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@@ -1,383 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* This file is for the backward compatible to the deprecated I2S APIs,
* The deprecated APIs will no longer supported in the future
* Please refer to "driver/i2s_std.h", "driver/i2s_pdm.h" and ""driver/i2s_tdm.h"" for the latest I2S driver
* Note that only one set of I2S APIs is allowed to be used at the same time
*/
#pragma once
#include "esp_types.h"
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "driver/i2s_types_legacy.h"
#if SOC_I2S_SUPPORTS_ADC
#include "driver/adc.h"
#endif
#if !CONFIG_I2S_SUPPRESS_DEPRECATE_WARN
#warning "This set of I2S APIs has been deprecated, \
please include 'driver/i2s_std.h', 'driver/i2s_pdm.h' or 'driver/i2s_tdm.h' instead. \
if you want to keep using the old APIs and ignore this warning, \
you can enable 'Suppress legacy driver deprecated warning' option under 'I2S Configuration' menu in Kconfig"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set I2S pin number
*
* @note
* The I2S peripheral output signals can be connected to multiple GPIO pads.
* However, the I2S peripheral input signal can only be connected to one GPIO pad.
*
* @param i2s_num I2S port number
*
* @param pin I2S Pin structure, or NULL to set 2-channel 8-bit internal DAC pin configuration (GPIO25 & GPIO26)
*
* Inside the pin configuration structure, set I2S_PIN_NO_CHANGE for any pin where
* the current configuration should not be changed.
*
* @note if *pin is set as NULL, this function will initialize both of the built-in DAC channels by default.
* if you don't want this to happen and you want to initialize only one of the DAC channels, you can call i2s_set_dac_mode instead.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_FAIL IO error
*/
esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
#if SOC_I2S_SUPPORTS_PDM_RX
/**
* @brief Set PDM mode down-sample rate
* In PDM RX mode, there would be 2 rounds of downsample process in hardware.
* In the first downsample process, the sampling number can be 16 or 8.
* In the second downsample process, the sampling number is fixed as 8.
* So the clock frequency in PDM RX mode would be (fpcm * 64) or (fpcm * 128) accordingly.
* @param i2s_num I2S port number
* @param downsample i2s RX down sample rate for PDM mode.
*
* @note After calling this function, it would call i2s_set_clk inside to update the clock frequency.
* Please call this function after I2S driver has been initialized.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_NO_MEM Out of memory
*/
esp_err_t i2s_set_pdm_rx_down_sample(i2s_port_t i2s_num, i2s_pdm_dsr_t downsample);
#endif
#if SOC_I2S_SUPPORTS_PDM_TX
/**
* @brief Set TX PDM mode up-sample rate
* @note If you have set PDM mode while calling 'i2s_driver_install',
* default PDM TX upsample parameters have already been set,
* no need to call this function again if you don't have to change the default configuration
*
* @param i2s_num I2S port number
* @param upsample_cfg Set I2S PDM up-sample rate configuration
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_NO_MEM Out of memory
*/
esp_err_t i2s_set_pdm_tx_up_sample(i2s_port_t i2s_num, const i2s_pdm_tx_upsample_cfg_t *upsample_cfg);
#endif
/**
* @brief Install and start I2S driver.
*
* @param i2s_num I2S port number
*
* @param i2s_config I2S configurations - see i2s_config_t struct
*
* @param queue_size I2S event queue size/depth.
*
* @param i2s_queue I2S event queue handle, if set NULL, driver will not use an event queue.
*
* This function must be called before any I2S driver read/write operations.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_NO_MEM Out of memory
* - ESP_ERR_INVALID_STATE Current I2S port is in use
*/
esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void *i2s_queue);
/**
* @brief Uninstall I2S driver.
*
* @param i2s_num I2S port number
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_INVALID_STATE I2S port has been uninstalled by others (e.g. LCD i80)
*/
esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num);
/**
* @brief Write data to I2S DMA transmit buffer.
*
* @param i2s_num I2S port number
*
* @param src Source address to write from
*
* @param size Size of data in bytes
*
* @param[out] bytes_written Number of bytes written, if timeout, the result will be less than the size passed in.
*
* @param ticks_to_wait TX buffer wait timeout in RTOS ticks. If this
* many ticks pass without space becoming available in the DMA
* transmit buffer, then the function will return (note that if the
* data is written to the DMA buffer in pieces, the overall operation
* may still take longer than this timeout.) Pass portMAX_DELAY for no
* timeout.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_write(i2s_port_t i2s_num, const void *src, size_t size, size_t *bytes_written, TickType_t ticks_to_wait);
/**
* @brief Write data to I2S DMA transmit buffer while expanding the number of bits per sample. For example, expanding 16-bit PCM to 32-bit PCM.
*
* @param i2s_num I2S port number
*
* @param src Source address to write from
*
* @param size Size of data in bytes
*
* @param src_bits Source audio bit
*
* @param aim_bits Bit wanted, no more than 32, and must be greater than src_bits
*
* @param[out] bytes_written Number of bytes written, if timeout, the result will be less than the size passed in.
*
* @param ticks_to_wait TX buffer wait timeout in RTOS ticks. If this
* many ticks pass without space becoming available in the DMA
* transmit buffer, then the function will return (note that if the
* data is written to the DMA buffer in pieces, the overall operation
* may still take longer than this timeout.) Pass portMAX_DELAY for no
* timeout.
*
* Format of the data in source buffer is determined by the I2S
* configuration (see i2s_config_t).
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_write_expand(i2s_port_t i2s_num, const void *src, size_t size, size_t src_bits, size_t aim_bits, size_t *bytes_written, TickType_t ticks_to_wait);
/**
* @brief Read data from I2S DMA receive buffer
*
* @param i2s_num I2S port number
*
* @param dest Destination address to read into
*
* @param size Size of data in bytes
*
* @param[out] bytes_read Number of bytes read, if timeout, bytes read will be less than the size passed in.
*
* @param ticks_to_wait RX buffer wait timeout in RTOS ticks. If this many ticks pass without bytes becoming available in the DMA receive buffer, then the function will return (note that if data is read from the DMA buffer in pieces, the overall operation may still take longer than this timeout.) Pass portMAX_DELAY for no timeout.
*
* @note If the built-in ADC mode is enabled, we should call i2s_adc_enable and i2s_adc_disable around the whole reading process,
* to prevent the data getting corrupted.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_read(i2s_port_t i2s_num, void *dest, size_t size, size_t *bytes_read, TickType_t ticks_to_wait);
/**
* @brief Set sample rate used for I2S RX and TX.
*
* The bit clock rate is determined by the sample rate and i2s_config_t configuration parameters (number of channels, bits_per_sample).
*
* `bit_clock = rate * (number of channels) * bits_per_sample`
*
* @param i2s_num I2S port number
*
* @param rate I2S sample rate (ex: 8000, 44100...)
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_NO_MEM Out of memory
*/
esp_err_t i2s_set_sample_rates(i2s_port_t i2s_num, uint32_t rate);
/**
* @brief Stop I2S driver
*
* There is no need to call i2s_stop() before calling i2s_driver_uninstall().
*
* Disables I2S TX/RX, until i2s_start() is called.
*
* @param i2s_num I2S port number
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_stop(i2s_port_t i2s_num);
/**
* @brief Start I2S driver
*
* It is not necessary to call this function after i2s_driver_install() (it is started automatically), however it is necessary to call it after i2s_stop().
*
*
* @param i2s_num I2S port number
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_start(i2s_port_t i2s_num);
/**
* @brief Zero the contents of the TX DMA buffer.
*
* Pushes zero-byte samples into the TX DMA buffer, until it is full.
*
* @param i2s_num I2S port number
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num);
#if SOC_I2S_SUPPORTS_PCM
/**
* @brief Configure I2S a/u-law decompress or compress
*
* @note This function should be called after i2s driver installed
* Only take effecttive when the i2s 'communication_format' is set to 'I2S_COMM_FORMAT_STAND_PCM_SHORT' or 'I2S_COMM_FORMAT_STAND_PCM_LONG'
*
* @param i2s_num I2S port number
*
* @param pcm_cfg including mode selection and a/u-law decompress or compress configuration parameter
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_pcm_config(i2s_port_t i2s_num, const i2s_pcm_cfg_t *pcm_cfg);
#endif
/**
* @brief Set clock & bit width used for I2S RX and TX.
*
* Similar to i2s_set_sample_rates(), but also sets bit width.
*
* 1. stop i2s;
* 2. calculate mclk, bck, bck_factor
* 3. malloc dma buffer;
* 4. start i2s
*
* @param i2s_num I2S port number
*
* @param rate I2S sample rate (ex: 8000, 44100...)
*
* @param bits_cfg I2S bits configuration
* the low 16 bits is for data bits per sample in one channel (see 'i2s_bits_per_sample_t')
* the high 16 bits is for total bits in one channel (see 'i2s_bits_per_chan_t')
* high 16bits =0 means same as the bits per sample.
*
* @param ch I2S channel, (I2S_CHANNEL_MONO, I2S_CHANNEL_STEREO or specific channel in TDM mode)
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_NO_MEM Out of memory
*/
esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, uint32_t bits_cfg, i2s_channel_t ch);
/**
* @brief get clock set on particular port number.
*
* @param i2s_num I2S port number
*
* @return
* - actual clock set by i2s driver
*/
float i2s_get_clk(i2s_port_t i2s_num);
#if SOC_I2S_SUPPORTS_ADC
/**
* @brief Set built-in ADC mode for I2S DMA, this function will initialize ADC pad,
* and set ADC parameters.
* @note In this mode, the ADC maximum sampling rate is 150KHz. Set the sampling rate through ``i2s_config_t``.
* @param adc_unit SAR ADC unit index
* @param adc_channel ADC channel index
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
/**
* @brief Start to use I2S built-in ADC mode
* @note This function would acquire the lock of ADC to prevent the data getting corrupted
* during the I2S peripheral is being used to do fully continuous ADC sampling.
*
* @param i2s_num i2s port index
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_INVALID_STATE Driver state error
*/
esp_err_t i2s_adc_enable(i2s_port_t i2s_num);
/**
* @brief Stop to use I2S built-in ADC mode
* @param i2s_num i2s port index
* @note This function would release the lock of ADC so that other tasks can use ADC.
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_ERR_INVALID_STATE Driver state error
*/
esp_err_t i2s_adc_disable(i2s_port_t i2s_num);
#endif // SOC_I2S_SUPPORTS_ADC
#if SOC_I2S_SUPPORTS_DAC
/**
* @brief Set I2S dac mode, I2S built-in DAC is disabled by default
*
* @param dac_mode DAC mode configurations - see i2s_dac_mode_t
*
* @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
* If either of the built-in DAC channel are enabled, the other one can not
* be used as RTC DAC function at the same time.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
#endif //SOC_I2S_SUPPORTS_DAC
#ifdef __cplusplus
}
#endif

251
components/driver/deprecated/driver/i2s_types_legacy.h
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@@ -1,251 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* This file is for the backward compatible to the deprecated I2S APIs,
* The deprecated APIs will no longer supported in the future
* Please refer to "hal/i2s_types.h" for the latest I2S driver types
* Note that only one set of I2S APIs is allowed to be used at the same time
*/
#pragma once
#include "hal/i2s_types.h"
#include "driver/i2s_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/******************** Deprecated Types **********************/
#define I2S_PIN_NO_CHANGE (-1) /*!< Used in i2s_pin_config_t for pins which should not be changed */
/**
* @brief I2S bit width per sample.
*/
typedef enum {
I2S_BITS_PER_SAMPLE_8BIT = 8, /*!< data bit-width: 8 */
I2S_BITS_PER_SAMPLE_16BIT = 16, /*!< data bit-width: 16 */
I2S_BITS_PER_SAMPLE_24BIT = 24, /*!< data bit-width: 24 */
I2S_BITS_PER_SAMPLE_32BIT = 32, /*!< data bit-width: 32 */
} i2s_bits_per_sample_t;
/**
* @brief I2S bit width per chan.
*/
typedef enum {
I2S_BITS_PER_CHAN_DEFAULT = (0), /*!< channel bit-width equals to data bit-width */
I2S_BITS_PER_CHAN_8BIT = (8), /*!< channel bit-width: 8 */
I2S_BITS_PER_CHAN_16BIT = (16), /*!< channel bit-width: 16 */
I2S_BITS_PER_CHAN_24BIT = (24), /*!< channel bit-width: 24 */
I2S_BITS_PER_CHAN_32BIT = (32), /*!< channel bit-width: 32 */
} i2s_bits_per_chan_t;
/**
* @brief I2S channel.
*/
typedef enum {
I2S_CHANNEL_MONO = 1, /*!< I2S channel (mono), one channel activated. In this mode, you only need to send one channel data but the fifo will copy same data for the other unactivated channels automatically, then both channels will transmit same data. */
I2S_CHANNEL_STEREO = 2, /*!< I2S channel (stereo), two (or more) channels activated. In this mode, these channels will transmit different data. */
#if SOC_I2S_SUPPORTS_TDM
// Bit map of activated chan.
// There are 16 channels in TDM mode.
// For TX module, only the activated channel send the audio data, the unactivated channel send a constant(configurable) or will be skipped if 'skip_msk' is set.
// For RX module, only receive the audio data in activated channels, the data in unactivated channels will be ignored.
// the bit map of activated channel can not exceed the maximum enabled channel number (i.e. 0x10000 << total_chan_num).
// e.g: active_chan_mask = (I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH3), here the active_chan_number is 2 and total_chan_num is not supposed to be smaller than 4.
I2S_TDM_ACTIVE_CH0 = (0x1 << 16), /*!< I2S channel 0 activated */
I2S_TDM_ACTIVE_CH1 = (0x1 << 17), /*!< I2S channel 1 activated */
I2S_TDM_ACTIVE_CH2 = (0x1 << 18), /*!< I2S channel 2 activated */
I2S_TDM_ACTIVE_CH3 = (0x1 << 19), /*!< I2S channel 3 activated */
I2S_TDM_ACTIVE_CH4 = (0x1 << 20), /*!< I2S channel 4 activated */
I2S_TDM_ACTIVE_CH5 = (0x1 << 21), /*!< I2S channel 5 activated */
I2S_TDM_ACTIVE_CH6 = (0x1 << 22), /*!< I2S channel 6 activated */
I2S_TDM_ACTIVE_CH7 = (0x1 << 23), /*!< I2S channel 7 activated */
I2S_TDM_ACTIVE_CH8 = (0x1 << 24), /*!< I2S channel 8 activated */
I2S_TDM_ACTIVE_CH9 = (0x1 << 25), /*!< I2S channel 9 activated */
I2S_TDM_ACTIVE_CH10 = (0x1 << 26), /*!< I2S channel 10 activated */
I2S_TDM_ACTIVE_CH11 = (0x1 << 27), /*!< I2S channel 11 activated */
I2S_TDM_ACTIVE_CH12 = (0x1 << 28), /*!< I2S channel 12 activated */
I2S_TDM_ACTIVE_CH13 = (0x1 << 29), /*!< I2S channel 13 activated */
I2S_TDM_ACTIVE_CH14 = (0x1 << 30), /*!< I2S channel 14 activated */
I2S_TDM_ACTIVE_CH15 = (0x1 << 31), /*!< I2S channel 15 activated */
#endif
} i2s_channel_t;
/**
* @brief I2S communication standard format
*/
typedef enum {
I2S_COMM_FORMAT_STAND_I2S = 0X01, /*!< I2S communication I2S Philips standard, data launch at second BCK*/
I2S_COMM_FORMAT_STAND_MSB = 0X02, /*!< I2S communication MSB alignment standard, data launch at first BCK*/
I2S_COMM_FORMAT_STAND_PCM_SHORT = 0x04, /*!< PCM Short standard, also known as DSP mode. The period of synchronization signal (WS) is 1 bck cycle.*/
I2S_COMM_FORMAT_STAND_PCM_LONG = 0x0C, /*!< PCM Long standard. The period of synchronization signal (WS) is channel_bit*bck cycles.*/
I2S_COMM_FORMAT_STAND_MAX, /*!< standard max*/
//old definition will be removed in the future.
I2S_COMM_FORMAT_I2S __attribute__((deprecated)) = 0x01, /*!< I2S communication format I2S, correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_MSB __attribute__((deprecated)) = 0x01, /*!< I2S format MSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_MSB) correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_LSB __attribute__((deprecated)) = 0x02, /*!< I2S format LSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_LSB) correspond to `I2S_COMM_FORMAT_STAND_MSB`*/
I2S_COMM_FORMAT_PCM __attribute__((deprecated)) = 0x04, /*!< I2S communication format PCM, correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_SHORT __attribute__((deprecated)) = 0x04, /*!< PCM Short, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_SHORT) correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_LONG __attribute__((deprecated)) = 0x08, /*!< PCM Long, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_LONG) correspond to `I2S_COMM_FORMAT_STAND_PCM_LONG`*/
} i2s_comm_format_t;
/**
* @brief I2S channel format type
*/
typedef enum {
I2S_CHANNEL_FMT_RIGHT_LEFT, /*!< Separated left and right channel */
I2S_CHANNEL_FMT_ALL_RIGHT, /*!< Load right channel data in both two channels */
I2S_CHANNEL_FMT_ALL_LEFT, /*!< Load left channel data in both two channels */
I2S_CHANNEL_FMT_ONLY_RIGHT, /*!< Only load data in right channel (mono mode) */
I2S_CHANNEL_FMT_ONLY_LEFT, /*!< Only load data in left channel (mono mode) */
#if SOC_I2S_SUPPORTS_TDM
// Multiple channels are available with TDM feature
I2S_CHANNEL_FMT_MULTIPLE, /*!< More than two channels are used */
#endif
} i2s_channel_fmt_t;
/**
* @brief I2S Mode
*/
typedef enum {
I2S_MODE_MASTER = (0x1 << 0), /*!< Master mode*/
I2S_MODE_SLAVE = (0x1 << 1), /*!< Slave mode*/
I2S_MODE_TX = (0x1 << 2), /*!< TX mode*/
I2S_MODE_RX = (0x1 << 3), /*!< RX mode*/
#if SOC_I2S_SUPPORTS_DAC
//built-in DAC functions are only supported on I2S0 for ESP32 chip.
I2S_MODE_DAC_BUILT_IN = (0x1 << 4), /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
#endif // SOC_I2S_SUPPORTS_DAC
#if SOC_I2S_SUPPORTS_ADC
I2S_MODE_ADC_BUILT_IN = (0x1 << 5), /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/
#endif // SOC_I2S_SUPPORTS_ADC
// PDM functions are only supported on I2S0 (all chips).
I2S_MODE_PDM = (0x1 << 6), /*!< I2S PDM mode*/
} i2s_mode_t;
#if SOC_I2S_SUPPORTS_DAC
/**
* @brief I2S DAC mode for i2s_set_dac_mode.
*
* @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
*/
typedef enum {
I2S_DAC_CHANNEL_DISABLE = 0, /*!< Disable I2S built-in DAC signals*/
I2S_DAC_CHANNEL_RIGHT_EN = 1, /*!< Enable I2S built-in DAC right channel, maps to DAC channel 0 on GPIO25*/
I2S_DAC_CHANNEL_LEFT_EN = 2, /*!< Enable I2S built-in DAC left channel, maps to DAC channel 1 on GPIO26*/
I2S_DAC_CHANNEL_BOTH_EN = 0x3, /*!< Enable both of the I2S built-in DAC channels.*/
I2S_DAC_CHANNEL_MAX = 0x4, /*!< I2S built-in DAC mode max index*/
} i2s_dac_mode_t;
#endif //SOC_I2S_SUPPORTS_DAC
/**
* @brief I2S event queue types
*/
typedef enum {
I2S_EVENT_DMA_ERROR, /*!< I2S DMA has no next descriptor for sending or receiving */
I2S_EVENT_TX_DONE, /*!< I2S DMA finished sending one DMA buffer */
I2S_EVENT_RX_DONE, /*!< I2S DMA finished receiving one DMA buffer */
I2S_EVENT_TX_Q_OVF, /*!< I2S DMA sending queue overflowed, the oldest data has been overwritten by the new data in the DMA buffer */
I2S_EVENT_RX_Q_OVF, /*!< I2S DMA receive queue overflowed, the oldest data has been overwritten by the new data in the DMA buffer */
} i2s_event_type_t;
/**
* @brief Event structure used in I2S event queue
*/
typedef struct {
i2s_event_type_t type; /*!< I2S event type */
size_t size; /*!< I2S data size for I2S_DATA event*/
} i2s_event_t;
/**
* @brief I2S GPIO pins configuration
*/
typedef struct {
int mck_io_num; /*!< MCK pin, output */
int bck_io_num; /*!< BCK pin, input in slave role, output in master role */
int ws_io_num; /*!< WS pin, input in slave role, output in master role */
int data_out_num; /*!< DATA pin, output */
int data_in_num; /*!< DATA pin, input */
} i2s_pin_config_t;
#if SOC_I2S_SUPPORTS_PCM
/**
* @brief I2S PCM configuration
*
*/
typedef struct {
i2s_pcm_compress_t pcm_type; /*!< I2S PCM a/u-law decompress or compress type */
} i2s_pcm_cfg_t;
#endif
#if SOC_I2S_SUPPORTS_PDM_TX
/**
* @brief Default I2S PDM Up-Sampling Rate configuration
*/
#define I2S_PDM_DEFAULT_UPSAMPLE_CONFIG(rate) { \
.sample_rate = rate, \
.fp = 960, \
.fs = (rate) / 100, \
}
/**
* @brief I2S PDM up-sample rate configuration
* @note TX PDM can only be set to the following two up-sampling rate configurations:
* 1: fp = 960, fs = sample_rate / 100, in this case, Fpdm = 128*48000
* 2: fp = 960, fs = 480, in this case, Fpdm = 128*Fpcm = 128*sample_rate
* If the pdm receiver do not care the pdm serial clock, it's recommended set Fpdm = 128*48000.
* Otherwise, the second configuration should be applied.
*/
typedef struct {
int sample_rate; /*!< I2S PDM sample rate */
int fp; /*!< I2S PDM TX up-sampling parameter. Normally it should be set to 960 */
int fs; /*!< I2S PDM TX up-sampling parameter. When it is set to 480, the pdm clock frequency Fpdm = 128 * sample_rate, when it is set to sample_rate / 100， Fpdm will be fixed to 128*48000 */
} i2s_pdm_tx_upsample_cfg_t;
#endif
/**
* @brief I2S driver configuration parameters
*
*/
typedef struct {
i2s_mode_t mode; /*!< I2S work mode */
uint32_t sample_rate; /*!< I2S sample rate */
i2s_bits_per_sample_t bits_per_sample; /*!< I2S sample bits in one channel */
i2s_channel_fmt_t channel_format; /*!< I2S channel format.*/
i2s_comm_format_t communication_format; /*!< I2S communication format */
int intr_alloc_flags; /*!< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info */
union {
int dma_desc_num; /*!< The total number of descriptors used by I2S DMA to receive/transmit data */
int dma_buf_count __attribute__((deprecated)); /*!< This is an alias to 'dma_desc_num' for backward compatibility */
};
union {
int dma_frame_num; /*!< Frame number for one-time sampling. Frame here means the total data from all the channels in a WS cycle */
int dma_buf_len __attribute__((deprecated)); /*!< This is an alias to 'dma_frame_num' for backward compatibility */
};
bool use_apll; /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */
bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor if there is underflow condition (helps in avoiding noise in case of data unavailability) */
int fixed_mclk; /*!< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value. If fixed_mclk set, mclk_multiple won't take effect */
i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of I2S master clock(MCLK) to sample rate */
i2s_bits_per_chan_t bits_per_chan; /*!< I2S total bits in one channel， only take effect when larger than 'bits_per_sample', default '0' means equal to 'bits_per_sample' */
#if SOC_I2S_SUPPORTS_TDM
i2s_channel_t chan_mask; /*!< I2S active channel bit mask, set value in `i2s_channel_t` to enable specific channel, the bit map of active channel can not exceed (0x1<<total_chan). */
uint32_t total_chan; /*!< I2S Total number of channels. If it is smaller than the biggest active channel number, it will be set to this number automatically. */
bool left_align; /*!< Set to enable left alignment */
bool big_edin; /*!< Set to enable big endian */
bool bit_order_msb; /*!< Set to enable msb order */
bool skip_msk; /*!< Set to enable skip mask. If it is enabled, only the data of the enabled channels will be sent, otherwise all data stored in DMA TX buffer will be sent */
#endif // SOC_I2S_SUPPORTS_TDM
} i2s_driver_config_t;
typedef i2s_driver_config_t i2s_config_t; // for backward compatible
#ifdef __cplusplus
}
#endif

2003
components/driver/deprecated/i2s_legacy.c
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8
components/driver/test_apps/.build-test-rules.yml
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@@ -6,14 +6,6 @@ components/driver/test_apps/dac_test_apps/legacy_dac_driver:
depends_components:
- esp_adc
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac:
disable:
- if: SOC_I2S_SUPPORTS_ADC_DAC != 1
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver:
disable:
- if: SOC_I2S_SUPPORTED != 1
components/driver/test_apps/legacy_adc_driver:
disable:
- if: SOC_ADC_SUPPORTED != 1

8
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/CMakeLists.txt
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@@ -1,8 +0,0 @@
# This is the project CMakeLists.txt file for the test subproject
cmake_minimum_required(VERSION 3.16)
# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
set(COMPONENTS main)
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(i2s_adc_dac_test)

2
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/README.md
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@@ -1,2 +0,0 @@
| Supported Targets | ESP32 |
| ----------------- | ----- |

7
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/CMakeLists.txt
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@@ -1,7 +0,0 @@
set(srcs "test_app_main.c"
"test_i2s_adc.c"
"test_i2s_dac.c")
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity driver esp_event esp_adc
WHOLE_ARCHIVE)

53
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_app_main.c
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@@ -1,53 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "unity.h"
#include "unity_test_runner.h"
#include "esp_heap_caps.h"
// Some resources are lazy allocated in I2S driver, the threadhold is left for that case
#define TEST_MEMORY_LEAK_THRESHOLD (-400)
static size_t before_free_8bit;
static size_t before_free_32bit;
static void check_leak(size_t before_free, size_t after_free, const char *type)
{
ssize_t delta = after_free - before_free;
printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
}
void setUp(void)
{
before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
}
void tearDown(void)
{
size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
check_leak(before_free_8bit, after_free_8bit, "8BIT");
check_leak(before_free_32bit, after_free_32bit, "32BIT");
}
void app_main(void)
{
// ___ ____ ____ _____ _
// |_ _|___ \/ ___| |_ _|__ ___| |_
// | | __) \___ \ | |/ _ \/ __| __|
// | | / __/ ___) | | | __/\__ \ |_
// |___|_____|____/ |_|\___||___/\__|
printf(" ___ ____ ____ _____ _ \r\n");
printf(" |_ _|___ \\/ ___| |_ _|__ ___| |_ \r\n");
printf(" | | __) \\___ \\ | |/ _ \\/ __| __|\r\n");
printf(" | | / __/ ___) | | | __/\\__ \\ |_ \r\n");
printf(" |___|_____|____/ |_|\\___||___/\\__|(ADC/DAC)\r\n");
unity_run_menu();
}

4980
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_dac_audio_file.h
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File diff suppressed because it is too large Load Diff

251
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_adc.c
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@@ -1,251 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
Tests for the adc device driver on ESP32 only
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp_system.h"
#include "driver/adc.h"
#include "driver/rtc_io.h"
#include "driver/gpio.h"
#include "soc/adc_periph.h"
#include "unity.h"
#include "esp_system.h"
#include "esp_event.h"
#include "esp_log.h"
#include "esp_rom_sys.h"
/*
* ADC DMA testcase
*/
#include "driver/i2s.h"
//i2s number
#define EXAMPLE_I2S_NUM (0)
//i2s sample rate
#define EXAMPLE_I2S_SAMPLE_RATE (150000)
//i2s data bits
#define EXAMPLE_I2S_SAMPLE_BITS (16)
//enable display buffer for debug
#define EXAMPLE_I2S_BUF_DEBUG (0)
//I2S read buffer length
#define EXAMPLE_I2S_READ_LEN (16 * 1024)
//I2S data format, ADC-I2S only support mono.
#define EXAMPLE_I2S_FORMAT I2S_CHANNEL_FMT_ONLY_RIGHT
//I2S built-in ADC unit
#define I2S_ADC_UNIT ADC_UNIT_1
//I2S built-in ADC channel
#define I2S_ADC_CHANNEL ADC1_CHANNEL_4
#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
static void adc_fake_tie_middle(adc_unit_t adc_unit, adc_channel_t channel)
{
gpio_num_t gpio_num = 0;
if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLUP_PULLDOWN));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
}
if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLUP_PULLDOWN));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
}
vTaskDelay(10 / portTICK_PERIOD_MS);
}
static void adc_fake_tie_high(adc_unit_t adc_unit, adc_channel_t channel)
{
gpio_num_t gpio_num = 0;
if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLUP_ONLY));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY));
TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 1));
}
if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLUP_ONLY));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY));
TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 1));
}
vTaskDelay(10 / portTICK_PERIOD_MS);
}
static void adc_fake_tie_low(adc_unit_t adc_unit, adc_channel_t channel)
{
gpio_num_t gpio_num = 0;
if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLDOWN_ONLY));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY));
TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 0));
}
if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_en(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLDOWN_ONLY));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY));
TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 0));
}
vTaskDelay(10 / portTICK_PERIOD_MS);
}
static void adc_io_normal(adc_unit_t adc_unit, adc_channel_t channel)
{
gpio_num_t gpio_num = 0;
if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_FLOATING));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
}
if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));
TEST_ESP_OK(rtc_gpio_pulldown_dis(gpio_num));
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_FLOATING));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
}
vTaskDelay(10 / portTICK_PERIOD_MS);
}
/**
* @brief I2S ADC/DAC mode init.
*/
static void example_i2s_init(void)
{
int i2s_num = EXAMPLE_I2S_NUM;
i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_ADC_BUILT_IN,
.sample_rate = EXAMPLE_I2S_SAMPLE_RATE,
.bits_per_sample = EXAMPLE_I2S_SAMPLE_BITS,
.channel_format = EXAMPLE_I2S_FORMAT,
.intr_alloc_flags = 0,
.dma_desc_num = 2,
.dma_frame_num = 1024,
.use_apll = 0,
};
//install and start i2s driver
TEST_ESP_OK(i2s_driver_install(i2s_num, &i2s_config, 0, NULL));
//init ADC pad
TEST_ESP_OK(i2s_set_adc_mode(I2S_ADC_UNIT, I2S_ADC_CHANNEL));
}
static void example_i2s_deinit(void)
{
TEST_ESP_OK(i2s_driver_uninstall(EXAMPLE_I2S_NUM));
}
/**
* @brief debug buffer data
*/
static void example_disp_buf(uint8_t *buf, int length)
{
printf("\n======");
for (int i = 0; i < length; i += 2) {
uint16_t data = ((uint16_t)buf[i + 1] << 8) | (uint16_t)buf[i];
adc_digi_output_data_t *p = (adc_digi_output_data_t *)&data;
if ((i) % 16 == 0) {
printf("\n");
}
printf("[%d_%d] ", p->type1.channel, p->type1.data);
}
printf("\n======\n");
}
static esp_err_t adc_dma_data_check(uint8_t *buf, int length, int ideal_level)
{
for (int i = 0; i < length; i += 2) {
uint16_t data = ((uint16_t)buf[i + 1] << 8) | (uint16_t)buf[i];
adc_digi_output_data_t *p = (adc_digi_output_data_t *)&data;
if (p->type1.channel != I2S_ADC_CHANNEL) {
TEST_FAIL_MESSAGE("I2S-DMA data channel error!");
}
if (ideal_level == 1) { // high level 3.3v
TEST_ASSERT_EQUAL(0xFFF, p->type1.data);
} else if (ideal_level == 0) { // low level 0v
TEST_ASSERT_LESS_THAN(10, p->type1.data);
} else if (ideal_level == 2) { // middle level 1.4v
TEST_ASSERT_INT_WITHIN(128, 1586, p->type1.data);
} else if (ideal_level == 3) { // normal level
} else { // no check
}
}
return ESP_OK;
}
static void adc_dma_read(uint8_t *buf, int length)
{
size_t bytes_read = 0;
int flash_wr_size = 0;
vTaskDelay(pdTICKS_TO_MS(100));
while (flash_wr_size < length) {
//read data from I2S bus, in this case, from ADC.
TEST_ESP_OK(i2s_read(EXAMPLE_I2S_NUM, (void *) buf + flash_wr_size, length - flash_wr_size, &bytes_read, portMAX_DELAY));
flash_wr_size += bytes_read;
example_disp_buf((uint8_t *) buf, 128);
}
}
TEST_CASE("ADC_DMA_read", "[adc dma]")
{
int i2s_read_len = EXAMPLE_I2S_READ_LEN;
char *i2s_read_buff = (char *) calloc(i2s_read_len, sizeof(char));
example_i2s_init();
TEST_ESP_OK(i2s_adc_enable(EXAMPLE_I2S_NUM));
adc_fake_tie_low(I2S_ADC_UNIT, I2S_ADC_CHANNEL);
adc_dma_read((uint8_t *)i2s_read_buff, i2s_read_len);
adc_dma_data_check((uint8_t *)i2s_read_buff, i2s_read_len, 0);
adc_fake_tie_middle(I2S_ADC_UNIT, I2S_ADC_CHANNEL);
adc_dma_read((uint8_t *)i2s_read_buff, i2s_read_len);
adc_dma_data_check((uint8_t *)i2s_read_buff, i2s_read_len, 2);
adc_fake_tie_high(I2S_ADC_UNIT, I2S_ADC_CHANNEL);
adc_dma_read((uint8_t *)i2s_read_buff, i2s_read_len);
adc_dma_data_check((uint8_t *)i2s_read_buff, i2s_read_len, 1);
adc_io_normal(I2S_ADC_UNIT, I2S_ADC_CHANNEL);
TEST_ESP_OK(i2s_adc_disable(EXAMPLE_I2S_NUM));
if (i2s_read_buff) {
free(i2s_read_buff);
i2s_read_buff = NULL;
}
example_i2s_deinit();
}
#endif // CONFIG_IDF_TARGET_ESP32

157
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_dac.c
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@@ -1,157 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
Tests for the dac device driver on ESP32 only
Hardware connection:
- ESP32: GPIO25 <---> GPIO26
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp_system.h"
#include "unity.h"
#include "esp_system.h"
#include "esp_event.h"
#include "esp_log.h"
#include "test_dac_audio_file.h"
#include "driver/i2s.h"
#include "driver/dac.h"
/*
* DAC DMA config.
*/
//enable record sound and save in flash
#define RECORD_IN_FLASH_EN (1)
//enable replay recorded sound in flash
#define REPLAY_FROM_FLASH_EN (1)
//i2s number
#define EXAMPLE_I2S_NUM (0)
//i2s sample rate
#define EXAMPLE_I2S_SAMPLE_RATE (16000)
//i2s data bits
#define EXAMPLE_I2S_SAMPLE_BITS (16)
//enable display buffer for debug
#define EXAMPLE_I2S_BUF_DEBUG (0)
//I2S read buffer length
#define EXAMPLE_I2S_READ_LEN (16 * 1024)
//I2S data format
#define EXAMPLE_I2S_FORMAT (I2S_CHANNEL_FMT_RIGHT_LEFT)
//I2S channel number
#define EXAMPLE_I2S_CHANNEL_NUM ((EXAMPLE_I2S_FORMAT < I2S_CHANNEL_FMT_ONLY_RIGHT) ? (2) : (1))
/**
* @brief I2S ADC/DAC mode init.
*/
static void example_i2s_init(void)
{
int i2s_num = EXAMPLE_I2S_NUM;
i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_DAC_BUILT_IN,
.sample_rate = EXAMPLE_I2S_SAMPLE_RATE,
.bits_per_sample = EXAMPLE_I2S_SAMPLE_BITS,
.channel_format = EXAMPLE_I2S_FORMAT,
.intr_alloc_flags = 0,
.dma_desc_num = 2,
.dma_frame_num = 1024,
.use_apll = 0,
};
//install and start i2s driver
TEST_ESP_OK(i2s_driver_install(i2s_num, &i2s_config, 0, NULL));
//init DAC pad
TEST_ESP_OK(i2s_set_dac_mode(I2S_DAC_CHANNEL_BOTH_EN));
}
static void example_i2s_deinit(void)
{
TEST_ESP_OK(i2s_set_dac_mode(I2S_DAC_CHANNEL_DISABLE));
TEST_ESP_OK(i2s_driver_uninstall(EXAMPLE_I2S_NUM));
}
/**
* @brief Set i2s clock for example audio file
*/
static void example_set_file_play_mode(void)
{
TEST_ESP_OK(i2s_set_clk(EXAMPLE_I2S_NUM, 16000, EXAMPLE_I2S_SAMPLE_BITS, 1));
}
/**
* @brief Scale data to 16bit/32bit for I2S DMA output.
* DAC can only output 8bit data value.
* I2S DMA will still send 16 bit or 32bit data, the highest 8bit contains DAC data.
*/
static int example_i2s_dac_data_scale(uint8_t *d_buff, uint8_t *s_buff, uint32_t len)
{
uint32_t j = 0;
#if (EXAMPLE_I2S_SAMPLE_BITS == 16)
for (int i = 0; i < len; i++) {
d_buff[j++] = 0;
d_buff[j++] = s_buff[i];
}
return (len * 2);
#else
for (int i = 0; i < len; i++) {
d_buff[j++] = 0;
d_buff[j++] = 0;
d_buff[j++] = 0;
d_buff[j++] = s_buff[i];
}
return (len * 4);
#endif
}
/**
* @brief debug buffer data
*/
static void example_disp_buf(uint8_t *buf, int length)
{
printf("======\n");
for (int i = 0; i < length; i++) {
printf("%02x ", buf[i]);
if ((i + 1) % 8 == 0) {
printf("\n");
}
}
printf("======\n");
}
/**
* @brief Reset i2s clock and mode
*/
static void example_reset_play_mode(void)
{
TEST_ESP_OK(i2s_set_clk(EXAMPLE_I2S_NUM, EXAMPLE_I2S_SAMPLE_RATE, EXAMPLE_I2S_SAMPLE_BITS, EXAMPLE_I2S_CHANNEL_NUM));
}
TEST_CASE("DAC_DMA_output", "[dac]")
{
size_t bytes_written;
int i2s_read_len = EXAMPLE_I2S_READ_LEN;
uint8_t *i2s_write_buff = (uint8_t *) calloc(i2s_read_len, sizeof(char));
int offset = 0;
int tot_size = sizeof(audio_table);
printf("Playing file example: \n");
example_i2s_init();
example_set_file_play_mode();
while (offset < tot_size) {
int play_len = ((tot_size - offset) > (4 * 1024)) ? (4 * 1024) : (tot_size - offset);
int i2s_wr_len = example_i2s_dac_data_scale(i2s_write_buff, (uint8_t *)(audio_table + offset), play_len);
i2s_write(EXAMPLE_I2S_NUM, i2s_write_buff, i2s_wr_len, &bytes_written, portMAX_DELAY);
offset += play_len;
example_disp_buf((uint8_t *) i2s_write_buff, 32);
}
example_reset_play_mode();
free(i2s_write_buff);
example_i2s_deinit();
}
#endif // CONFIG_IDF_TARGET_ESP32

19
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/pytest_legacy_i2s_adc_dac.py
View File

@@ -1,19 +0,0 @@
# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Apache-2.0
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
'release',
],
indirect=True,
)
@idf_parametrize('target', ['esp32'], indirect=['target'])
def test_i2s_adc_dac(dut: Dut) -> None:
# ADC_DMA_read test takes more than 30 sec
dut.run_all_single_board_cases(timeout=60)

8
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/sdkconfig.ci.release
View File

@@ -1,8 +0,0 @@
CONFIG_PM_ENABLE=y
CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
CONFIG_COMPILER_DUMP_RTL_FILES=y
# silent the error check, as the error string are stored in rodata, causing RTL check failure
CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y

5
components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/sdkconfig.defaults
View File

@@ -1,5 +0,0 @@
CONFIG_I2S_SUPPRESS_DEPRECATE_WARN=y
CONFIG_ADC_SUPPRESS_DEPRECATE_WARN=y
CONFIG_DAC_SUPPRESS_DEPRECATE_WARN=y
CONFIG_I2S_ENABLE_DEBUG_LOG=y
CONFIG_ESP_TASK_WDT_EN=n

8
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/CMakeLists.txt
View File

@@ -1,8 +0,0 @@
# This is the project CMakeLists.txt file for the test subproject
cmake_minimum_required(VERSION 3.16)
# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
set(COMPONENTS main)
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(i2s_legacy_test)

2
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/README.md
View File

@@ -1,2 +0,0 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

6
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/CMakeLists.txt
View File

@@ -1,6 +0,0 @@
set(srcs "test_app_main.c"
"test_legacy_i2s.c")
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_pcnt driver
WHOLE_ARCHIVE)

53
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_app_main.c
View File

@@ -1,53 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "unity.h"
#include "unity_test_runner.h"
#include "esp_heap_caps.h"
// Some resources are lazy allocated in I2S driver, the threadhold is left for that case
#define TEST_MEMORY_LEAK_THRESHOLD (-400)
static size_t before_free_8bit;
static size_t before_free_32bit;
static void check_leak(size_t before_free, size_t after_free, const char *type)
{
ssize_t delta = after_free - before_free;
printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
}
void setUp(void)
{
before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
}
void tearDown(void)
{
size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
check_leak(before_free_8bit, after_free_8bit, "8BIT");
check_leak(before_free_32bit, after_free_32bit, "32BIT");
}
void app_main(void)
{
// ___ ____ ____ _____ _
// |_ _|___ \/ ___| |_ _|__ ___| |_
// | | __) \___ \ | |/ _ \/ __| __|
// | | / __/ ___) | | | __/\__ \ |_
// |___|_____|____/ |_|\___||___/\__|
printf(" ___ ____ ____ _____ _ \r\n");
printf(" |_ _|___ \\/ ___| |_ _|__ ___| |_ \r\n");
printf(" | | __) \\___ \\ | |/ _ \\/ __| __|\r\n");
printf(" | | / __/ ___) | | | __/\\__ \\ |_ \r\n");
printf(" |___|_____|____/ |_|\\___||___/\\__| (legacy)\r\n");
unity_run_menu();
}

977
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c
View File

@@ -1,977 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* I2S test environment UT_T1_I2S:
* We use internal signals instead of external wiring, but please keep the following IO connections, or connect nothing to prevent the signal from being disturbed.
* connect GPIO15 and GPIO19, GPIO25(ESP32)/GPIO17(ESP32-S2) and GPIO26, GPIO21 and GPIO22(ESP32)/GPIO20(ESP32-S2)
* Please do not connect GPIO32(ESP32) any pull-up resistors externally, it will be used to test i2s adc function.
*/
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "driver/i2s.h"
#include "hal/i2s_hal.h"
#include "soc/i2s_periph.h"
#include "soc/soc_caps.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "hal/gpio_hal.h"
#include "unity.h"
#include "math.h"
#include "esp_rom_gpio.h"
#if SOC_PCNT_SUPPORTED
#include "driver/pulse_cnt.h"
#include "soc/pcnt_periph.h"
#endif
#ifdef CONFIG_PM_ENABLE
#include "esp_pm.h"
#endif
#include "../../test_inc/test_i2s.h"
#define PERCENT_DIFF 0.0001
#define I2S_TEST_MODE_SLAVE_TO_MASTER 0
#define I2S_TEST_MODE_MASTER_TO_SLAVE 1
#define I2S_TEST_MODE_LOOPBACK 2
// mode: 0, master rx, slave tx. mode: 1, master tx, slave rx. mode: 2, master tx rx loop-back
// Since ESP32-S2 has only one I2S, only loop back test can be tested.
static void i2s_test_io_config(int mode)
{
// Connect internal signals using IO matrix.
gpio_func_sel(MASTER_BCK_IO, PIN_FUNC_GPIO);
gpio_func_sel(MASTER_WS_IO, PIN_FUNC_GPIO);
gpio_func_sel(DATA_OUT_IO, PIN_FUNC_GPIO);
gpio_set_direction(MASTER_BCK_IO, GPIO_MODE_INPUT_OUTPUT);
gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
gpio_set_direction(DATA_OUT_IO, GPIO_MODE_INPUT_OUTPUT);
switch (mode) {
#if SOC_I2S_NUM > 1
case I2S_TEST_MODE_SLAVE_TO_MASTER: {
esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, i2s_periph_signal[0].m_rx_bck_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, i2s_periph_signal[1].s_tx_bck_sig, 0);
esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_rx_ws_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_WS_IO, i2s_periph_signal[1].s_tx_ws_sig, 0);
esp_rom_gpio_connect_out_signal(DATA_OUT_IO, i2s_periph_signal[1].data_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(DATA_OUT_IO, i2s_periph_signal[0].data_in_sig, 0);
}
break;
case I2S_TEST_MODE_MASTER_TO_SLAVE: {
esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, i2s_periph_signal[0].m_tx_bck_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, i2s_periph_signal[1].s_rx_bck_sig, 0);
esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_WS_IO, i2s_periph_signal[1].s_rx_ws_sig, 0);
esp_rom_gpio_connect_out_signal(DATA_OUT_IO, i2s_periph_signal[0].data_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(DATA_OUT_IO, i2s_periph_signal[1].data_in_sig, 0);
}
break;
#endif
case I2S_TEST_MODE_LOOPBACK: {
esp_rom_gpio_connect_out_signal(DATA_OUT_IO, i2s_periph_signal[0].data_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(DATA_OUT_IO, i2s_periph_signal[0].data_in_sig, 0);
}
break;
default: {
TEST_FAIL_MESSAGE("error: mode not supported");
}
break;
}
}
#if SOC_I2S_SUPPORTS_ADC
#define ADC1_CHANNEL_4_IO 32
/* Only ESP32 need I2S adc/dac test */
TEST_CASE("I2S_adc_test", "[i2s_legacy]")
{
// init I2S ADC
i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_ADC_BUILT_IN,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.intr_alloc_flags = 0,
.dma_desc_num = 2,
.dma_frame_num = 1024,
.use_apll = 0,
};
// install and start I2S driver
i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL);
// init ADC pad
i2s_set_adc_mode(ADC_UNIT_1, ADC1_CHANNEL_4);
// enable adc sampling, ADC_WIDTH_BIT_12, ADC_ATTEN_DB_12 hard-coded in adc_i2s_mode_init
i2s_adc_enable(I2S_NUM_0);
// init read buffer
uint16_t *i2sReadBuffer = (uint16_t *)calloc(1024, sizeof(uint16_t));
size_t bytesRead;
for (int loop = 0; loop < 10; loop++) {
for (int level = 0; level <= 1; level++) {
if (level == 0) {
gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLDOWN_ONLY);
} else {
gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLUP_ONLY);
}
vTaskDelay(pdMS_TO_TICKS(200));
// read data from adc, will block until buffer is full
i2s_read(I2S_NUM_0, (void *)i2sReadBuffer, 1024 * sizeof(uint16_t), &bytesRead, portMAX_DELAY);
// calc average
int64_t adcSumValue = 0;
for (size_t i = 0; i < 1024; i++) {
adcSumValue += i2sReadBuffer[i] & 0xfff;
}
int adcAvgValue = adcSumValue / 1024;
printf("adc average val: %d\n", adcAvgValue);
if (level == 0) {
if (adcAvgValue > 100) {
i2s_adc_disable(I2S_NUM_0);
free(i2sReadBuffer);
i2s_driver_uninstall(I2S_NUM_0);
TEST_ASSERT_LESS_THAN(100, adcAvgValue);
}
} else {
if (adcAvgValue < 4000) {
i2s_adc_disable(I2S_NUM_0);
free(i2sReadBuffer);
i2s_driver_uninstall(I2S_NUM_0);
TEST_ASSERT_GREATER_THAN(4000, adcAvgValue);
}
}
}
}
i2s_adc_disable(I2S_NUM_0);
free(i2sReadBuffer);
i2s_driver_uninstall(I2S_NUM_0);
}
#endif
/**
* i2s initialize test
* 1. i2s_driver_install
* 2. i2s_set_pin
*/
TEST_CASE("I2S_basic_driver_installation_uninstallation_and_settings_test", "[i2s_legacy]")
{
// dac, adc i2s
i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 60,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
// normal i2s
i2s_pin_config_t pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
QueueHandle_t evt_que;
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 16, &evt_que));
TEST_ASSERT(evt_que);
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
//error param test
TEST_ASSERT(i2s_driver_install(SOC_I2S_NUM, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
TEST_ASSERT(i2s_driver_install(I2S_NUM_0, NULL, 0, NULL) == ESP_ERR_INVALID_ARG);
i2s_config.dma_desc_num = 1;
TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
i2s_config.dma_desc_num = 129;
TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, i2s_driver_uninstall(I2S_NUM_0));
}
static bool whether_contains_exapected_data(uint16_t *src, uint32_t src_len, uint32_t src_step, uint32_t start_val, uint32_t val_step)
{
uint32_t val = start_val;
uint32_t index_step = 1;
for (int i = 0; val < 100 && i < src_len; i += index_step) {
if (src[i] == val) {
if (val == start_val && i < src_len - 8) {
printf("start index: %d ---> \n%d %d %d %d %d %d %d %d\n", i,
src[i], src[i + 1], src[i + 2], src[i + 3],
src[i + 4], src[i + 5], src[i + 6], src[i + 7]);
}
index_step = src_step;
val += val_step;
} else {
index_step = 1;
val = start_val;
}
}
return val >= 100;
}
/**
* @brief Test mono and stereo mode of I2S by loopback
* @note Only rx channel distinguish left mono and right mono, tx channel does not
* @note 1. Check switch mono/stereo by 'i2s_set_clk'
* 2. Check rx right mono and left mono (requiring tx works in stereo mode)
* 3. Check tx mono (requiring rx works in stereo mode)
*/
TEST_CASE("I2S_legacy_mono_stereo_loopback_test", "[i2s_legacy]")
{
#define WRITE_BUF_LEN 2000
#define READ_BUF_LEN 4000
#define RETEY_TIMES 3
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_ONLY_RIGHT,
.communication_format = I2S_COMM_FORMAT_STAND_MSB,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
i2s_pin_config_t master_pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = DATA_IN_IO
};
/* Install I2S in duplex mode */
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_stop(I2S_NUM_0));
/* Config TX as stereo channel directly, because legacy driver can't support config tx&rx separately */
#if SOC_I2S_HW_VERSION_1
i2s_ll_tx_select_std_slot(&I2S0, I2S_STD_SLOT_BOTH, false);
#else
i2s_ll_tx_select_std_slot(&I2S0, I2S_STD_SLOT_BOTH);
#endif
i2s_ll_tx_enable_mono_mode(&I2S0, false);
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
i2s_test_io_config(I2S_TEST_MODE_LOOPBACK);
TEST_ESP_OK(i2s_start(I2S_NUM_0));
uint16_t *w_buf = calloc(1, WRITE_BUF_LEN);
uint16_t *r_buf = calloc(1, READ_BUF_LEN);
size_t w_bytes = 0;
size_t r_bytes = 0;
uint32_t retry = 0;
bool is_failed = false;
for (int n = 0; n < WRITE_BUF_LEN / 2; n++) {
w_buf[n] = n % 100;
}
/* rx right mono test
* tx format: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ...
* rx receive: 0x01[R] 0x03[R] ... */
TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
for (retry = 0; retry < RETEY_TIMES; retry++) {
TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
#if CONFIG_IDF_TARGET_ESP32
/* The data of tx/rx channels are flipped on ESP32 */
for (int n = 0; n < READ_BUF_LEN / 2; n += 2) {
int16_t temp = r_buf[n];
r_buf[n] = r_buf[n + 1];
r_buf[n + 1] = temp;
}
#endif
/* Expected: 1 3 5 7 9 ... 97 99 */
if (whether_contains_exapected_data(r_buf, READ_BUF_LEN / 2, 1, 1, 2)) {
break;
}
}
if (retry >= RETEY_TIMES) {
printf("rx right mono test failed\n");
is_failed = true;
goto err;
}
printf("rx right mono test passed\n");
/* tx/rx stereo test
* tx format: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ...
* rx receive: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ... */
TEST_ESP_OK(i2s_set_clk(I2S_NUM_0, SAMPLE_RATE, SAMPLE_BITS, I2S_CHANNEL_STEREO));
TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
for (retry = 0; retry < RETEY_TIMES; retry++) {
TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
/* Expected: 1 2 3 4 ... 98 99 */
if (whether_contains_exapected_data(r_buf, READ_BUF_LEN / 2, 1, 1, 1)) {
break;
}
}
if (retry >= RETEY_TIMES) {
printf("tx/rx stereo test failed\n");
is_failed = true;
goto err;
}
printf("tx/rx stereo test passed\n");
/* tx mono rx right mono test
* tx format: 0x01[L] 0x01[R] 0x02[L] 0x02[R] ...
* rx receive: 0x01[R] 0x02[R] ... */
TEST_ESP_OK(i2s_set_clk(I2S_NUM_0, SAMPLE_RATE, I2S_BITS_PER_SAMPLE_32BIT, I2S_CHANNEL_MONO));
TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
for (retry = 0; retry < RETEY_TIMES; retry++) {
TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
/* Expected: 1 2 3 4 ... 98 99 */
if (whether_contains_exapected_data(r_buf, READ_BUF_LEN / 2, 1, 1, 1)) {
break;
}
}
if (retry >= RETEY_TIMES) {
printf("tx/rx mono test failed\n");
is_failed = true;
goto err;
}
printf("tx/rx mono test passed\n");
/* Reinstalling I2S to test rx left mono */
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
master_i2s_config.channel_format = I2S_CHANNEL_FMT_ONLY_LEFT;
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_stop(I2S_NUM_0));
#if SOC_I2S_HW_VERSION_1
i2s_ll_tx_select_std_slot(&I2S0, I2S_STD_SLOT_BOTH, false);
#else
i2s_ll_tx_select_std_slot(&I2S0, I2S_STD_SLOT_BOTH);
#endif
i2s_ll_tx_enable_mono_mode(&I2S0, false);
TEST_ESP_OK(i2s_start(I2S_NUM_0));
/* rx left mono test
* tx format: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ...
* rx receive: 0x00[R] 0x02[R] ... */
TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
for (retry = 0; retry < RETEY_TIMES; retry++) {
TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
#if CONFIG_IDF_TARGET_ESP32
/* The data of tx/rx channels are flipped on ESP32 */
for (int n = 0; n < READ_BUF_LEN / 2; n += 2) {
int16_t temp = r_buf[n];
r_buf[n] = r_buf[n + 1];
r_buf[n + 1] = temp;
}
#endif
/* Expected: 2 4 6 8 10 ... 96 98 */
if (whether_contains_exapected_data(r_buf, READ_BUF_LEN / 2, 1, 2, 2)) {
break;
}
}
if (retry >= RETEY_TIMES) {
printf("rx left mono test failed\n");
is_failed = true;
goto err;
}
printf("rx left mono test passed\n");
err:
if (is_failed) {
for (int i = 0; i < READ_BUF_LEN / 2; i++) {
printf("%x ", r_buf[i]);
}
printf("\n");
}
free(w_buf);
free(r_buf);
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
TEST_ASSERT_FALSE(is_failed);
}
#if SOC_I2S_SUPPORTS_TDM
TEST_CASE("I2S_TDM_loopback_test_with_master_tx_and_rx", "[i2s_legacy]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_MULTIPLE,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.total_chan = 4,
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1 | I2S_TDM_ACTIVE_CH2 | I2S_TDM_ACTIVE_CH3,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
};
i2s_pin_config_t master_pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = DATA_IN_IO
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
i2s_test_io_config(I2S_TEST_MODE_LOOPBACK);
printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size());
uint8_t *data_wr = (uint8_t *)calloc(1, sizeof(uint8_t) * 400);
size_t i2s_bytes_write = 0;
size_t bytes_read = 0;
int length = 0;
uint8_t *i2s_read_buff = (uint8_t *)calloc(1, sizeof(uint8_t) * 10000);
for (int i = 0; i < 100; i++) {
data_wr[i] = i + 1;
}
int flag = 0; // break loop flag
int end_position = 0;
// write data to slave
i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
while (!flag) {
if (length >= 10000 - 500) {
break;
}
i2s_read(I2S_NUM_0, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portMAX_DELAY);
if (bytes_read > 0) {
for (int i = length; i < length + bytes_read; i++) {
if (i2s_read_buff[i] == 100) {
flag = 1;
end_position = i;
break;
}
}
}
length = length + bytes_read;
}
// test the read data right or not
for (int i = end_position - 99; i <= end_position; i++) {
TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
}
free(data_wr);
free(i2s_read_buff);
i2s_driver_uninstall(I2S_NUM_0);
}
#endif
#if SOC_I2S_NUM > 1
/* ESP32S2 and ESP32C3 has only single I2S port and hence following test cases are not applicable */
TEST_CASE("I2S_write_and_read_test_with_master_tx_and_slave_rx", "[i2s_legacy]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
i2s_pin_config_t master_pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE);
printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size());
i2s_config_t slave_i2s_config = {
.mode = I2S_MODE_SLAVE | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
i2s_pin_config_t slave_pin_config = {
.mck_io_num = -1,
.bck_io_num = SLAVE_BCK_IO,
.ws_io_num = SLAVE_WS_IO,
.data_out_num = -1,
.data_in_num = DATA_IN_IO,
};
// slave driver installed and receive data
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE);
printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size());
uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
size_t i2s_bytes_write = 0;
size_t bytes_read = 0;
int length = 0;
uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
for (int i = 0; i < 100; i++) {
data_wr[i] = i + 1;
}
int flag = 0; // break loop flag
int end_position = 0;
// write data to slave
i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
printf("write data size: %d\n", i2s_bytes_write);
while (!flag) {
i2s_read(I2S_NUM_1, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portTICK_PERIOD_MS);
if (bytes_read > 0) {
printf("read data size: %d\n", bytes_read);
for (int i = length; i < length + bytes_read; i++) {
if (i2s_read_buff[i] == 100) {
flag = 1;
end_position = i;
break;
}
}
}
length = length + bytes_read;
}
// test the read data right or not
for (int i = end_position - 99; i <= end_position; i++) {
TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
}
free(data_wr);
free(i2s_read_buff);
i2s_driver_uninstall(I2S_NUM_0);
i2s_driver_uninstall(I2S_NUM_1);
}
TEST_CASE("I2S_write_and_read_test_master_rx_and_slave_tx", "[i2s_legacy]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 1,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
i2s_pin_config_t master_pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = -1,
.data_in_num = DATA_IN_IO,
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MASTER);
printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size());
i2s_config_t slave_i2s_config = {
.mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only RX
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 1,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
i2s_pin_config_t slave_pin_config = {
.mck_io_num = -1,
.bck_io_num = SLAVE_BCK_IO,
.ws_io_num = SLAVE_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
// slave driver installed and receive data
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MASTER);
printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size());
uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
size_t i2s_bytes_write = 0;
size_t bytes_read = 0;
int length = 0;
uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
for (int i = 0; i < 100; i++) {
data_wr[i] = i + 1;
}
// slave write data to master
i2s_write(I2S_NUM_1, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
printf("write data size: %d\n", i2s_bytes_write);
int flag = 0; // break loop flag
volatile int end_position = 0;
// write data to slave
while (!flag) {
TEST_ESP_OK(i2s_read(I2S_NUM_0, i2s_read_buff + length, 10000 - length, &bytes_read, 1000 / portTICK_PERIOD_MS));
if (bytes_read > 0) {
printf("read data size: %d\n", bytes_read);
for (int i = length; i < length + bytes_read; i++) {
if (i2s_read_buff[i] == 100) {
flag = 1;
end_position = i;
break;
}
}
}
length = length + bytes_read;
}
// test the read data right or not
for (int i = end_position - 99; i <= end_position; i++) {
TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
}
free(data_wr);
free(i2s_read_buff);
i2s_driver_uninstall(I2S_NUM_0);
i2s_driver_uninstall(I2S_NUM_1);
}
#endif
TEST_CASE("I2S_memory_leaking_test", "[i2s_legacy]")
{
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
i2s_pin_config_t master_pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = -1,
.data_in_num = DATA_IN_IO
};
uint8_t *w_buf = calloc(1, 2000);
TEST_ASSERT(w_buf);
uint8_t *r_buf = calloc(1, 2000);
TEST_ASSERT(r_buf);
size_t w_bytes = 0;
size_t r_bytes = 0;
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, 2000, &w_bytes, portMAX_DELAY));
TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, 2000, &r_bytes, portMAX_DELAY));
i2s_driver_uninstall(I2S_NUM_0);
int initial_size = esp_get_free_heap_size();
for (int i = 0; i < 50; i++) {
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, 2000, &w_bytes, portMAX_DELAY));
TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, 2000, &r_bytes, portMAX_DELAY));
i2s_driver_uninstall(I2S_NUM_0);
TEST_ASSERT(initial_size == esp_get_free_heap_size());
}
vTaskDelay(100 / portTICK_PERIOD_MS);
TEST_ASSERT(initial_size == esp_get_free_heap_size());
free(w_buf);
free(r_buf);
}
#if SOC_I2S_SUPPORTS_APLL
/*
* The I2S APLL clock variation test used to test the difference between the different sample rates, different bits per sample
* and the APLL clock generate for it. The TEST_CASE passes PERCENT_DIFF variation from the provided sample rate in APLL generated clock
* The percentage difference calculated as (mod((obtained clock rate - desired clock rate)/(desired clock rate))) * 100.
*/
TEST_CASE("I2S_APLL_clock_variation_test", "[i2s_legacy]")
{
i2s_pin_config_t pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 60,
.use_apll = true,
.intr_alloc_flags = 0,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
int initial_size = esp_get_free_heap_size();
uint32_t sample_rate_arr[8] = { 10675, 11025, 16000, 22050, 32000, 44100, 48000, 96000 };
int bits_per_sample_arr[3] = { 16, 24, 32 };
for (int i = 0; i < (sizeof(sample_rate_arr) / sizeof(sample_rate_arr[0])); i++) {
for (int j = 0; j < (sizeof(bits_per_sample_arr) / sizeof(bits_per_sample_arr[0])); j++) {
i2s_config.sample_rate = sample_rate_arr[i];
i2s_config.bits_per_sample = bits_per_sample_arr[j];
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
TEST_ASSERT((fabs((i2s_get_clk(I2S_NUM_0) - sample_rate_arr[i])) / (sample_rate_arr[i])) * 100 < PERCENT_DIFF);
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
TEST_ASSERT(initial_size == esp_get_free_heap_size());
}
}
vTaskDelay(100 / portTICK_PERIOD_MS);
TEST_ASSERT(initial_size == esp_get_free_heap_size());
}
#endif
#if SOC_I2S_SUPPORTS_DAC
TEST_CASE("I2S_dac_test", "[i2s_legacy]")
{
// dac, adc i2s
i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 60,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
};
//install and start i2s driver
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
//for internal DAC, this will enable both of the internal channels
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, NULL));
//stop & destroy i2s driver
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
}
#endif
/*------------------------------ Clock Test --------------------------------*/
#if SOC_PCNT_SUPPORTED
#define TEST_I2S_PERIOD_MS 100
static void i2s_test_common_sample_rate(i2s_port_t id)
{
/* Prepare configuration for the PCNT unit */
pcnt_unit_handle_t pcnt_unit = NULL;
pcnt_channel_handle_t pcnt_chan = NULL;
pcnt_unit_config_t unit_config = {
.high_limit = (int16_t)0x7fff,
.low_limit = (int16_t)0x8000,
};
pcnt_chan_config_t chan_config = {
.edge_gpio_num = MASTER_WS_IO,
.level_gpio_num = -1,
};
TEST_ESP_OK(pcnt_new_unit(&unit_config, &pcnt_unit));
TEST_ESP_OK(pcnt_unit_set_glitch_filter(pcnt_unit, NULL));
TEST_ESP_OK(pcnt_new_channel(pcnt_unit, &chan_config, &pcnt_chan));
TEST_ESP_OK(pcnt_channel_set_edge_action(pcnt_chan, PCNT_CHANNEL_EDGE_ACTION_INCREASE, PCNT_CHANNEL_EDGE_ACTION_HOLD));
TEST_ESP_OK(pcnt_channel_set_level_action(pcnt_chan, PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_KEEP));
TEST_ESP_OK(pcnt_unit_enable(pcnt_unit));
// Reconfig GPIO signal
gpio_func_sel(MASTER_WS_IO, PIN_FUNC_GPIO);
gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_WS_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0);
const uint32_t test_freq[] = {
8000, 10000, 11025, 12000, 16000, 22050,
24000, 32000, 44100, 48000, 64000, 88200,
96000, 128000, 144000, 196000
};
int real_pulse = 0;
#if CONFIG_IDF_ENV_FPGA || CONFIG_IDF_TARGET_ESP32P4
// Limit the test sample rate on FPGA platform due to the low frequency it supports.
int case_cnt = 10;
#else
int case_cnt = sizeof(test_freq) / sizeof(uint32_t);
#endif
#if SOC_I2S_SUPPORTS_PLL_F96M
// 196000 Hz sample rate doesn't support on PLL_96M target
case_cnt = 15;
#endif
// Acquire the PM lock in case Dynamic Frequency Scaling(DFS) lower the frequency
#ifdef CONFIG_PM_ENABLE
esp_pm_lock_handle_t pm_lock;
esp_pm_lock_type_t pm_type = ESP_PM_APB_FREQ_MAX;
TEST_ESP_OK(esp_pm_lock_create(pm_type, 0, "legacy_i2s_test", &pm_lock));
esp_pm_lock_acquire(pm_lock);
#endif
for (int i = 0; i < case_cnt; i++) {
int expt_pulse = (int16_t)((float)test_freq[i] * (TEST_I2S_PERIOD_MS / 1000.0));
TEST_ESP_OK(i2s_set_clk(id, test_freq[i], SAMPLE_BITS, I2S_CHANNEL_STEREO));
vTaskDelay(1); // Waiting for hardware totally started
// pcnt will count the pulse number on WS signal in 100ms
TEST_ESP_OK(pcnt_unit_clear_count(pcnt_unit));
TEST_ESP_OK(pcnt_unit_start(pcnt_unit));
vTaskDelay(pdMS_TO_TICKS(TEST_I2S_PERIOD_MS));
TEST_ESP_OK(pcnt_unit_stop(pcnt_unit));
TEST_ESP_OK(pcnt_unit_get_count(pcnt_unit, &real_pulse));
printf("[%"PRIu32" Hz] %d pulses, expected %d, err %d\n", test_freq[i], real_pulse, expt_pulse, real_pulse - expt_pulse);
// Check if the error between real pulse number and expected pulse number is within 1%
TEST_ASSERT_INT_WITHIN(expt_pulse * 0.01, expt_pulse, real_pulse);
}
#ifdef CONFIG_PM_ENABLE
esp_pm_lock_release(pm_lock);
esp_pm_lock_delete(pm_lock);
#endif
TEST_ESP_OK(pcnt_del_channel(pcnt_chan));
TEST_ESP_OK(pcnt_unit_stop(pcnt_unit));
TEST_ESP_OK(pcnt_unit_disable(pcnt_unit));
TEST_ESP_OK(pcnt_del_unit(pcnt_unit));
}
TEST_CASE("I2S clock frequency test", "[i2s_legacy]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_desc_num = 6,
.dma_frame_num = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
#if SOC_I2S_SUPPORTS_TDM
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
.total_chan = 2,
.left_align = false,
.big_edin = false,
.bit_order_msb = false,
.skip_msk = false
#endif
};
i2s_pin_config_t master_pin_config = {
.mck_io_num = -1,
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
/* Non-APLL test */
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
i2s_test_common_sample_rate(I2S_NUM_0);
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
/* APLL test */
#if SOC_I2S_SUPPORTS_APLL
master_i2s_config.use_apll = true;
master_i2s_config.mclk_multiple = I2S_MCLK_MULTIPLE_256;
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
i2s_test_common_sample_rate(I2S_NUM_0);
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
#endif
}
#endif // SOC_PCNT_SUPPORTED

22
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/pytest_legacy_i2s.py
View File

@@ -1,22 +0,0 @@
# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Apache-2.0
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
'release',
],
indirect=True,
)
@idf_parametrize(
'target',
['esp32', 'esp32s2', 'esp32c3', 'esp32c5', 'esp32s3', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c61'],
indirect=['target'],
)
def test_legacy_i2s(dut: Dut) -> None:
dut.run_all_single_board_cases()

5
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/sdkconfig.ci.release
View File

@@ -1,5 +0,0 @@
CONFIG_PM_ENABLE=y
CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

4
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/sdkconfig.defaults
View File

@@ -1,4 +0,0 @@
CONFIG_I2S_SUPPRESS_DEPRECATE_WARN=y
CONFIG_ADC_SUPPRESS_DEPRECATE_WARN=y
CONFIG_I2S_ENABLE_DEBUG_LOG=y
CONFIG_ESP_TASK_WDT_EN=n

67
components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h
View File

@@ -1,67 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SAMPLE_RATE (48000)
#define SAMPLE_BITS (16)
#if CONFIG_IDF_TARGET_ESP32
#define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4
#define MASTER_WS_IO 5
#define SLAVE_BCK_IO 21
#define SLAVE_WS_IO 22
#define DATA_IN_IO 19
#define DATA_OUT_IO 18
#elif CONFIG_IDF_TARGET_ESP32S2
#define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4
#define MASTER_WS_IO 5
#define SLAVE_BCK_IO 14
#define SLAVE_WS_IO 15
#define DATA_IN_IO 19
#define DATA_OUT_IO 18
#elif CONFIG_IDF_TARGET_ESP32C3
#define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4
#define MASTER_WS_IO 5
#define SLAVE_BCK_IO 14
#define SLAVE_WS_IO 15
#define DATA_IN_IO 19
#define DATA_OUT_IO 18
#elif CONFIG_IDF_TARGET_ESP32S3
#define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4
#define MASTER_WS_IO 5
#define SLAVE_BCK_IO 14
#define SLAVE_WS_IO 15
#define DATA_IN_IO 19
#define DATA_OUT_IO 18
#elif CONFIG_IDF_TARGET_ESP32P4
#define MASTER_MCK_IO 51
#define MASTER_BCK_IO 45
#define MASTER_WS_IO 46
#define SLAVE_BCK_IO 22
#define SLAVE_WS_IO 23
#define DATA_IN_IO 47
#define DATA_OUT_IO 48
#else
#define MASTER_MCK_IO 0
#define MASTER_BCK_IO 4
#define MASTER_WS_IO 5
#define SLAVE_BCK_IO 2
#define SLAVE_WS_IO 3
#define DATA_IN_IO 6
#define DATA_OUT_IO 7
#endif
#ifdef __cplusplus
}
#endif

1
docs/en/api-reference/peripherals/i2s.rst
View File

@@ -350,7 +350,6 @@ Kconfig Options
^^^^^^^^^^^^^^^
- :ref:`CONFIG_I2S_ISR_IRAM_SAFE` controls whether the default ISR handler can work when the cache is disabled. See `IRAM Safe <#iram-safe>`__ for more information.
- :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN` controls whether to suppress the compiling warning message while using the legacy I2S driver.
- :ref:`CONFIG_I2S_ENABLE_DEBUG_LOG` is used to enable the debug log output. Enable this option increases the firmware binary size.
Application Example

4
docs/en/migration-guides/release-5.x/5.0/peripherals.rst
View File

@@ -462,12 +462,14 @@ LCD
.. only:: SOC_I2S_SUPPORTED
.. _deprecate_i2s_legacy_driver:
I2S Driver
----------
The I2S driver has been redesigned (see :doc:`I2S Driver <../../../api-reference/peripherals/i2s>`), which aims to rectify the shortcomings of the driver that were exposed when supporting all the new features of ESP32-C3 & ESP32-S3. The new driver's APIs are available by including corresponding I2S mode's header files :component_file:`esp_driver_i2s/include/driver/i2s_std.h`, :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h`, or :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h`.
Meanwhile, the old driver's APIs in :component_file:`driver/deprecated/driver/i2s.h` are still supported for backward compatibility. But there will be warnings if users keep using the old APIs in their projects, these warnings can be suppressed by the Kconfig option :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN`.
Meanwhile, the old driver's APIs in ``driver/i2s.h`` are still supported for backward compatibility. But there will be warnings if users keep using the old APIs in their projects, these warnings can be suppressed by the Kconfig option ``CONFIG_I2S_SUPPRESS_DEPRECATE_WARN``.
Here is the general overview of the current I2S files:

7
docs/en/migration-guides/release-6.x/6.0/peripherals.rst
View File

@@ -54,3 +54,10 @@ Legacy Timer Group Driver is Removed
------------------------------------
The legacy timer group driver ``driver/timer.h`` is deprecated since version 5.0 (see :ref:`deprecate_gptimer_legacy_driver`). Starting from version 6.0, the legacy driver is completely removed. The new driver is placed in the :component:`esp_driver_gptimer`, and the header file path is ``driver/gptimer.h``.
.. only:: SOC_I2S_SUPPORTED
Legacy I2S Driver is Removed
------------------------------------
The legacy i2s driver ``driver/i2s.h`` is deprecated since version 5.0 (see :ref:`deprecate_i2s_legacy_driver`). Starting from version 6.0, the legacy driver is completely removed. The new driver is placed in the :component:`esp_driver_i2s`, and the header file path is ``driver/i2s_std.h``, ``driver/i2s_pdm.h`` and ``driver/i2s_tdm.h``.

1
docs/zh_CN/api-reference/peripherals/i2s.rst
View File

@@ -350,7 +350,6 @@ Kconfig 选项
^^^^^^^^^^^^
- :ref:`CONFIG_I2S_ISR_IRAM_SAFE` 控制默认 ISR 处理程序能否在禁用 cache 的情况下工作。更多信息可参考 `IRAM 安全 <#iram-safe>`__。
- :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN` 控制是否在使用原有 I2S 驱动时关闭警告信息。
- :ref:`CONFIG_I2S_ENABLE_DEBUG_LOG` 用于启用调试日志输出。启用该选项将增加固件的二进制文件大小。
应用实例

4
docs/zh_CN/migration-guides/release-5.x/5.0/peripherals.rst
View File

@@ -462,12 +462,14 @@ LCD
.. only:: SOC_I2S_SUPPORTED
.. _deprecate_i2s_legacy_driver:
I2S 驱动
-----------------------
旧版 I2S 驱动在支持 ESP32-C3 和 ESP32-S3 新功能时暴露了很多缺点，为解决这些缺点，I2S 驱动已更新（请参考:doc:`I2S Driver <../../../api-reference/peripherals/i2s>`）。用户可以通过引用不同 I2S 模式对应的头文件来使用新版驱动的 API，如 :component_file:`esp_driver_i2s/include/driver/i2s_std.h`， :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h` 以及 :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h`。
为保证前向兼容，旧版驱动的 API 仍然在 :component_file:`driver/deprecated/driver/i2s.h` 中可用。但使用旧版 API 会触发编译警告，该警告可通过配置 Kconfig 选项 :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN` 来关闭。
为保证前向兼容，旧版驱动的 API 仍然在 ``driver/i2s.h`` 可用。但使用旧版 API 会触发编译警告，该警告可通过配置 Kconfig 选项 ``CONFIG_I2S_SUPPRESS_DEPRECATE_WARN`` 来关闭。
以下是更新后的 I2S 文件概况。

7
docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
View File

@@ -54,3 +54,10 @@ I2C 从机在 v5.4 上已经被重新设计。在当前版本上，老的 I2C
----------------------
旧版的定时器组驱动 ``driver/timer.h`` 在 5.0 的版本中就已经被弃用 （参考 :ref:`deprecate_gptimer_legacy_driver`）。从 6.0 版本开始，旧版驱动被完全移除。新驱动位于 :component:`esp_driver_gptimer` 组件中，头文件引用路径为 ``driver/gptimer.h``。
.. only:: SOC_I2S_SUPPORTED
旧版 I2S 驱动被移除
----------------------
旧版的 I2S 驱动 ``driver/i2s.h`` 在 5.0 的版本中就已经被弃用（请参考 :ref:`deprecate_i2s_legacy_driver`）。从 6.0 版本开始，旧版驱动被完全移除。新驱动位于 :component:`esp_driver_i2s` 组件中，头文件引用路径为 ``driver/i2s_std.h``, ``driver/i2s_pdm.h`` and ``driver/i2s_tdm.h``。

3
tools/idf_py_actions/hints.yml
View File

@@ -496,3 +496,6 @@
-
re_variables: ['driver/timer.h']
hint_variables: ['legacy timer group', 'driver/gptimer.h', 'esp_driver_gptimer']
-
re_variables: ['driver/i2s.h']
hint_variables: ['legacy I2S', 'driver/i2s_std.h, driver/i2s_pdm.h, driver/i2s_tdm.h', 'esp_driver_i2s']