forked from espressif/esp-idf
Merge branch 'feature/esp_intr_flash' into 'master'
feat(intr): added option for placing intr api in flash Closes IDF-12523 See merge request espressif/esp-idf!37935
This commit is contained in:
@@ -284,4 +284,9 @@ menu "Hardware Settings"
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Due to the poor low-temperature characteristics of
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RC32K (it cannot operate below -40 degrees Celsius),
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please avoid using it whenever possible
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config ESP_INTR_IN_IRAM
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bool "Place esp_intr_alloc functions in IRAM" if SPI_FLASH_AUTO_SUSPEND
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default y
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endmenu
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@@ -30,6 +30,12 @@
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#include "esp_ipc.h"
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#endif
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#if CONFIG_ESP_INTR_IN_IRAM
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#define ESP_INTR_IRAM_ATTR IRAM_ATTR
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#else
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#define ESP_INTR_IRAM_ATTR
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#endif // CONFIG_ESP_INTR_IN_IRAM
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/* For targets that uses a CLIC as their interrupt controller, CPU_INT_LINES_COUNT represents the external interrupts count */
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#define CPU_INT_LINES_COUNT 32
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@@ -453,7 +459,7 @@ static int get_available_int(int flags, int cpu, int force, int source)
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}
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//Common shared isr handler. Chain-call all ISRs.
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static void IRAM_ATTR shared_intr_isr(void *arg)
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static void ESP_INTR_IRAM_ATTR shared_intr_isr(void *arg)
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{
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vector_desc_t *vd = (vector_desc_t*)arg;
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shared_vector_desc_t *sh_vec = vd->shared_vec_info;
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@@ -476,7 +482,7 @@ static void IRAM_ATTR shared_intr_isr(void *arg)
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#if CONFIG_APPTRACE_SV_ENABLE
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//Common non-shared isr handler wrapper.
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static void IRAM_ATTR non_shared_intr_isr(void *arg)
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static void ESP_INTR_IRAM_ATTR non_shared_intr_isr(void *arg)
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{
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non_shared_isr_arg_t *ns_isr_arg = (non_shared_isr_arg_t*)arg;
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portENTER_CRITICAL_ISR(&spinlock);
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@@ -729,7 +735,7 @@ esp_err_t esp_intr_alloc_bind(int source, int flags, intr_handler_t handler, voi
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}
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esp_err_t IRAM_ATTR esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram)
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esp_err_t ESP_INTR_IRAM_ATTR esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram)
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{
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if (!handle) {
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return ESP_ERR_INVALID_ARG;
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@@ -879,7 +885,7 @@ int esp_intr_get_cpu(intr_handle_t handle)
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//Muxing an interrupt source to interrupt 6, 7, 11, 15, 16 or 29 cause the interrupt to effectively be disabled.
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#define INT_MUX_DISABLED_INTNO 6
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esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
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esp_err_t ESP_INTR_IRAM_ATTR esp_intr_enable(intr_handle_t handle)
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{
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if (!handle) {
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return ESP_ERR_INVALID_ARG;
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@@ -907,7 +913,7 @@ esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
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return ESP_OK;
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}
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esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
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esp_err_t ESP_INTR_IRAM_ATTR esp_intr_disable(intr_handle_t handle)
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{
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if (handle == NULL) {
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return ESP_ERR_INVALID_ARG;
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@@ -950,7 +956,7 @@ esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
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return ESP_OK;
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}
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void IRAM_ATTR esp_intr_noniram_disable(void)
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void ESP_INTR_IRAM_ATTR esp_intr_noniram_disable(void)
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{
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portENTER_CRITICAL_SAFE(&spinlock);
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uint32_t oldint;
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@@ -969,7 +975,7 @@ void IRAM_ATTR esp_intr_noniram_disable(void)
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portEXIT_CRITICAL_SAFE(&spinlock);
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}
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void IRAM_ATTR esp_intr_noniram_enable(void)
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void ESP_INTR_IRAM_ATTR esp_intr_noniram_enable(void)
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{
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portENTER_CRITICAL_SAFE(&spinlock);
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uint32_t cpu = esp_cpu_get_core_id();
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@@ -988,20 +994,20 @@ void IRAM_ATTR esp_intr_noniram_enable(void)
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//equivalents here.
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void IRAM_ATTR ets_isr_unmask(uint32_t mask) {
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void ESP_INTR_IRAM_ATTR ets_isr_unmask(uint32_t mask) {
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esp_cpu_intr_enable(mask);
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}
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void IRAM_ATTR ets_isr_mask(uint32_t mask) {
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void ESP_INTR_IRAM_ATTR ets_isr_mask(uint32_t mask) {
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esp_cpu_intr_disable(mask);
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}
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void IRAM_ATTR esp_intr_enable_source(int inum)
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void ESP_INTR_IRAM_ATTR esp_intr_enable_source(int inum)
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{
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esp_cpu_intr_enable(1 << inum);
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}
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void IRAM_ATTR esp_intr_disable_source(int inum)
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void ESP_INTR_IRAM_ATTR esp_intr_disable_source(int inum)
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{
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esp_cpu_intr_disable(1 << inum);
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}
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@@ -15,3 +15,4 @@ CONFIG_SPI_FLASH_AUTO_SUSPEND=y
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CONFIG_LIBC_MISC_IN_IRAM=n
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CONFIG_ESP_TIMER_IN_IRAM=n
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CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM=n
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CONFIG_ESP_INTR_IN_IRAM=n
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