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refactor(i2s): rename the confusing port number

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This commit is contained in:
laokaiyao
2024-10-23 16:11:35 +08:00
parent 96632b7b02
commit ecb52d3af3
36 changed files with 119 additions and 173 deletions
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4
components/esp_system/port/soc/esp32c3/clk.c
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@@ -235,7 +235,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_TWAI_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_I2S0_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
@@ -274,7 +274,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_I2C_EXT1_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_I2S0_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;

4
components/esp_system/port/soc/esp32c5/clk.c
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@@ -242,7 +242,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_TWAI_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_I2S0_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
@@ -272,7 +272,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_I2C_EXT1_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_I2S0_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;

2
components/esp_system/port/soc/esp32s2/clk.c
View File

@@ -240,7 +240,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
DPORT_PWM0_CLK_EN |
DPORT_TWAI_CLK_EN |
DPORT_PWM1_CLK_EN |
DPORT_I2S1_CLK_EN |
DPORT_SPI2_DMA_CLK_EN |
DPORT_SPI3_DMA_CLK_EN |
DPORT_PWM2_CLK_EN |
@@ -276,7 +275,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
DPORT_UHCI1_CLK_EN |
DPORT_SPI3_CLK_EN |
DPORT_I2C_EXT1_CLK_EN |
DPORT_I2S1_CLK_EN |
DPORT_SPI2_DMA_CLK_EN |
DPORT_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;

10
components/hal/esp32c3/include/hal/clk_gate_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -35,8 +35,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return SYSTEM_UART1_CLK_EN;
case PERIPH_I2C0_MODULE:
return SYSTEM_I2C_EXT0_CLK_EN;
case PERIPH_I2S1_MODULE:
return SYSTEM_I2S1_CLK_EN;
case PERIPH_I2S0_MODULE:
return SYSTEM_I2S0_CLK_EN;
case PERIPH_TIMG0_MODULE:
return SYSTEM_TIMERGROUP_CLK_EN;
case PERIPH_TIMG1_MODULE:
@@ -106,8 +106,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return SYSTEM_UART1_RST;
case PERIPH_I2C0_MODULE:
return SYSTEM_I2C_EXT0_RST;
case PERIPH_I2S1_MODULE:
return SYSTEM_I2S1_RST;
case PERIPH_I2S0_MODULE:
return SYSTEM_I2S0_RST;
case PERIPH_TIMG0_MODULE:
return SYSTEM_TIMERGROUP_RST;
case PERIPH_TIMG1_MODULE:

6
components/hal/esp32c3/include/hal/i2s_ll.h
View File

@@ -47,7 +47,7 @@ extern "C" {
static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
{
(void)i2s_id;
SYSTEM.perip_clk_en0.reg_i2s1_clk_en = enable;
SYSTEM.perip_clk_en0.reg_i2s0_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
@@ -63,8 +63,8 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
static inline void i2s_ll_reset_register(int i2s_id)
{
(void)i2s_id;
SYSTEM.perip_rst_en0.reg_i2s1_rst = 1;
SYSTEM.perip_rst_en0.reg_i2s1_rst = 0;
SYSTEM.perip_rst_en0.reg_i2s0_rst = 1;
SYSTEM.perip_rst_en0.reg_i2s0_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section

8
components/hal/esp32c6/include/hal/clk_gate_ll.h
View File

@@ -36,7 +36,7 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return PCR_UART1_CLK_EN;
case PERIPH_I2C0_MODULE:
return PCR_I2C_CLK_EN;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_CLK_EN;
case PERIPH_TIMG0_MODULE:
return PCR_TG0_CLK_EN;
@@ -104,7 +104,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return PCR_UART1_RST_EN;
case PERIPH_I2C0_MODULE:
return PCR_I2C_RST_EN;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_RST_EN;
case PERIPH_TIMG0_MODULE:
return PCR_TG0_RST_EN;
@@ -183,7 +183,7 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
return PCR_UART1_CONF_REG;
case PERIPH_I2C0_MODULE:
return PCR_I2C_CONF_REG;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_CONF_REG;
case PERIPH_TIMG0_MODULE:
return PCR_TIMERGROUP0_CONF_REG;
@@ -249,7 +249,7 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
return PCR_UART1_CONF_REG;
case PERIPH_I2C0_MODULE:
return PCR_I2C_CONF_REG;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_CONF_REG;
case PERIPH_TIMG0_MODULE:
return PCR_TIMERGROUP0_CONF_REG;

8
components/hal/esp32h2/include/hal/clk_gate_ll.h
View File

@@ -38,7 +38,7 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return PCR_I2C0_CLK_EN;
case PERIPH_I2C1_MODULE:
return PCR_I2C1_CLK_EN;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_CLK_EN;
case PERIPH_TIMG0_MODULE:
return PCR_TG0_CLK_EN;
@@ -119,7 +119,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return PCR_I2C0_RST_EN;
case PERIPH_I2C1_MODULE:
return PCR_I2C1_RST_EN;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_RST_EN;
case PERIPH_TIMG0_MODULE:
return PCR_TG0_RST_EN;
@@ -224,7 +224,7 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
return PCR_I2C0_CONF_REG;
case PERIPH_I2C1_MODULE:
return PCR_I2C1_CONF_REG;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_CONF_REG;
case PERIPH_TIMG0_MODULE:
return PCR_TIMERGROUP0_CONF_REG;
@@ -291,7 +291,7 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
return PCR_I2C0_CONF_REG;
case PERIPH_I2C1_MODULE:
return PCR_I2C1_CONF_REG;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S0_MODULE:
return PCR_I2S_CONF_REG;
case PERIPH_TIMG0_MODULE:
return PCR_TIMERGROUP0_CONF_REG;

23
components/hal/esp32s2/include/hal/i2s_ll.h
View File

@@ -90,18 +90,11 @@ static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en)
*/
static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
{
(void) i2s_id;
if (enable) {
if (i2s_id == 0) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
} else {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
}
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
} else {
if (i2s_id == 0) {
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
} else {
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
}
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
}
}
@@ -116,13 +109,9 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
*/
static inline void i2s_ll_reset_register(int i2s_id)
{
if (i2s_id == 0) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
} else {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
}
(void) i2s_id;
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
}
/// use a macro to wrap the function, force the caller to use it in a critical section

2
components/soc/esp32c3/i2s_periph.c
View File

@@ -29,6 +29,6 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.data_out_sigs[1] = I2SO_SD1_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_I2S1_INTR_SOURCE,
.irq = ETS_I2S0_INTR_SOURCE,
}
};

4
components/soc/esp32c3/include/soc/interrupts.h
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@@ -35,7 +35,7 @@ typedef enum {
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
@@ -51,7 +51,7 @@ typedef enum {
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalid Access, LEVEL*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */

2
components/soc/esp32c3/include/soc/periph_defs.h
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@@ -18,7 +18,7 @@ typedef enum {
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,

20
components/soc/esp32c3/interrupts.c
View File

@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
@@ -35,7 +27,7 @@ const char *const esp_isr_names[] = {
[17] = "GPIO_NMI",
[18] = "SPI1",
[19] = "SPI2",
[20] = "I2S1",
[20] = "I2S0",
[21] = "UART0",
[22] = "UART1",
[23] = "LEDC",

12
components/soc/esp32c3/register/soc/interrupt_core0_reg.h
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@@ -174,13 +174,13 @@ extern "C" {
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0
#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
#define INTERRUPT_CORE0_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
/* INTERRUPT_CORE0_I2S_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0
#define INTERRUPT_CORE0_I2S_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_I2S_INT_MAP_M ((INTERRUPT_CORE0_I2S_INT_MAP_V)<<(INTERRUPT_CORE0_I2S_INT_MAP_S))
#define INTERRUPT_CORE0_I2S_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_I2S_INT_MAP_S 0
#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */

30
components/soc/esp32c3/register/soc/sensitive_reg.h
View File

@@ -1308,12 +1308,12 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003
@@ -1574,12 +1574,12 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003
@@ -2152,12 +2152,12 @@ extern "C" {
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S 14
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN 0x00000003

6
components/soc/esp32c3/register/soc/sensitive_struct.h
View File

@@ -583,7 +583,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved6 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_0_can: 2; /*core_0_pif_pms_constrain_world_0_can*/
uint32_t reserved12 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1: 2; /*core_0_pif_pms_constrain_world_0_i2s1*/
uint32_t reg_core_0_pif_pms_constrain_world_0_i2s0: 2; /*core_0_pif_pms_constrain_world_0_i2s0*/
uint32_t reserved16 : 6;
uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt: 2; /*core_0_pif_pms_constrain_world_0_rwbt*/
uint32_t reserved24 : 2;
@@ -661,7 +661,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved6 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2; /*core_0_pif_pms_constrain_world_1_can*/
uint32_t reserved12 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2; /*core_0_pif_pms_constrain_world_1_i2s1*/
uint32_t reg_core_0_pif_pms_constrain_world_1_i2s0: 2; /*core_0_pif_pms_constrain_world_1_i2s0*/
uint32_t reserved16 : 6;
uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2; /*core_0_pif_pms_constrain_world_1_rwbt*/
uint32_t reserved24 : 2;
@@ -898,7 +898,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved6 : 4;
uint32_t reg_backup_bus_pms_constrain_can: 2; /*backup_bus_pms_constrain_can*/
uint32_t reserved12 : 2;
uint32_t reg_backup_bus_pms_constrain_i2s1: 2; /*backup_bus_pms_constrain_i2s1*/
uint32_t reg_backup_bus_pms_constrain_i2s0: 2; /*backup_bus_pms_constrain_i2s0*/
uint32_t reserved16 : 6;
uint32_t reg_backup_bus_pms_constrain_rwbt: 2; /*backup_bus_pms_constrain_rwbt*/
uint32_t reserved24 : 2;

34
components/soc/esp32c3/register/soc/system_reg.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -134,12 +134,12 @@ extern "C" {
#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22))
#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1
#define SYSTEM_SPI2_DMA_CLK_EN_S 22
/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S1_CLK_EN (BIT(21))
#define SYSTEM_I2S1_CLK_EN_M (BIT(21))
#define SYSTEM_I2S1_CLK_EN_V 0x1
#define SYSTEM_I2S1_CLK_EN_S 21
#define SYSTEM_I2S0_CLK_EN (BIT(21))
#define SYSTEM_I2S0_CLK_EN_M (BIT(21))
#define SYSTEM_I2S0_CLK_EN_V 0x1
#define SYSTEM_I2S0_CLK_EN_S 21
/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM1_CLK_EN (BIT(20))
@@ -236,12 +236,6 @@ extern "C" {
#define SYSTEM_UART1_CLK_EN_M (BIT(5))
#define SYSTEM_UART1_CLK_EN_V 0x1
#define SYSTEM_UART1_CLK_EN_S 5
/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S0_CLK_EN (BIT(4))
#define SYSTEM_I2S0_CLK_EN_M (BIT(4))
#define SYSTEM_I2S0_CLK_EN_V 0x1
#define SYSTEM_I2S0_CLK_EN_S 4
/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_WDG_CLK_EN (BIT(3))
@@ -384,12 +378,12 @@ extern "C" {
#define SYSTEM_SPI2_DMA_RST_M (BIT(22))
#define SYSTEM_SPI2_DMA_RST_V 0x1
#define SYSTEM_SPI2_DMA_RST_S 22
/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
/* SYSTEM_I2S0_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S1_RST (BIT(21))
#define SYSTEM_I2S1_RST_M (BIT(21))
#define SYSTEM_I2S1_RST_V 0x1
#define SYSTEM_I2S1_RST_S 21
#define SYSTEM_I2S0_RST (BIT(21))
#define SYSTEM_I2S0_RST_M (BIT(21))
#define SYSTEM_I2S0_RST_V 0x1
#define SYSTEM_I2S0_RST_S 21
/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM1_RST (BIT(20))
@@ -486,12 +480,6 @@ extern "C" {
#define SYSTEM_UART1_RST_M (BIT(5))
#define SYSTEM_UART1_RST_V 0x1
#define SYSTEM_UART1_RST_S 5
/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S0_RST (BIT(4))
#define SYSTEM_I2S0_RST_M (BIT(4))
#define SYSTEM_I2S0_RST_V 0x1
#define SYSTEM_I2S0_RST_S 4
/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_WDG_RST (BIT(3))

10
components/soc/esp32c3/register/soc/system_struct.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -54,7 +54,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_spi01_clk_en : 1; /*reg_spi01_clk_en*/
uint32_t reg_uart_clk_en : 1; /*reg_uart_clk_en*/
uint32_t reg_wdg_clk_en : 1; /*reg_wdg_clk_en*/
uint32_t reg_i2s0_clk_en : 1; /*reg_i2s0_clk_en*/
uint32_t reserved_04 : 1; /*reserved*/
uint32_t reg_uart1_clk_en : 1; /*reg_uart1_clk_en*/
uint32_t reg_spi2_clk_en : 1; /*reg_spi2_clk_en*/
uint32_t reg_i2c_ext0_clk_en : 1; /*reg_i2c_ext0_clk_en*/
@@ -71,7 +71,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_i2c_ext1_clk_en : 1; /*reg_i2c_ext1_clk_en*/
uint32_t reg_can_clk_en : 1; /*reg_can_clk_en*/
uint32_t reg_pwm1_clk_en : 1; /*reg_pwm1_clk_en*/
uint32_t reg_i2s1_clk_en : 1; /*reg_i2s1_clk_en*/
uint32_t reg_i2s0_clk_en : 1; /*reg_i2s0_clk_en*/
uint32_t reg_spi2_dma_clk_en : 1; /*reg_spi2_dma_clk_en*/
uint32_t reg_usb_device_clk_en : 1; /*reg_usb_device_clk_en*/
uint32_t reg_uart_mem_clk_en : 1; /*reg_uart_mem_clk_en*/
@@ -108,7 +108,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_spi01_rst : 1; /*reg_spi01_rst*/
uint32_t reg_uart_rst : 1; /*reg_uart_rst*/
uint32_t reg_wdg_rst : 1; /*reg_wdg_rst*/
uint32_t reg_i2s0_rst : 1; /*reg_i2s0_rst*/
uint32_t reserved_04 : 1; /*reserved*/
uint32_t reg_uart1_rst : 1; /*reg_uart1_rst*/
uint32_t reg_spi2_rst : 1; /*reg_spi2_rst*/
uint32_t reg_i2c_ext0_rst : 1; /*reg_i2c_ext0_rst*/
@@ -125,7 +125,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_i2c_ext1_rst : 1; /*reg_i2c_ext1_rst*/
uint32_t reg_can_rst : 1; /*reg_can_rst*/
uint32_t reg_pwm1_rst : 1; /*reg_pwm1_rst*/
uint32_t reg_i2s1_rst : 1; /*reg_i2s1_rst*/
uint32_t reg_i2s0_rst : 1; /*reg_i2s0_rst*/
uint32_t reg_spi2_dma_rst : 1; /*reg_spi2_dma_rst*/
uint32_t reg_usb_device_rst : 1; /*reg_usb_device_rst*/
uint32_t reg_uart_mem_rst : 1; /*reg_uart_mem_rst*/

2
components/soc/esp32c5/i2s_periph.c
View File

@@ -30,7 +30,7 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.data_out_sigs[1] = I2SO_SD1_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_I2S1_INTR_SOURCE,
.irq = ETS_I2S0_INTR_SOURCE,
}
};

2
components/soc/esp32c5/include/soc/interrupts.h
View File

@@ -58,7 +58,7 @@ typedef enum {
ETS_HP_APM_M4_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/

2
components/soc/esp32c5/interrupts.c
View File

@@ -50,7 +50,7 @@ const char *const esp_isr_names[] = {
[ETS_HP_APM_M4_INTR_SOURCE] = "HP_APM_M4",
[ETS_LP_APM0_INTR_SOURCE] = "LP_APM0",
[ETS_MSPI_INTR_SOURCE] = "MSPI",
[ETS_I2S1_INTR_SOURCE] = "I2S1",
[ETS_I2S0_INTR_SOURCE] = "I2S0",
[ETS_UHCI0_INTR_SOURCE] = "UHCI0",
[ETS_UART0_INTR_SOURCE] = "UART0",
[ETS_UART1_INTR_SOURCE] = "UART1",

2
components/soc/esp32c6/i2s_periph.c
View File

@@ -30,7 +30,7 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.data_out_sigs[1] = I2SO_SD1_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_I2S1_INTR_SOURCE,
.irq = ETS_I2S0_INTR_SOURCE,
}
};

2
components/soc/esp32c6/include/soc/interrupts.h
View File

@@ -56,7 +56,7 @@ typedef enum {
ETS_HP_APM_M3_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/

2
components/soc/esp32c6/include/soc/periph_defs.h
View File

@@ -19,7 +19,7 @@ typedef enum {
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,

2
components/soc/esp32c6/interrupts.c
View File

@@ -48,7 +48,7 @@ const char *const esp_isr_names[] = {
[38] = "HP_APM_M3",
[39] = "LP_APM0",
[40] = "MSPI",
[41] = "I2S1",
[41] = "I2S0",
[42] = "UHCI0",
[43] = "UART0",
[44] = "UART1",

16
components/soc/esp32c6/register/soc/interrupt_matrix_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -502,17 +502,17 @@ extern "C" {
#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_S 0
/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
/** INTMTX_CORE0_I2S_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
/** INTMTX_CORE0_I2S_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_S 0
#define INTMTX_CORE0_I2S_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2S_INTR_MAP_M (INTMTX_CORE0_I2S_INTR_MAP_V << INTMTX_CORE0_I2S_INTR_MAP_S)
#define INTMTX_CORE0_I2S_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2S_INTR_MAP_S 0
/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
* register description

12
components/soc/esp32c6/register/soc/interrupt_matrix_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -585,19 +585,19 @@ typedef union {
uint32_t val;
} interrupt_matrix_mspi_intr_map_reg_t;
/** Type of i2s1_intr_map register
/** Type of i2s_intr_map register
* register description
*/
typedef union {
struct {
/** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0;
/** i2s_intr_map : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
uint32_t i2s1_intr_map:5;
uint32_t i2s_intr_map:5;
uint32_t reserved_5:27;
};
uint32_t val;
} interrupt_matrix_i2s1_intr_map_reg_t;
} interrupt_matrix_i2s_intr_map_reg_t;
/** Type of uhci0_intr_map register
* register description
@@ -1199,7 +1199,7 @@ typedef struct interrupt_matrix_dev_t {
volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
volatile interrupt_matrix_lp_apm0_intr_map_reg_t lp_apm0_intr_map;
volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map;
volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map;
volatile interrupt_matrix_i2s_intr_map_reg_t i2s_intr_map;
volatile interrupt_matrix_uhci0_intr_map_reg_t uhci0_intr_map;
volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map;
volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map;

2
components/soc/esp32h2/i2s_periph.c
View File

@@ -29,7 +29,7 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.data_out_sig = I2SO_SD_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_I2S1_INTR_SOURCE,
.irq = ETS_I2S0_INTR_SOURCE,
}
};

2
components/soc/esp32h2/include/soc/interrupts.h
View File

@@ -46,7 +46,7 @@ typedef enum {
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/

2
components/soc/esp32h2/include/soc/periph_defs.h
View File

@@ -19,7 +19,7 @@ typedef enum {
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,

2
components/soc/esp32h2/interrupts.c
View File

@@ -38,7 +38,7 @@ const char *const esp_isr_names[] = {
[28] = "HP_APM_M2",
[29] = "HP_APM_M3",
[30] = "MSPI",
[31] = "I2S1",
[31] = "I2S0",
[32] = "UHCI0",
[33] = "UART0",
[34] = "UART1",

18
components/soc/esp32h2/register/soc/interrupt_matrix_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -383,17 +383,17 @@ extern "C" {
#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_S 0
/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
/** INTMTX_CORE0_I2S_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2S1_INTR mapping register
#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
/** INTMTX_CORE0_I2S_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2S_INTR mapping register
*/
#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_S 0
#define INTMTX_CORE0_I2S_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2S_INTR_MAP_M (INTMTX_CORE0_I2S_INTR_MAP_V << INTMTX_CORE0_I2S_INTR_MAP_S)
#define INTMTX_CORE0_I2S_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2S_INTR_MAP_S 0
/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
* register description

14
components/soc/esp32h2/register/soc/interrupt_matrix_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -445,19 +445,19 @@ typedef union {
uint32_t val;
} intmtx_core0_mspi_intr_map_reg_t;
/** Type of i2s1_intr_map register
/** Type of i2s_intr_map register
* register description
*/
typedef union {
struct {
/** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2S1_INTR mapping register
/** i2s_intr_map : R/W; bitpos: [4:0]; default: 0;
* CORE0_i2s_INTR mapping register
*/
uint32_t i2s1_intr_map:5;
uint32_t i2s_intr_map:5;
uint32_t reserved_5:27;
};
uint32_t val;
} intmtx_core0_i2s1_intr_map_reg_t;
} intmtx_core0_i2s_intr_map_reg_t;
/** Type of uhci0_intr_map register
* register description
@@ -1021,7 +1021,7 @@ typedef struct interrupt_matrix_dev_t {
volatile intmtx_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
volatile intmtx_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
volatile intmtx_core0_mspi_intr_map_reg_t mspi_intr_map;
volatile intmtx_core0_i2s1_intr_map_reg_t i2s1_intr_map;
volatile intmtx_core0_i2s_intr_map_reg_t i2s_intr_map;
volatile intmtx_core0_uhci0_intr_map_reg_t uhci0_intr_map;
volatile intmtx_core0_uart0_intr_map_reg_t uart0_intr_map;
volatile intmtx_core0_uart1_intr_map_reg_t uart1_intr_map;

2
components/soc/esp32s2/interrupts.c
View File

@@ -43,7 +43,7 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
[33] = "SPI2",
[34] = "SPI3",
[35] = "I2S0",
[36] = "I2S1",
[36] = "RESERVED",
[37] = "UART0",
[38] = "UART1",
[39] = "UART2",

8
components/soc/esp32s2/register/soc/interrupt_reg.h
View File

@@ -299,14 +299,6 @@ extern "C" {
#define DPORT_PRO_I2S0_INT_MAP_V 0x1F
#define DPORT_PRO_I2S0_INT_MAP_S 0
#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x090)
/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_I2S1_INT_MAP 0x0000001F
#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
#define DPORT_PRO_I2S1_INT_MAP_V 0x1F
#define DPORT_PRO_I2S1_INT_MAP_S 0
#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x094)
/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */

14
components/soc/esp32s2/register/soc/system_reg.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -236,12 +236,6 @@ extern "C" {
#define DPORT_SPI2_DMA_CLK_EN_M (BIT(22))
#define DPORT_SPI2_DMA_CLK_EN_V 0x1
#define DPORT_SPI2_DMA_CLK_EN_S 22
/* DPORT_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2S1_CLK_EN (BIT(21))
#define DPORT_I2S1_CLK_EN_M (BIT(21))
#define DPORT_I2S1_CLK_EN_V 0x1
#define DPORT_I2S1_CLK_EN_S 21
/* DPORT_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM1_CLK_EN (BIT(20))
@@ -464,12 +458,6 @@ extern "C" {
#define DPORT_SPI2_DMA_RST_M (BIT(22))
#define DPORT_SPI2_DMA_RST_V 0x1
#define DPORT_SPI2_DMA_RST_S 22
/* DPORT_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2S1_RST (BIT(21))
#define DPORT_I2S1_RST_M (BIT(21))
#define DPORT_I2S1_RST_V 0x1
#define DPORT_I2S1_RST_S 21
/* DPORT_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM1_RST (BIT(20))

1
tools/ci/check_copyright_ignore.txt
View File

@@ -524,7 +524,6 @@ components/soc/esp32/include/soc/touch_sensor_channel.h
components/soc/esp32/include/soc/uart_pins.h
components/soc/esp32/include/soc/wdev_reg.h
components/soc/esp32/ledc_periph.c
components/soc/esp32c3/interrupts.c
components/soc/esp32c3/ledc_periph.c
components/soc/esp32s2/adc_periph.c
components/soc/esp32s2/include/soc/bb_reg.h