sdio: c6 support

components/driver/.build-test-rules.yml

@@ -81,8 +81,10 @@ components/driver/test_apps/rs485:
 components/driver/test_apps/sdio:
   disable:
     - if: SOC_SDIO_SLAVE_SUPPORTED != 1
+  disable_test:
+    - if: IDF_TARGET == "esp32c6"
       temporary: true
-      reason: Not supported.
+      reason: lack of runners
 
 components/driver/test_apps/spi/master:
   disable:

components/driver/sdio_slave.c

@@ -78,7 +78,6 @@ The driver of FIFOs works as below:
 #include <string.h>
 #include "driver/sdio_slave.h"
 #include "soc/sdio_slave_periph.h"
-#include "esp32/rom/lldesc.h"
 #include "esp_log.h"
 #include "esp_intr_alloc.h"
 #include "freertos/FreeRTOS.h"
@@ -176,16 +175,16 @@ static inline void critical_exit_recv(void);
 
 static void deinit_context(void);
 
-static inline void show_ll(lldesc_t *item)
+static inline void show_ll(sdio_slave_ll_desc_t *item)
 {
     ESP_EARLY_LOGI(TAG, "=> %p: size: %d(%d), eof: %d, owner: %d", item, item->size, item->length, item->eof, item->owner);
     ESP_EARLY_LOGI(TAG, "   buf: %p, stqe_next: %p", item->buf, item->qe.stqe_next);
 }
 
-static void __attribute((unused)) dump_ll(lldesc_t *queue)
+static void __attribute((unused)) dump_ll(sdio_slave_ll_desc_t *queue)
 {
     int cnt = 0;
-    lldesc_t *item = queue;
+    sdio_slave_ll_desc_t *item = queue;
     while (item != NULL) {
         cnt++;
         show_ll(item);
@@ -294,7 +293,7 @@ static void configure_pin(int pin, uint32_t func, bool pullup)
 static inline esp_err_t sdio_slave_hw_init(sdio_slave_config_t *config)
 {
     //initialize pin
-    const sdio_slave_slot_info_t *slot = &sdio_slave_slot_info[1];
+    const sdio_slave_slot_info_t *slot = &sdio_slave_slot_info[0];
 
     bool pullup = config->flags & SDIO_SLAVE_FLAG_INTERNAL_PULLUP;
     configure_pin(slot->clk_gpio, slot->func, false);   //clk doesn't need a pullup
@@ -330,7 +329,7 @@ static void recover_pin(int pin, int sdio_func)
 
 static void sdio_slave_hw_deinit(void)
 {
-    const sdio_slave_slot_info_t *slot = &sdio_slave_slot_info[1];
+    const sdio_slave_slot_info_t *slot = &sdio_slave_slot_info[0];
     recover_pin(slot->clk_gpio, slot->func);
     recover_pin(slot->cmd_gpio, slot->func);
     recover_pin(slot->d0_gpio, slot->func);

components/driver/test_apps/sdio/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 |
+| Supported Targets | ESP32 | ESP32-C6 |
-| ----------------- | ----- |
+| ----------------- | ----- | -------- |

components/hal/CMakeLists.txt

@@ -134,10 +134,12 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "spi_slave_hd_hal.c")
     endif()
 
+    if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED)
+        list(APPEND srcs "sdio_slave_hal.c")
+    endif()
 
     if(${target} STREQUAL "esp32")
         list(APPEND srcs
-            "sdio_slave_hal.c"
             "touch_sensor_hal.c"
             "esp32/touch_sensor_hal.c"
             "esp32/gpio_hal_workaround.c")

components/hal/esp32/include/hal/sdio_slave_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 /*******************************************************************************
  * NOTICE
@@ -40,6 +32,33 @@
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
 
 
+/*
+ *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
+ *
+ * --------------------------------------------------------------
+ * | own | EoF | sub_sof | 5'b0   | length [11:0] | size [11:0] |
+ * --------------------------------------------------------------
+ * |            buf_ptr [31:0]                                  |
+ * --------------------------------------------------------------
+ * |            next_desc_ptr [31:0]                            |
+ * --------------------------------------------------------------
+ */
+
+/* this bitfield is start from the LSB!!! */
+typedef struct sdio_slave_ll_desc_s {
+    volatile uint32_t size  : 12,
+             length: 12,
+             offset: 5, /* starting from bit24, h/w reserved 5bit, s/w use it as offset in buffer */
+             sosf  : 1, /* start of sub-frame */
+             eof   : 1, /* end of frame */
+             owner : 1; /* hw or sw */
+    volatile const uint8_t *buf;       /* point to buffer data */
+    union {
+        volatile uint32_t empty;
+        STAILQ_ENTRY(sdio_slave_ll_desc_s) qe;  /* pointing to the next desc */
+    };
+} sdio_slave_ll_desc_t;
+
 /// Mask of general purpose interrupts sending from the host.
 typedef enum {
     SDIO_SLAVE_LL_SLVINT_0 = BIT(0),    ///< General purpose interrupt bit 0.
@@ -155,7 +174,7 @@ static inline void sdio_slave_ll_send_reset(slc_dev_t *slc)
  * @param slc Address of the SLC registers
  * @param desc Descriptor to send
  */
-static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const lldesc_t *desc)
+static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const sdio_slave_ll_desc_t *desc)
 {
     slc->slc0_rx_link.addr = (uint32_t)desc;
     slc->slc0_rx_link.start = 1;
@@ -289,7 +308,7 @@ static inline void sdio_slave_ll_recv_intr_ena(slc_dev_t *slc, bool ena)
  * @param slc Address of the SLC registers
  * @param desc Descriptor of the receiving buffer.
  */
-static inline void sdio_slave_ll_recv_start(slc_dev_t *slc, lldesc_t *desc)
+static inline void sdio_slave_ll_recv_start(slc_dev_t *slc, sdio_slave_ll_desc_t *desc)
 {
     slc->slc0_tx_link.addr = (uint32_t)desc;
     slc->slc0_tx_link.start = 1;

components/hal/esp32c6/include/hal/clk_gate_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -72,6 +72,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
             return PCR_DS_CLK_EN;
         case PERIPH_TEMPSENSOR_MODULE:
             return PCR_TSENS_CLK_EN;
+        case PERIPH_SDIO_SLAVE_MODULE:
+            return PCR_SDIO_SLAVE_CLK_EN;
         // case PERIPH_RNG_MODULE:
         //     return PCR_WIFI_CLK_RNG_EN;
         // case PERIPH_WIFI_MODULE:
@@ -164,6 +166,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
             return PCR_HMAC_RST_EN;
         case PERIPH_DS_MODULE:
             return PCR_DS_RST_EN;
+        case PERIPH_SDIO_SLAVE_MODULE:
+            return PCR_SDIO_SLAVE_RST_EN;
         // case PERIPH_RNG_MODULE:
         //     return PCR_WIFI_CLK_RNG_EN;
         // case PERIPH_WIFI_MODULE:
@@ -244,6 +248,8 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
             return PCR_DS_CONF_REG;
         case PERIPH_TEMPSENSOR_MODULE:
             return PCR_TSENS_CLK_CONF_REG;
+        case PERIPH_SDIO_SLAVE_MODULE:
+            return PCR_SDIO_SLAVE_CONF_REG;
     default:
         return 0;
     }
@@ -304,6 +310,8 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
             return PCR_DS_CONF_REG;
         case PERIPH_TEMPSENSOR_MODULE:
             return PCR_TSENS_CLK_CONF_REG;
+        case PERIPH_SDIO_SLAVE_MODULE:
+            return PCR_SDIO_SLAVE_CONF_REG;
     default:
         return 0;
     }

components/hal/esp32c6/include/hal/sdio_slave_ll.h

@@ -0,0 +1,500 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+// The LL layer for SDIO slave register operations
+// It's strange but `tx_*` regs for host->slave transfers while `rx_*` regs for slave->host transfers
+// To reduce ambiguity, we call (host->slave, tx) transfers receiving and (slave->host, rx) transfers receiving
+
+#pragma once
+
+#include "hal/sdio_slave_hal.h"
+#include "soc/slc_struct.h"
+#include "soc/slc_reg.h"
+#include "soc/host_struct.h"
+#include "soc/host_reg.h"
+#include "soc/hinf_struct.h"
+#include "soc/lldesc.h"
+
+/// Get address of the only SLC registers
+#define sdio_slave_ll_get_slc(ID)   (&SLC)
+/// Get address of the only HOST registers
+#define sdio_slave_ll_get_host(ID)  (&HOST)
+/// Get address of the only HINF registers
+#define sdio_slave_ll_get_hinf(ID)  (&HINF)
+
+
+/*
+ *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
+ *
+ * --------------------------------------------------------------
+ * | own | EoF | sub_sof | 1'b0   | length [13:0] | size [13:0] |
+ * --------------------------------------------------------------
+ * |            buf_ptr [31:0]                                  |
+ * --------------------------------------------------------------
+ * |            next_desc_ptr [31:0]                            |
+ * --------------------------------------------------------------
+ */
+
+/* this bitfield is start from the LSB!!! */
+typedef struct sdio_slave_ll_desc_s {
+    volatile uint32_t size  : 14,
+             length: 14,
+             offset: 1, /* starting from bit28, h/w reserved 1bit, s/w use it as offset in buffer */
+             sosf  : 1, /* start of sub-frame */
+             eof   : 1, /* end of frame */
+             owner : 1; /* hw or sw */
+    volatile const uint8_t *buf;       /* point to buffer data */
+    union {
+        volatile uint32_t empty;
+        STAILQ_ENTRY(sdio_slave_ll_desc_s) qe;  /* pointing to the next desc */
+    };
+} sdio_slave_ll_desc_t;
+
+/// Mask of general purpose interrupts sending from the host.
+typedef enum {
+    SDIO_SLAVE_LL_SLVINT_0 = BIT(0),    ///< General purpose interrupt bit 0.
+    SDIO_SLAVE_LL_SLVINT_1 = BIT(1),
+    SDIO_SLAVE_LL_SLVINT_2 = BIT(2),
+    SDIO_SLAVE_LL_SLVINT_3 = BIT(3),
+    SDIO_SLAVE_LL_SLVINT_4 = BIT(4),
+    SDIO_SLAVE_LL_SLVINT_5 = BIT(5),
+    SDIO_SLAVE_LL_SLVINT_6 = BIT(6),
+    SDIO_SLAVE_LL_SLVINT_7 = BIT(7),
+} sdio_slave_ll_slvint_t;
+
+/**
+ * Initialize the hardware.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_init(slc_dev_t *slc)
+{
+    slc->slc0int_ena.val = 0;
+
+    slc->slcconf0.slc0_rx_auto_wrback = 1;
+    slc->slcconf0.slc0_token_auto_clr = 0;
+    slc->slcconf0.slc0_rx_loop_test = 0;
+    slc->slcconf0.slc0_tx_loop_test = 0;
+
+    slc->slcconf1.slc0_rx_stitch_en = 0;
+    slc->slcconf1.slc0_tx_stitch_en = 0;
+    slc->slcconf1.slc0_len_auto_clr = 0;
+
+    slc->slc_rx_dscr_conf.slc0_token_no_replace = 1;
+}
+
+/**
+ * Set the timing for the communication
+ *
+ * @param host Address of the host registers
+ * @param timing Timing configuration to set
+ */
+static inline void sdio_slave_ll_set_timing(host_dev_t *host, sdio_slave_timing_t timing)
+{
+    switch(timing) {
+        case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
+            host->conf.frc_sdio20 = 0x1f;
+            host->conf.frc_sdio11 = 0;
+            host->conf.frc_pos_samp = 0x1f;
+            host->conf.frc_neg_samp = 0;
+            break;
+        case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
+            host->conf.frc_sdio20 = 0x1f;
+            host->conf.frc_sdio11 = 0;
+            host->conf.frc_pos_samp = 0;
+            host->conf.frc_neg_samp = 0x1f;
+            break;
+        case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
+            host->conf.frc_sdio20 = 0;
+            host->conf.frc_sdio11 = 0x1f;
+            host->conf.frc_pos_samp = 0x1f;
+            host->conf.frc_neg_samp = 0;
+            break;
+        case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
+            host->conf.frc_sdio20 = 0;
+            host->conf.frc_sdio11 = 0x1f;
+            host->conf.frc_pos_samp = 0;
+            host->conf.frc_neg_samp = 0x1f;
+            break;
+    }
+}
+
+/**
+ * Set the HS supported bit to be read by the host.
+ *
+ * @param hinf Address of the hinf registers
+ * @param hs true if supported, otherwise false.
+ */
+static inline void sdio_slave_ll_enable_hs(hinf_dev_t *hinf, bool hs)
+{
+    if (hs) {
+        hinf->cfg_data1.sdio_ver = 0x232;
+        hinf->cfg_data1.highspeed_enable = 1;
+    }
+}
+
+/**
+ * Set the IO Ready bit to be read by the host.
+ *
+ * @param hinf Address of the hinf registers
+ * @param ready true if ready, otherwise false.
+ */
+static inline void sdio_slave_ll_set_ioready(hinf_dev_t *hinf, bool ready)
+{
+    hinf->cfg_data1.sdio_ioready1 = (ready ? 1 : 0);   //set IO ready to 1 to stop host from using
+}
+
+/*---------------------------------------------------------------------------
+ *                  Send
+ *--------------------------------------------------------------------------*/
+/**
+ * Reset the sending DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_reset(slc_dev_t *slc)
+{
+    //reset to flush previous packets
+    slc->slcconf0.slc0_rx_rst = 1;
+    slc->slcconf0.slc0_rx_rst = 0;
+}
+
+/**
+ * Start the sending DMA with the given descriptor.
+ *
+ * @param slc Address of the SLC registers
+ * @param desc Descriptor to send
+ */
+static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const sdio_slave_ll_desc_t *desc)
+{
+    slc->slc0rx_link_addr.slc0_rxlink_addr = (uint32_t)desc;
+    slc->slc0rx_link.slc0_rxlink_start = 1;
+}
+
+/**
+ * Write the PKT_LEN register to be written by the host to a certain value.
+ *
+ * @param slc Address of the SLC registers
+ * @param len Length to write
+ */
+static inline void sdio_slave_ll_send_write_len(slc_dev_t *slc, uint32_t len)
+{
+    slc->slc0_len_conf.val = FIELD_TO_VALUE2(SDIO_SLC0_LEN_WDATA, len) | FIELD_TO_VALUE2(SDIO_SLC0_LEN_WR, 1);
+}
+
+/**
+ * Read the value of PKT_LEN register. The register may keep the same until read
+ * by the host.
+ *
+ * @param host Address of the host registers
+ * @return The value of PKT_LEN register.
+ */
+static inline uint32_t sdio_slave_ll_send_read_len(host_dev_t *host)
+{
+    return host->pkt_len.hostslchost_slc0_len;
+}
+
+/**
+ * Enable the rx_done interrupt. (sending)
+ *
+ * @param slc Address of the SLC registers
+ * @param ena true if enable, otherwise false.
+ */
+static inline void sdio_slave_ll_send_part_done_intr_ena(slc_dev_t *slc, bool ena)
+{
+    slc->slc0int_ena.slc0_rx_done_int_ena = (ena ? 1 : 0);
+}
+
+/**
+ * Clear the rx_done interrupt. (sending)
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_part_done_clear(slc_dev_t *slc)
+{
+    slc->slc0int_clr.slc0_rx_done_int_clr = 1;
+}
+
+/**
+ * Check whether the hardware is ready for the SW to use rx_done to invoke
+ * the ISR.
+ *
+ * @param slc Address of the SLC registers
+ * @return true if ready, otherwise false.
+ */
+static inline bool sdio_slave_ll_send_invoker_ready(slc_dev_t *slc)
+{
+    return slc->slc0int_raw.slc0_rx_done_int_raw;
+}
+
+/**
+ * Stop the sending DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_stop(slc_dev_t *slc)
+{
+    slc->slc0rx_link.slc0_rxlink_stop = 1;
+}
+
+/**
+ * Enable the sending interrupt (rx_eof).
+ *
+ * @param slc Address of the SLC registers
+ * @param ena true to enable, false to disable
+ */
+static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
+{
+    slc->slc0int_ena.slc0_rx_eof_int_ena = (ena? 1: 0);
+}
+
+/**
+ * Clear the sending interrupt (rx_eof).
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_intr_clr(slc_dev_t *slc)
+{
+    slc->slc0int_clr.slc0_rx_eof_int_clr = 1;
+}
+
+/**
+ * Check whether the sending is done.
+ *
+ * @param slc Address of the SLC registers
+ * @return true if done, otherwise false
+ */
+static inline bool sdio_slave_ll_send_done(slc_dev_t *slc)
+{
+    return slc->slc0int_st.slc0_rx_eof_int_st != 0;
+}
+
+/**
+ * Clear the host interrupt indicating the slave having packet to be read.
+ *
+ * @param host Address of the host registers
+ */
+static inline void sdio_slave_ll_send_hostint_clr(host_dev_t *host)
+{
+    host->slc0host_int_clr.slc0_rx_new_packet_int_clr = 1;
+}
+
+/*---------------------------------------------------------------------------
+ *                  Receive
+ *--------------------------------------------------------------------------*/
+/**
+ * Enable the receiving interrupt.
+ *
+ * @param slc Address of the SLC registers
+ * @param ena
+ */
+static inline void sdio_slave_ll_recv_intr_ena(slc_dev_t *slc, bool ena)
+{
+    slc->slc0int_ena.slc0_tx_done_int_ena = (ena ? 1 : 0);
+}
+
+/**
+ * Start receiving DMA with the given descriptor.
+ *
+ * @param slc Address of the SLC registers
+ * @param desc Descriptor of the receiving buffer.
+ */
+static inline void sdio_slave_ll_recv_start(slc_dev_t *slc, sdio_slave_ll_desc_t *desc)
+{
+    slc->slc0tx_link_addr.slc0_txlink_addr = (uint32_t)desc;
+    slc->slc0tx_link.slc0_txlink_start = 1;
+}
+
+/**
+ * Increase the receiving buffer counter by 1.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_size_inc(slc_dev_t *slc)
+{
+    // fields wdata and inc_more should be written by the same instruction.
+    slc->slc0token1.val = FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WDATA, 1) | FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_INC_MORE, 1);
+}
+
+/**
+ * Reset the receiving buffer.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_size_reset(slc_dev_t *slc)
+{
+    slc->slc0token1.val = FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WDATA, 0) | FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WR, 1);
+}
+
+/**
+ * Check whether there is a receiving finished event.
+ *
+ * @param slc Address of the SLC registers
+ * @return
+ */
+static inline bool sdio_slave_ll_recv_done(slc_dev_t *slc)
+{
+    return slc->slc0int_raw.slc0_tx_done_int_raw != 0;
+}
+
+/**
+ * Clear the receiving finished interrupt.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_done_clear(slc_dev_t *slc)
+{
+    slc->slc0int_clr.slc0_tx_done_int_clr = 1;
+}
+
+/**
+ * Restart the DMA. Call after you modified the next pointer of the tail descriptor to the appended
+ * descriptor.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_restart(slc_dev_t *slc)
+{
+    slc->slc0tx_link.slc0_txlink_restart = 1;
+}
+
+/**
+ * Reset the receiving DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_reset(slc_dev_t *slc)
+{
+    slc->slcconf0.slc0_tx_rst = 1;
+    slc->slcconf0.slc0_tx_rst = 0;
+}
+
+/**
+ * Stop the receiving DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_stop(slc_dev_t *slc)
+{
+    slc->slc0tx_link.slc0_txlink_stop = 1;
+}
+
+/*---------------------------------------------------------------------------
+ *                  Host
+ *--------------------------------------------------------------------------*/
+/**
+ * Get the address of the shared general purpose register. Internal.
+ *
+ * @param host Address of the host registers
+ * @param pos Position of the register, 0-63 except 24-27.
+ * @return address of the register.
+ */
+static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t* host, int pos)
+{
+    return (intptr_t )&(host->conf_w0) + pos + (pos>23?4:0) + (pos>31?12:0);
+}
+
+/**
+ * Get the value of the shared general purpose register.
+ *
+ * @param host Address of the host registers
+ * @param pos Position of the register, 0-63, except 24-27.
+ * @return value of the register.
+ */
+static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
+{
+    return *(uint8_t*)sdio_slave_ll_host_get_w_reg(host, pos);
+}
+
+/**
+ * Set the value of the shared general purpose register.
+ *
+ * @param host Address of the host registers
+ * @param pos Position of the register, 0-63, except 24-27.
+ * @param reg Value to set.
+ */
+static inline void sdio_slave_ll_host_set_reg(host_dev_t* host, int pos, uint8_t reg)
+{
+    uint32_t* addr = (uint32_t*)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
+    uint32_t shift = (pos % 4) * 8;
+    *addr &= ~(0xff << shift);
+    *addr |= ((uint32_t)reg << shift);
+}
+
+/**
+ * Get the interrupt enable bits for the host.
+ *
+ * @param host Address of the host registers
+ * @return Enabled interrupts
+ */
+static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t* host)
+{
+    return host->slc0host_func1_int_ena.val;
+}
+
+/**
+ * Set the interrupt enable bits for the host.
+ *
+ * @param host Address of the host registers
+ * @param mask Mask of interrupts to enable
+ */
+static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_slave_hostint_t *mask)
+{
+    host->slc0host_func1_int_ena.val = (*mask);
+}
+
+/**
+ * Clear the interrupt bits for the host.
+ * @param host Address of the host registers
+ * @param mask Mask of interrupts to clear.
+ */
+static inline void sdio_slave_ll_host_intr_clear(host_dev_t* host, const sdio_slave_hostint_t *mask)
+{
+    host->slc0host_int_clr.val = (*mask);
+}
+
+/**
+ * Send general purpose interrupts to the host.
+ * @param slc Address of the SLC registers
+ * @param mask Mask of interrupts to seend to host
+ */
+static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_hostint_t *mask)
+{
+    //use registers in SLC to trigger, rather than write HOST registers directly
+    //other interrupts than tohost interrupts are not supported yet
+    slc->slcintvec_tohost.slc0_tohost_intvec = (*mask);
+}
+
+/**
+ * Enable some of the slave interrups (send from host)
+ *
+ * @param slc Address of the SLC registers
+ * @param mask Mask of interrupts to enable, all those set to 0 will be disabled.
+ */
+static inline void sdio_slave_ll_slvint_set_ena(slc_dev_t *slc, const sdio_slave_ll_slvint_t *mask)
+{
+    //other interrupts are not enabled
+    slc->slc0int_ena.val = (slc->slc0int_ena.val & (~0xff)) | ((*mask) & 0xff);
+}
+
+/**
+ * Fetch the slave interrupts (send from host) and clear them.
+ *
+ * @param slc Address of the SLC registers
+ * @param out_slv_int Output of the slave interrupts fetched and cleared.
+ */
+static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_ll_slvint_t *out_slv_int)
+{
+    sdio_slave_ll_slvint_t slv_int = slc->slc0int_st.val & 0xff;
+    *out_slv_int = slv_int;
+    slc->slc0int_clr.val = slv_int;
+}

components/hal/include/hal/sdio_slave_hal.h

@@ -141,7 +141,6 @@ The HAL is used as below:
 
 #pragma once
 #include <esp_err.h>
-#include "soc/lldesc.h"
 #include "hal/sdio_slave_types.h"
 #include "hal/sdio_slave_ll.h"
 
@@ -172,15 +171,15 @@ typedef struct {
 
 /// DMA descriptor with extra fields
 typedef struct sdio_slave_hal_send_desc_s {
-    lldesc_t dma_desc;    ///< Used by Hardware, has pointer linking to next desc
+    sdio_slave_ll_desc_t dma_desc;    ///< Used by Hardware, has pointer linking to next desc
     uint32_t pkt_len;     ///< Accumulated length till this descriptor
     void*   arg;          ///< Holding arguments indicating this buffer */
 } sdio_slave_hal_send_desc_t;
 
 /// Descriptor used by the receiving part, call `sdio_slave_hal_recv_init_desc`
 /// to initialize it before use.
-typedef lldesc_t sdio_slave_hal_recv_desc_t;
+typedef sdio_slave_ll_desc_t sdio_slave_hal_recv_desc_t;
-#define sdio_slave_hal_recv_desc_s lldesc_s
+#define sdio_slave_hal_recv_desc_s sdio_slave_ll_desc_s
 typedef STAILQ_HEAD(recv_stailq_head_s, sdio_slave_hal_recv_desc_s) sdio_slave_hal_recv_stailq_t;
 
 

components/hal/sdio_slave_hal.c

@@ -46,7 +46,7 @@ static inline int sdio_ringbuf_return(sdio_ringbuf_t* buf, uint8_t *ptr);
 #define _SEND_DESC_NEXT(x)    STAILQ_NEXT(&((sdio_slave_hal_send_desc_t*)x)->dma_desc, qe)
 #define SEND_DESC_NEXT(x)    (sdio_slave_hal_send_desc_t*)_SEND_DESC_NEXT(x)
 #define SEND_DESC_NEXT_SET(x, target)    do { \
-        _SEND_DESC_NEXT(x)=(lldesc_t*)target; \
+        _SEND_DESC_NEXT(x)=(sdio_slave_ll_desc_t*)target; \
     }while(0)
 
 static esp_err_t link_desc_to_last(uint8_t* desc, void* arg)
@@ -259,7 +259,7 @@ static inline send_state_t send_get_state(sdio_slave_context_t* hal)
     return hal->send_state;
 }
 
-DMA_ATTR static const lldesc_t start_desc = {
+DMA_ATTR static const sdio_slave_ll_desc_t start_desc = {
     .owner = 1,
     .buf = (void*)0x3ffbbbbb, //assign a dma-capable pointer other than NULL, which will not be used
     .size = 1,
@@ -319,7 +319,7 @@ static void send_new_packet(sdio_slave_context_t *hal)
 
     sdio_slave_ll_send_stop(hal->slc);
     sdio_slave_ll_send_reset(hal->slc);
-    sdio_slave_ll_send_start(hal->slc, (lldesc_t*)start_desc);
+    sdio_slave_ll_send_start(hal->slc, (sdio_slave_ll_desc_t*)start_desc);
 
     // update pkt_len register to allow host reading.
     sdio_slave_ll_send_write_len(hal->slc, end_desc->pkt_len);
@@ -552,10 +552,10 @@ esp_err_t sdio_slave_hal_send_queue(sdio_slave_context_t* hal, uint8_t *addr, si
  *                  Receive
  *--------------------------------------------------------------------------*/
 
-static lldesc_t* recv_get_first_empty_buf(sdio_slave_context_t* hal)
+static sdio_slave_ll_desc_t* recv_get_first_empty_buf(sdio_slave_context_t* hal)
 {
     sdio_slave_hal_recv_stailq_t *const queue = &(hal->recv_link_list);
-    lldesc_t *desc = STAILQ_FIRST(queue);
+    sdio_slave_ll_desc_t *desc = STAILQ_FIRST(queue);
     while(desc && desc->owner == 0) {
         desc = STAILQ_NEXT(desc, qe);
     }
@@ -593,19 +593,19 @@ bool sdio_slave_hal_recv_done(sdio_slave_context_t *hal)
     return ret;
 }
 
-lldesc_t *sdio_slave_hal_recv_unload_desc(sdio_slave_context_t *hal)
+sdio_slave_ll_desc_t *sdio_slave_hal_recv_unload_desc(sdio_slave_context_t *hal)
 {
     sdio_slave_hal_recv_stailq_t *const queue = &hal->recv_link_list;
-    lldesc_t *desc = STAILQ_FIRST(queue);
+    sdio_slave_ll_desc_t *desc = STAILQ_FIRST(queue);
     if (desc) {
         STAILQ_REMOVE_HEAD(queue, qe);
     }
     return desc;
 }
 
-void sdio_slave_hal_recv_init_desc(sdio_slave_context_t* hal, lldesc_t *desc, uint8_t *start)
+void sdio_slave_hal_recv_init_desc(sdio_slave_context_t* hal, sdio_slave_ll_desc_t *desc, uint8_t *start)
 {
-    *desc = (lldesc_t) {
+    *desc = (sdio_slave_ll_desc_t) {
         .size = hal->recv_buffer_size,
         .buf = start,
     };
@@ -614,7 +614,7 @@ void sdio_slave_hal_recv_init_desc(sdio_slave_context_t* hal, lldesc_t *desc, ui
 void sdio_slave_hal_recv_start(sdio_slave_context_t *hal)
 {
     sdio_slave_ll_recv_reset(hal->slc);
-    lldesc_t *desc = recv_get_first_empty_buf(hal);
+    sdio_slave_ll_desc_t *desc = recv_get_first_empty_buf(hal);
     if (!desc) {
         HAL_LOGD(TAG, "recv: restart without desc");
     } else {
@@ -627,7 +627,7 @@ void sdio_slave_hal_recv_start(sdio_slave_context_t *hal)
 void sdio_slave_hal_recv_reset_counter(sdio_slave_context_t *hal)
 {
     sdio_slave_ll_recv_size_reset(hal->slc);
-    lldesc_t *desc = recv_get_first_empty_buf(hal);
+    sdio_slave_ll_desc_t *desc = recv_get_first_empty_buf(hal);
     while (desc != NULL) {
         sdio_slave_ll_recv_size_inc(hal->slc);
         desc = STAILQ_NEXT(desc, qe);
@@ -637,7 +637,7 @@ void sdio_slave_hal_recv_reset_counter(sdio_slave_context_t *hal)
 void sdio_slave_hal_recv_flush_one_buffer(sdio_slave_context_t *hal)
 {
     sdio_slave_hal_recv_stailq_t *const queue = &hal->recv_link_list;
-    lldesc_t *desc = STAILQ_FIRST(queue);
+    sdio_slave_ll_desc_t *desc = STAILQ_FIRST(queue);
     assert (desc != NULL && desc->owner == 0);
     STAILQ_REMOVE_HEAD(queue, qe);
     desc->owner = 1;
@@ -646,12 +646,12 @@ void sdio_slave_hal_recv_flush_one_buffer(sdio_slave_context_t *hal)
     //we only add it to the tail here, without start the DMA nor increase buffer num.
 }
 
-void sdio_slave_hal_load_buf(sdio_slave_context_t *hal, lldesc_t *desc)
+void sdio_slave_hal_load_buf(sdio_slave_context_t *hal, sdio_slave_ll_desc_t *desc)
 {
     sdio_slave_hal_recv_stailq_t *const queue = &(hal->recv_link_list);
     desc->owner = 1;
 
-    lldesc_t *const tail = STAILQ_LAST(queue, lldesc_s, qe);
+    sdio_slave_ll_desc_t *const tail = STAILQ_LAST(queue, sdio_slave_ll_desc_s, qe);
 
     STAILQ_INSERT_TAIL(queue, desc, qe);
     if (hal->recv_cur_ret == NULL) {
@@ -671,7 +671,7 @@ void sdio_slave_hal_load_buf(sdio_slave_context_t *hal, lldesc_t *desc)
     sdio_slave_ll_recv_size_inc(hal->slc);
 }
 
-static inline void show_queue_item(lldesc_t *item)
+static inline void show_queue_item(sdio_slave_ll_desc_t *item)
 {
     HAL_EARLY_LOGI(TAG, "=> %p: size: %d(%d), eof: %d, owner: %d", item, item->size, item->length, item->eof, item->owner);
     HAL_EARLY_LOGI(TAG, "   buf: %p, stqe_next: %p", item->buf, item->qe.stqe_next);
@@ -680,7 +680,7 @@ static inline void show_queue_item(lldesc_t *item)
 static void __attribute((unused)) dump_queue(sdio_slave_hal_recv_stailq_t *queue)
 {
     int cnt = 0;
-    lldesc_t *item = NULL;
+    sdio_slave_ll_desc_t *item = NULL;
     HAL_EARLY_LOGI(TAG, ">>>>> first: %p, last: %p <<<<<", queue->stqh_first, queue->stqh_last);
     STAILQ_FOREACH(item, queue, qe) {
         cnt++;

components/soc/esp32/include/soc/sdio_slave_pins.h

@@ -1,19 +1,10 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
 
-//     http://www.apache.org/licenses/LICENSE-2.0
+#pragma once
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SDIO_SLAVE_PINS_H_
-#define _SOC_SDIO_SLAVE_PINS_H_
 
 #define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  6
 #define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  11
@@ -30,5 +21,3 @@
 #define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2   12
 #define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3   13
 #define SDIO_SLAVE_SLOT1_FUNC               4
-
-#endif /* _SOC_SDIO_SLAVE_PINS_H_ */

components/soc/esp32/sdio_slave_periph.c

@@ -1,36 +1,23 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 #include <stdint.h>
 #include "soc/sdio_slave_periph.h"
 #include "soc/gpio_periph.h"
 
-// I/O slot of sdio slave:
+/**
-// 0: GPIO 6, 11, 7, 8, 9, 10,
+ * I/O slot of sdio slave:
-// 1: GPIO 14, 15, 2, 4, 12, 13 for CLK, CMD, D0, D1, D2, D3 respectively.
+ * Slot 0: GPIO 6, 11, 7, 8, 9, 10.
-// only one peripheral for SDIO and only one slot can work at the same time.
+ * Slot 1: GPIO 14, 15, 2, 4, 12, 13 for CLK, CMD, D0, D1, D2, D3 respectively.
-// currently slot 0 is occupied by SPI for flash
+ *
-const sdio_slave_slot_info_t sdio_slave_slot_info[2]  = {
+ * @note 1: Only one peripheral for SDIO and only one slot can work at the same time.
+ * @note 2: Slot 0 is occupied by SPI for Flash, therefore we only use Slot 1
+ */
+const sdio_slave_slot_info_t sdio_slave_slot_info[1]  = {
     {
-        .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK,
-        .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD,
-        .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0,
-        .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1,
-        .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2,
-        .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3,
-        .func = SDIO_SLAVE_SLOT0_FUNC,
-    }, {
         .clk_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK,
         .cmd_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD,
         .d0_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0,

components/soc/esp32c6/CMakeLists.txt

@@ -16,7 +16,8 @@ set(srcs
     "uart_periph.c"
     "temperature_sensor_periph.c"
     "timer_periph.c"
-    "twai_periph.c")
+    "twai_periph.c"
+    "sdio_slave_periph.c")
 
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -127,6 +127,10 @@ config SOC_SECURE_BOOT_SUPPORTED
     bool
     default y
 
+config SOC_SDIO_SLAVE_SUPPORTED
+    bool
+    default y
+
 config SOC_BOD_SUPPORTED
     bool
     default y

components/soc/esp32c6/include/soc/host_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -2654,7 +2654,7 @@ typedef union {
 } slchost_inf_st_reg_t;
 
 
-typedef struct slchost_dev_t {
+typedef struct host_dev_t {
     uint32_t reserved_000[4];
     volatile slchost_func2_0_reg_t func2_0;
     volatile slchost_func2_1_reg_t func2_1;
@@ -2725,12 +2725,12 @@ typedef struct slchost_dev_t {
     uint32_t reserved_180[28];
     volatile slchost_conf_reg_t conf;
     volatile slchost_inf_st_reg_t inf_st;
-} slchost_dev_t;
+} host_dev_t;
 
-extern slchost_dev_t HOST;
+extern host_dev_t HOST;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(slchost_dev_t) == 0x1f8, "Invalid size of slchost_dev_t structure");
+_Static_assert(sizeof(host_dev_t) == 0x1f8, "Invalid size of host_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32c6/include/soc/periph_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,6 +33,7 @@ typedef enum {
     PERIPH_ECC_MODULE,
     PERIPH_HMAC_MODULE,
     PERIPH_DS_MODULE,
+    PERIPH_SDIO_SLAVE_MODULE,
     PERIPH_GDMA_MODULE,
     PERIPH_MCPWM0_MODULE,
     PERIPH_ETM_MODULE,

components/soc/esp32c6/include/soc/sdio_slave_pins.h

@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  18
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  19
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0   20
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1   21
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2   22
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3   23
+#define SDIO_SLAVE_SLOT0_FUNC               0

components/soc/esp32c6/include/soc/soc_caps.h

@@ -60,6 +60,7 @@
 #define SOC_ECC_SUPPORTED               1
 #define SOC_FLASH_ENC_SUPPORTED         1
 #define SOC_SECURE_BOOT_SUPPORTED       1
+#define SOC_SDIO_SLAVE_SUPPORTED        1
 #define SOC_BOD_SUPPORTED               1
 #define SOC_APM_SUPPORTED               1
 

components/soc/esp32c6/sdio_slave_periph.c

@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "soc/sdio_slave_periph.h"
+#include "soc/sdio_slave_pins.h"
+
+const sdio_slave_slot_info_t sdio_slave_slot_info[1]  = {
+    {
+        .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK,
+        .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD,
+        .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0,
+        .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1,
+        .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2,
+        .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3,
+        .func = SDIO_SLAVE_SLOT0_FUNC,
+    },
+};

components/soc/esp32s2/include/soc/sdio_slave_pins.h

@@ -1,34 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SDIO_SLAVE_PINS_H_
-#define _SOC_SDIO_SLAVE_PINS_H_
-
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  12
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  11
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0   13
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1   14
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2   9
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3   10
-#define SDIO_SLAVE_SLOT0_FUNC               0
-
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK  36
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD  35
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0   37
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1   38
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2   33
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3   34
-#define SDIO_SLAVE_SLOT1_FUNC               3
-
-#endif /* _SOC_SDIO_SLAVE_PINS_H_ */

components/soc/esp32s3/CMakeLists.txt

@@ -13,7 +13,6 @@ set(srcs
     "pcnt_periph.c"
     "rmt_periph.c"
     "rtc_io_periph.c"
-    "sdio_slave_periph.c"
     "sdmmc_periph.c"
     "spi_periph.c"
     "temperature_sensor_periph.c"

components/soc/esp32s3/include/soc/sdio_slave_pins.h

@@ -1,31 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  6
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  11
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0   7
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1   8
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2   9
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3   10
-#define SDIO_SLAVE_SLOT0_FUNC               0
-
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK  14
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD  15
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0   2
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1   4
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2   12
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3   13
-#define SDIO_SLAVE_SLOT1_FUNC               4

components/soc/esp32s3/include/soc/soc_pins.h

@@ -15,6 +15,5 @@
 #include "soc/usb_pins.h"
 #include "soc/gpio_pins.h"
 #include "soc/spi_pins.h"
-#include "soc/sdio_slave_pins.h"
 #include "soc/sdmmc_pins.h"
 #include "soc/touch_sensor_pins.h"

components/soc/esp32s3/sdio_slave_periph.c

@@ -1,42 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#include <stdint.h>
-#include "soc/sdio_slave_periph.h"
-#include "soc/gpio_periph.h"
-
-// I/O slot of sdio slave:
-// 0: GPIO 6, 11, 7, 8, 9, 10,
-// 1: GPIO 14, 15, 2, 4, 12, 13 for CLK, CMD, D0, D1, D2, D3 respectively.
-// only one peripheral for SDIO and only one slot can work at the same time.
-// currently slot 0 is occupied by SPI for flash
-const sdio_slave_slot_info_t sdio_slave_slot_info[2]  = {
-    {
-        .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK,
-        .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD,
-        .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0,
-        .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1,
-        .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2,
-        .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3,
-        .func = SDIO_SLAVE_SLOT0_FUNC,
-    }, {
-        .clk_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK,
-        .cmd_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD,
-        .d0_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0,
-        .d1_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1,
-        .d2_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2,
-        .d3_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3,
-        .func = SDIO_SLAVE_SLOT1_FUNC,
-    },
-};

examples/peripherals/sdio/slave/README.md

@@ -1,4 +1,4 @@
-| Supported Targets | ESP32 |
+| Supported Targets | ESP32 | ESP32-C6 |
-| ----------------- | ----- |
+| ----------------- | ----- | -------- |
 
 See README.md in the parent folder

tools/ci/check_copyright_ignore.txt

@@ -863,7 +863,6 @@ components/soc/esp32/include/soc/rtc_cntl_struct.h
 components/soc/esp32/include/soc/rtc_i2c_reg.h
 components/soc/esp32/include/soc/rtc_io_reg.h
 components/soc/esp32/include/soc/rtc_io_struct.h
-components/soc/esp32/include/soc/sdio_slave_pins.h
 components/soc/esp32/include/soc/sdmmc_pins.h
 components/soc/esp32/include/soc/sdmmc_reg.h
 components/soc/esp32/include/soc/sens_reg.h
@@ -885,7 +884,6 @@ components/soc/esp32/include/soc/uhci_reg.h
 components/soc/esp32/include/soc/uhci_struct.h
 components/soc/esp32/include/soc/wdev_reg.h
 components/soc/esp32/ledc_periph.c
-components/soc/esp32/sdio_slave_periph.c
 components/soc/esp32/sdmmc_periph.c
 components/soc/esp32/spi_periph.c
 components/soc/esp32/uart_periph.c