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Merge branch 'feature/support_esp32h2_hw_support' into 'master'

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Feature/support esp32h2 hw support

Closes IDF-3378 and IDF-3396

See merge request espressif/esp-idf!14545
This commit is contained in:
Shu Chen
2021-08-26 06:00:27 +00:00
parent 21c05e1b93 11dfd802e0
commit f8f9e545e8
25 changed files with 1827 additions and 634 deletions
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1
Kconfig
View File

@@ -11,7 +11,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_ENV_FPGA
# This option is for internal use only
bool
default "y" if IDF_TARGET="esp32h2" # ESP32H2-TODO: IDF-3378
option env="IDF_ENV_FPGA"
config IDF_TARGET_ARCH_RISCV

7
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
View File

@@ -254,12 +254,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
// This check is always included in the bootloader so it can
// print the minimum revision error message later in the boot
if (bootloader_common_get_chip_revision() < 3) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
}
}
static inline void bootloader_glitch_reset_disable(void)

5
components/esp_hw_support/clk_ctrl_os.c
View File

@@ -6,6 +6,7 @@
#include <freertos/FreeRTOS.h>
#include "soc/clk_ctrl_os.h"
#include "sdkconfig.h"
#define DELAY_RTC_CLK_SWITCH 5
@@ -19,7 +20,11 @@ bool periph_rtc_dig_clk8m_enable(void)
portENTER_CRITICAL(&periph_spinlock);
if (s_periph_ref_counts == 0) {
rtc_dig_clk8m_enable();
#if CONFIG_IDF_TARGET_ESP32H2
s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_RC32K, 100));
#else
s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, 100));
#endif
if (s_rtc_clk_freq == 0) {
portEXIT_CRITICAL(&periph_spinlock);
return false;

120
components/esp_hw_support/port/esp32h2/private_include/regi2c_bbpll.h
View File

@@ -50,71 +50,39 @@
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_DIV 3
#define I2C_BBPLL_OC_DIV_MSB 5
#define I2C_BBPLL_OC_DIV_LSB 0
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_CHGP_DCUR 4
#define I2C_BBPLL_OC_CHGP_DCUR_MSB 2
#define I2C_BBPLL_OC_CHGP_DCUR_LSB 0
#define I2C_BBPLL_OC_BUFF_DCUR 4
#define I2C_BBPLL_OC_BUFF_DCUR_MSB 5
#define I2C_BBPLL_OC_BUFF_DCUR_LSB 3
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 6
#define I2C_BBPLL_OC_TSCHGP_LSB 6
#define I2C_BBPLL_OC_ENB_FCAL 4
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_OC_LPF_DR 5
#define I2C_BBPLL_OC_LPF_DR_MSB 1
#define I2C_BBPLL_OC_LPF_DR_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_OC_VCO_DCUR 5
#define I2C_BBPLL_OC_VCO_DCUR_MSB 3
#define I2C_BBPLL_OC_VCO_DCUR_LSB 2
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL 5
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL 5
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
@@ -138,38 +106,14 @@
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_OC_VCO_DBIAS 9
#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 1
#define I2C_BBPLL_DTEST_LSB 0
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_ENT_PLL_MSB 2
#define I2C_BBPLL_ENT_PLL_LSB 2
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6
#define I2C_BBPLL_DIV_CPU 10
#define I2C_BBPLL_DIV_CPU_MSB 3
#define I2C_BBPLL_DIV_CPU_LSB 3

110
components/esp_hw_support/port/esp32h2/private_include/regi2c_bias.h
View File

@@ -14,9 +14,109 @@
* bootloader_hardware_init function in bootloader_esp32c3.c.
*/
#define I2C_BIAS 0X6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS 0x6a
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
#define I2C_BIAS_DREG_1P6 0
#define I2C_BIAS_DREG_1P6_MSB 3
#define I2C_BIAS_DREG_1P6_LSB 0
#define I2C_BIAS_DREG_0P8 0
#define I2C_BIAS_DREG_0P8_MSB 7
#define I2C_BIAS_DREG_0P8_LSB 4
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
#define I2C_BIAS_DREG_1P2 1
#define I2C_BIAS_DREG_1P2_MSB 7
#define I2C_BIAS_DREG_1P2_LSB 4
#define I2C_BIAS_ENT_CPREG 2
#define I2C_BIAS_ENT_CPREG_MSB 0
#define I2C_BIAS_ENT_CPREG_LSB 0
#define I2C_BIAS_ENT_CGM 2
#define I2C_BIAS_ENT_CGM_MSB 1
#define I2C_BIAS_ENT_CGM_LSB 1
#define I2C_BIAS_CGM_BIAS 2
#define I2C_BIAS_CGM_BIAS_MSB 3
#define I2C_BIAS_CGM_BIAS_LSB 2
#define I2C_BIAS_DREF_IGM 2
#define I2C_BIAS_DREF_IGM_MSB 4
#define I2C_BIAS_DREF_IGM_LSB 4
#define I2C_BIAS_RC_DVREF 2
#define I2C_BIAS_RC_DVREF_MSB 6
#define I2C_BIAS_RC_DVREF_LSB 5
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP 2
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_MSB 7
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_LSB 7
#define I2C_BIAS_RC_ENX 3
#define I2C_BIAS_RC_ENX_MSB 0
#define I2C_BIAS_RC_ENX_LSB 0
#define I2C_BIAS_RC_START 3
#define I2C_BIAS_RC_START_MSB 1
#define I2C_BIAS_RC_START_LSB 1
#define I2C_BIAS_RC_DCAP_EXT 3
#define I2C_BIAS_RC_DCAP_EXT_MSB 7
#define I2C_BIAS_RC_DCAP_EXT_LSB 2
#define I2C_BIAS_XPD_RC 4
#define I2C_BIAS_XPD_RC_MSB 0
#define I2C_BIAS_XPD_RC_LSB 0
#define I2C_BIAS_ENT_CONSTI 4
#define I2C_BIAS_ENT_CONSTI_MSB 1
#define I2C_BIAS_ENT_CONSTI_LSB 1
#define I2C_BIAS_XPD_ICX 4
#define I2C_BIAS_XPD_ICX_MSB 2
#define I2C_BIAS_XPD_ICX_LSB 2
#define I2C_BIAS_RC_RSTB 4
#define I2C_BIAS_RC_RSTB_MSB 3
#define I2C_BIAS_RC_RSTB_LSB 3
#define I2C_BIAS_RC_DIV 4
#define I2C_BIAS_RC_DIV_MSB 7
#define I2C_BIAS_RC_DIV_LSB 4
#define I2C_BIAS_RC_CAP 5
#define I2C_BIAS_RC_CAP_MSB 5
#define I2C_BIAS_RC_CAP_LSB 0
#define I2C_BIAS_RC_UD 5
#define I2C_BIAS_RC_UD_MSB 6
#define I2C_BIAS_RC_UD_LSB 6
#define I2C_BIAS_RC_LOCKB 5
#define I2C_BIAS_RC_LOCKB_MSB 7
#define I2C_BIAS_RC_LOCKB_LSB 7
#define I2C_BIAS_RC_CHG_COUNT 6
#define I2C_BIAS_RC_CHG_COUNT_MSB 4
#define I2C_BIAS_RC_CHG_COUNT_LSB 0
#define I2C_BIAS_XPD_CPREG 7
#define I2C_BIAS_XPD_CPREG_MSB 0
#define I2C_BIAS_XPD_CPREG_LSB 0
#define I2C_BIAS_XPD_CGM 7
#define I2C_BIAS_XPD_CGM_MSB 1
#define I2C_BIAS_XPD_CGM_LSB 1
#define I2C_BIAS_DTEST 7
#define I2C_BIAS_DTEST_MSB 3
#define I2C_BIAS_DTEST_LSB 2
#define I2C_BIAS_DRES12K 7
#define I2C_BIAS_DRES12K_MSB 7
#define I2C_BIAS_DRES12K_LSB 4

121
components/esp_hw_support/port/esp32h2/private_include/regi2c_lp_bias.h
View File

@@ -14,42 +14,105 @@
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_init function in rtc_init.c.
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_XPD_REG_SLP 0
#define I2C_ULP_XPD_REG_SLP_MSB 1
#define I2C_ULP_XPD_REG_SLP_LSB 1
#define I2C_ULP_IR_FORCE_XPD_CK 0
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
#define I2C_ULP_DBIAS_SLP 0
#define I2C_ULP_DBIAS_SLP_MSB 7
#define I2C_ULP_DBIAS_SLP_LSB 4
#define I2C_ULP_IR_FORCE_XPD_IPH 0
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_MSB 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_LSB 1
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
#define I2C_ULP_IR_FORCE_XPD_IPH 1
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 2
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 2
#define I2C_ULP_O_DONE_FLAG 3
#define I2C_ULP_O_DONE_FLAG_MSB 0
#define I2C_ULP_O_DONE_FLAG_LSB 0
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF 1
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_MSB 3
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_LSB 3
#define I2C_ULP_BG_O_DONE_FLAG 3
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP 1
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_MSB 4
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_LSB 4
#define I2C_ULP_OCODE 4
#define I2C_ULP_OCODE_MSB 7
#define I2C_ULP_OCODE_LSB 0
#define I2C_ULP_IR_ZOS_XPD 2
#define I2C_ULP_IR_ZOS_XPD_MSB 0
#define I2C_ULP_IR_ZOS_XPD_LSB 0
#define I2C_ULP_IR_FORCE_CODE 5
#define I2C_ULP_IR_FORCE_CODE_MSB 6
#define I2C_ULP_IR_FORCE_CODE_LSB 6
#define I2C_ULP_IR_ZOS_RSTB 2
#define I2C_ULP_IR_ZOS_RSTB_MSB 1
#define I2C_ULP_IR_ZOS_RSTB_LSB 1
#define I2C_ULP_EXT_CODE 6
#define I2C_ULP_EXT_CODE_MSB 7
#define I2C_ULP_EXT_CODE_LSB 0
#define I2C_ULP_IR_ZOS_RESTART 2
#define I2C_ULP_IR_ZOS_RESTART_MSB 2
#define I2C_ULP_IR_ZOS_RESTART_LSB 2
#define I2C_ULP_DTEST 3
#define I2C_ULP_DTEST_MSB 1
#define I2C_ULP_DTEST_LSB 0
#define I2C_ULP_ENT_BG 3
#define I2C_ULP_ENT_BG_MSB 2
#define I2C_ULP_ENT_BG_LSB 2
#define I2C_ULP_MODE_LVDET 3
#define I2C_ULP_MODE_LVDET_MSB 3
#define I2C_ULP_MODE_LVDET_LSB 3
#define I2C_ULP_DREF_LVDET 3
#define I2C_ULP_DREF_LVDET_MSB 6
#define I2C_ULP_DREF_LVDET_LSB 4
#define I2C_ULP_XPD_LVDET 3
#define I2C_ULP_XPD_LVDET_MSB 7
#define I2C_ULP_XPD_LVDET_LSB 7
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG 4
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_MSB 0
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_LSB 0
#define I2C_ULP_INT_XPD_XTAL_BUF 4
#define I2C_ULP_INT_XPD_XTAL_BUF_MSB 1
#define I2C_ULP_INT_XPD_XTAL_BUF_LSB 1
#define I2C_ULP_INT_XPD_RC_CK 4
#define I2C_ULP_INT_XPD_RC_CK_MSB 2
#define I2C_ULP_INT_XPD_RC_CK_LSB 2
#define I2C_ULP_XTAL_DPHASE 4
#define I2C_ULP_XTAL_DPHASE_MSB 3
#define I2C_ULP_XTAL_DPHASE_LSB 3
#define I2C_ULP_INT_XPD_XTAL_LIN_REG 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_MSB 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_LSB 4
#define I2C_ULP_XTAL_RESTART_DC_CAL 4
#define I2C_ULP_XTAL_RESTART_DC_CAL_MSB 5
#define I2C_ULP_XTAL_RESTART_DC_CAL_LSB 5
#define I2C_ULP_XTAL_DAC 5
#define I2C_ULP_XTAL_DAC_MSB 3
#define I2C_ULP_XTAL_DAC_LSB 0
#define I2C_ULP_XTAL_DBLEED 6
#define I2C_ULP_XTAL_DBLEED_MSB 4
#define I2C_ULP_XTAL_DBLEED_LSB 0
#define I2C_ULP_XTAL_CAL_DONE 6
#define I2C_ULP_XTAL_CAL_DONE_MSB 5
#define I2C_ULP_XTAL_CAL_DONE_LSB 5
#define I2C_ULP_ZOS_DONE 6
#define I2C_ULP_ZOS_DONE_MSB 6
#define I2C_ULP_ZOS_DONE_LSB 6

280
components/esp_hw_support/port/esp32h2/private_include/regi2c_pmu.h Normal file
View File

@@ -0,0 +1,280 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_PMU 0x6d
#define I2C_PMU_HOSTID 0
#define I2C_PMU_THRES_HIGH_7_0 0
#define I2C_PMU_THRES_HIGH_7_0_MSB 7
#define I2C_PMU_THRES_HIGH_7_0_LSB 0
#define I2C_PMU_THRES_LOW_7_0 1
#define I2C_PMU_THRES_LOW_7_0_MSB 7
#define I2C_PMU_THRES_LOW_7_0_LSB 0
#define I2C_PMU_THRES_HIGH_11_8 2
#define I2C_PMU_THRES_HIGH_11_8_MSB 3
#define I2C_PMU_THRES_HIGH_11_8_LSB 0
#define I2C_PMU_THRES_LOW_11_8 2
#define I2C_PMU_THRES_LOW_11_8_MSB 7
#define I2C_PMU_THRES_LOW_11_8_LSB 4
#define I2C_PMU_PVT_DELAY_INIT 3
#define I2C_PMU_PVT_DELAY_INIT_MSB 7
#define I2C_PMU_PVT_DELAY_INIT_LSB 0
#define I2C_PMU_PVT_DELAY_COUNT 4
#define I2C_PMU_PVT_DELAY_COUNT_MSB 5
#define I2C_PMU_PVT_DELAY_COUNT_LSB 0
#define I2C_PMU_OR_EN_CONT_CAL 4
#define I2C_PMU_OR_EN_CONT_CAL_MSB 7
#define I2C_PMU_OR_EN_CONT_CAL_LSB 7
#define I2C_PMU_I2C_RTC_DREG 5
#define I2C_PMU_I2C_RTC_DREG_MSB 4
#define I2C_PMU_I2C_RTC_DREG_LSB 0
#define I2C_PMU_I2C_DIG_DREG 6
#define I2C_PMU_I2C_DIG_DREG_MSB 4
#define I2C_PMU_I2C_DIG_DREG_LSB 0
#define I2C_PMU_I2C_RTC_DREG_SLP 7
#define I2C_PMU_I2C_RTC_DREG_SLP_MSB 3
#define I2C_PMU_I2C_RTC_DREG_SLP_LSB 0
#define I2C_PMU_I2C_DIG_DREG_SLP 7
#define I2C_PMU_I2C_DIG_DREG_SLP_MSB 7
#define I2C_PMU_I2C_DIG_DREG_SLP_LSB 4
#define I2C_PMU_EN_I2C_RTC_DREG 10
#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0
#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0
#define I2C_PMU_EN_I2C_DIG_DREG 10
#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1
#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1
#define I2C_PMU_EN_I2C_RTC_DREG_SLP 10
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2
#define I2C_PMU_EN_I2C_DIG_DREG_SLP 10
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3
#define I2C_PMU_ENX_RTC_DREG 11
#define I2C_PMU_ENX_RTC_DREG_MSB 0
#define I2C_PMU_ENX_RTC_DREG_LSB 0
#define I2C_PMU_ENX_DIG_DREG 11
#define I2C_PMU_ENX_DIG_DREG_MSB 1
#define I2C_PMU_ENX_DIG_DREG_LSB 1
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3 11
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_MSB 2
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_LSB 2
#define I2C_PMU_OR_XPD_RTC_REG 11
#define I2C_PMU_OR_XPD_RTC_REG_MSB 4
#define I2C_PMU_OR_XPD_RTC_REG_LSB 4
#define I2C_PMU_OR_XPD_DIG_REG 11
#define I2C_PMU_OR_XPD_DIG_REG_MSB 5
#define I2C_PMU_OR_XPD_DIG_REG_LSB 5
#define I2C_PMU_OR_PD_RTC_REG_SLP 11
#define I2C_PMU_OR_PD_RTC_REG_SLP_MSB 6
#define I2C_PMU_OR_PD_RTC_REG_SLP_LSB 6
#define I2C_PMU_OR_PD_DIG_REG_SLP 11
#define I2C_PMU_OR_PD_DIG_REG_SLP_MSB 7
#define I2C_PMU_OR_PD_DIG_REG_SLP_LSB 7
#define I2C_PMU_INT_DREG 12
#define I2C_PMU_INT_DREG_MSB 4
#define I2C_PMU_INT_DREG_LSB 0
#define I2C_PMU_O_UDF 12
#define I2C_PMU_O_UDF_MSB 5
#define I2C_PMU_O_UDF_LSB 5
#define I2C_PMU_O_OVF 12
#define I2C_PMU_O_OVF_MSB 6
#define I2C_PMU_O_OVF_LSB 6
#define I2C_PMU_O_UPDATE 12
#define I2C_PMU_O_UPDATE_MSB 7
#define I2C_PMU_O_UPDATE_LSB 7
#define I2C_PMU_PVT_COUNT 13
#define I2C_PMU_PVT_COUNT_MSB 7
#define I2C_PMU_PVT_COUNT_LSB 0
#define I2C_PMU_PVT_COUNT 14
#define I2C_PMU_PVT_COUNT_MSB 3
#define I2C_PMU_PVT_COUNT_LSB 0
#define I2C_PMU_IC_VGOOD_LVDET 14
#define I2C_PMU_IC_VGOOD_LVDET_MSB 4
#define I2C_PMU_IC_VGOOD_LVDET_LSB 4
#define I2C_PMU_IC_POWER_GOOD_DCDC 14
#define I2C_PMU_IC_POWER_GOOD_DCDC_MSB 5
#define I2C_PMU_IC_POWER_GOOD_DCDC_LSB 5
#define I2C_PMU_IC_VGOOD_DIGDET 14
#define I2C_PMU_IC_VGOOD_DIGDET_MSB 6
#define I2C_PMU_IC_VGOOD_DIGDET_LSB 6
#define I2C_PMU_OR_XPD_DCDC 15
#define I2C_PMU_OR_XPD_DCDC_MSB 0
#define I2C_PMU_OR_XPD_DCDC_LSB 0
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC 15
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_MSB 1
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_LSB 1
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC 15
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_MSB 2
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_LSB 2
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC 15
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_MSB 3
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_LSB 3
#define I2C_PMU_OR_ENX_REG_DCDC 15
#define I2C_PMU_OR_ENX_REG_DCDC_MSB 4
#define I2C_PMU_OR_ENX_REG_DCDC_LSB 4
#define I2C_PMU_OR_UNLOCK_DCDC 15
#define I2C_PMU_OR_UNLOCK_DCDC_MSB 5
#define I2C_PMU_OR_UNLOCK_DCDC_LSB 5
#define I2C_PMU_OR_FORCE_LOCK_DCDC 15
#define I2C_PMU_OR_FORCE_LOCK_DCDC_MSB 6
#define I2C_PMU_OR_FORCE_LOCK_DCDC_LSB 6
#define I2C_PMU_OR_ENB_SLOW_CLK 15
#define I2C_PMU_OR_ENB_SLOW_CLK_MSB 7
#define I2C_PMU_OR_ENB_SLOW_CLK_LSB 7
#define I2C_PMU_OC_SCK_DCAP 16
#define I2C_PMU_OC_SCK_DCAP_MSB 7
#define I2C_PMU_OC_SCK_DCAP_LSB 0
#define I2C_PMU_OC_XPD_LVDET 17
#define I2C_PMU_OC_XPD_LVDET_MSB 0
#define I2C_PMU_OC_XPD_LVDET_LSB 0
#define I2C_PMU_OC_MODE_LVDET 17
#define I2C_PMU_OC_MODE_LVDET_MSB 1
#define I2C_PMU_OC_MODE_LVDET_LSB 1
#define I2C_PMU_OR_XPD_TRX 17
#define I2C_PMU_OR_XPD_TRX_MSB 2
#define I2C_PMU_OR_XPD_TRX_LSB 2
#define I2C_PMU_OR_EN_RESET_CHIP 17
#define I2C_PMU_OR_EN_RESET_CHIP_MSB 3
#define I2C_PMU_OR_EN_RESET_CHIP_LSB 3
#define I2C_PMU_OC_DREF_LVDET 17
#define I2C_PMU_OC_DREF_LVDET_MSB 6
#define I2C_PMU_OC_DREF_LVDET_LSB 4
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE 17
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_MSB 7
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_LSB 7
#define I2C_PMU_DTEST 18
#define I2C_PMU_DTEST_MSB 1
#define I2C_PMU_DTEST_LSB 0
#define I2C_PMU_ENT_BIAS 18
#define I2C_PMU_ENT_BIAS_MSB 2
#define I2C_PMU_ENT_BIAS_LSB 2
#define I2C_PMU_ENT_VDD 18
#define I2C_PMU_ENT_VDD_MSB 5
#define I2C_PMU_ENT_VDD_LSB 3
#define I2C_PMU_EN_DMUX 18
#define I2C_PMU_EN_DMUX_MSB 6
#define I2C_PMU_EN_DMUX_LSB 6
#define I2C_PMU_WD_DISABLE 18
#define I2C_PMU_WD_DISABLE_MSB 7
#define I2C_PMU_WD_DISABLE_LSB 7
#define I2C_PMU_DTEST_DCDC 19
#define I2C_PMU_DTEST_DCDC_MSB 0
#define I2C_PMU_DTEST_DCDC_LSB 0
#define I2C_PMU_TESTEN_DCDC 19
#define I2C_PMU_TESTEN_DCDC_MSB 1
#define I2C_PMU_TESTEN_DCDC_LSB 1
#define I2C_PMU_ADD_DCDC 19
#define I2C_PMU_ADD_DCDC_MSB 6
#define I2C_PMU_ADD_DCDC_LSB 4
#define I2C_PMU_OR_POCPENB_DCDC 20
#define I2C_PMU_OR_POCPENB_DCDC_MSB 0
#define I2C_PMU_OR_POCPENB_DCDC_LSB 0
#define I2C_PMU_OR_SSTIME_DCDC 20
#define I2C_PMU_OR_SSTIME_DCDC_MSB 1
#define I2C_PMU_OR_SSTIME_DCDC_LSB 1
#define I2C_PMU_OR_CCM_DCDC 20
#define I2C_PMU_OR_CCM_DCDC_MSB 2
#define I2C_PMU_OR_CCM_DCDC_LSB 2
#define I2C_PMU_OR_VSET_LOW_DCDC 20
#define I2C_PMU_OR_VSET_LOW_DCDC_MSB 7
#define I2C_PMU_OR_VSET_LOW_DCDC_LSB 3
#define I2C_PMU_OR_FSW_DCDC 21
#define I2C_PMU_OR_FSW_DCDC_MSB 2
#define I2C_PMU_OR_FSW_DCDC_LSB 0
#define I2C_PMU_OR_DCMLEVEL_DCDC 21
#define I2C_PMU_OR_DCMLEVEL_DCDC_MSB 4
#define I2C_PMU_OR_DCMLEVEL_DCDC_LSB 3
#define I2C_PMU_OR_DCM2ENB_DCDC 21
#define I2C_PMU_OR_DCM2ENB_DCDC_MSB 5
#define I2C_PMU_OR_DCM2ENB_DCDC_LSB 5
#define I2C_PMU_OR_RAMP_DCDC 21
#define I2C_PMU_OR_RAMP_DCDC_MSB 6
#define I2C_PMU_OR_RAMP_DCDC_LSB 6
#define I2C_PMU_OR_RAMPLEVEL_DCDC 21
#define I2C_PMU_OR_RAMPLEVEL_DCDC_MSB 7
#define I2C_PMU_OR_RAMPLEVEL_DCDC_LSB 7
#define I2C_PMU_OR_VSET_HIGH_DCDC 22
#define I2C_PMU_OR_VSET_HIGH_DCDC_MSB 4
#define I2C_PMU_OR_VSET_HIGH_DCDC_LSB 0
#define I2C_PMU_OC_DEL_SSEND 22
#define I2C_PMU_OC_DEL_SSEND_MSB 7
#define I2C_PMU_OC_DEL_SSEND_LSB 5
#define I2C_PMU_OC_XPD_DIGDET 23
#define I2C_PMU_OC_XPD_DIGDET_MSB 0
#define I2C_PMU_OC_XPD_DIGDET_LSB 0
#define I2C_PMU_OC_MODE_DIGDET 23
#define I2C_PMU_OC_MODE_DIGDET_MSB 1
#define I2C_PMU_OC_MODE_DIGDET_LSB 1
#define I2C_PMU_OC_DREF_DIGDET 23
#define I2C_PMU_OC_DREF_DIGDET_MSB 6
#define I2C_PMU_OC_DREF_DIGDET_LSB 4

108
components/esp_hw_support/port/esp32h2/private_include/regi2c_ulp.h Normal file
View File

@@ -0,0 +1,108 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_XPD_REG_SLP 0
#define I2C_ULP_XPD_REG_SLP_MSB 1
#define I2C_ULP_XPD_REG_SLP_LSB 1
#define I2C_ULP_DBIAS_SLP 0
#define I2C_ULP_DBIAS_SLP_MSB 7
#define I2C_ULP_DBIAS_SLP_LSB 4
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_MSB 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_LSB 1
#define I2C_ULP_IR_FORCE_XPD_IPH 1
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 2
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 2
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF 1
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_MSB 3
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_LSB 3
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP 1
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_MSB 4
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_LSB 4
#define I2C_ULP_IR_ZOS_XPD 2
#define I2C_ULP_IR_ZOS_XPD_MSB 0
#define I2C_ULP_IR_ZOS_XPD_LSB 0
#define I2C_ULP_IR_ZOS_RSTB 2
#define I2C_ULP_IR_ZOS_RSTB_MSB 1
#define I2C_ULP_IR_ZOS_RSTB_LSB 1
#define I2C_ULP_IR_ZOS_RESTART 2
#define I2C_ULP_IR_ZOS_RESTART_MSB 2
#define I2C_ULP_IR_ZOS_RESTART_LSB 2
#define I2C_ULP_DTEST 3
#define I2C_ULP_DTEST_MSB 1
#define I2C_ULP_DTEST_LSB 0
#define I2C_ULP_ENT_BG 3
#define I2C_ULP_ENT_BG_MSB 2
#define I2C_ULP_ENT_BG_LSB 2
#define I2C_ULP_MODE_LVDET 3
#define I2C_ULP_MODE_LVDET_MSB 3
#define I2C_ULP_MODE_LVDET_LSB 3
#define I2C_ULP_DREF_LVDET 3
#define I2C_ULP_DREF_LVDET_MSB 6
#define I2C_ULP_DREF_LVDET_LSB 4
#define I2C_ULP_XPD_LVDET 3
#define I2C_ULP_XPD_LVDET_MSB 7
#define I2C_ULP_XPD_LVDET_LSB 7
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG 4
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_MSB 0
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_LSB 0
#define I2C_ULP_INT_XPD_XTAL_BUF 4
#define I2C_ULP_INT_XPD_XTAL_BUF_MSB 1
#define I2C_ULP_INT_XPD_XTAL_BUF_LSB 1
#define I2C_ULP_INT_XPD_RC_CK 4
#define I2C_ULP_INT_XPD_RC_CK_MSB 2
#define I2C_ULP_INT_XPD_RC_CK_LSB 2
#define I2C_ULP_XTAL_DPHASE 4
#define I2C_ULP_XTAL_DPHASE_MSB 3
#define I2C_ULP_XTAL_DPHASE_LSB 3
#define I2C_ULP_INT_XPD_XTAL_LIN_REG 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_MSB 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_LSB 4
#define I2C_ULP_XTAL_RESTART_DC_CAL 4
#define I2C_ULP_XTAL_RESTART_DC_CAL_MSB 5
#define I2C_ULP_XTAL_RESTART_DC_CAL_LSB 5
#define I2C_ULP_XTAL_DAC 5
#define I2C_ULP_XTAL_DAC_MSB 3
#define I2C_ULP_XTAL_DAC_LSB 0
#define I2C_ULP_XTAL_DBLEED 6
#define I2C_ULP_XTAL_DBLEED_MSB 4
#define I2C_ULP_XTAL_DBLEED_LSB 0
#define I2C_ULP_XTAL_CAL_DONE 6
#define I2C_ULP_XTAL_CAL_DONE_MSB 5
#define I2C_ULP_XTAL_CAL_DONE_LSB 5
#define I2C_ULP_ZOS_DONE 6
#define I2C_ULP_ZOS_DONE_MSB 6
#define I2C_ULP_ZOS_DONE_LSB 6

411
components/esp_hw_support/port/esp32h2/rtc_clk.c
View File

@@ -15,6 +15,7 @@
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
#include "soc/rtc.h"
#include "i2c_bbpll.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/efuse_reg.h"
#include "soc/syscon_reg.h"
@@ -26,14 +27,19 @@
static const char *TAG = "rtc_clk";
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
#define RTC_PLL_FREQ_96M 96
#define RTC_OSC_FREQ_RC8M 18
#define DELAY_RTC_CLK_SWITCH 5
#define RTC_CNTL_ANA_CONF0_CAL_REG 0x6000e040
#define RTC_CNTL_ANA_CONF0_CAL_START BIT(2)
#define RTC_CNTL_ANA_CONF0_CAL_STOP BIT(3)
#define RTC_CNTL_ANA_CONF0_CAL_DONE BIT(24)
// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
// Current PLL frequency, in 96MHZ. Zero if PLL is not enabled.
static int s_cur_pll_freq;
static void rtc_clk_cpu_freq_to_8m(void);
void rtc_clk_cpu_freq_to_8m(void);
static uint32_t rtc_clk_ahb_freq_set(uint32_t div);
void rtc_clk_32k_enable_internal(x32k_config_t cfg)
{
@@ -47,6 +53,9 @@ void rtc_clk_32k_enable_internal(x32k_config_t cfg)
void rtc_clk_32k_enable(bool enable)
{
if (enable) {
/* need to hangup gpio0 & 1 before enable xtal_32k */
rtc_gpio_hangup(0);
rtc_gpio_hangup(1);
x32k_config_t cfg = X32K_CONFIG_DEFAULT();
rtc_clk_32k_enable_internal(cfg);
} else {
@@ -55,16 +64,26 @@ void rtc_clk_32k_enable(bool enable)
}
}
void rtc_clk_rc32k_dfreq(uint32_t dfreq)
{
REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, dfreq);
}
void rtc_clk_rc32k_enable(bool enable)
{
rc32k_config_t cfg = RC32K_CONFIG_DEFAULT();
rtc_clk_rc32k_dfreq(cfg.dfreq);
REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_XPD, enable);
}
void rtc_clk_32k_enable_external(void)
{
/* TODO ESP32-C3 IDF-2408: external 32k source may need different settings */
x32k_config_t cfg = X32K_CONFIG_DEFAULT();
rtc_clk_32k_enable_internal(cfg);
rtc_clk_32k_enable(true);
}
void rtc_clk_32k_bootstrap(uint32_t cycle)
{
/* No special bootstrapping needed for ESP32-C3, 'cycle' argument is to keep the signature
/* No special bootstrapping needed for ESP32-H2, 'cycle' argument is to keep the signature
* same as for the ESP32. Just enable the XTAL here.
*/
(void) cycle;
@@ -82,53 +101,11 @@ bool rtc_clk_32k_enabled(void)
return !disabled;
}
void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
{
if (clk_8m_en) {
// CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); // ESP32H2-TODO: IDF-3396
/* no need to wait once enabled by software */
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
esp_rom_delay_us(DELAY_8M_ENABLE);
} else {
// SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
}
/* d256 should be independent configured with 8M
* Maybe we can split this function into 8m and dmd256
*/
if (d256_en) {
// CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
} else {
// SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
}
}
bool rtc_clk_8m_enabled(void)
{
return false;
// return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; // ESP32H2-TODO: IDF-3396
}
bool rtc_clk_8md256_enabled(void)
{
return false;
// return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; // ESP32H2-TODO: IDF-3396
}
void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
{
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
/* Why we need to connect this clock to digital?
* Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead?
*/
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
/* The clk_8m_d256 will be closed when rtc_state in SLEEP,
so if the slow_clk is 8md256, clk_8m must be force power on
*/
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
rtc_clk_32k_enable((slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
rtc_clk_rc32k_enable((slow_freq == RTC_SLOW_FREQ_RC32K) ? 1 : 0);
esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
}
@@ -142,7 +119,7 @@ uint32_t rtc_clk_slow_freq_get_hz(void)
switch (rtc_clk_slow_freq_get()) {
case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
case RTC_SLOW_FREQ_RC32K: return RTC_SLOW_CLK_FREQ_RC32;
}
return 0;
}
@@ -170,100 +147,32 @@ static void rtc_clk_bbpll_enable(void)
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
}
static void rtc_clk_bbpll_cali_stop(void)
{
while (!REG_GET_BIT(RTC_CNTL_ANA_CONF0_CAL_REG, RTC_CNTL_ANA_CONF0_CAL_DONE));
REG_CLR_BIT(RTC_CNTL_ANA_CONF0_CAL_REG, RTC_CNTL_ANA_CONF0_CAL_STOP);
REG_SET_BIT(RTC_CNTL_ANA_CONF0_CAL_REG, RTC_CNTL_ANA_CONF0_CAL_START);
}
void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
{
uint8_t div_ref;
uint8_t div7_0;
uint8_t dr1;
uint8_t dr3;
uint8_t dchgp;
uint8_t dcur;
uint8_t dbias;
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
if (pll_freq == RTC_PLL_FREQ_480M) {
/* Set this register to let the digital part know 480M PLL is used */
// SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); // ESP32H2-TODO: IDF-3396
/* Configure 480M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 26;
dr1 = 1;
dr3 = 1;
dchgp = 4;
dcur = 0;
dbias = 2;
break;
default:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
}
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
uint8_t div5_0;
if ((pll_freq == RTC_PLL_FREQ_96M) && (xtal_freq == RTC_XTAL_FREQ_32M)) {
/* Configure 96M PLL */
div_ref = 0;
div5_0 = 1;
} else {
/* Clear this register to let the digital part know 320M PLL is used */
// CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); // ESP32H2-TODO: IDF-3396
/* Configure 320M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 6;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
default:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
}
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
div_ref = 0;
div5_0 = 1;
SOC_LOGE(TAG, "invalid pll frequency");
}
uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
uint8_t i2c_bbpll_div_7_0 = div7_0;
uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, div_ref);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DIV, div5_0); //I2C_BBPLL_OC_DIV_5_0
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 3); // need update to 3 since s2
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
s_cur_pll_freq = pll_freq;
}
@@ -274,19 +183,21 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
*/
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
{
// int per_conf = DPORT_CPUPERIOD_SEL_80;
if (cpu_freq_mhz == 80) {
/* nothing to do */
} else if (cpu_freq_mhz == 160) {
// per_conf = DPORT_CPUPERIOD_SEL_160;
int div = 1;
if (RTC_PLL_FREQ_96M % cpu_freq_mhz == 0) {
div = RTC_PLL_FREQ_96M / cpu_freq_mhz;
} else {
SOC_LOGE(TAG, "invalid frequency");
abort();
}
// REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf); // ESP32H2-TODO: IDF-3396
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
rtc_clk_apb_freq_update(80 * MHZ);
rtc_clk_cpu_freq_set(DPORT_SOC_CLK_SEL_PLL, div - 1);
if (cpu_freq_mhz > RTC_XTAL_FREQ_32M) {
rtc_clk_ahb_freq_set(2);
} else {
rtc_clk_ahb_freq_set(1);
}
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
ets_update_cpu_frequency(cpu_freq_mhz);
}
@@ -295,62 +206,32 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
uint32_t source_freq_mhz;
rtc_cpu_freq_src_t source;
uint32_t divider;
uint32_t real_freq_mhz;
uint32_t xtal_freq = (uint32_t) rtc_clk_xtal_freq_get();
if (freq_mhz <= xtal_freq) {
divider = xtal_freq / freq_mhz;
real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
if (real_freq_mhz != freq_mhz) {
// no suitable divider
return false;
}
source_freq_mhz = xtal_freq;
source = RTC_CPU_FREQ_SRC_XTAL;
} else if (freq_mhz == 80) {
real_freq_mhz = freq_mhz;
if (freq_mhz > xtal_freq) {
source = RTC_CPU_FREQ_SRC_PLL;
source_freq_mhz = RTC_PLL_FREQ_480M;
divider = 6;
} else if (freq_mhz == 160) {
real_freq_mhz = freq_mhz;
source = RTC_CPU_FREQ_SRC_PLL;
source_freq_mhz = RTC_PLL_FREQ_480M;
divider = 3;
source_freq_mhz = RTC_PLL_FREQ_96M;
divider = RTC_PLL_FREQ_96M / freq_mhz;
rtc_clk_ahb_freq_set(2);
} else {
// unsupported frequency
return false;
source = root_clk_get();
source_freq_mhz = root_clk_slt(source);
divider = source_freq_mhz / freq_mhz;
rtc_clk_ahb_freq_set(1);
}
*out_config = (rtc_cpu_freq_config_t) {
.source = source,
.div = divider,
.source_freq_mhz = source_freq_mhz,
.freq_mhz = real_freq_mhz
.freq_mhz = freq_mhz
};
return true;
}
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
{
uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) {
rtc_clk_bbpll_disable();
}
} else if (config->source == RTC_CPU_FREQ_SRC_PLL) {
if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) {
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
}
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
} else if (config->source == RTC_CPU_FREQ_SRC_8M) {
rtc_clk_cpu_freq_to_8m();
if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) {
rtc_clk_bbpll_disable();
}
}
uint32_t src_freq_mhz = root_clk_slt(config->source);
uint32_t div = src_freq_mhz / (config->freq_mhz);
rtc_clk_cpu_freq_set(config->source, div);
}
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
@@ -363,29 +244,37 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
switch (soc_clk_sel) {
case DPORT_SOC_CLK_SEL_XTAL: {
source = RTC_CPU_FREQ_SRC_XTAL;
div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
freq_mhz = source_freq_mhz / div;
break;
}
break;
case DPORT_SOC_CLK_SEL_PLL: {
// ESP32H2-TODO: IDF-3396
source = 0;
div = 0;
source_freq_mhz = 0;
freq_mhz = 0;
source = RTC_CPU_FREQ_SRC_PLL;
div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
source_freq_mhz = RTC_PLL_FREQ_96M;
freq_mhz = source_freq_mhz / div;
break;
}
case DPORT_SOC_CLK_SEL_8M:
case DPORT_SOC_CLK_SEL_8M: {
source = RTC_CPU_FREQ_SRC_8M;
source_freq_mhz = 8;
div = 1;
freq_mhz = source_freq_mhz;
source_freq_mhz = RTC_OSC_FREQ_RC8M;
div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
freq_mhz = source_freq_mhz / div;
break;
default:
}
case DPORT_SOC_CLK_SEL_XTAL_D2: {
source = RTC_CPU_FREQ_SRC_XTAL_D2;
div = REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
freq_mhz = source_freq_mhz / div / 2;
break;
}
default: {
SOC_LOGE(TAG, "unsupported frequency configuration");
abort();
}
}
*out_config = (rtc_cpu_freq_config_t) {
.source = source,
.source_freq_mhz = source_freq_mhz,
@@ -410,7 +299,6 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
void rtc_clk_cpu_freq_set_xtal(void)
{
int freq_mhz = (int) rtc_clk_xtal_freq_get();
rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
rtc_clk_bbpll_disable();
}
@@ -422,20 +310,17 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
{
ets_update_cpu_frequency(freq);
/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1);
rtc_clk_cpu_freq_set(DPORT_SOC_CLK_SEL_XTAL, div);
/* no need to adjust the REF_TICK */
/* switch clock source */
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL);
rtc_clk_apb_freq_update(freq * MHZ);
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
}
static void rtc_clk_cpu_freq_to_8m(void)
void rtc_clk_cpu_freq_to_8m(void)
{
ets_update_cpu_frequency(8);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M);
rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
ets_update_cpu_frequency(RTC_OSC_FREQ_RC8M);
root_clk_slt(DPORT_SOC_CLK_SEL_8M);
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
}
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
@@ -443,7 +328,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
if (!clk_val_is_valid(xtal_freq_reg)) {
SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
return RTC_XTAL_FREQ_40M;
return RTC_XTAL_FREQ_32M;
}
return reg_val_to_clk_val(xtal_freq_reg);
}
@@ -458,41 +343,121 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq)
WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
}
uint32_t rtc_clk_apb_freq_get(void)
{
uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
// round to the nearest MHz
freq_hz += MHZ / 2;
uint32_t remainder = freq_hz % MHZ;
return freq_hz - remainder;
uint32_t apb_div = REG_GET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_APB_DIV_NUM) + 1;
return rtc_clk_ahb_freq_get() / apb_div;
}
uint32_t rtc_clk_ahb_freq_get()
{
rtc_cpu_freq_config_t cpu_config;
uint32_t ahb_div = REG_GET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_AHB_DIV_NUM) + 1;
rtc_clk_cpu_freq_get_config(&cpu_config) ;
return cpu_config.freq_mhz / ahb_div;
}
uint32_t rtc_clk_ahb_freq_set(uint32_t div)
{
REG_SET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_AHB_DIV_NUM, div - 1);
return rtc_clk_ahb_freq_get();
}
uint32_t rtc_clk_apb_freq_set(uint32_t div)
{
REG_SET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_APB_DIV_NUM, div - 1);
return rtc_clk_apb_freq_get();
}
void rtc_clk_cpu_freq_set(uint32_t source, uint32_t div)
{
if (root_clk_get() != source) {
root_clk_slt(source);
}
REG_SET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_CPU_DIV_NUM, div - 1);
}
void rtc_clk_divider_set(uint32_t div)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, div);
REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, div - 1);
SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
}
void rtc_clk_8m_divider_set(uint32_t div)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, div);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, div - 1);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
}
void rtc_dig_clk8m_enable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
void rtc_dig_clk8m_disable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
}
uint32_t read_spll_freq(void)
{
return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SPLL_FREQ);
}
uint32_t read_xtal_freq(void)
{
return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_CLK_XTAL_FREQ);
}
/* Select clock root source for esp32h2. return source clk freq_mhz
*/
uint32_t root_clk_slt(uint32_t source)
{
uint32_t root_clk_freq_mhz;
switch (source) {
case RTC_CPU_FREQ_SRC_XTAL:
root_clk_freq_mhz = RTC_XTAL_FREQ_32M;
rtc_clk_bbpll_disable();
break;
case RTC_CPU_FREQ_SRC_PLL:
// SPLL_ENABLE
root_clk_freq_mhz = RTC_PLL_FREQ_96M;
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(RTC_XTAL_FREQ_32M, root_clk_freq_mhz);
rtc_clk_bbpll_cali_stop();
break;
case RTC_CPU_FREQ_SRC_8M:
root_clk_freq_mhz = RTC_OSC_FREQ_RC8M;
rtc_dig_clk8m_enable();
rtc_clk_8m_divider_set(1);
rtc_clk_bbpll_disable();
break;
case RTC_CPU_FREQ_SRC_XTAL_D2:
root_clk_freq_mhz = RTC_XTAL_FREQ_32M / 2;
rtc_clk_bbpll_disable();
break;
default:
SOC_LOGE(TAG, "unsupported source clk configuration");
root_clk_freq_mhz = RTC_XTAL_FREQ_32M;
rtc_clk_bbpll_disable();
source = 0;
break;
}
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, source);
return root_clk_freq_mhz;
}
uint32_t root_clk_get()
{
uint32_t src_slt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
return src_slt;
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/

1
components/esp_hw_support/port/esp32h2/rtc_clk_common.h
View File

@@ -14,6 +14,7 @@
#define DPORT_SOC_CLK_SEL_XTAL 0
#define DPORT_SOC_CLK_SEL_PLL 1
#define DPORT_SOC_CLK_SEL_8M 2
#define DPORT_SOC_CLK_SEL_XTAL_D2 3
#define RTC_FAST_CLK_FREQ_8M 8500000

23
components/esp_hw_support/port/esp32h2/rtc_clk_init.c
View File

@@ -8,11 +8,14 @@
#include <stdint.h>
#include <stddef.h>
#include <stdlib.h>
#include "sdkconfig.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "hal/cpu_hal.h"
@@ -21,7 +24,11 @@
#include "sdkconfig.h"
#include "rtc_clk_common.h"
#include "esp_rom_uart.h"
#include "soc/efuse_reg.h"
#include "soc/syscon_reg.h"
#include "soc/system_reg.h"
#include "rtc_clk_common.h"
#include "esp_rom_sys.h"
static const char *TAG = "rtc_clk_init";
void rtc_clk_init(rtc_clk_config_t cfg)
@@ -39,24 +46,25 @@ void rtc_clk_init(rtc_clk_config_t cfg)
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
/* enable modem clk */
REG_WRITE(SYSTEM_MODEM_CLK_EN_REG, UINT32_MAX);
/* Configure 150k clock division */
rtc_clk_divider_set(cfg.clk_rtc_clk_div);
/* Configure 8M clock division */
rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
/* Enable the internal bus used to configure PLLs */
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_APLL_M | ANA_I2C_BBPLL_M);
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
esp_rom_uart_tx_wait_idle(0);
rtc_clk_xtal_freq_update(xtal_freq);
rtc_clk_apb_freq_update(xtal_freq * MHZ);
rtc_clk_apb_freq_update(rtc_clk_apb_freq_get() * MHZ);
/* Set CPU frequency */
rtc_clk_cpu_freq_get_config(&old_config);
uint32_t freq_before = old_config.freq_mhz;
root_clk_slt(cfg.root_clk_slt);
bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
if (!res) {
SOC_LOGE(TAG, "invalid CPU frequency value");
@@ -72,8 +80,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
rtc_clk_32k_enable(true);
}
if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
rtc_clk_8m_enable(true, need_8md256);
rtc_dig_clk8m_enable();
}
rtc_clk_fast_freq_set(cfg.fast_freq);
rtc_clk_slow_freq_set(cfg.slow_freq);

121
components/esp_hw_support/port/esp32h2/rtc_init.c
View File

@@ -9,23 +9,26 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/efuse_periph.h"
#include "soc/gpio_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "soc/syscon_reg.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "i2c_pmu.h"
#include "soc/clkrst_reg.h"
// ESP32H2-TODO: IDF-3396
void pmu_ctl(void);
void dcdc_ctl(uint32_t mode);
void regulator_slt(regulator_config_t regula_cfg);
void rtc_init(rtc_config_t cfg)
{
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
@@ -44,8 +47,6 @@ void rtc_init(rtc_config_t cfg)
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
// set_rtc_dig_dbias(); // ESP32H2-TODO: IDF-3396
if (cfg.clkctl_init) {
//clear CMMU clock force on
CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
@@ -69,10 +70,6 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
//open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
//cancel bbpll force pu if setting no force power up
if (!cfg.bbpll_fpu) {
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
@@ -86,14 +83,8 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
if (cfg.rtc_dboost_fpd) {
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
}
//clear i2c_reset_protect pd force, need tested in low temperature.
//CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD);
// clear i2c_reset_protect pd force, need tested in low temperature.
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD);
/* If this mask is enabled, all soc memories cannot enter power down mode */
/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
@@ -104,18 +95,25 @@ void rtc_init(rtc_config_t cfg)
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0);
rtc_sleep_pu(pu_cfg);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
//cancel digital PADS force pu
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU); //
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_MEM_FORCE_PU); //
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); //
//cancel digital PADS force no iso
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO);
//cancel digital PADS force no iso
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); //
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_MEM_FORCE_NOISO); //
if (cfg.cpu_waiti_clk_gate) {
CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
} else {
@@ -125,10 +123,49 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
}
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
if (cfg.pmu_ctl) {
/* pmu init*/
pmu_ctl();
}
/* config dcdc frequency */
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL0_REG, RTC_CNTL_FSW_DCDC, RTC_CNTL_DCDC_FREQ_DEFAULT);
}
void pmu_ctl(void)
{
pmu_config_t pmu_cfg = PMU_CONFIG_DEFAULT();
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_EN_CONT_CAL, pmu_cfg.or_en_cont_cal);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_ENX_RTC_DREG, pmu_cfg.enx_rtc_dreg);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_ENX_DIG_DREG, pmu_cfg.enx_dig_dreg);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, pmu_cfg.en_i2c_rtc_dreg);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, pmu_cfg.en_i2c_dig_dreg);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, pmu_cfg.en_i2c_rtc_dreg_slp);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG_SLP, pmu_cfg.en_i2c_dig_dreg_slp);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_SLAVE_3P3, pmu_cfg.or_xpd_rtc_slave_3p3);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, pmu_cfg.or_xpd_rtc_reg);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DIG_REG, pmu_cfg.or_xpd_dig_reg);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_PD_RTC_REG_SLP, pmu_cfg.or_pd_rtc_reg_slp);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_PD_DIG_REG_SLP, pmu_cfg.or_pd_dig_reg_slp);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DCDC, pmu_cfg.or_xpd_dcdc);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC, pmu_cfg.or_disalbe_deep_sleep_dcdc);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC, pmu_cfg.or_disalbe_light_sleep_dcdc);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENALBE_TRX_MODE_DCDC, pmu_cfg.or_enalbe_trx_mode_dcdc);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENX_REG_DCDC, pmu_cfg.or_enx_reg_dcdc);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_UNLOCK_DCDC, pmu_cfg.or_unlock_dcdc);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_FORCE_LOCK_DCDC, pmu_cfg.or_force_lock_dcdc);
// REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENB_SLOW_CLK, pmu_cfg.or_enb_slow_clk);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_TRX, pmu_cfg.or_xpd_trx);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_EN_RESET_CHIP, pmu_cfg.or_en_reset_chip);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_FORCE_XPD_REG_SLAVE, pmu_cfg.or_force_xpd_reg_slave);
}
void dslp_osc_pd(void){
REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG,RTC_CNTL_RC32K_XPD, 0);
REG_SET_FIELD(RTC_CNTL_PLL8M_REG, RTC_CNTL_XPD_PLL8M, 0);
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
{
rtc_vddsdio_config_t result;
@@ -166,3 +203,41 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
val |= RTC_CNTL_SDIO_PD_EN;
REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
}
void dig_gpio_setpd(uint32_t gpio_no, bool pd)
{
SET_PERI_REG_BITS(PERIPHS_IO_MUX_XTAL_32K_P_U + 4 * gpio_no, 0x1, pd, FUN_PD_S);
}
void dig_gpio_setpu(uint32_t gpio_no, bool pu)
{
SET_PERI_REG_BITS(PERIPHS_IO_MUX_XTAL_32K_P_U + 4 * gpio_no, 0x1, pu, FUN_PU_S);
}
void dig_gpio_in_en(uint32_t gpio_no, bool enable)
{
SET_PERI_REG_BITS(PERIPHS_IO_MUX_XTAL_32K_P_U + 4 * gpio_no, 0x1, enable, FUN_IE_S);
}
void dig_gpio_out_en(uint32_t gpio_no, bool enable)
{
if (enable)
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, 1 << gpio_no);
else
SET_PERI_REG_MASK(GPIO_ENABLE_W1TC_REG, 1 << gpio_no);
}
void dig_gpio_mcusel(uint32_t gpio_no, uint32_t mcu_sel)
{
SET_PERI_REG_BITS(PERIPHS_IO_MUX_XTAL_32K_P_U + 4 * gpio_no, MCU_SEL, mcu_sel, MCU_SEL_S);
}
void rtc_gpio_hangup(uint32_t gpio_no)
{
dig_gpio_setpd(gpio_no, 0);
dig_gpio_setpu(gpio_no, 0);
dig_gpio_out_en(gpio_no, 0);
dig_gpio_in_en(gpio_no, 0);
dig_gpio_mcusel(gpio_no, 1);
}

2
components/esp_hw_support/port/esp32h2/rtc_pm.c
View File

@@ -44,7 +44,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
switch (sleep_mode) {
case PM_LIGHT_SLEEP:
cfg.wifi_pd_en = 1;
// cfg.wifi_pd_en = 1; // ESP32-H2 TO-DO: IDF-3693
cfg.dig_dbias_wak = 4;
cfg.dig_dbias_slp = 0;
cfg.rtc_dbias_wak = 0;

228
components/esp_hw_support/port/esp32h2/rtc_sleep.c
View File

@@ -10,23 +10,26 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/rtc.h"
#include "soc/i2s_reg.h"
#include "soc/bb_reg.h"
#include "soc/nrx_reg.h"
#include "soc/fe_reg.h"
#include "soc/timer_group_reg.h"
#include "soc/system_reg.h"
#include "soc/rtc.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/rtc.h"
#include "regi2c_ctrl.h"
#include "esp_efuse.h"
#include "i2c_pmu.h"
#include "soc_log.h"
#include "esp_rom_uart.h"
/**
* Configure whether certain peripherals are powered down in deep sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
*/
static const char *TAG = "rtc_sleep";
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
@@ -53,17 +56,111 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
}
}
void dcdc_ctl(uint32_t mode)
{
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_IDLE, RTC_CNTL_DCDC_TRX_MODE);
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_MONITOR, RTC_CNTL_DCDC_TRX_MODE);
if ((mode & 0x10) == 0x10) {
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, mode);
} else if (mode == 0) {
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_TRX_MODE);
} else if (mode == 1) {
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_LSLP_MODE);
} else if (mode == 2) {
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_DSLP_MODE);
} else {
SOC_LOGE(TAG, "invalid dcdc mode!\n");
}
}
void regulator_set(regulator_cfg_t cfg)
{
// DIG REGULATOR0
if (cfg.dig_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
}
// DIG REGULATOR1
if (cfg.dig_regul1_en) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
}
// RTC REGULATOR0
if (cfg.rtc_regul0_en) {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1);
}
}
void regulator_slt(regulator_config_t regula_cfg)
{
// dig regulator
if (regula_cfg.dig_source == 1) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
}
// rtc regulator
if (regula_cfg.rtc_source == 1) {
REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
}
}
void dbias_switch_set(dbias_swt_cfg_t cfg)
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
}
void left_up_trx_fpu(bool fpu)
{
if (fpu) {
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP, 0);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_BIAS_BUF, 0);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 0);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU);
}
}
void rtc_sleep_pmu_init(void)
{
dcdc_ctl(DCDC_SLP_DSLP_MODE);
dbias_swt_cfg_t swt_cfg = DBIAS_SWITCH_CONFIG_DEFAULT();
dbias_switch_set(swt_cfg);
regulator_config_t regula0_cfg = REGULATOR0_CONFIG_DEFAULT();
regulator_slt(regula0_cfg);
regulator_config_t regula1_cfg = REGULATOR1_CONFIG_DEFAULT();
regulator_slt(regula1_cfg);
regulator_cfg_t rg_set = REGULATOR_SET_DEFAULT();
regulator_set(rg_set);
left_up_trx_fpu(0);
}
void rtc_sleep_init(rtc_sleep_config_t cfg)
{
if (cfg.lslp_mem_inf_fpu) {
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
if (cfg.wifi_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
}
if (cfg.bt_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
} else {
@@ -79,43 +176,43 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
}
if (cfg.dig_ret_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN);
}
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
// ESP32-H2 TO-DO: IDF-3693
if (cfg.deep_slp) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, atten_deep_sleep);
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
// CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
// SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT);
}
/* enable VDDSDIO control by state machine */
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
/* gating XTAL clock */
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING);
esp_rom_uart_tx_wait_idle(0);
}
void rtc_sleep_low_init(uint32_t slowclk_period)
@@ -141,7 +238,6 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
/* Start entry into sleep mode */
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
;
@@ -172,56 +268,56 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
const unsigned CRC_LEN = 0x7ff;
asm volatile(
/* Start CRC calculation */
"sw %1, 0(%0)\n" // set RTC_MEM_CRC_ADDR & RTC_MEM_CRC_LEN
"or t0, %1, %2\n"
"sw t0, 0(%0)\n" // set RTC_MEM_CRC_START
/* Start CRC calculation */
"sw %1, 0(%0)\n" // set RTC_MEM_CRC_ADDR & RTC_MEM_CRC_LEN
"or t0, %1, %2\n"
"sw t0, 0(%0)\n" // set RTC_MEM_CRC_START
/* Wait for the CRC calculation to finish */
".Lwaitcrc:\n"
"fence\n"
"lw t0, 0(%0)\n"
"li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n"
"and t0, t0, t1\n"
"beqz t0, .Lwaitcrc\n"
"not %2, %2\n" // %2 -> ~DPORT_RTC_MEM_CRC_START
"and t0, t0, %2\n"
"sw t0, 0(%0)\n" // clear RTC_MEM_CRC_START
"fence\n"
"not %2, %2\n" // %2 -> DPORT_RTC_MEM_CRC_START, probably unnecessary but gcc assumes inputs unchanged
/* Wait for the CRC calculation to finish */
".Lwaitcrc:\n"
"fence\n"
"lw t0, 0(%0)\n"
"li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n"
"and t0, t0, t1\n"
"beqz t0, .Lwaitcrc\n"
"not %2, %2\n" // %2 -> ~DPORT_RTC_MEM_CRC_START
"and t0, t0, %2\n"
"sw t0, 0(%0)\n" // clear RTC_MEM_CRC_START
"fence\n"
"not %2, %2\n" // %2 -> DPORT_RTC_MEM_CRC_START, probably unnecessary but gcc assumes inputs unchanged
/* Store the calculated value in RTC_MEM_CRC_REG */
"lw t0, 0(%3)\n"
"sw t0, 0(%4)\n"
"fence\n"
/* Store the calculated value in RTC_MEM_CRC_REG */
"lw t0, 0(%3)\n"
"sw t0, 0(%4)\n"
"fence\n"
/* Set register bit to go into deep sleep */
"lw t0, 0(%5)\n"
"or t0, t0, %6\n"
"sw t0, 0(%5)\n"
"fence\n"
/* Set register bit to go into deep sleep */
"lw t0, 0(%5)\n"
"or t0, t0, %6\n"
"sw t0, 0(%5)\n"
"fence\n"
/* Wait for sleep reject interrupt (never finishes if successful) */
".Lwaitsleep:"
"fence\n"
"lw t0, 0(%7)\n"
"and t0, t0, %8\n"
"beqz t0, .Lwaitsleep\n"
/* Wait for sleep reject interrupt (never finishes if successful) */
".Lwaitsleep:"
"fence\n"
"lw t0, 0(%7)\n"
"and t0, t0, %8\n"
"beqz t0, .Lwaitsleep\n"
:
:
"r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), // %0
"r" ( (CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S)
| (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), // %1
"r" (SYSTEM_RTC_MEM_CRC_START), // %2
"r" (SYSTEM_RTC_FASTMEM_CRC_REG), // %3
"r" (RTC_MEMORY_CRC_REG), // %4
"r" (RTC_CNTL_STATE0_REG), // %5
"r" (RTC_CNTL_SLEEP_EN), // %6
"r" (RTC_CNTL_INT_RAW_REG), // %7
"r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
: "t0", "t1" // working registers
);
:
:
"r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), // %0
"r" ( (CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S)
| (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), // %1
"r" (SYSTEM_RTC_MEM_CRC_START), // %2
"r" (SYSTEM_RTC_FASTMEM_CRC_REG), // %3
"r" (RTC_MEMORY_CRC_REG), // %4
"r" (RTC_CNTL_STATE0_REG), // %5
"r" (RTC_CNTL_SLEEP_EN), // %6
"r" (RTC_CNTL_INT_RAW_REG), // %7
"r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
: "t0", "t1" // working registers
);
return rtc_sleep_finish(0);
}

27
components/esp_hw_support/port/esp32h2/rtc_time.c
View File

@@ -40,18 +40,19 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get();
if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
cal_clk = RTC_CAL_32K_XTAL;
} else if (slow_freq == RTC_SLOW_FREQ_8MD256) {
cal_clk = RTC_CAL_8MD256;
} else if (slow_freq == RTC_SLOW_FREQ_RC32K) {
cal_clk = RTC_CAL_RC32K;
}
}
/* Enable requested clock (150k clock is always on) */
int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
bool dig_32k_xtal_state = REG_GET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) {
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
if (cal_clk == RTC_CAL_8MD256) {
// SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); // ESP32H2-TODO: IDF-3396
}
bool dig_rc32k_state = REG_GET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN);
if (cal_clk == RTC_CAL_RC32K && !dig_rc32k_state) {
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN, 1);
}
/* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
@@ -72,9 +73,9 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = RTC_SLOW_CLK_FREQ_32K;
} else if (cal_clk == RTC_CAL_8MD256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = RTC_SLOW_CLK_FREQ_8MD256;
} else if (cal_clk == RTC_CAL_RC32K) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = RTC_SLOW_CLK_FREQ_RC32;
} else {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = RTC_SLOW_CLK_FREQ_150K;
@@ -85,7 +86,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* Wait for calibration to finish up to another us_time_estimate */
esp_rom_delay_us(us_time_estimate);
esp_rom_delay_us(us_time_estimate * 3);
uint32_t cal_val;
while (true) {
if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
@@ -98,12 +99,8 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
}
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
if (cal_clk == RTC_CAL_8MD256) {
// CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); // ESP32H2-TODO: IDF-3396
}
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN, dig_rc32k_state);
return cal_val;
}

16
components/esp_system/port/soc/esp32h2/clk.c
View File

@@ -23,6 +23,7 @@
#include "esp_clk_internal.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/rtc.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
#include "soc/soc.h"
@@ -35,7 +36,6 @@
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive
@@ -62,7 +62,7 @@
typedef enum {
SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator
SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL
SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256
SLOW_CLK_RC32K = RTC_SLOW_FREQ_RC32K, //!< Internal 32 KHz RC oscillator
SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
} slow_clk_sel_t;
@@ -73,7 +73,6 @@ static const char *TAG = "clk";
__attribute__((weak)) void esp_clk_init(void)
{
#if !CONFIG_IDF_ENV_FPGA
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
soc_reset_reason_t rst_reas;
rst_reas = esp_rom_get_reset_reason(0);
@@ -82,10 +81,9 @@ static const char *TAG = "clk";
}
rtc_init(cfg);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M);
rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
#endif
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
@@ -176,8 +174,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
rtc_slow_freq = RTC_SLOW_FREQ_RTC;
}
}
} else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) {
rtc_clk_8m_enable(true, true);
}
rtc_clk_slow_freq_set(rtc_slow_freq);
@@ -211,7 +208,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk = 0;
uint32_t common_perip_clk1 = 0;
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
soc_reset_reason_t rst_reas[1];
rst_reas[0] = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
@@ -219,7 +217,7 @@ soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if (rst_reason >= RESET_REASON_CPU0_MWDT0 && rst_reason <= RESET_REASON_CPU0_RTC_WDT && rst_reason != RESET_REASON_SYS_BROWN_OUT) {
if ((rst_reas[0] >= RESET_REASON_CPU0_MWDT0 && rst_reas[0] <= RESET_REASON_CPU0_RTC_WDT && rst_reas[0] != RESET_REASON_SYS_BROWN_OUT)) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
} else {

1
components/esptool_py/Kconfig.projbuild
View File

@@ -56,7 +56,6 @@ menu "Serial flasher config"
config ESPTOOLPY_NO_STUB
bool "Disable download stub"
default "y" if IDF_TARGET_ESP32H2 # ESP32H2-TODO: IDF-3378
default "n"
help
The flasher tool sends a precompiled download stub first by default. That stub allows things

3
components/hal/esp32h2/brownout_hal.c
View File

@@ -17,12 +17,13 @@
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "i2c_pmu.h"
#include "regi2c_brownout.h"
void brownout_hal_config(const brownout_hal_config_t *cfg)
{
REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, cfg->threshold);
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_DREF_LVDET, cfg->threshold);
typeof(RTCCNTL.brown_out) brown_out_reg = {
.close_flash_ena = cfg->flash_power_down,
.pd_rf_ena = cfg->rf_power_down,

141
components/soc/esp32h2/i2c_bbpll.h
View File

@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -24,7 +16,8 @@
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
@@ -58,71 +51,39 @@
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_DIV 3
#define I2C_BBPLL_OC_DIV_MSB 5
#define I2C_BBPLL_OC_DIV_LSB 0
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_CHGP_DCUR 4
#define I2C_BBPLL_OC_CHGP_DCUR_MSB 2
#define I2C_BBPLL_OC_CHGP_DCUR_LSB 0
#define I2C_BBPLL_OC_BUFF_DCUR 4
#define I2C_BBPLL_OC_BUFF_DCUR_MSB 5
#define I2C_BBPLL_OC_BUFF_DCUR_LSB 3
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 6
#define I2C_BBPLL_OC_TSCHGP_LSB 6
#define I2C_BBPLL_OC_ENB_FCAL 4
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_OC_LPF_DR 5
#define I2C_BBPLL_OC_LPF_DR_MSB 1
#define I2C_BBPLL_OC_LPF_DR_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_OC_VCO_DCUR 5
#define I2C_BBPLL_OC_VCO_DCUR_MSB 3
#define I2C_BBPLL_OC_VCO_DCUR_LSB 2
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL 5
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL 5
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
@@ -146,38 +107,14 @@
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_BBADC_DELAY1 9
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 1
#define I2C_BBPLL_DTEST_LSB 0
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_ENT_PLL_MSB 2
#define I2C_BBPLL_ENT_PLL_LSB 2
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6
#define I2C_BBPLL_DIV_CPU 10
#define I2C_BBPLL_DIV_CPU_MSB 3
#define I2C_BBPLL_DIV_CPU_LSB 3

112
components/soc/esp32h2/i2c_bias.h Normal file
View File

@@ -0,0 +1,112 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_BIAS 0x6a
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P6 0
#define I2C_BIAS_DREG_1P6_MSB 3
#define I2C_BIAS_DREG_1P6_LSB 0
#define I2C_BIAS_DREG_0P8 0
#define I2C_BIAS_DREG_0P8_MSB 7
#define I2C_BIAS_DREG_0P8_LSB 4
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
#define I2C_BIAS_DREG_1P2 1
#define I2C_BIAS_DREG_1P2_MSB 7
#define I2C_BIAS_DREG_1P2_LSB 4
#define I2C_BIAS_ENT_CPREG 2
#define I2C_BIAS_ENT_CPREG_MSB 0
#define I2C_BIAS_ENT_CPREG_LSB 0
#define I2C_BIAS_ENT_CGM 2
#define I2C_BIAS_ENT_CGM_MSB 1
#define I2C_BIAS_ENT_CGM_LSB 1
#define I2C_BIAS_CGM_BIAS 2
#define I2C_BIAS_CGM_BIAS_MSB 3
#define I2C_BIAS_CGM_BIAS_LSB 2
#define I2C_BIAS_DREF_IGM 2
#define I2C_BIAS_DREF_IGM_MSB 4
#define I2C_BIAS_DREF_IGM_LSB 4
#define I2C_BIAS_RC_DVREF 2
#define I2C_BIAS_RC_DVREF_MSB 6
#define I2C_BIAS_RC_DVREF_LSB 5
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP 2
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_MSB 7
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_LSB 7
#define I2C_BIAS_RC_ENX 3
#define I2C_BIAS_RC_ENX_MSB 0
#define I2C_BIAS_RC_ENX_LSB 0
#define I2C_BIAS_RC_START 3
#define I2C_BIAS_RC_START_MSB 1
#define I2C_BIAS_RC_START_LSB 1
#define I2C_BIAS_RC_DCAP_EXT 3
#define I2C_BIAS_RC_DCAP_EXT_MSB 7
#define I2C_BIAS_RC_DCAP_EXT_LSB 2
#define I2C_BIAS_XPD_RC 4
#define I2C_BIAS_XPD_RC_MSB 0
#define I2C_BIAS_XPD_RC_LSB 0
#define I2C_BIAS_ENT_CONSTI 4
#define I2C_BIAS_ENT_CONSTI_MSB 1
#define I2C_BIAS_ENT_CONSTI_LSB 1
#define I2C_BIAS_XPD_ICX 4
#define I2C_BIAS_XPD_ICX_MSB 2
#define I2C_BIAS_XPD_ICX_LSB 2
#define I2C_BIAS_RC_RSTB 4
#define I2C_BIAS_RC_RSTB_MSB 3
#define I2C_BIAS_RC_RSTB_LSB 3
#define I2C_BIAS_RC_DIV 4
#define I2C_BIAS_RC_DIV_MSB 7
#define I2C_BIAS_RC_DIV_LSB 4
#define I2C_BIAS_RC_CAP 5
#define I2C_BIAS_RC_CAP_MSB 5
#define I2C_BIAS_RC_CAP_LSB 0
#define I2C_BIAS_RC_UD 5
#define I2C_BIAS_RC_UD_MSB 6
#define I2C_BIAS_RC_UD_LSB 6
#define I2C_BIAS_RC_LOCKB 5
#define I2C_BIAS_RC_LOCKB_MSB 7
#define I2C_BIAS_RC_LOCKB_LSB 7
#define I2C_BIAS_RC_CHG_COUNT 6
#define I2C_BIAS_RC_CHG_COUNT_MSB 4
#define I2C_BIAS_RC_CHG_COUNT_LSB 0
#define I2C_BIAS_XPD_CPREG 7
#define I2C_BIAS_XPD_CPREG_MSB 0
#define I2C_BIAS_XPD_CPREG_LSB 0
#define I2C_BIAS_XPD_CGM 7
#define I2C_BIAS_XPD_CGM_MSB 1
#define I2C_BIAS_XPD_CGM_LSB 1
#define I2C_BIAS_DTEST 7
#define I2C_BIAS_DTEST_MSB 3
#define I2C_BIAS_DTEST_LSB 2
#define I2C_BIAS_DRES12K 7
#define I2C_BIAS_DRES12K_MSB 7
#define I2C_BIAS_DRES12K_LSB 4

280
components/soc/esp32h2/i2c_pmu.h Normal file
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@@ -0,0 +1,280 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_PMU 0x6d
#define I2C_PMU_HOSTID 0
#define I2C_PMU_THRES_HIGH_7_0 0
#define I2C_PMU_THRES_HIGH_7_0_MSB 7
#define I2C_PMU_THRES_HIGH_7_0_LSB 0
#define I2C_PMU_THRES_LOW_7_0 1
#define I2C_PMU_THRES_LOW_7_0_MSB 7
#define I2C_PMU_THRES_LOW_7_0_LSB 0
#define I2C_PMU_THRES_HIGH_11_8 2
#define I2C_PMU_THRES_HIGH_11_8_MSB 3
#define I2C_PMU_THRES_HIGH_11_8_LSB 0
#define I2C_PMU_THRES_LOW_11_8 2
#define I2C_PMU_THRES_LOW_11_8_MSB 7
#define I2C_PMU_THRES_LOW_11_8_LSB 4
#define I2C_PMU_PVT_DELAY_INIT 3
#define I2C_PMU_PVT_DELAY_INIT_MSB 7
#define I2C_PMU_PVT_DELAY_INIT_LSB 0
#define I2C_PMU_PVT_DELAY_COUNT 4
#define I2C_PMU_PVT_DELAY_COUNT_MSB 5
#define I2C_PMU_PVT_DELAY_COUNT_LSB 0
#define I2C_PMU_OR_EN_CONT_CAL 4
#define I2C_PMU_OR_EN_CONT_CAL_MSB 7
#define I2C_PMU_OR_EN_CONT_CAL_LSB 7
#define I2C_PMU_I2C_RTC_DREG 5
#define I2C_PMU_I2C_RTC_DREG_MSB 4
#define I2C_PMU_I2C_RTC_DREG_LSB 0
#define I2C_PMU_I2C_DIG_DREG 6
#define I2C_PMU_I2C_DIG_DREG_MSB 4
#define I2C_PMU_I2C_DIG_DREG_LSB 0
#define I2C_PMU_I2C_RTC_DREG_SLP 7
#define I2C_PMU_I2C_RTC_DREG_SLP_MSB 3
#define I2C_PMU_I2C_RTC_DREG_SLP_LSB 0
#define I2C_PMU_I2C_DIG_DREG_SLP 7
#define I2C_PMU_I2C_DIG_DREG_SLP_MSB 7
#define I2C_PMU_I2C_DIG_DREG_SLP_LSB 4
#define I2C_PMU_EN_I2C_RTC_DREG 10
#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0
#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0
#define I2C_PMU_EN_I2C_DIG_DREG 10
#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1
#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1
#define I2C_PMU_EN_I2C_RTC_DREG_SLP 10
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2
#define I2C_PMU_EN_I2C_DIG_DREG_SLP 10
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3
#define I2C_PMU_ENX_RTC_DREG 11
#define I2C_PMU_ENX_RTC_DREG_MSB 0
#define I2C_PMU_ENX_RTC_DREG_LSB 0
#define I2C_PMU_ENX_DIG_DREG 11
#define I2C_PMU_ENX_DIG_DREG_MSB 1
#define I2C_PMU_ENX_DIG_DREG_LSB 1
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3 11
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_MSB 2
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_LSB 2
#define I2C_PMU_OR_XPD_RTC_REG 11
#define I2C_PMU_OR_XPD_RTC_REG_MSB 4
#define I2C_PMU_OR_XPD_RTC_REG_LSB 4
#define I2C_PMU_OR_XPD_DIG_REG 11
#define I2C_PMU_OR_XPD_DIG_REG_MSB 5
#define I2C_PMU_OR_XPD_DIG_REG_LSB 5
#define I2C_PMU_OR_PD_RTC_REG_SLP 11
#define I2C_PMU_OR_PD_RTC_REG_SLP_MSB 6
#define I2C_PMU_OR_PD_RTC_REG_SLP_LSB 6
#define I2C_PMU_OR_PD_DIG_REG_SLP 11
#define I2C_PMU_OR_PD_DIG_REG_SLP_MSB 7
#define I2C_PMU_OR_PD_DIG_REG_SLP_LSB 7
#define I2C_PMU_INT_DREG 12
#define I2C_PMU_INT_DREG_MSB 4
#define I2C_PMU_INT_DREG_LSB 0
#define I2C_PMU_O_UDF 12
#define I2C_PMU_O_UDF_MSB 5
#define I2C_PMU_O_UDF_LSB 5
#define I2C_PMU_O_OVF 12
#define I2C_PMU_O_OVF_MSB 6
#define I2C_PMU_O_OVF_LSB 6
#define I2C_PMU_O_UPDATE 12
#define I2C_PMU_O_UPDATE_MSB 7
#define I2C_PMU_O_UPDATE_LSB 7
#define I2C_PMU_PVT_COUNT_7_0 13
#define I2C_PMU_PVT_COUNT_7_0_MSB 7
#define I2C_PMU_PVT_COUNT_7_0_LSB 0
#define I2C_PMU_PVT_COUNT_11_8 14
#define I2C_PMU_PVT_COUNT_11_8_MSB 3
#define I2C_PMU_PVT_COUNT_11_8_LSB 0
#define I2C_PMU_IC_VGOOD_LVDET 14
#define I2C_PMU_IC_VGOOD_LVDET_MSB 4
#define I2C_PMU_IC_VGOOD_LVDET_LSB 4
#define I2C_PMU_IC_POWER_GOOD_DCDC 14
#define I2C_PMU_IC_POWER_GOOD_DCDC_MSB 5
#define I2C_PMU_IC_POWER_GOOD_DCDC_LSB 5
#define I2C_PMU_IC_VGOOD_DIGDET 14
#define I2C_PMU_IC_VGOOD_DIGDET_MSB 6
#define I2C_PMU_IC_VGOOD_DIGDET_LSB 6
#define I2C_PMU_OR_XPD_DCDC 15
#define I2C_PMU_OR_XPD_DCDC_MSB 0
#define I2C_PMU_OR_XPD_DCDC_LSB 0
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC 15
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_MSB 1
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_LSB 1
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC 15
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_MSB 2
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_LSB 2
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC 15
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_MSB 3
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_LSB 3
#define I2C_PMU_OR_ENX_REG_DCDC 15
#define I2C_PMU_OR_ENX_REG_DCDC_MSB 4
#define I2C_PMU_OR_ENX_REG_DCDC_LSB 4
#define I2C_PMU_OR_UNLOCK_DCDC 15
#define I2C_PMU_OR_UNLOCK_DCDC_MSB 5
#define I2C_PMU_OR_UNLOCK_DCDC_LSB 5
#define I2C_PMU_OR_FORCE_LOCK_DCDC 15
#define I2C_PMU_OR_FORCE_LOCK_DCDC_MSB 6
#define I2C_PMU_OR_FORCE_LOCK_DCDC_LSB 6
#define I2C_PMU_OR_ENB_SLOW_CLK 15
#define I2C_PMU_OR_ENB_SLOW_CLK_MSB 7
#define I2C_PMU_OR_ENB_SLOW_CLK_LSB 7
#define I2C_PMU_OC_SCK_DCAP 16
#define I2C_PMU_OC_SCK_DCAP_MSB 7
#define I2C_PMU_OC_SCK_DCAP_LSB 0
#define I2C_PMU_OC_XPD_LVDET 17
#define I2C_PMU_OC_XPD_LVDET_MSB 0
#define I2C_PMU_OC_XPD_LVDET_LSB 0
#define I2C_PMU_OC_MODE_LVDET 17
#define I2C_PMU_OC_MODE_LVDET_MSB 1
#define I2C_PMU_OC_MODE_LVDET_LSB 1
#define I2C_PMU_OR_XPD_TRX 17
#define I2C_PMU_OR_XPD_TRX_MSB 2
#define I2C_PMU_OR_XPD_TRX_LSB 2
#define I2C_PMU_OR_EN_RESET_CHIP 17
#define I2C_PMU_OR_EN_RESET_CHIP_MSB 3
#define I2C_PMU_OR_EN_RESET_CHIP_LSB 3
#define I2C_PMU_OC_DREF_LVDET 17
#define I2C_PMU_OC_DREF_LVDET_MSB 6
#define I2C_PMU_OC_DREF_LVDET_LSB 4
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE 17
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_MSB 7
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_LSB 7
#define I2C_PMU_DTEST 18
#define I2C_PMU_DTEST_MSB 1
#define I2C_PMU_DTEST_LSB 0
#define I2C_PMU_ENT_BIAS 18
#define I2C_PMU_ENT_BIAS_MSB 2
#define I2C_PMU_ENT_BIAS_LSB 2
#define I2C_PMU_ENT_VDD 18
#define I2C_PMU_ENT_VDD_MSB 5
#define I2C_PMU_ENT_VDD_LSB 3
#define I2C_PMU_EN_DMUX 18
#define I2C_PMU_EN_DMUX_MSB 6
#define I2C_PMU_EN_DMUX_LSB 6
#define I2C_PMU_WD_DISABLE 18
#define I2C_PMU_WD_DISABLE_MSB 7
#define I2C_PMU_WD_DISABLE_LSB 7
#define I2C_PMU_DTEST_DCDC 19
#define I2C_PMU_DTEST_DCDC_MSB 0
#define I2C_PMU_DTEST_DCDC_LSB 0
#define I2C_PMU_TESTEN_DCDC 19
#define I2C_PMU_TESTEN_DCDC_MSB 1
#define I2C_PMU_TESTEN_DCDC_LSB 1
#define I2C_PMU_ADD_DCDC 19
#define I2C_PMU_ADD_DCDC_MSB 6
#define I2C_PMU_ADD_DCDC_LSB 4
#define I2C_PMU_OR_POCPENB_DCDC 20
#define I2C_PMU_OR_POCPENB_DCDC_MSB 0
#define I2C_PMU_OR_POCPENB_DCDC_LSB 0
#define I2C_PMU_OR_SSTIME_DCDC 20
#define I2C_PMU_OR_SSTIME_DCDC_MSB 1
#define I2C_PMU_OR_SSTIME_DCDC_LSB 1
#define I2C_PMU_OR_CCM_DCDC 20
#define I2C_PMU_OR_CCM_DCDC_MSB 2
#define I2C_PMU_OR_CCM_DCDC_LSB 2
#define I2C_PMU_OR_VSET_LOW_DCDC 20
#define I2C_PMU_OR_VSET_LOW_DCDC_MSB 7
#define I2C_PMU_OR_VSET_LOW_DCDC_LSB 3
#define I2C_PMU_OR_FSW_DCDC 21
#define I2C_PMU_OR_FSW_DCDC_MSB 2
#define I2C_PMU_OR_FSW_DCDC_LSB 0
#define I2C_PMU_OR_DCMLEVEL_DCDC 21
#define I2C_PMU_OR_DCMLEVEL_DCDC_MSB 4
#define I2C_PMU_OR_DCMLEVEL_DCDC_LSB 3
#define I2C_PMU_OR_DCM2ENB_DCDC 21
#define I2C_PMU_OR_DCM2ENB_DCDC_MSB 5
#define I2C_PMU_OR_DCM2ENB_DCDC_LSB 5
#define I2C_PMU_OR_RAMP_DCDC 21
#define I2C_PMU_OR_RAMP_DCDC_MSB 6
#define I2C_PMU_OR_RAMP_DCDC_LSB 6
#define I2C_PMU_OR_RAMPLEVEL_DCDC 21
#define I2C_PMU_OR_RAMPLEVEL_DCDC_MSB 7
#define I2C_PMU_OR_RAMPLEVEL_DCDC_LSB 7
#define I2C_PMU_OR_VSET_HIGH_DCDC 22
#define I2C_PMU_OR_VSET_HIGH_DCDC_MSB 4
#define I2C_PMU_OR_VSET_HIGH_DCDC_LSB 0
#define I2C_PMU_OC_DEL_SSEND 22
#define I2C_PMU_OC_DEL_SSEND_MSB 7
#define I2C_PMU_OC_DEL_SSEND_LSB 5
#define I2C_PMU_OC_XPD_DIGDET 23
#define I2C_PMU_OC_XPD_DIGDET_MSB 0
#define I2C_PMU_OC_XPD_DIGDET_LSB 0
#define I2C_PMU_OC_MODE_DIGDET 23
#define I2C_PMU_OC_MODE_DIGDET_MSB 1
#define I2C_PMU_OC_MODE_DIGDET_LSB 1
#define I2C_PMU_OC_DREF_DIGDET 23
#define I2C_PMU_OC_DREF_DIGDET_MSB 6
#define I2C_PMU_OC_DREF_DIGDET_LSB 4

108
components/soc/esp32h2/i2c_ulp.h Normal file
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@@ -0,0 +1,108 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_XPD_REG_SLP 0
#define I2C_ULP_XPD_REG_SLP_MSB 1
#define I2C_ULP_XPD_REG_SLP_LSB 1
#define I2C_ULP_DBIAS_SLP 0
#define I2C_ULP_DBIAS_SLP_MSB 7
#define I2C_ULP_DBIAS_SLP_LSB 4
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_MSB 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_LSB 1
#define I2C_ULP_IR_FORCE_XPD_IPH 1
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 2
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 2
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF 1
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_MSB 3
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_LSB 3
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP 1
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_MSB 4
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_LSB 4
#define I2C_ULP_IR_ZOS_XPD 2
#define I2C_ULP_IR_ZOS_XPD_MSB 0
#define I2C_ULP_IR_ZOS_XPD_LSB 0
#define I2C_ULP_IR_ZOS_RSTB 2
#define I2C_ULP_IR_ZOS_RSTB_MSB 1
#define I2C_ULP_IR_ZOS_RSTB_LSB 1
#define I2C_ULP_IR_ZOS_RESTART 2
#define I2C_ULP_IR_ZOS_RESTART_MSB 2
#define I2C_ULP_IR_ZOS_RESTART_LSB 2
#define I2C_ULP_DTEST 3
#define I2C_ULP_DTEST_MSB 1
#define I2C_ULP_DTEST_LSB 0
#define I2C_ULP_ENT_BG 3
#define I2C_ULP_ENT_BG_MSB 2
#define I2C_ULP_ENT_BG_LSB 2
#define I2C_ULP_MODE_LVDET 3
#define I2C_ULP_MODE_LVDET_MSB 3
#define I2C_ULP_MODE_LVDET_LSB 3
#define I2C_ULP_DREF_LVDET 3
#define I2C_ULP_DREF_LVDET_MSB 6
#define I2C_ULP_DREF_LVDET_LSB 4
#define I2C_ULP_XPD_LVDET 3
#define I2C_ULP_XPD_LVDET_MSB 7
#define I2C_ULP_XPD_LVDET_LSB 7
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG 4
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_MSB 0
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_LSB 0
#define I2C_ULP_INT_XPD_XTAL_BUF 4
#define I2C_ULP_INT_XPD_XTAL_BUF_MSB 1
#define I2C_ULP_INT_XPD_XTAL_BUF_LSB 1
#define I2C_ULP_INT_XPD_RC_CK 4
#define I2C_ULP_INT_XPD_RC_CK_MSB 2
#define I2C_ULP_INT_XPD_RC_CK_LSB 2
#define I2C_ULP_XTAL_DPHASE 4
#define I2C_ULP_XTAL_DPHASE_MSB 3
#define I2C_ULP_XTAL_DPHASE_LSB 3
#define I2C_ULP_INT_XPD_XTAL_LIN_REG 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_MSB 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_LSB 4
#define I2C_ULP_XTAL_RESTART_DC_CAL 4
#define I2C_ULP_XTAL_RESTART_DC_CAL_MSB 5
#define I2C_ULP_XTAL_RESTART_DC_CAL_LSB 5
#define I2C_ULP_XTAL_DAC 5
#define I2C_ULP_XTAL_DAC_MSB 3
#define I2C_ULP_XTAL_DAC_LSB 0
#define I2C_ULP_XTAL_DBLEED 6
#define I2C_ULP_XTAL_DBLEED_MSB 4
#define I2C_ULP_XTAL_DBLEED_LSB 0
#define I2C_ULP_XTAL_CAL_DONE 6
#define I2C_ULP_XTAL_CAL_DONE_MSB 5
#define I2C_ULP_XTAL_CAL_DONE_LSB 5
#define I2C_ULP_ZOS_DONE 6
#define I2C_ULP_ZOS_DONE_MSB 6
#define I2C_ULP_ZOS_DONE_LSB 6

221
components/soc/esp32h2/include/soc/rtc.h
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@@ -54,12 +54,12 @@ extern "C" {
#define MHZ (1000000)
#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
#define RTC_SLOW_CLK_FREQ_150K 150000
#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256)
#define RTC_SLOW_CLK_FREQ_150K 130000
#define RTC_SLOW_CLK_FREQ_32K 32768
#define RTC_SLOW_CLK_FREQ_RC32 32768
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
@@ -68,14 +68,27 @@ extern "C" {
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_1V00 0
#define RTC_CNTL_DBIAS_1V05 4
#define RTC_CNTL_DBIAS_1V10 5
#define RTC_CNTL_DBIAS_1V15 6
#define RTC_CNTL_DBIAS_1V20 7
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_1V00 0
#define RTC_CNTL_DBIAS_1V05 4
#define RTC_CNTL_DBIAS_1V10 5
#define RTC_CNTL_DBIAS_1V15 6
#define RTC_CNTL_DBIAS_1V20 7
#define RTC_CNTL_DBIAS_DEFAULT 8
/* The value of 1V00 can be adjusted between 0~3*/
/* dcdc mode
*/
#define RTC_CNTL_DCDC_TRX_MODE 0b100
#define RTC_CNTL_DCDC_LSLP_MODE 0b110
#define RTC_CNTL_DCDC_DSLP_MODE 0b101
#define RTC_CNTL_DCDC_FREQ_DEFAULT 3
#define DCDC_SLP_TRX_MODE 0
#define DCDC_SLP_LSLP_MODE 1
#define DCDC_SLP_DSLP_MODE 2
#define RTC_CNTL_DIG_DBIAS_0V85 0
#define RTC_CNTL_DIG_DBIAS_0V90 1
#define RTC_CNTL_DIG_DBIAS_0V95 2
@@ -105,8 +118,10 @@ extern "C" {
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 600
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 707
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
@@ -138,28 +153,14 @@ typedef enum {
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
/**
* @brief CPU frequency values
*/
typedef enum {
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
RTC_CPU_320M_80M = 5, //!< for test
RTC_CPU_320M_160M = 6, //!< for test
RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset
} rtc_cpu_freq_t;
/**
* @brief CPU clock source
*/
typedef enum {
RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
RTC_CPU_FREQ_SRC_APLL //!< APLL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (96M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 18M RTC oscillator
RTC_CPU_FREQ_SRC_XTAL_D2 //!< XTAL/2
} rtc_cpu_freq_src_t;
/**
@@ -178,7 +179,7 @@ typedef struct rtc_cpu_freq_config_s {
typedef enum {
RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_SLOW_FREQ_RC32K = 2, //!< Internal 32 KHz RC oscillator
} rtc_slow_freq_t;
/**
@@ -202,7 +203,7 @@ typedef enum {
*/
typedef enum {
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_RC32K = 1, //!< Internal 32 kHz RC oscillator
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
} rtc_cal_sel_t;
@@ -217,21 +218,23 @@ typedef struct {
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h2 (default 0: xtal_32M)
} rtc_clk_config_t;
/**
* Default initializer for rtc_clk_config_t
*/
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = RTC_XTAL_FREQ_40M, \
.cpu_freq_mhz = 80, \
.xtal_freq = RTC_XTAL_FREQ_32M, \
.cpu_freq_mhz = 32, \
.fast_freq = RTC_FAST_FREQ_8M, \
.slow_freq = RTC_SLOW_FREQ_RTC, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.clk_rtc_clk_div = 1, \
.clk_8m_clk_div = 1, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
.root_clk_slt = 0, \
}
typedef struct {
@@ -241,6 +244,7 @@ typedef struct {
uint32_t dbuf: 1;
} x32k_config_t;
#define X32K_CONFIG_DEFAULT() { \
.dac = 3, \
.dres = 3, \
@@ -248,6 +252,14 @@ typedef struct {
.dbuf = 1, \
}
typedef struct {
uint32_t dfreq : 10;
} rc32k_config_t;
#define RC32K_CONFIG_DEFAULT() {\
.dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT,\
}
typedef struct {
uint16_t wifi_powerup_cycles : 7;
uint16_t wifi_wait_cycles : 9;
@@ -499,6 +511,10 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
*/
uint32_t rtc_clk_apb_freq_get(void);
void rtc_clk_cpu_freq_set(uint32_t source, uint32_t div);
uint32_t rtc_clk_ahb_freq_get(void);
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/**
@@ -633,7 +649,7 @@ typedef struct {
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t dig_ret_pd_en : 1; //!< power down dig_ret
uint32_t bt_pd_en : 1; //!< power down BT
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
@@ -662,7 +678,7 @@ typedef struct {
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, \
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
@@ -683,7 +699,7 @@ typedef struct {
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI
#define RTC_SLEEP_PD_DIG_RET BIT(6) //!< Power down WIFI
#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
@@ -791,11 +807,11 @@ typedef struct {
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
uint32_t xtal_fpu : 1;
uint32_t bbpll_fpu : 1;
uint32_t cpu_waiti_clk_gate : 1;
uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise.
uint32_t pmu_ctl : 1;
} rtc_config_t;
/**
@@ -810,17 +826,93 @@ typedef struct {
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
.clkctl_init = 1, \
.pwrctl_init = 1, \
.rtc_dboost_fpd = 1, \
.xtal_fpu = 0, \
.bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1, \
.cali_ocode = 0\
.cali_ocode = 0, \
.pmu_ctl = 1\
}
typedef struct {
/* data */
uint32_t or_en_cont_cal : 1; //!< default:0 rtc_init:0 pvt can be enable by either this register or digital -- if_en_cont_cal
uint32_t enx_rtc_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure rtc regulator voltage level instead of pvt result -- int_dreg
uint32_t enx_dig_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure dig regulator voltage level instead of pvt result -- int_dreg
uint32_t en_i2c_rtc_dreg : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg; 0: if_rtc_dreg
uint32_t en_i2c_dig_dreg : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg; 0: if_dig_dreg
uint32_t en_i2c_rtc_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg_slp; 0: if_rtc_dreg_slp
uint32_t en_i2c_dig_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg_slp; 0: if_dig_dreg_slp
uint32_t or_xpd_rtc_slave_3p3 : 1; //!< default:1 rtc_init:0 to turn off rtc slave, which is only required before DCDC running
uint32_t or_xpd_rtc_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_rtc_reg
uint32_t or_xpd_dig_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dig_reg
uint32_t or_pd_rtc_reg_slp : 1; //!< default:0 rtc_init:1 configure this i2c to control rtc_sleep_regulator on off, no coressponding digital control signal
uint32_t or_pd_dig_reg_slp : 1; //!< default:0 rtc_init:0 default value 0 puts dig_sleep_regulator controlled by digital -- if_xpd_dig_reg_slp
uint32_t or_xpd_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dcdc
uint32_t or_disalbe_deep_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_deep_sleep_dcdc
uint32_t or_disalbe_light_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_light_sleep_dcdc
uint32_t or_enalbe_trx_mode_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_trx_mode_dcdc
uint32_t or_enx_reg_dcdc : 1; //!< default:0 rtc_init:1 handover dcdc configuration registers to digital control signals, including popenb, sstime, ccm, vset, fsw, dcmlevel, dcm2enb, ramp, ramplevel
uint32_t or_unlock_dcdc : 1; //!< default:0 rtc_init:0 not used in this version of silicon, can be unleashed if metal change if_vgood_lock_dcdc signal to high
uint32_t or_force_lock_dcdc : 1; //!< default:0 rtc_init:0 dcdc will be locked and shut-off if this register sets to 1
uint32_t or_enb_slow_clk : 1; //!< default:0 rtc_init:1 handover slow clock control to digital -- if_enb_slow_clk
uint32_t or_xpd_trx : 1; //!< default:1 rtc_init:0 handover trx control to digital -- if_xpd_trx
uint32_t or_en_reset_chip : 1; //!< default:0 rtc_init:1 handover reset chip control to digital -- if_reset_chip
uint32_t or_force_xpd_reg_slave : 1; //!< default:0 rtc_init:1 set this reg to 1 after DCDC ready, to have rtc & dig slave control independent of DCDC status
} pmu_config_t;
#define PMU_CONFIG_DEFAULT() {\
.or_en_cont_cal = 0, \
.enx_rtc_dreg = 1, \
.enx_dig_dreg = 1, \
.en_i2c_rtc_dreg = 0, \
.en_i2c_dig_dreg = 0, \
.en_i2c_rtc_dreg_slp = 0, \
.en_i2c_dig_dreg_slp = 0, \
.or_xpd_rtc_slave_3p3 = 0, \
.or_xpd_rtc_reg = 0, \
.or_xpd_dig_reg = 0, \
.or_pd_rtc_reg_slp = 0, \
.or_pd_dig_reg_slp = 0, \
.or_xpd_dcdc = 0, \
.or_disalbe_deep_sleep_dcdc = 0, \
.or_disalbe_light_sleep_dcdc = 0, \
.or_enalbe_trx_mode_dcdc = 0, \
.or_enx_reg_dcdc = 1, \
.or_unlock_dcdc = 0, \
.or_force_lock_dcdc = 0, \
.or_xpd_trx = 0, \
.or_en_reset_chip = 1, \
.or_force_xpd_reg_slave = 1\
}
typedef struct {
uint32_t swt_idle: 1; //!< If 1, swt_idle is sleep mode ; if 0, swt_idle is active mode
uint32_t swt_monitor: 1; //!< If 1, swt_monitor is sleep mode ; if 0, swt_monitor is active mode
uint32_t swt_slp: 1; //!< If 1, swt_slp is sleep mode ; if 0, swt_slp is active mode
} dbias_swt_cfg_t;
#define DBIAS_SWITCH_CONFIG_DEFAULT(){\
.swt_idle = 0, \
.swt_monitor = 1, \
.swt_slp = 1\
}
typedef struct {
/* data */
uint32_t dig_regul0_en: 1; //!< If 1, dig_regulator0 is ctl by fsm; if 0, dig_regulator0 force pd.
uint32_t dig_regul1_en: 1; //!< If 1, dig_regulator1 is ctl by fsm; if 0, dig_regulator1 force pd.
uint32_t rtc_regul0_en: 1; //!< If 1, rtc_regulator0 is ctl by fsm; if 0, rtc_regulator0 force pd.
} regulator_cfg_t;
#define REGULATOR_SET_DEFAULT(){\
.dig_regul0_en = 1, \
.dig_regul1_en = 1, \
.rtc_regul0_en = 1, \
}
/**
* Initialize RTC clock and power control related functions
* @param cfg configuration options as rtc_config_t
*/
* Initialize RTC clock and power control related functions
* @param cfg configuration options as rtc_config_t
*/
void rtc_init(rtc_config_t cfg);
/**
@@ -853,6 +945,47 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
*/
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
/* Select clock root source for esp32h2. return source clk freq_mhz
*/
uint32_t root_clk_slt(uint32_t source);
uint32_t root_clk_get(void);
/**
* Regulator config
*/
typedef struct {
uint32_t dig_source : 1;
uint32_t dig_active_dbias : 5;
uint32_t dig_slp_dbias : 5;
uint32_t rtc_source : 1;
uint32_t rtc_active_dbias : 5;
uint32_t rtc_slp_dbias : 5;
} regulator_config_t;
#define REGULATOR0_CONFIG_DEFAULT() {\
.dig_source = 0, \
.dig_active_dbias = 20, \
.dig_slp_dbias = 8, \
.rtc_source = 0, \
.rtc_active_dbias = 20, \
.rtc_slp_dbias = 8 \
}
#define REGULATOR1_CONFIG_DEFAULT() {\
.dig_source = 1, \
.dig_active_dbias = 15, \
.dig_slp_dbias = 8, \
.rtc_source = 1, \
.rtc_active_dbias = 15, \
.rtc_slp_dbias = 8 \
}
/**
* gpio hangup
*/
void rtc_gpio_hangup(uint32_t gpio_no);
#ifdef __cplusplus
}
#endif

4
components/soc/esp32h2/include/soc/soc.h
View File

@@ -228,10 +228,10 @@
#if CONFIG_IDF_ENV_FPGA
#define APB_CLK_FREQ ( 32*1000000 )
#else
#define APB_CLK_FREQ ( 80*1000000 )
#define APB_CLK_FREQ ( 96*1000000 )
#endif
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define RTC_CLK_FREQ (17.5*1000000)
#define XTAL_CLK_FREQ (32*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ

10
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -245,9 +245,6 @@
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
@@ -255,16 +252,9 @@
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_WIFI_PD (1)
#define SOC_PM_SUPPORT_BT_PD (1)