forked from espressif/esp-idf
feat(driver_spi): c5 eco2 support master rx timing sample phase
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -698,13 +698,14 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active)
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*----------------------------------------------------------------------------*/
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/**
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* Set the standard clock mode for master.
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* This config take effect only when SPI_CLK (pre-div before periph) div >=2
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*
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* @param hw Beginning address of the peripheral registers.
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* @param enable_std True for std timing, False for half cycle delay sampling.
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*/
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static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point)
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{
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//This is not supported
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hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1);
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}
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/**
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@@ -712,7 +713,7 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_
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*/
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static inline bool spi_ll_master_is_rx_std_sample_supported(void)
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{
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return false;
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return true;
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}
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/**
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@@ -21,7 +21,6 @@
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
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#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
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#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C5
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#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5
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#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5
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#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
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@@ -23,7 +23,6 @@ api-reference/storage/fatfsgen.rst
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api-reference/storage/index.rst
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api-reference/storage/nvs_partition_parse.rst
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api-reference/peripherals/twai.rst
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api-reference/peripherals/spi_features.rst
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api-reference/peripherals/touch_pad.rst
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api-reference/peripherals/sd_pullup_requirements.rst
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api-reference/peripherals/index.rst
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