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feat(driver_spi): c5 eco2 support master rx timing sample phase

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wanckl
2025-04-11 15:08:41 +08:00
parent 16d79103aa
commit fb2f5cc1da
5 changed files with 593 additions and 599 deletions
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7
components/hal/esp32c5/include/hal/spi_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -698,13 +698,14 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active)
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
/** /**
* Set the standard clock mode for master. * Set the standard clock mode for master.
* This config take effect only when SPI_CLK (pre-div before periph) div >=2
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
* @param enable_std True for std timing, False for half cycle delay sampling. * @param enable_std True for std timing, False for half cycle delay sampling.
*/ */
static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point) static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point)
{ {
//This is not supported hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1);
} }
/** /**
@@ -712,7 +713,7 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_
*/ */
static inline bool spi_ll_master_is_rx_std_sample_supported(void) static inline bool spi_ll_master_is_rx_std_sample_supported(void)
{ {
return false; return true;
} }
/** /**

1
components/soc/esp32c5/include/soc/soc.h
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@@ -21,7 +21,6 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5 #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C5
#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5 #define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 #define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1

592
components/soc/esp32c5/register/soc/spi_reg.h
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591
components/soc/esp32c5/register/soc/spi_struct.h
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1
docs/docs_not_updated/esp32c5.txt
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@@ -23,7 +23,6 @@ api-reference/storage/fatfsgen.rst
api-reference/storage/index.rst api-reference/storage/index.rst
api-reference/storage/nvs_partition_parse.rst api-reference/storage/nvs_partition_parse.rst
api-reference/peripherals/twai.rst api-reference/peripherals/twai.rst
api-reference/peripherals/spi_features.rst
api-reference/peripherals/touch_pad.rst api-reference/peripherals/touch_pad.rst
api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/index.rst api-reference/peripherals/index.rst