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Merge branch 'feature/esp32c61_i2s_support' into 'master'

Browse Source 
feat(i2s): support i2s on esp32c61

Closes IDF-9312 and IDF-9313

See merge request espressif/esp-idf!32905
This commit is contained in:
Gao Xu
2024-10-25 11:18:44 +08:00
parent c27db10042 8ab0cdde60
commit ffcf40cee3
36 changed files with 1396 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

1
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/pytest_legacy_i2s.py
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@@ -12,6 +12,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.esp32c61
@pytest.mark.generic
@pytest.mark.parametrize(
'config',

4
components/esp_driver_i2s/test_apps/.build-test-rules.yml
View File

@@ -11,6 +11,10 @@ components/esp_driver_i2s/test_apps/i2s_multi_dev:
disable:
- if: SOC_I2S_SUPPORTED != 1
- if: SOC_I2S_HW_VERSION_2 != 1
disable_test:
- if: IDF_TARGET in ["esp32c61"] # TODO: [ESP32C61] IDF-11442
temporary: true
reason: lack of runners
depends_components:
- esp_driver_i2s

4
components/esp_driver_i2s/test_apps/i2s/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

1
components/esp_driver_i2s/test_apps/i2s/pytest_i2s.py
View File

@@ -12,6 +12,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32s3
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.esp32c61
@pytest.mark.generic
@pytest.mark.parametrize(
'config',

4
components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md
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@@ -1,3 +1,3 @@
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |

3
components/esp_hw_support/port/esp32c61/esp_clk_tree.c
View File

@@ -33,6 +33,9 @@ uint32_t *freq_value)
case SOC_MOD_CLK_PLL_F80M:
clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_PLL_F120M:
clk_src_freq = CLK_LL_PLL_120M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_PLL_F160M:
clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
break;

2
components/hal/esp32c3/include/hal/i2s_ll.h
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@@ -366,7 +366,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/**
* @brief Configure I2S RX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
* @note mclk on ESP32C3 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients

4
components/hal/esp32c5/include/hal/i2s_ll.h
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@@ -398,7 +398,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/**
* @brief Configure I2S RX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
* @note mclk on ESP32C5 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients
@@ -945,7 +945,7 @@ static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
*/
static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_enable)
{
// Due to the lack of `PDM to PCM` module on ESP32-H2, PDM RX is not available
// Due to the lack of `PDM to PCM` module on ESP32-C5, PDM RX is not available
HAL_ASSERT(!pdm_enable);
hw->rx_conf.rx_pdm_en = 0;
hw->rx_conf.rx_tdm_en = 1;

2
components/hal/esp32c6/include/hal/i2s_ll.h
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@@ -388,7 +388,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/**
* @brief Configure I2S RX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
* @note mclk on ESP32C6 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients

1241
components/hal/esp32c61/include/hal/i2s_ll.h Normal file
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File diff suppressed because it is too large Load Diff

2
components/hal/esp32h2/include/hal/i2s_ll.h
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@@ -395,7 +395,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/**
* @brief Configure I2S RX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
* @note mclk on ESP32H2 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients

2
components/hal/esp32p4/include/hal/i2s_ll.h
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@@ -652,7 +652,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/**
* @brief Configure I2S RX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
* @note mclk on ESP32P4 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients

2
components/hal/esp32s2/include/hal/i2s_ll.h
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@@ -346,7 +346,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/**
* @brief Configure I2S RX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
* @note mclk on ESP32S2 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients

2
components/hal/esp32s3/include/hal/i2s_ll.h
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@@ -372,7 +372,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/**
* @brief Configure I2S RX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
* @note mclk on ESP32S3 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients

34
components/soc/esp32c61/i2s_periph.c Normal file
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@@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
.m_tx_bck_sig = I2SO_BCK_OUT_IDX,
.m_rx_bck_sig = I2SI_BCK_OUT_IDX,
.m_tx_ws_sig = I2SO_WS_OUT_IDX,
.m_rx_ws_sig = I2SI_WS_OUT_IDX,
.s_tx_bck_sig = I2SO_BCK_IN_IDX,
.s_rx_bck_sig = I2SI_BCK_IN_IDX,
.s_tx_ws_sig = I2SO_WS_IN_IDX,
.s_rx_ws_sig = I2SI_WS_IN_IDX,
.data_out_sigs[0] = I2SO_SD_OUT_IDX,
.data_out_sigs[1] = I2SO_SD1_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_I2S0_INTR_SOURCE,
}
};

52
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@@ -55,6 +55,10 @@ config SOC_EFUSE_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_GPSPI_SUPPORTED
bool
default y
@@ -443,6 +447,54 @@ config SOC_I2C_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_TX_SYNC_CNT
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PLL_F120M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_PDM_MAX_TX_LINES
int
default 2
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y

4
components/soc/esp32c61/include/soc/clk_tree_defs.h
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@@ -120,6 +120,7 @@ typedef enum {
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F120M, /*!< PLL_F120M_CLK is derived from PLL (clock gating + fixed divider of 4), it has a fixed frequency of 120MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_SPLL, /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
@@ -213,13 +214,14 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
#define SOC_I2S_CLKS {I2S_CLK_SRC_PLL_120M, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
/**
* @brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_120M = SOC_MOD_CLK_PLL_F120M, /*!< Select PLL_F120M as the source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */

2
components/soc/esp32c61/include/soc/interrupts.h
View File

@@ -53,7 +53,7 @@ typedef enum {
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE,
ETS_I2S0_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
ETS_UART1_INTR_SOURCE,
ETS_UART2_INTR_SOURCE,

23
components/soc/esp32c61/include/soc/soc_caps.h
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@@ -33,7 +33,7 @@
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1
// \#define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313
#define SOC_I2S_SUPPORTED 1
#define SOC_GPSPI_SUPPORTED 1
#define SOC_I2C_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1
@@ -232,15 +232,18 @@
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
// /*-------------------------- I2S CAPS ----------------------------------------*/
// #define SOC_I2S_NUM (1U)
// #define SOC_I2S_HW_VERSION_2 (1)
// #define SOC_I2S_SUPPORTS_XTAL (1)
// #define SOC_I2S_SUPPORTS_PLL_F160M (1)
// #define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PLL_F120M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_SUPPORTS_TDM (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)

2
components/soc/esp32c61/ld/esp32c61.peripherals.ld
View File

@@ -15,7 +15,7 @@ PROVIDE ( LEDC_GAMMA_RAM = 0x60007400 );
PROVIDE ( TIMERG0 = 0x60008000 );
PROVIDE ( TIMERG1 = 0x60009000 );
PROVIDE ( SYSTIMER = 0x6000A000 );
PROVIDE ( I2S = 0x6000C000 );
PROVIDE ( I2S0 = 0x6000C000 );
PROVIDE ( ADC = 0x6000E000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
PROVIDE ( INTMTX = 0x60010000 );

16
components/soc/esp32c61/register/soc/i2s_reg.h
View File

@@ -694,22 +694,6 @@ extern "C" {
#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U
#define I2S_RX_PDM_HP_BYPASS_S 25
/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
*/
#define I2S_RX_IIR_HP_MULT12_5 0x00000007U
#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U
#define I2S_RX_IIR_HP_MULT12_5_S 26
/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
*/
#define I2S_RX_IIR_HP_MULT12_0 0x00000007U
#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U
#define I2S_RX_IIR_HP_MULT12_0_S 29
/** I2S_RX_TDM_CTRL_REG register
* I2S TX TDM mode control register

19
components/soc/esp32c61/register/soc/i2s_struct.h
View File

@@ -263,16 +263,7 @@ typedef union {
* I2S PDM RX bypass hp filter or not.
*/
uint32_t rx_pdm_hp_bypass:1;
/** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
*/
uint32_t rx_iir_hp_mult12_5:3;
/** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
*/
uint32_t rx_iir_hp_mult12_0:3;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_rx_pdm2pcm_conf_reg_t;
@@ -859,7 +850,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */
@@ -989,8 +980,8 @@ typedef struct {
volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
volatile i2s_rxeof_num_reg_t rx_eof_num;
volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf;
volatile i2s_fifo_cnt_reg_t fifo_cnt;
@@ -999,7 +990,7 @@ typedef struct {
volatile i2s_date_reg_t date;
} i2s_dev_t;
extern i2s_dev_t I2S;
extern i2s_dev_t I2S0;
#ifndef __cplusplus
_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");

1
docs/docs_not_updated/esp32c61.txt
View File

@@ -47,7 +47,6 @@ api-reference/peripherals/usb_host/usb_host_notes_design.rst
api-reference/peripherals/usb_device.rst
api-reference/peripherals/sdspi_host.rst
api-reference/peripherals/dac.rst
api-reference/peripherals/i2s.rst
api-reference/peripherals/touch_element.rst
api-reference/peripherals/ppa.rst
api-reference/peripherals/ana_cmpr.rst

4
docs/en/api-reference/peripherals/i2s.rst
View File

@@ -78,6 +78,10 @@ Clock Source
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`: 160 MHz PLL clock.
.. only:: SOC_I2S_SUPPORTS_PLL_F120M
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_120M`: 120 MHz PLL clock.
.. only:: SOC_I2S_SUPPORTS_PLL_F96M
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`: 96 MHz PLL clock.

4
docs/zh_CN/api-reference/peripherals/i2s.rst
View File

@@ -78,6 +78,10 @@ I2S 时钟
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`：160 MHz PLL 时钟。
.. only:: SOC_I2S_SUPPORTS_PLL_F120M
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_120M`：120 MHz PLL 时钟。
.. only:: SOC_I2S_SUPPORTS_PLL_F96M
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`：96 MHz PLL 时钟。

2
examples/peripherals/.build-test-rules.yml
View File

@@ -102,7 +102,7 @@ examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm:
- if: SOC_I2S_SUPPORTS_TDM != 1 or (SOC_I2C_SUPPORTED != 1 or SOC_GPSPI_SUPPORTED != 1)
reason: rely on I2S TDM mode to receive audio, I2C to config es7210 and SPI to save audio to SD card
disable_test:
- if: IDF_TARGET == "esp32p4"
- if: IDF_TARGET in ["esp32p4", "esp32c61"]
temporary: true
reason: lack of runners
depends_components:

4
examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# I2S Basic PDM Mode Example

1
examples/peripherals/i2s/i2s_basic/i2s_pdm/pytest_i2s_pdm.py
View File

@@ -11,6 +11,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.esp32c61
@pytest.mark.generic
@pytest.mark.parametrize(
'config',

4
examples/peripherals/i2s/i2s_basic/i2s_std/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# I2S Basic Standard Mode Example

1
examples/peripherals/i2s/i2s_basic/i2s_std/pytest_i2s_std.py
View File

@@ -12,6 +12,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.esp32c61
@pytest.mark.generic
def test_i2s_basic_example(dut: Dut) -> None:

4
examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# I2S Basic TDM Mode Example

1
examples/peripherals/i2s/i2s_basic/i2s_tdm/pytest_i2s_tdm.py
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@@ -10,6 +10,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.esp32c61
@pytest.mark.generic
def test_i2s_tdm_example(dut: Dut) -> None:

4
examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# I2S TDM Example -- ES7210 4-Ch ADC Codec

4
examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
# I2S ES8311 Example

1
examples/peripherals/i2s/i2s_codec/i2s_es8311/pytest_i2s_es8311.py
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@@ -12,6 +12,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.esp32c61
@pytest.mark.generic
def test_i2s_es8311_example_generic(dut: Dut) -> None:
dut.expect('i2s es8311 codec example start')