Merge branch 'fix/prov_ble_read_offset_v4.1' into 'release/v4.1'

BLE provisioning: Add check for valid ble read offset (v4.1)

See merge request espressif/esp-idf!9745

.flake8

@@ -141,17 +141,15 @@ exclude =
     __pycache__,
     # submodules
         components/bootloader/subproject/components/micro-ecc/micro-ecc,
-        components/bt/host/nimble/nimble,
         components/esptool_py/esptool,
         components/expat/expat,
         components/json/cJSON,
         components/libsodium/libsodium,
         components/mbedtls/mbedtls,
         components/nghttp/nghttp2,
-        components/tinyusb,
+        components/bt/host/nimble/nimble,
         components/unity/unity,
         examples/build_system/cmake/import_lib/main/lib/tinyxml2,
-        examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib,
     # other third-party libraries
         tools/kconfig_new/kconfiglib.py,
         tools/kconfig_new/menuconfig.py,
@@ -164,4 +162,4 @@ exclude =
         components/wifi_provisioning/python/wifi_config_pb2.py,
         components/wifi_provisioning/python/wifi_constants_pb2.py,
         components/esp_local_ctrl/python/esp_local_ctrl_pb2.py,
-        examples/provisioning/legacy/custom_config/components/custom_provisioning/python/custom_config_pb2.py,
+        examples/provisioning/custom_config/components/custom_provisioning/python/custom_config_pb2.py,

.github/workflows/python_lint.yml

@@ -13,7 +13,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        python-version: [2.7, 3.5, 3.6, 3.7, 3.8]
+        python-version: [2.7, 3.5, 3.6, 3.7]
 
     steps:
       - name: Checkout
@@ -24,10 +24,9 @@ jobs:
           python-version: ${{ matrix.python-version }}
       - name: Install dependencies
         run: |
-          export IDF_PATH=${GITHUB_WORKSPACE}
           pip install --upgrade pip
           pip install -r requirements.txt
       - name: Lint with flake8
         run: |
           pip install flake8
-          flake8 . --config=.flake8 --benchmark
+          flake8 . --config=.flake8

.gitignore

@@ -27,7 +27,13 @@ examples/**/sdkconfig.old
 examples/**/build
 
 # Doc build artifacts
-docs/_build/
+docs/*/_build/
+docs/*/doxygen-warning-log.txt
+docs/*/sphinx-warning-log.txt
+docs/*/sphinx-warning-log-sanitized.txt
+docs/*/xml/
+docs/*/xml_in/
+docs/*/man/
 docs/doxygen_sqlite3.db
 
 # Downloaded font files
@@ -40,15 +46,6 @@ tools/unit-test-app/sdkconfig.old
 tools/unit-test-app/build
 tools/unit-test-app/builds
 tools/unit-test-app/output
-tools/unit-test-app/test_configs
-
-# Unit Test CMake compile log folder
-log_ut_cmake
-
-# test application build files
-tools/test_apps/**/build
-tools/test_apps/**/sdkconfig
-tools/test_apps/**/sdkconfig.old
 
 # IDF monitor test
 tools/test_idf_monitor/outputs
@@ -82,4 +79,4 @@ flake8_output.txt
 build
 
 # lock files for examples and components
-dependencies.lock
+dependencies.lock

.gitlab-ci.yml

@@ -6,7 +6,7 @@ stages:
   - target_test
   - post_check
   - deploy
-  - post_deploy
+  - post_check
 
 variables:
 # System environment
@@ -33,6 +33,8 @@ variables:
   # tell build system do not check submodule update as we download archive instead of clone
   IDF_SKIP_CHECK_SUBMODULES: 1
 
+  UNIT_TEST_BUILD_SYSTEM: cmake
+  EXAMPLE_TEST_BUILD_SYSTEM: cmake
   IDF_PATH: "$CI_PROJECT_DIR"
   BATCH_BUILD: "1"
   V: "0"
@@ -44,8 +46,6 @@ variables:
 # target test config file, used by assign test job
   CI_TARGET_TEST_CONFIG_FILE: "$CI_PROJECT_DIR/tools/ci/config/target-test.yml"
 
-  # Versioned esp-idf-doc env image to use for all document building jobs
-  ESP_IDF_DOC_ENV_IMAGE: "$CI_DOCKER_REGISTRY/esp-idf-doc-env:v4"
 
 
 # before each job, we need to check if this job is filtered by bot stage/job filter
@@ -53,9 +53,6 @@ variables:
   python $APPLY_BOT_FILTER_SCRIPT || exit 0
 
 .setup_tools_unless_target_test: &setup_tools_unless_target_test |
-  if [[ -n "$IDF_DONT_USE_MIRRORS" ]]; then
-  export IDF_MIRROR_PREFIX_MAP=
-  fi
   if [[ "$SETUP_TOOLS" == "1" || "$CI_JOB_STAGE" != "target_test" ]]; then
   tools/idf_tools.py --non-interactive install && eval "$(tools/idf_tools.py --non-interactive export)" || exit 1
   fi
@@ -77,6 +74,7 @@ before_script:
   # Set some options and environment for CI
   - source tools/ci/configure_ci_environment.sh
   - *setup_tools_unless_target_test
+
   - *fetch_submodules
 
 # used for check scripts which we want to run unconditionally
@@ -113,14 +111,7 @@ before_script:
   tags:
     - host_test
   dependencies: []
-  extends: .before_script_lesser
-
-.python_lint_template:
-  stage: pre_check
-  image: $CI_DOCKER_REGISTRY/esp32-ci-env$BOT_DOCKER_IMAGE_TAG
-  tags:
-    - host_test
-  dependencies: []
+  extends: .before_script_lesser_nofilter
 
 .macos_build_template:
   stage: build
@@ -149,4 +140,3 @@ include:
   - '/tools/ci/config/target-test.yml'
   - '/tools/ci/config/post_check.yml'
   - '/tools/ci/config/deploy.yml'
-  - '/tools/ci/config/post_deploy.yml'

.gitmodules

@@ -79,10 +79,3 @@
 	path = components/esp_wifi/lib
 	url = ../../espressif/esp32-wifi-lib.git
 
-[submodule "components/tinyusb/tinyusb"]
-	path = components/tinyusb/tinyusb
-	url = ../../espressif/tinyusb.git
-
-[submodule "examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib"]
-	path = examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib
-	url = ../../espressif/esp-cryptoauthlib.git

CONTRIBUTING.rst

@@ -6,7 +6,7 @@ We welcome contributions to the esp-idf project!
 How to Contribute
 -----------------
 
-Contributions to esp-idf - fixing bugs, adding features, adding documentation - are welcome. We accept contributions via `Github Pull Requests <https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/about-pull-requests>`_.
+Contributions to esp-idf - fixing bugs, adding features, adding documentation - are welcome. We accept contributions via `Github Pull Requests <https://help.github.com/articles/about-pull-requests/>`_.
 
 Before Contributing
 -------------------
@@ -27,7 +27,7 @@ Before sending us a Pull Request, please consider this list of points:
 
 * Example contributions are also welcome. Please check the :doc:`creating-examples` guide for these.
 
-* If the contribution contains multiple commits, are they grouped together into logical changes (one major change per pull request)? Are any commits with names like "fixed typo" `squashed into previous commits <https://eli.thegreenplace.net/2014/02/19/squashing-github-pull-requests-into-a-single-commit/>`_?
+* If the contribution contains multiple commits, are they grouped together into logical changes (one major change per pull request)? Are any commits with names like "fixed typo" `squashed into previous commits <http://eli.thegreenplace.net/2014/02/19/squashing-github-pull-requests-into-a-single-commit/>`_?
 
 * If you're unsure about any of these points, please open the Pull Request anyhow and then ask us for feedback.
 

Kconfig

@@ -24,22 +24,23 @@ mainmenu "Espressif IoT Development Framework Configuration"
         bool
         default "y" if IDF_TARGET="esp32"
 
-    config IDF_TARGET_ESP32S2
+    config IDF_TARGET_ESP32S2BETA
         bool
-        default "y" if IDF_TARGET="esp32s2"
+        default "y" if IDF_TARGET="esp32s2beta"
         select FREERTOS_UNICORE
 
     config IDF_FIRMWARE_CHIP_ID
         hex
         default 0x0000 if IDF_TARGET_ESP32
-        default 0x0002 if IDF_TARGET_ESP32S2
+        # note: S2 beta uses Chip ID 0 still, S2 will use 0x0002
+        default 0x0000 if IDF_TARGET_ESP32S2BETA
         default 0xFFFF
 
     menu "SDK tool configuration"
         config SDK_TOOLPREFIX
             string "Compiler toolchain path/prefix"
             default "xtensa-esp32-elf-" if IDF_TARGET_ESP32
-            default "xtensa-esp32s2-elf-" if IDF_TARGET_ESP32S2
+            default "xtensa-esp32s2-elf-" if IDF_TARGET_ESP32S2BETA
             help
                 The prefix/path that is used to call the toolchain. The default setting assumes
                 a crosstool-ng gcc setup that is in your PATH.
@@ -133,8 +134,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
                     CONFIG_APP_BUILD_TYPE_ELF_RAM=y
                     CONFIG_VFS_SUPPORT_TERMIOS=
                     CONFIG_NEWLIB_NANO_FORMAT=y
-                    CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT=y
-                    CONFIG_ESP_DEBUG_STUBS_ENABLE=
+                    CONFIG_ESP32_PANIC_PRINT_HALT=y
+                    CONFIG_ESP32_DEBUG_STUBS_ENABLE=
                     CONFIG_ESP_ERR_TO_NAME_LOOKUP=
 
 

README.md

@@ -2,7 +2,9 @@
 
 * [中文版](./README_CN.md)
 
-ESP-IDF is the official development framework for the **ESP32** and **ESP32-S** Series SoCs.
+[![Documentation Status](https://readthedocs.com/projects/espressif-esp-idf/badge/?version=latest)](https://docs.espressif.com/projects/esp-idf/en/latest/?badge=latest)
+
+ESP-IDF is the official development framework for the [ESP32](https://espressif.com/en/products/hardware/esp32/overview) chip.
 
 # Developing With ESP-IDF
 
@@ -10,12 +12,8 @@ ESP-IDF is the official development framework for the **ESP32** and **ESP32-S**
 
 See setup guides for detailed instructions to set up the ESP-IDF:
 
-| Chip | Getting Started Guides for ESP-IDF |
-|:----:|:----|
-| <img src="docs/_static/chip-esp32.svg" height="85" alt="ESP32"> |  <ul><li>[stable](https://docs.espressif.com/projects/esp-idf/en/stable/get-started/) version</li><li>[latest (master branch)](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/) version</li></ul> |
-| <img src="docs/_static/chip-esp32-s2.svg" height="100" alt="ESP32-S2"> | <ul><li>[latest (master branch)](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/get-started/) version</li></ul> |
-
-**Note:** Each ESP-IDF release has its own documentation. Please see Section [Versions](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/versions.html) how to find documentation and how to checkout specific release of ESP-IDF.
+* [Getting Started Guide for the stable ESP-IDF version](https://docs.espressif.com/projects/esp-idf/en/stable/get-started/)
+* [Getting Started Guide for the latest (master branch) ESP-IDF version](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/)
 
 ### Non-GitHub forks
 
@@ -79,7 +77,7 @@ You don't need to run `idf.py build` before running `idf.py flash`, `idf.py flas
 
 ## Viewing Serial Output
 
-The `idf.py monitor` target uses the [idf_monitor tool](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html) to display serial output from ESP32 or ESP32-S Series SoCs. idf_monitor also has a range of features to decode crash output and interact with the device. [Check the documentation page for details](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html).
+The `idf.py monitor` target uses the [idf_monitor tool](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html) to display serial output from the ESP32. idf_monitor also has a range of features to decode crash output and interact with the device. [Check the documentation page for details](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html).
 
 Exit the monitor by typing Ctrl-].
 

README_CN.md

@@ -2,7 +2,9 @@
 
 * [English Version](./README.md)
 
-ESP-IDF 是由乐鑫官方推出的针对 **ESP32** 和 **ESP32-S2** 系列芯片的开发框架。
+[![Documentation Status](https://readthedocs.com/projects/espressif-esp-idf/badge/?version=latest)](https://docs.espressif.com/projects/esp-idf/zh_CN/latest/?badge=latest)
+
+ESP-IDF 是由乐鑫官方推出的针对 [ESP32](https://espressif.com/en/products/hardware/esp32/overview) 系列芯片的开发框架。
 
 # 使用 ESP-IDF 进行开发
 
@@ -10,13 +12,8 @@ ESP-IDF 是由乐鑫官方推出的针对 **ESP32** 和 **ESP32-S2** 系列芯
 
 请参阅如下指南搭建 ESP-IDF 的开发环境：
 
-| 芯片 | ESP-IDF 入门指南 |
-|:----:|:----|
-| <img src="docs/_static/chip-esp32.svg" height="85" alt="ESP32"> | <ul><li>[稳定](https://docs.espressif.com/projects/esp-idf/zh_CN/stable/get-started/) 版</li><li>[最新（master 分支)](https://docs.espressif.com/projects/esp-idf/zh_CN/latest/get-started/) 版本</li></ul> |
-| <img src="docs/_static/chip-esp32-s2.svg" height="100" alt="ESP32-S2"> | <ul><li>[最新（master 分支)](https://docs.espressif.com/projects/esp-idf/zh_CN/latest/esp32s2/get-started/) 版本</li></ul> |
-
-**注意：** 每个 ESP-IDF 版本都有其对应的文档。 请参阅 [版本](https://docs.espressif.com/projects/esp-idf/zh_CN/latest/esp32/versions.html) 部分，如何查找文档以及如何检出ESP-IDF的特定发行版。
-
+* [ESP-IDF 稳定版本的入门指南](https://docs.espressif.com/projects/esp-idf/en/stable/get-started/)
+* [ESP-IDF 开发版本（master 分支）的入门指南](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/)
 
 ### 非 GitHub 分叉的 ESP-IDF 项目
 
@@ -77,7 +74,7 @@ ESP-IDF 中的子模块采用相对路径（[详见 .gitmodules 文件](.gitmodu
 
 ## 观察串口输入
 
-`idf.py monitor` 会调用 [idf_monitor 工具](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html)来显示 ESP32 和 ESP32-S2 的串口输出。`idf_monitor` 还包含一系列的功能来解析程序崩溃后的输出结果并与设备进行交互。更多详细内容，请参阅[文档](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html).
+`idf.py monitor` 会调用 [idf_monitor 工具](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html)来显示 ESP32 的串口输出。`idf_monitor` 还包含一系列的功能来解析程序崩溃后的输出结果并与设备进行交互。更多详细内容，请参阅[文档](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html).
 
 输入 `Ctrl-]` 可退出监视器。
 

components/app_trace/app_trace.c

@@ -158,7 +158,7 @@
 #include <sys/param.h>
 #include "soc/soc.h"
 #include "soc/dport_reg.h"
-#if CONFIG_IDF_TARGET_ESP32S2
+#if CONFIG_IDF_TARGET_ESP32S2BETA
 #include "soc/sensitive_reg.h"
 #endif
 #include "eri.h"
@@ -210,7 +210,7 @@ const static char *TAG = "esp_apptrace";
 #define TRACEMEM_MUX_BLK0_ONLY                  1
 #define TRACEMEM_MUX_BLK1_ONLY                  2
 #define TRACEMEM_MUX_PROBLK1_APPBLK0            3
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
 #define TRACEMEM_MUX_BLK0_NUM                   19
 #define TRACEMEM_MUX_BLK1_NUM                   20
 #define TRACEMEM_BLK_NUM2ADDR(_n_)              (0x3FFB8000UL + 0x4000UL*((_n_)-4))
@@ -244,7 +244,7 @@ static volatile uint8_t *s_trax_blocks[] = {
     (volatile uint8_t *) 0x3FFFC000,
     (volatile uint8_t *) 0x3FFF8000
 };
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
 static volatile uint8_t *s_trax_blocks[] = {
     (volatile uint8_t *)TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK0_NUM),
     (volatile uint8_t *)TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK1_NUM)
@@ -435,7 +435,7 @@ static inline void esp_apptrace_trax_select_memory_block(int block_num)
     // select memory block to be exposed to the TRAX module (accessed by host)
 #if CONFIG_IDF_TARGET_ESP32
     DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, block_num ? TRACEMEM_MUX_BLK0_ONLY : TRACEMEM_MUX_BLK1_ONLY);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     DPORT_WRITE_PERI_REG(DPORT_PMS_OCCUPY_3_REG, block_num ? BIT(TRACEMEM_MUX_BLK0_NUM-4) : BIT(TRACEMEM_MUX_BLK1_NUM-4));
 #endif
 }

components/app_trace/app_trace_util.c

@@ -18,8 +18,8 @@
 #include "sdkconfig.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/clk.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/clk.h"
 #endif
 
 ///////////////////////////////////////////////////////////////////////////////

components/app_trace/gcov/gcov_rtio.c

@@ -23,11 +23,11 @@
 #include "soc/timer_periph.h"
 #include "esp_app_trace.h"
 #include "esp_private/dbg_stubs.h"
-#include "hal/wdt_hal.h"
+#include "hal/timer_ll.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/libc_stubs.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/libc_stubs.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/libc_stubs.h"
 #endif
 
 #if CONFIG_APPTRACE_GCOV_ENABLE
@@ -68,12 +68,8 @@ static int esp_dbg_stub_gcov_dump_do(void)
     int ret = ESP_OK;
     FILE* old_stderr = stderr;
     FILE* old_stdout = stdout;
-    static struct syscall_stub_table *old_tables[portNUM_PROCESSORS];
+    struct syscall_stub_table* old_table = syscall_table_ptr_pro;
 
-    old_tables[0] = syscall_table_ptr_pro;
-#if portNUM_PROCESSORS > 1
-    old_tables[1] = syscall_table_ptr_app;
-#endif
     ESP_EARLY_LOGV(TAG, "Alloc apptrace down buf %d bytes", ESP_GCOV_DOWN_BUF_SIZE);
     void *down_buf = malloc(ESP_GCOV_DOWN_BUF_SIZE);
     if (down_buf == NULL) {
@@ -84,14 +80,12 @@ static int esp_dbg_stub_gcov_dump_do(void)
     esp_apptrace_down_buffer_config(down_buf, ESP_GCOV_DOWN_BUF_SIZE);
     ESP_EARLY_LOGV(TAG, "Dump data...");
     // incase of dual-core chip APP and PRO CPUs share the same table, so it is safe to save only PRO's table
-    memcpy(&s_gcov_stub_table, syscall_table_ptr_pro, sizeof(s_gcov_stub_table));
+    memcpy(&s_gcov_stub_table, old_table, sizeof(s_gcov_stub_table));
     s_gcov_stub_table._lock_acquire_recursive = &gcov_stub_lock_acquire_recursive;
     s_gcov_stub_table._lock_release_recursive = &gcov_stub_lock_release_recursive;
     s_gcov_stub_table._lock_try_acquire_recursive = &gcov_stub_lock_try_acquire_recursive,
+
     syscall_table_ptr_pro = &s_gcov_stub_table;
-#if portNUM_PROCESSORS > 1
-    syscall_table_ptr_app = &s_gcov_stub_table;
-#endif
     stderr = (FILE*) &__sf_fake_stderr;
     stdout = (FILE*) &__sf_fake_stdout;
     __gcov_dump();
@@ -99,10 +93,8 @@ static int esp_dbg_stub_gcov_dump_do(void)
     __gcov_reset();
     stdout = old_stdout;
     stderr = old_stderr;
-    syscall_table_ptr_pro = old_tables[0];
-#if portNUM_PROCESSORS > 1
-    syscall_table_ptr_app = old_tables[1];
-#endif
+    syscall_table_ptr_pro = old_table;
+
     ESP_EARLY_LOGV(TAG, "Free apptrace down buf");
     free(down_buf);
     ESP_EARLY_LOGV(TAG, "Finish file transfer session");
@@ -110,7 +102,6 @@ static int esp_dbg_stub_gcov_dump_do(void)
     if (ret != ESP_OK) {
         ESP_EARLY_LOGE(TAG, "Failed to send files transfer stop cmd (%d)!", ret);
     }
-    ESP_EARLY_LOGV(TAG, "exit %d", ret);
     return ret;
 }
 
@@ -142,16 +133,14 @@ void esp_gcov_dump(void)
     esp_cpu_stall(other_core);
 #endif
     while (!esp_apptrace_host_is_connected(ESP_APPTRACE_DEST_TRAX)) {
-        wdt_hal_context_t twdt = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
-        wdt_hal_context_t iwdt = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
-        //Feed the Task Watchdog (TG0) to prevent it from timing out
-        wdt_hal_write_protect_disable(&twdt);
-        wdt_hal_feed(&twdt);
-        wdt_hal_write_protect_enable(&twdt);
-        //Likewise, feed the Interrupt Watchdog (TG1) to prevent a reboot
-        wdt_hal_write_protect_disable(&iwdt);
-        wdt_hal_feed(&iwdt);
-        wdt_hal_write_protect_enable(&iwdt);
+        // to avoid complains that task watchdog got triggered for other tasks
+        timer_ll_wdt_set_protect(&TIMERG0, false);
+        timer_ll_wdt_feed(&TIMERG0);
+        timer_ll_wdt_set_protect(&TIMERG0, true);
+        // to avoid reboot on INT_WDT
+        timer_ll_wdt_set_protect(&TIMERG1, false);
+        timer_ll_wdt_feed(&TIMERG1);
+        timer_ll_wdt_set_protect(&TIMERG1, true);
     }
 
     esp_dbg_stub_gcov_dump_do();
@@ -164,9 +153,7 @@ void esp_gcov_dump(void)
 void *gcov_rtio_fopen(const char *path, const char *mode)
 {
     ESP_EARLY_LOGV(TAG, "%s '%s' '%s'", __FUNCTION__, path, mode);
-    void *f = esp_apptrace_fopen(ESP_APPTRACE_DEST_TRAX, path, mode);
-    ESP_EARLY_LOGV(TAG, "%s ret %p", __FUNCTION__, f);
-    return f;
+    return esp_apptrace_fopen(ESP_APPTRACE_DEST_TRAX, path, mode);
 }
 
 int gcov_rtio_fclose(void *stream)

components/app_trace/project_include.cmake

@@ -5,24 +5,12 @@ function(idf_create_coverage_report report_dir)
     set(gcov_tool ${CONFIG_SDK_TOOLPREFIX}gcov)
     idf_build_get_property(project_name PROJECT_NAME)
 
-    add_custom_target(pre-cov-report
+    add_custom_target(lcov-report
         COMMENT "Generating coverage report in: ${report_dir}"
         COMMAND ${CMAKE_COMMAND} -E echo "Using gcov: ${gcov_tool}"
         COMMAND ${CMAKE_COMMAND} -E make_directory ${report_dir}/html
-        )
-
-    add_custom_target(lcov-report
-        COMMENT "WARNING: lcov-report is deprecated. Please use gcovr-report instead."
         COMMAND lcov --gcov-tool ${gcov_tool} -c -d ${CMAKE_CURRENT_BINARY_DIR} -o ${report_dir}/${project_name}.info
-        COMMAND genhtml -o ${report_dir}/html ${report_dir}/${project_name}.info
-        DEPENDS pre-cov-report
-        )
-
-    add_custom_target(gcovr-report
-        COMMAND gcovr -r ${project_dir} --gcov-executable ${gcov_tool} -s --html-details ${report_dir}/html/index.html
-        WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
-        DEPENDS pre-cov-report
-        )
+        COMMAND genhtml -o ${report_dir}/html ${report_dir}/${project_name}.info)
 endfunction()
 
 # idf_clean_coverage_report
@@ -32,4 +20,4 @@ function(idf_clean_coverage_report report_dir)
     add_custom_target(cov-data-clean
         COMMENT "Clean coverage report in: ${report_dir}"
         COMMAND ${CMAKE_COMMAND} -E remove_directory ${report_dir})
-endfunction()
+endfunction()

components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c

@@ -66,9 +66,9 @@ Revision: $Rev: 3734 $
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/ets_sys.h"
 #include "esp32/clk.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/ets_sys.h"
-#include "esp32s2/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/clk.h"
 #endif
 #include "esp_app_trace.h"
 #include "esp_app_trace_util.h"
@@ -78,9 +78,9 @@ Revision: $Rev: 3734 $
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/ets_sys.h"
 #include "esp32/clk.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/ets_sys.h"
-#include "esp32s2/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/clk.h"
 #endif
 
 
@@ -140,7 +140,7 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI;
 // CCOUNT is incremented at CPU frequency
 #if CONFIG_IDF_TARGET_ESP32
 #define SYSVIEW_TIMESTAMP_FREQ  (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000)
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
 #define SYSVIEW_TIMESTAMP_FREQ  (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000)
 #endif
 #endif // TS_USE_CCOUNT

components/app_trace/sys_view/esp32/SEGGER_RTT_esp32.c

@@ -20,8 +20,8 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/ets_sys.h"
 #endif
 #include "esp_app_trace.h"
 

components/app_trace/test/CMakeLists.txt

@@ -1,3 +1,3 @@
 idf_component_register(SRC_DIRS "."
-                    PRIV_INCLUDE_DIRS "."
-                    PRIV_REQUIRES unity)
+                    INCLUDE_DIRS "."
+                    REQUIRES unity)

components/app_update/CMakeLists.txt

@@ -7,18 +7,11 @@ idf_component_register(SRCS "esp_ota_ops.c"
 # linker will ignore this structure as it has no other files depending on it.
 target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_app_desc")
 
-if(CONFIG_APP_PROJECT_VER_FROM_CONFIG)
-    # Ignore current PROJECT_VER (which was set in __project_get_revision()).
-    # Gets the version from the CONFIG_APP_PROJECT_VER.
-    idf_build_set_property(PROJECT_VER "${CONFIG_APP_PROJECT_VER}")
-endif()
-
 # cut PROJECT_VER and PROJECT_NAME to required 32 characters.
 idf_build_get_property(project_ver PROJECT_VER)
 idf_build_get_property(project_name PROJECT_NAME)
 string(SUBSTRING "${project_ver}" 0 31 PROJECT_VER_CUT)
 string(SUBSTRING "${project_name}" 0 31 PROJECT_NAME_CUT)
-message(STATUS "App \"${PROJECT_NAME_CUT}\" version: ${PROJECT_VER_CUT}")
 
 set_source_files_properties(
     SOURCE "esp_app_desc.c"
@@ -62,11 +55,6 @@ if(NOT BOOTLOADER_BUILD)
                         --partition-table-offset ${PARTITION_TABLE_OFFSET}
                         erase_otadata)
 
-        idf_component_get_property(main_args esptool_py FLASH_ARGS)
-        idf_component_get_property(sub_args esptool_py FLASH_SUB_ARGS)
-        esptool_py_flash_target(otadata-flash "${main_args}" "${sub_args}")
-        esptool_py_flash_target_image(otadata-flash otadata "${otadata_offset}" "${blank_otadata_file}")
-
-        esptool_py_flash_target_image(flash otadata "${otadata_offset}" "${blank_otadata_file}")
+        esptool_py_flash_project_args(otadata ${otadata_offset} "${blank_otadata_file}" FLASH_IN_PROJECT)
     endif()
 endif()

components/app_update/Kconfig.projbuild

@@ -22,20 +22,6 @@ menu "Application manager"
             The PROJECT_NAME variable from the build system will not affect the firmware image.
             This value will not be contained in the esp_app_desc structure.
 
-    config APP_PROJECT_VER_FROM_CONFIG
-        bool "Get the project version from Kconfig"
-        default n
-        help
-            If this is enabled, then config item APP_PROJECT_VER will be used for the variable PROJECT_VER.
-            Other ways to set PROJECT_VER will be ignored.
-
-    config APP_PROJECT_VER
-        string "Project version"
-        default "1"
-        depends on APP_PROJECT_VER_FROM_CONFIG
-        help
-            Project version
-
     config APP_RETRIEVE_LEN_ELF_SHA
         int "The length of APP ELF SHA is stored in RAM(chars)"
         default 16

components/app_update/component.mk

@@ -8,49 +8,49 @@
 COMPONENT_ADD_LDFLAGS += -u esp_app_desc
 
 ifndef IS_BOOTLOADER_BUILD
-    # If ``CONFIG_APP_PROJECT_VER_FROM_CONFIG`` option is set, the value of ``CONFIG_APP_PROJECT_VER`` will be used
-    # Else, if ``PROJECT_VER`` variable set in project Makefile file, its value will be used.
-    # Else, if the ``$PROJECT_PATH/version.txt`` exists, its contents will be used as ``PROJECT_VER``.
-    # Else, if the project is located inside a Git repository, the output of git describe will be used.
-    # Otherwise, ``PROJECT_VER`` will be "1".
-    ifdef CONFIG_APP_PROJECT_VER_FROM_CONFIG
-        PROJECT_VER:= $(CONFIG_APP_PROJECT_VER)
-    else
-        ifneq ("${PROJECT_VER}", "")
-            PROJECT_VER:= $(PROJECT_VER)
-        else
-            ifneq ("$(wildcard ${PROJECT_PATH}/version.txt)","")
-                PROJECT_VER := $(shell cat ${PROJECT_PATH}/version.txt)
-            else
-                GIT_PROJECT_VER := $(shell cd ${PROJECT_PATH} && git describe --always --tags --dirty 2> /dev/null)
-                ifeq ("${GIT_PROJECT_VER}", "")
-                    PROJECT_VER := "1"
-                    $(info Project is not inside a git repository, or git repository has no commits)
-                    $(info will not use 'git describe' to determine PROJECT_VER.)
-                else
-                    PROJECT_VER:= $(GIT_PROJECT_VER)
-                endif # a git repository
-            endif # version.txt
-        endif # PROJECT_VER
-    endif # CONFIG_APP_PROJECT_VER_FROM_CONFIG
+GET_PROJECT_VER ?=
+ifeq ("${PROJECT_VER}", "")
+ifeq ("$(wildcard ${PROJECT_PATH}/version.txt)","")
 
-    # cut PROJECT_VER and PROJECT_NAME to required 32 characters.
-    PROJECT_VER_CUT  := $(shell echo "$(PROJECT_VER)"  | cut -c 1-31)
-    PROJECT_NAME_CUT := $(shell echo "$(PROJECT_NAME)" | cut -c 1-31)
+GET_PROJECT_VER := $(shell cd ${PROJECT_PATH} && git describe --always --tags --dirty 2> /dev/null)
+ifeq ("${GET_PROJECT_VER}", "")
+GET_PROJECT_VER := "1"
+$(info Project is not inside a git repository, will not use 'git describe' to determine PROJECT_VER.)
+endif
 
-    $(info App "$(PROJECT_NAME_CUT)" version: $(PROJECT_VER_CUT))
+else
+# read from version.txt
+GET_PROJECT_VER := $(shell cat ${PROJECT_PATH}/version.txt)
+endif
+endif
+# If ``PROJECT_VER`` variable set in project Makefile file, its value will be used.
+# Else, if the ``$PROJECT_PATH/version.txt`` exists, its contents will be used as ``PROJECT_VER``.
+# Else, if the project is located inside a Git repository, the output of git describe will be used.
+# Otherwise, ``PROJECT_VER`` will be "1".
 
-    NEW_DEFINES:= "$(PROJECT_VER_CUT) $(PROJECT_NAME_CUT) $(IDF_VER)"
-    ifeq ("$(wildcard ${TMP_DEFINES})","")
-        OLD_DEFINES:= ""
-    else
-        OLD_DEFINES:= "$(shell cat $(TMP_DEFINES))"
-    endif
+ifeq ("${PROJECT_VER}", "")
+PROJECT_VER:= $(GET_PROJECT_VER)
+else
+PROJECT_VER:= $(PROJECT_VER)
+endif
 
-    # If NEW_DEFINES (PROJECT_VER, PROJECT_NAME) were changed then rebuild only esp_app_desc.
-    ifneq (${NEW_DEFINES}, ${OLD_DEFINES})
-        $(shell echo $(NEW_DEFINES) > $(TMP_DEFINES); rm -f esp_app_desc.o;)
-    endif
+# cut PROJECT_VER and PROJECT_NAME to required 32 characters.
+PROJECT_VER_CUT  := $(shell echo "$(PROJECT_VER)"  | cut -c 1-31)
+PROJECT_NAME_CUT := $(shell echo "$(PROJECT_NAME)" | cut -c 1-31)
 
-    esp_app_desc.o: CPPFLAGS += -D PROJECT_VER=\""$(PROJECT_VER_CUT)"\" -D PROJECT_NAME=\""$(PROJECT_NAME_CUT)"\"
-endif # IS_BOOTLOADER_BUILD
+$(info App "$(PROJECT_NAME_CUT)" version: $(PROJECT_VER_CUT))
+
+NEW_DEFINES:= "$(PROJECT_VER_CUT) $(PROJECT_NAME_CUT) $(IDF_VER)"
+ifeq ("$(wildcard ${TMP_DEFINES})","")
+OLD_DEFINES:= ""
+else
+OLD_DEFINES:= "$(shell cat $(TMP_DEFINES))"
+endif
+
+# If NEW_DEFINES (PROJECT_VER, PROJECT_NAME) were changed then rebuild only esp_app_desc.
+ifneq (${NEW_DEFINES}, ${OLD_DEFINES})
+$(shell echo $(NEW_DEFINES) > $(TMP_DEFINES); rm -f esp_app_desc.o;)
+endif
+
+esp_app_desc.o: CPPFLAGS += -D PROJECT_VER=\""$(PROJECT_VER_CUT)"\" -D PROJECT_NAME=\""$(PROJECT_NAME_CUT)"\"
+endif

components/app_update/esp_ota_ops.c

@@ -250,43 +250,6 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size)
     return ESP_ERR_INVALID_ARG;
 }
 
-esp_err_t esp_ota_write_with_offset(esp_ota_handle_t handle, const void *data, size_t size, uint32_t offset)
-{
-    const uint8_t *data_bytes = (const uint8_t *)data;
-    esp_err_t ret;
-    ota_ops_entry_t *it;
-
-    if (data == NULL) {
-        ESP_LOGE(TAG, "write data is invalid");
-        return ESP_ERR_INVALID_ARG;
-    }
-
-    // find ota handle in linked list
-    for (it = LIST_FIRST(&s_ota_ops_entries_head); it != NULL; it = LIST_NEXT(it, entries)) {
-        if (it->handle == handle) {
-            // must erase the partition before writing to it
-            assert(it->erased_size > 0 && "must erase the partition before writing to it");
-
-            /* esp_ota_write_with_offset is used to write data in non contiguous manner.
-             * Hence, unaligned data(less than 16 bytes) cannot be cached if flash encryption is enabled.
-             */
-            if (esp_flash_encryption_enabled() && (size % 16)) {
-                ESP_LOGE(TAG, "Size should be 16byte aligned for flash encryption case");
-                return ESP_ERR_INVALID_ARG;
-            }
-            ret = esp_partition_write(it->part, offset, data_bytes, size);
-            if (ret == ESP_OK) {
-                it->wrote_size += size;
-            }
-            return ret;
-        }
-    }
-
-    // OTA handle is not found in linked list
-    ESP_LOGE(TAG,"OTA handle not found");
-    return ESP_ERR_INVALID_ARG;
-}
-
 esp_err_t esp_ota_end(esp_ota_handle_t handle)
 {
     ota_ops_entry_t *it;

components/app_update/include/esp_ota_ops.h

@@ -117,29 +117,6 @@ esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp
  */
 esp_err_t esp_ota_write(esp_ota_handle_t handle, const void* data, size_t size);
 
-/**
- * @brief   Write OTA update data to partition
- *
- * This function can write data in non contiguous manner.
- * If flash encryption is enabled, data should be 16 byte aligned.
- *
- * @param handle  Handle obtained from esp_ota_begin
- * @param data    Data buffer to write
- * @param size    Size of data buffer in bytes
- * @param offset  Offset in flash partition
- *
- * @note While performing OTA, if the packets arrive out of order, esp_ota_write_with_offset() can be used to write data in non contiguous manner.
- *       Use of esp_ota_write_with_offset() in combination with esp_ota_write() is not recommended.
- *
- * @return
- *    - ESP_OK: Data was written to flash successfully.
- *    - ESP_ERR_INVALID_ARG: handle is invalid.
- *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
- *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
- *    - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
- */
-esp_err_t esp_ota_write_with_offset(esp_ota_handle_t handle, const void *data, size_t size, uint32_t offset);
-
 /**
  * @brief Finish OTA update and validate newly written app image.
  *

components/app_update/test/CMakeLists.txt

@@ -1,4 +1,4 @@
 idf_component_register(SRC_DIRS "."
-                       PRIV_INCLUDE_DIRS "."
-                       PRIV_REQUIRES unity test_utils app_update bootloader_support nvs_flash
+                       INCLUDE_DIRS "."
+                       REQUIRES unity test_utils app_update bootloader_support nvs_flash
                       )

components/app_update/test/test_ota_ops.c

@@ -84,7 +84,7 @@ TEST_CASE("esp_ota_get_next_update_partition logic", "[ota]")
     TEST_ASSERT_EQUAL_PTR(ota_0, p);
 }
 
-TEST_CASE("esp_ota_get_partition_description", "[ota]")
+TEST_CASE("esp_ota_get_partition_description ", "[ota]")
 {
     const esp_partition_t *running = esp_ota_get_running_partition();
     TEST_ASSERT_NOT_NULL(running);

components/app_update/test/test_switch_ota.c

@@ -10,9 +10,9 @@
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/spi_flash.h"
 #include "esp32/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/spi_flash.h"
+#include "esp32s2beta/rom/rtc.h"
 #endif
 
 #include "freertos/FreeRTOS.h"
@@ -48,34 +48,9 @@ static void copy_app_partition(esp_ota_handle_t update_handle, const esp_partiti
 {
     const void *partition_bin = NULL;
     spi_flash_mmap_handle_t  data_map;
-    ESP_LOGI(TAG, "start the copy process");
     TEST_ESP_OK(esp_partition_mmap(curr_app, 0, curr_app->size, SPI_FLASH_MMAP_DATA, &partition_bin, &data_map));
     TEST_ESP_OK(esp_ota_write(update_handle, (const void *)partition_bin, curr_app->size));
     spi_flash_munmap(data_map);
-    ESP_LOGI(TAG, "finish the copy process");
-}
-
-/* @brief Copies a current app to next partition using handle.
- *
- * @param[in] update_handle - Handle of API ota.
- * @param[in] cur_app - Current app.
- */
-static void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const esp_partition_t *curr_app)
-{
-    const void *partition_bin = NULL;
-    spi_flash_mmap_handle_t  data_map;
-    ESP_LOGI(TAG, "start the copy process");
-    uint32_t offset = 0, bytes_to_write = curr_app->size;
-    uint32_t write_bytes;
-    while (bytes_to_write > 0) {
-        write_bytes = (bytes_to_write > (4 * 1024)) ? (4 * 1024) : bytes_to_write;
-        TEST_ESP_OK(esp_partition_mmap(curr_app, offset, write_bytes, SPI_FLASH_MMAP_DATA, &partition_bin, &data_map));
-        TEST_ESP_OK(esp_ota_write_with_offset(update_handle, (const void *)partition_bin, write_bytes, offset));
-        spi_flash_munmap(data_map);
-        bytes_to_write -= write_bytes;
-        offset += write_bytes;
-    }
-    ESP_LOGI(TAG, "finish the copy process");
 }
 
 #if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST)
@@ -128,26 +103,6 @@ static void copy_current_app_to_next_part(const esp_partition_t *cur_app_partiti
     TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition));
 }
 
-/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition.
- *
- * @param[in] cur_app_partition - Current app.
- * @param[in] next_app_partition - Next app for boot.
- */
-static void copy_current_app_to_next_part_with_offset(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition)
-{
-    esp_ota_get_next_update_partition(NULL);
-    TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition);
-    ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%x", next_app_partition->subtype, next_app_partition->address);
-
-    esp_ota_handle_t update_handle = 0;
-    TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle));
-
-    copy_app_partition_with_offset(update_handle, cur_app_partition);
-
-    TEST_ESP_OK(esp_ota_end(update_handle));
-    TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition));
-}
-
 /* @brief Erase otadata partition
  */
 static void erase_ota_data(void)
@@ -161,7 +116,6 @@ static void erase_ota_data(void)
  */
 static void reboot_as_deep_sleep(void)
 {
-    ESP_LOGI(TAG, "reboot as deep sleep");
     esp_sleep_enable_timer_wakeup(2000);
     esp_deep_sleep_start();
 }
@@ -171,21 +125,10 @@ static void reboot_as_deep_sleep(void)
 static void copy_current_app_to_next_part_and_reboot(void)
 {
     const esp_partition_t *cur_app = esp_ota_get_running_partition();
-    ESP_LOGI(TAG, "copy current app to next part");
     copy_current_app_to_next_part(cur_app, get_next_update_partition());
     reboot_as_deep_sleep();
 }
 
-/* @brief Copies a current app to next partition (OTA0-15) using esp_ota_write_with_offest(), after that ESP is rebooting and run this (the next) OTAx.
- */
-static void copy_current_app_to_next_part_with_offset_and_reboot(void)
-{
-    const esp_partition_t *cur_app = esp_ota_get_running_partition();
-    ESP_LOGI(TAG, "copy current app to next part");
-    copy_current_app_to_next_part_with_offset(cur_app, get_next_update_partition());
-    reboot_as_deep_sleep();
-}
-
 /* @brief Get running app.
  *
  * @return The next partition of OTA(OTA0-15).
@@ -313,7 +256,6 @@ static void start_test(void)
     ESP_LOGI(TAG, "boot count 1 - reset");
     boot_count = 1;
     erase_ota_data();
-    ESP_LOGI(TAG, "ota_data erased");
     reboot_as_deep_sleep();
 }
 
@@ -793,32 +735,3 @@ static void test_erase_last_app_rollback(void)
 // 4 Stage: run OTA1           -> check it -> erase OTA0 and rollback                          -> reboot
 // 5 Stage: run factory        -> check it -> erase OTA_DATA for next tests                    -> PASS
 TEST_CASE_MULTIPLE_STAGES("Test erase_last_boot_app_partition. factory, OTA1, OTA0, factory", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET, DEEPSLEEP_RESET, SW_CPU_RESET]", start_test, test_erase_last_app_flow, test_erase_last_app_flow, test_erase_last_app_flow, test_erase_last_app_rollback);
-
-static void test_flow6(void)
-{
-    boot_count++;
-    ESP_LOGI(TAG, "boot count %d", boot_count);
-    const esp_partition_t *cur_app = get_running_firmware();
-    switch (boot_count) {
-        case 2:
-            ESP_LOGI(TAG, "Factory");
-            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_FACTORY, cur_app->subtype);
-            copy_current_app_to_next_part_with_offset_and_reboot();
-            break;
-        case 3:
-            ESP_LOGI(TAG, "OTA0");
-            TEST_ASSERT_EQUAL(ESP_PARTITION_SUBTYPE_APP_OTA_0, cur_app->subtype);
-            mark_app_valid();
-            erase_ota_data();
-            break;
-        default:
-            erase_ota_data();
-            TEST_FAIL_MESSAGE("Unexpected stage");
-            break;
-    }
-}
-
-// 1 Stage: After POWER_RESET erase OTA_DATA for this test              -> reboot through deep sleep.
-// 2 Stage: run factory -> check it -> copy factory to OTA0             -> reboot  --//--
-// 3 Stage: run OTA0    -> check it -> erase OTA_DATA for next tests    -> PASS
-TEST_CASE_MULTIPLE_STAGES("Switching between factory, OTA0 using esp_ota_write_with_offset", "[app_update][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", start_test, test_flow6, test_flow6);

components/bootloader/CMakeLists.txt

@@ -5,17 +5,17 @@ if(BOOTLOADER_BUILD OR NOT CONFIG_APP_BUILD_BOOTLOADER)
     return()
 endif()
 
-add_dependencies(bootloader partition_table_bin)
-
 # When secure boot is enabled, do not flash bootloader along with invocation of `idf.py flash`
 if(NOT CONFIG_SECURE_BOOT)
     set(flash_bootloader FLASH_IN_PROJECT)
 endif()
 
-esptool_py_custom_target(bootloader-flash bootloader "bootloader")
-esptool_py_flash_target_image(bootloader-flash bootloader "0x1000" "${BOOTLOADER_BUILD_DIR}/bootloader.bin")
+# Set values used in flash_bootloader_args.in and generate flash file
+# for bootloader
+esptool_py_flash_project_args(bootloader 0x1000
+                            ${BOOTLOADER_BUILD_DIR}/bootloader.bin
+                            ${flash_bootloader}
+                            FLASH_FILE_TEMPLATE flash_bootloader_args.in)
 
-# Also attach an image to the project flash target
-if(NOT CONFIG_SECURE_BOOT)
-    esptool_py_flash_target_image(flash bootloader "0x1000" "${BOOTLOADER_BUILD_DIR}/bootloader.bin")
-endif()
+esptool_py_custom_target(bootloader-flash bootloader "bootloader")
+add_dependencies(bootloader partition_table)

components/bootloader/Kconfig.projbuild

@@ -231,11 +231,11 @@ menu "Bootloader config"
         depends on BOOTLOADER_APP_ANTI_ROLLBACK
         range 1 32 if IDF_TARGET_ESP32
         default 32 if IDF_TARGET_ESP32
-        range 1 16 if IDF_TARGET_ESP32S2
-        default 16 if IDF_TARGET_ESP32S2
+        range 1 16 if IDF_TARGET_ESP32S2BETA
+        default 16 if IDF_TARGET_ESP32S2BETA
         help
             The size of the efuse secure version field.
-            Its length is limited to 32 bits for ESP32 and 16 bits for ESP32-S2.
+            Its length is limited to 32 bits for ESP32 and 16 bits for ESP32S2BETA.
             This determines how many times the security version can be increased.
 
     config BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
@@ -551,7 +551,7 @@ menu "Security features"
     choice SECURE_FLASH_ENCRYPTION_KEYSIZE
         bool "Size of generated AES-XTS key"
         default SECURE_FLASH_ENCRYPTION_AES128
-        depends on IDF_TARGET_ESP32S2 && SECURE_FLASH_ENC_ENABLED
+        depends on IDF_TARGET_ESP32S2BETA && SECURE_FLASH_ENC_ENABLED
         help
             Size of generated AES-XTS key.
 
@@ -587,7 +587,6 @@ menu "Security features"
 
         config SECURE_FLASH_ENCRYPTION_MODE_RELEASE
             bool "Release"
-            select SECURE_ENABLE_SECURE_ROM_DL_MODE
 
     endchoice
 
@@ -602,7 +601,7 @@ menu "Security features"
 
         config SECURE_BOOT_ALLOW_ROM_BASIC
             bool "Leave ROM BASIC Interpreter available on reset"
-            depends on (SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT) && IDF_TARGET_ESP32
+            depends on SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
             default N
             help
                 By default, the BASIC ROM Console starts on reset if no valid bootloader is
@@ -665,7 +664,7 @@ menu "Security features"
 
         config SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC
             bool "Leave UART bootloader decryption enabled"
-            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && IDF_TARGET_ESP32
+            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
             default N
             help
                 If not set (default), the bootloader will permanently disable UART bootloader decryption access on
@@ -699,48 +698,5 @@ menu "Security features"
                 the wrong device. The device needs to have flash encryption already enabled using espefuse.py.
 
     endmenu  # Potentially Insecure
-
-    config SECURE_DISABLE_ROM_DL_MODE
-        bool "Permanently disable ROM Download Mode"
-        depends on !IDF_TARGET_ESP32 || ESP32_REV_MIN_3
-        default n
-        help
-            If set, during startup the app will burn an eFuse bit to permanently disable the UART ROM
-            Download Mode. This prevents any future use of esptool.py, espefuse.py and similar tools.
-
-            Once disabled, if the SoC is booted with strapping pins set for ROM Download Mode
-            then an error is printed instead.
-
-            It is recommended to enable this option in any production application where Flash
-            Encryption and/or Secure Boot is enabled and access to Download Mode is not required.
-
-            It is also possible to permanently disable Download Mode by calling
-            esp_efuse_disable_rom_download_mode() at runtime.
-
-    config SECURE_ENABLE_SECURE_ROM_DL_MODE
-        bool "Permanently switch to ROM UART Secure Download mode"
-        depends on IDF_TARGET_ESP32S2 && !SECURE_DISABLE_ROM_DL_MODE
-        help
-            If set, during startup the app will burn an eFuse bit to permanently switch the UART ROM
-            Download Mode into a separate Secure Download mode. This option can only work if
-            Download Mode is not already disabled by eFuse.
-
-            Secure Download mode limits the use of Download Mode functions to simple flash read,
-            write and erase operations, plus a command to return a summary of currently enabled
-            security features.
-
-            Secure Download mode is not compatible with the esptool.py flasher stub feature,
-            espefuse.py, read/writing memory or registers, encrypted download, or any other
-            features that interact with unsupported Download Mode commands.
-
-            Secure Download mode should be enabled in any application where Flash Encryption
-            and/or Secure Boot is enabled. Disabling this option does not immediately cancel
-            the benefits of the security features, but it increases the potential "attack
-            surface" for an attacker to try and bypass them with a successful physical attack.
-
-            It is also possible to enable secure download mode at runtime by calling
-            esp_efuse_enable_rom_secure_download_mode()
-
-
 endmenu  # Security features
 

components/bootloader/flash_bootloader_args.in

@@ -0,0 +1,4 @@
+--flash_mode ${ESPFLASHMODE}
+--flash_size ${ESPFLASHSIZE}
+--flash_freq ${ESPFLASHFREQ}
+${OFFSET} ${IMAGE}

components/bootloader/subproject/CMakeLists.txt

@@ -29,16 +29,9 @@ project(bootloader)
 idf_build_set_property(COMPILE_DEFINITIONS "-DBOOTLOADER_BUILD=1" APPEND)
 idf_build_set_property(COMPILE_OPTIONS "-fno-stack-protector" APPEND)
 
-idf_component_get_property(main_args esptool_py FLASH_ARGS)
-idf_component_get_property(sub_args esptool_py FLASH_SUB_ARGS)
-
-# String for printing flash command
-string(REPLACE ";" " " esptoolpy_write_flash
-    "${ESPTOOLPY} --port=(PORT) --baud=(BAUD) ${main_args} "
-    "write_flash ${sub_args}")
-
 string(REPLACE ";" " " espsecurepy "${ESPSECUREPY}")
 string(REPLACE ";" " " espefusepy "${ESPEFUSEPY}")
+set(esptoolpy_write_flash "${ESPTOOLPY_WRITE_FLASH_STR}")
 
 if(CONFIG_SECURE_BOOTLOADER_REFLASHABLE)
     if(CONFIG_SECURE_BOOTLOADER_KEY_ENCODING_192BIT)

components/bootloader/subproject/main/ld/esp32/bootloader.ld

@@ -11,6 +11,8 @@ Linker file used to link the bootloader.
 
 MEMORY
 {
+  /* I/O */
+  dport0_seg (RW) :                 	org = 0x3FF00000, len = 0x10
   /* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache */
   iram_loader_seg (RWX) :           org = 0x40078000, len = 0x8000  /* 32KB, APP CPU cache */
   /* 63kB, IRAM. We skip the first 1k to prevent the entry point being
@@ -52,7 +54,7 @@ SECTIONS
     *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)
     *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
-    *libsoc.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)
     *libsoc.a:rtc_clk.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)

components/bootloader/subproject/main/ld/esp32s2/bootloader.rom.ld

@@ -1,13 +0,0 @@
-/*
- * ESP32S2 ROM address table
- * Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796
-*/
-PROVIDE (ets_update_cpu_frequency = 0x4000d8a4);
-
-PROVIDE (MD5Final = 0x4000530c);
-PROVIDE (MD5Init = 0x4000526c);
-PROVIDE (MD5Update = 0x4000528c);
-/* bootloader will use following functions from xtensa hal library */
-xthal_get_ccount = 0x4001aa90;
-xthal_get_ccompare = 0x4001aabc;
-xthal_set_ccompare = 0x4001aa98;

components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld

@@ -1,13 +1,22 @@
-/* Simplified memory map for the bootloader.
- * Make sure the bootloader can load into main memory without overwriting itself.
- */
+/*
+Linker file used to link the bootloader.
+*/
 
 
+/* Simplified memory map for the bootloader
+
+   The main purpose is to make sure the bootloader can load into main memory
+   without overwriting itself.
+*/
+
 MEMORY
 {
-  iram_seg (RWX) :                  org = 0x40050000, len = 0x4000  /* 16KB, SRAM Block_14 */
-  iram_loader_seg (RWX) :           org = 0x40054000, len = 0x4000  /* 16KB, SRAM Block_15 */
-  dram_seg (RW) :                   org = 0x3FFE8000, len = 0x2800  /* 10KB, Top of SRAM Block_16, and before ROM data and stack */
+  /* I/O */
+  dport0_seg (RW) :                 org = 0x3FF00000, len = 0x10
+  iram_loader_seg (RWX) :           org = 0x40062000, len = 0x4000  /* 16KB, IRAM */
+  iram_seg (RWX) :                  org = 0x40066000, len = 0x4000  /* 16KB, IRAM */
+  /* 8k at the end of DRAM, before ROM data & stack */
+  dram_seg (RW) :                   org = 0x3FFFA000, len = 0x2000
 }
 
 /*  Default entry point:  */
@@ -38,7 +47,7 @@ SECTIONS
     *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)
     *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
-    *libsoc.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)
     *(.fini)

components/bootloader/subproject/main/ld/esp32s2beta/bootloader.rom.ld

@@ -0,0 +1,14 @@
+/*
+ * ESP32S2 ROM address table
+ * Generated for ROM with MD5sum: f054d40c5f6b9207d3827460a6f5748c
+*/
+PROVIDE ( ets_update_cpu_frequency = 0x4000d954 );
+
+/* ToDo: Following address may need modification */
+PROVIDE ( MD5Final = 0x400056e8 );
+PROVIDE ( MD5Init = 0x40005648 );
+PROVIDE ( MD5Update = 0x40005668 );
+/* bootloader will use following functions from xtensa hal library */
+xthal_get_ccount = 0x40015cbc;
+xthal_get_ccompare = 0x40015ce8;
+xthal_set_ccompare = 0x40015cc4;

components/bootloader_support/CMakeLists.txt

@@ -2,17 +2,20 @@ set(srcs
     "src/bootloader_clock.c"
     "src/bootloader_common.c"
     "src/bootloader_flash.c"
-    "src/bootloader_mem.c"
     "src/bootloader_random.c"
     "src/bootloader_utility.c"
     "src/esp_image_format.c"
-    "src/flash_encrypt.c"
     "src/flash_partitions.c"
     "src/flash_qio_mode.c"
     "src/bootloader_flash_config_${IDF_TARGET}.c"
     "src/bootloader_efuse_${IDF_TARGET}.c"
     )
 
+if(IDF_TARGET STREQUAL "esp32")
+    # Not supported on ESP32S2Beta yet
+    list(APPEND srcs "src/flash_encrypt.c")
+endif()
+
 if(BOOTLOADER_BUILD)
     set(include_dirs "include" "include_bootloader")
     set(priv_requires micro-ecc spi_flash efuse)

components/bootloader_support/component.mk

@@ -19,8 +19,8 @@ ifndef IS_BOOTLOADER_BUILD
 COMPONENT_OBJEXCLUDE := src/bootloader_init.o
 endif
 
-COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2.o \
-			src/bootloader_efuse_esp32s2.o
+COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2beta.o \
+			src/bootloader_efuse_esp32s2beta.o
 
 ifndef CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME
 ifndef CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME

components/bootloader_support/include/bootloader_common.h

@@ -19,8 +19,8 @@
 // RESET_REASON is declared in rom/rtc.h
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/rtc.h"
 #endif
 
 #ifdef __cplusplus

components/bootloader_support/include/esp_app_format.h

@@ -19,7 +19,6 @@
  */
 typedef enum {
     ESP_CHIP_ID_ESP32 = 0x0000,  /*!< chip ID: ESP32 */
-    ESP_CHIP_ID_ESP32S2 = 0x0002,  /*!< chip ID: ESP32S2 */
     ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;
 

components/bootloader_support/include/esp_flash_encrypt.h

@@ -52,7 +52,7 @@ static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_e
     uint32_t flash_crypt_cnt;
 #if CONFIG_IDF_TARGET_ESP32
     flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT);
 #endif
     /* __builtin_parity is in flash, so we calculate parity inline */
@@ -128,10 +128,6 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length);
  * is enabled but secure boot is not used. This should protect against
  * serial re-flashing of an unauthorised code in absence of secure boot.
  *
- * @note On ESP32 V3 only, write protecting FLASH_CRYPT_CNT will also prevent
- * disabling UART Download Mode. If both are wanted, call
- * esp_efuse_disable_rom_download_mode() before calling this function.
- *
  */
 void esp_flash_write_protect_crypt_cnt(void);
 

components/bootloader_support/include/esp_secure_boot.h

@@ -19,8 +19,8 @@
 #include "esp_image_format.h"
 
 #include "sdkconfig.h"
-#if CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/efuse.h"
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/efuse.h"
 #else
 #include "esp32/rom/secure_boot.h"
 #endif
@@ -57,7 +57,7 @@ static inline bool esp_secure_boot_enabled(void)
     #elif CONFIG_SECURE_BOOT_V2_ENABLED
         return ets_use_secure_boot_v2();
     #endif
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     return ets_efuse_secure_boot_enabled();
 #endif
     return false; /* Secure Boot not enabled in menuconfig */

components/bootloader_support/src/bootloader_clock.c

@@ -16,14 +16,13 @@
 #include "soc/rtc.h"
 #include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
-#include "soc/rtc_cntl_reg.h"
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/uart.h"
 #include "esp32/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/uart.h"
-#include "esp32s2/rom/rtc.h"
+#else
+#include "esp32s2beta/rom/uart.h"
+#include "esp32s2beta/rom/rtc.h"
 #endif
 
 void bootloader_clock_configure(void)
@@ -35,15 +34,15 @@ void bootloader_clock_configure(void)
     // and will be done with the bootloader much earlier than UART FIFO is empty.
     uart_tx_wait_idle(0);
 
-    /* Set CPU to 80MHz. Keep other clocks unmodified. */
-    int cpu_freq_mhz = 80;
-    
-#if CONFIG_IDF_TARGET_ESP32
     /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
      * 240 MHz may cause the chip to lock up (see section 3.5 of the errata
      * document). For rev. 0, switch to 240 instead if it has been enabled
      * previously.
      */
+#if CONFIG_IDF_TARGET_ESP32
+    /* Set CPU to 80MHz. Keep other clocks unmodified. */
+    int cpu_freq_mhz = 80;
+
     uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
     if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
             DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
@@ -54,9 +53,11 @@ void bootloader_clock_configure(void)
     rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
 #if CONFIG_IDF_TARGET_ESP32
     clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
-#endif
-    /* ESP32-S2 doesn't have XTAL_FREQ choice, always 40MHz */
     clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    clk_cfg.xtal_freq = RTC_XTAL_FREQ_40M;
+    clk_cfg.cpu_freq = RTC_CPU_FREQ_80M;
+#endif
     clk_cfg.slow_freq = rtc_clk_slow_freq_get();
     clk_cfg.fast_freq = rtc_clk_fast_freq_get();
     rtc_clk_init(clk_cfg);
@@ -65,20 +66,11 @@ void bootloader_clock_configure(void)
      * part of the start up time by enabling 32k XTAL early.
      * App startup code will wait until the oscillator has started up.
      */
-
-    /* TODO: move the clock option into esp_system, so that this doesn't have
-     * to continue:
-     */
-#if CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
+#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
     if (!rtc_clk_32k_enabled()) {
         rtc_clk_32k_bootstrap(CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES);
     }
 #endif
-#if CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS
-    if (!rtc_clk_32k_enabled()) {
-        rtc_clk_32k_bootstrap(0);
-    }
-#endif
 }
 
 #ifdef BOOTLOADER_BUILD

components/bootloader_support/src/bootloader_common.c

@@ -21,11 +21,11 @@
 #include "esp32/rom/spi_flash.h"
 #include "esp32/rom/crc.h"
 #include "esp32/rom/gpio.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/crc.h"
-#include "esp32s2/rom/ets_sys.h"
-#include "esp32s2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/spi_flash.h"
+#include "esp32s2beta/rom/crc.h"
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/gpio.h"
 #endif
 #include "esp_flash_partitions.h"
 #include "bootloader_flash.h"

components/bootloader_support/src/bootloader_efuse_esp32s2beta.c

@@ -16,8 +16,14 @@
 #include "bootloader_clock.h"
 #include "bootloader_common.h"
 
+int bootloader_clock_get_rated_freq_mhz()
+{
+    /* No known limitation: all chips are 240MHz rated */
+    return 240;
+}
+
 uint8_t bootloader_common_get_chip_revision(void)
 {
-    /* No other revisions for ESP32-S2 */
+    /* No other revisions for ESP32-S2beta */
     return 0;
 }

components/bootloader_support/src/bootloader_flash.c

@@ -16,8 +16,8 @@
 #include <bootloader_flash.h>
 #include <esp_log.h>
 #include <esp_flash_encrypt.h>
-#if CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/spi_flash.h"
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/spi_flash.h"
 #endif
 
 #ifndef BOOTLOADER_BUILD
@@ -71,7 +71,7 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool
     if (write_encrypted) {
 #if CONFIG_IDF_TARGET_ESP32
         return spi_flash_write_encrypted(dest_addr, src, size);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
         return SPI_Encrypt_Write(dest_addr, src, size);
 #endif
     } else {
@@ -91,14 +91,13 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 
 #else
 /* Bootloader version, uses ROM functions only */
-#include "soc/dport_reg.h"
+#include <soc/dport_reg.h>
 #if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/spi_flash.h"
-#include "esp32/rom/cache.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/cache.h"
-#include "soc/cache_memory.h"
+#include <esp32/rom/spi_flash.h>
+#include <esp32/rom/cache.h>
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include <esp32s2beta/rom/spi_flash.h>
+#include <esp32s2beta/rom/cache.h>
 #endif
 static const char *TAG = "bootloader_flash";
 
@@ -110,7 +109,7 @@ static const char *TAG = "bootloader_flash";
 #define MMU_SIZE          (0x320000)
 #define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
 #define FLASH_READ_VADDR MMU_BLOCK50_VADDR
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
 /* Use first 63 blocks in MMU for bootloader_mmap,
    63th block for bootloader_flash_read
 */
@@ -121,7 +120,7 @@ static const char *TAG = "bootloader_flash";
 #endif
 
 #define MMU_FREE_PAGES    (MMU_SIZE / FLASH_BLOCK_SIZE)
-
+    
 static bool mapped;
 
 // Current bootloader mapping (ab)used for bootloader_read()
@@ -152,7 +151,7 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Disable(0);
     Cache_Flush(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     uint32_t autoload = Cache_Suspend_ICache();
     Cache_Invalidate_ICache_All();
 #endif
@@ -160,21 +159,21 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
              src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned );
 #if CONFIG_IDF_TARGET_ESP32
     int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    int e = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
 #endif
     if (e != 0) {
         ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
 #if CONFIG_IDF_TARGET_ESP32
         Cache_Read_Enable(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
         Cache_Resume_ICache(autoload);
 #endif
         return NULL;
     }
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Enable(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     Cache_Resume_ICache(autoload);
 #endif
 
@@ -191,7 +190,7 @@ void bootloader_munmap(const void *mapping)
         Cache_Read_Disable(0);
         Cache_Flush(0);
         mmu_init(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
         //TODO, save the autoload value.
         Cache_Suspend_ICache();
         Cache_Invalidate_ICache_All();
@@ -221,13 +220,13 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Disable(0);
     Cache_Flush(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     uint32_t autoload = Cache_Suspend_ICache();
 #endif
     esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Enable(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     Cache_Resume_ICache(autoload);
 #endif
 
@@ -247,21 +246,21 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
 #if CONFIG_IDF_TARGET_ESP32
             Cache_Read_Disable(0);
             Cache_Flush(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
             uint32_t autoload = Cache_Suspend_ICache();
             Cache_Invalidate_ICache_All();
 #endif
             ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
 #if CONFIG_IDF_TARGET_ESP32
             int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
-#elif CONFIG_IDF_TARGET_ESP32S2
-            int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+            int e = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, FLASH_READ_VADDR, map_at, 64, 1, 0);
 #endif
             if (e != 0) {
                 ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
 #if CONFIG_IDF_TARGET_ESP32
                 Cache_Read_Enable(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
                 Cache_Resume_ICache(autoload);
 #endif
                 return ESP_FAIL;
@@ -269,7 +268,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
             current_read_mapping = map_at;
 #if CONFIG_IDF_TARGET_ESP32
             Cache_Read_Enable(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
             Cache_Resume_ICache(autoload);
 #endif
         }
@@ -326,7 +325,7 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool
     if (write_encrypted) {
 #if CONFIG_IDF_TARGET_ESP32
         return spi_to_esp_err(esp_rom_spiflash_write_encrypted(dest_addr, src, size));
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
         // TODO: use the same ROM AP here
         return spi_to_esp_err(SPI_Encrypt_Write(dest_addr, src, size));
 #endif

components/bootloader_support/src/bootloader_flash_config_esp32s2.c

@@ -1,84 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdbool.h>
-#include <assert.h>
-#include "string.h"
-#include "sdkconfig.h"
-#include "esp_err.h"
-#include "esp_log.h"
-#include "esp32s2/rom/gpio.h"
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/efuse.h"
-#include "soc/gpio_periph.h"
-#include "soc/efuse_reg.h"
-#include "soc/spi_reg.h"
-#include "soc/spi_mem_reg.h"
-#include "soc/spi_caps.h"
-#include "flash_qio_mode.h"
-#include "bootloader_flash_config.h"
-#include "bootloader_common.h"
-
-#define FLASH_IO_MATRIX_DUMMY_40M   0
-#define FLASH_IO_MATRIX_DUMMY_80M   0
-
-#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM    3
-
-void bootloader_flash_update_id()
-{
-    g_rom_flashchip.device_id = bootloader_read_flash_id();
-}
-
-void IRAM_ATTR bootloader_flash_cs_timing_config()
-{
-    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
-    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
-    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
-    SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
-    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
-    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
-}
-
-void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
-{
-    uint32_t spi_clk_div = 0;
-    switch (pfhdr->spi_speed) {
-        case ESP_IMAGE_SPI_SPEED_80M:
-            spi_clk_div = 1;
-            break;
-        case ESP_IMAGE_SPI_SPEED_40M:
-            spi_clk_div = 2;
-            break;
-        case ESP_IMAGE_SPI_SPEED_26M:
-            spi_clk_div = 3;
-            break;
-        case ESP_IMAGE_SPI_SPEED_20M:
-            spi_clk_div = 4;
-            break;
-        default:
-            break;
-    }
-    esp_rom_spiflash_config_clk(spi_clk_div, 0);
-}
-
-void IRAM_ATTR bootloader_flash_set_dummy_out(void)
-{
-    REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
-    REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
-}
-
-void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
-{
-    bootloader_configure_spi_pins(1);
-    bootloader_flash_set_dummy_out();
-}

components/bootloader_support/src/bootloader_flash_config_esp32s2beta.c

@@ -0,0 +1,118 @@
+// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp32s2beta/rom/gpio.h"
+#include "esp32s2beta/rom/spi_flash.h"
+#include "esp32s2beta/rom/efuse.h"
+#include "soc/gpio_periph.h"
+#include "soc/efuse_reg.h"
+#include "soc/spi_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/spi_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+
+#define FLASH_IO_MATRIX_DUMMY_40M   0
+#define FLASH_IO_MATRIX_DUMMY_80M   0
+
+#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM    3
+
+void bootloader_flash_update_id()
+{
+    g_rom_flashchip.device_id = bootloader_read_flash_id();
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+    SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S);
+    SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
+{
+    uint32_t spi_clk_div = 0;
+    switch (pfhdr->spi_speed) {
+        case ESP_IMAGE_SPI_SPEED_80M:
+            spi_clk_div = 1;
+            break;
+        case ESP_IMAGE_SPI_SPEED_40M:
+            spi_clk_div = 2;
+            break;
+        case ESP_IMAGE_SPI_SPEED_26M:
+            spi_clk_div = 3;
+            break;
+        case ESP_IMAGE_SPI_SPEED_20M:
+            spi_clk_div = 4;
+            break;
+        default:
+            break;
+    }
+    esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
+{
+
+}
+
+void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
+{
+    int spi_cache_dummy = 0;
+    int drv = 2;
+    switch (pfhdr->spi_mode) {
+    case ESP_IMAGE_SPI_MODE_QIO:
+        spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
+        break;
+    case ESP_IMAGE_SPI_MODE_DIO:
+        spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;   //qio 3
+        break;
+    case ESP_IMAGE_SPI_MODE_QOUT:
+    case ESP_IMAGE_SPI_MODE_DOUT:
+    default:
+        spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
+        break;
+    }
+
+    /* dummy_len_plus values defined in ROM for SPI flash configuration */
+    extern uint8_t g_rom_spiflash_dummy_len_plus[];
+    switch (pfhdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_80M:
+        g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
+        g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
+        SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
+                          SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+        drv = 3;
+        break;
+    case ESP_IMAGE_SPI_SPEED_40M:
+        g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
+        g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
+        SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
+                          SPI_MEM_USR_DUMMY_CYCLELEN_S);  //DUMMY
+        break;
+    default:
+        break;
+    }
+
+    bootloader_configure_spi_pins(drv);
+}

components/bootloader_support/src/bootloader_init.c

@@ -14,6 +14,7 @@
 #include <string.h>
 #include <stdint.h>
 #include "sdkconfig.h"
+#include "esp_attr.h"
 #include "esp_log.h"
 #include "bootloader_init.h"
 #include "bootloader_flash.h"
@@ -22,13 +23,15 @@
 #include "bootloader_clock.h"
 #include "bootloader_common.h"
 #include "esp_flash_encrypt.h"
+#include "hal/timer_ll.h"
 #include "soc/cpu.h"
 #include "soc/rtc.h"
-#include "hal/wdt_hal.h"
+#include "soc/rtc_wdt.h"
+
 
 static const char *TAG = "boot";
 
-esp_image_header_t bootloader_image_hdr;
+esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
 
 void bootloader_clear_bss_section(void)
 {
@@ -59,34 +62,21 @@ esp_err_t bootloader_check_bootloader_validity(void)
 
 void bootloader_config_wdt(void)
 {
-    /*
-     * At this point, the flashboot protection of RWDT and MWDT0 will have been
-     * automatically enabled. We can disable flashboot protection as it's not
-     * needed anymore. If configured to do so, we also initialize the RWDT to
-     * protect the remainder of the bootloader process.
-     */
-    //Disable RWDT flashboot protection.
-    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
-    wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-    wdt_hal_set_flashboot_en(&rtc_wdt_ctx, false);
-    wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
-    //Initialize and start RWDT to protect the  for bootloader if configured to do so
     ESP_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS);
-    wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
-    uint32_t stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
-    wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-    wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
-    wdt_hal_enable(&rtc_wdt_ctx);
-    wdt_hal_write_protect_enable(&rtc_wdt_ctx);
+    rtc_wdt_protect_off();
+    rtc_wdt_disable();
+    rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_3_2us);
+    rtc_wdt_set_length_of_reset_signal(RTC_WDT_CPU_RESET_SIG, RTC_WDT_LENGTH_3_2us);
+    rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_RTC);
+    rtc_wdt_set_time(RTC_WDT_STAGE0, CONFIG_BOOTLOADER_WDT_TIME_MS);
+    rtc_wdt_enable();
+    rtc_wdt_protect_on();
+#else /* disable watch dog */
+    rtc_wdt_disable();
 #endif
-
-    //Disable MWDT0 flashboot protection. But only after we've enabled the RWDT first so that there's not gap in WDT protection.
-    wdt_hal_context_t wdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
-    wdt_hal_write_protect_disable(&wdt_ctx);
-    wdt_hal_set_flashboot_en(&wdt_ctx, false);
-    wdt_hal_write_protect_enable(&wdt_ctx);
+    timer_ll_wdt_set_protect(&TIMERG0, false);
+    timer_ll_wdt_flashboot_en(&TIMERG0, false);
 }
 
 void bootloader_enable_random(void)

components/bootloader_support/src/bootloader_mem.c

@@ -1,48 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#include <stdbool.h>
-
-#include "xtensa/config/core.h"
-#include "hal/cpu_hal.h"
-#include "hal/mpu_hal.h"
-#include "hal/mpu_types.h"
-#include "soc/mpu_caps.h"
-#include "bootloader_mem.h"
-#include "xt_instr_macros.h"
-#include "xtensa/config/specreg.h"
-
-static inline void cpu_configure_region_protection(void)
-{
-    /* Currently, the only supported chips esp32 and esp32s2
-     * have the same configuration. Move this to the port layer once
-     * more chips with different configurations are supported.
-     * 
-     * Both chips have the address space divided into 8 regions, 512MB each.
-     */
-    const int illegal_regions[] = {0, 4, 5, 6, 7}; // 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
-    for (int i = 0; i < sizeof(illegal_regions) / sizeof(illegal_regions[0]); ++i) {
-        mpu_hal_set_region_access(illegal_regions[i], MPU_REGION_ILLEGAL);
-    }
-
-    mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
-}
-
-void bootloader_init_mem(void)
-{
-    cpu_hal_init_hwloop();
-
-    // protect memory region
-    cpu_configure_region_protection();
-}

components/bootloader_support/src/bootloader_random.c

@@ -11,7 +11,6 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#include "sdkconfig.h"
 #include "bootloader_random.h"
 #include "soc/cpu.h"
 #include "soc/wdev_reg.h"
@@ -21,10 +20,6 @@
 #include "soc/dport_reg.h"
 #include "soc/i2s_periph.h"
 #include "esp_log.h"
-#include "soc/io_mux_reg.h"
-#if CONFIG_IDF_TARGET_ESP32S2
-#include "soc/apb_saradc_reg.h"
-#endif
 
 #ifndef BOOTLOADER_BUILD
 #include "esp_system.h"
@@ -40,7 +35,9 @@ void bootloader_fill_random(void *buffer, size_t length)
 {
     uint8_t *buffer_bytes = (uint8_t *)buffer;
     uint32_t random;
+#if CONFIG_IDF_TARGET_ESP32
     uint32_t start, now;
+#endif
 
     assert(buffer != NULL);
 
@@ -53,12 +50,17 @@ void bootloader_fill_random(void *buffer, size_t length)
                as-is, we repeatedly read the RNG register and XOR all
                values.
             */
+#if CONFIG_IDF_TARGET_ESP32
             random = REG_READ(WDEV_RND_REG);
             RSR(CCOUNT, start);
             do {
                 random ^= REG_READ(WDEV_RND_REG);
                 RSR(CCOUNT, now);
             } while (now - start < 80 * 32 * 2); /* extra factor of 2 is precautionary */
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+            // ToDo: Get random from register
+            random = 12345678;
+#endif
         }
         buffer_bytes[i] = random >> ((i % 4) * 8);
     }
@@ -82,9 +84,9 @@ void bootloader_random_enable(void)
        Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M)
        in early bootloader startup must have been made.
     */
-#if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S);
     SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
+#if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
 
 #ifdef BOOTLOADER_BUILD
@@ -94,13 +96,7 @@ void bootloader_random_enable(void)
 #endif // BOOTLOADER_BUILD
     CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
     CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    /* Disable IO1 digital function for random function. */
-    PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U);
-    PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U);
-    PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U);
-    WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF);
-
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
     CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
@@ -111,42 +107,36 @@ void bootloader_random_enable(void)
     //--[7:4] channel_sel: 10-->en_test
     //--[3:2] bit_width  : 3-->12bit
     //--[1:0] atten      : 1-->3dB attenuation
-#if CONFIG_IDF_TARGET_ESP32
     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
     WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
+#if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
     SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
     SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
-    WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
-    WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
-    WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
     SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
 #endif
 
 #if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX);
+#endif
     SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S);
+
     SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */
+#if CONFIG_IDF_TARGET_ESP32
     SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S);
+#endif
     SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S);
     SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL);
     CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
+
     SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
+
     SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 4, APB_SARADC_SAR_CLK_DIV_S);
-    SET_PERI_REG_BITS(APB_SARADC_FSM_REG, APB_SARADC_RSTB_WAIT, 8, APB_SARADC_RSTB_WAIT_S); /* was 1 */
-    SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 0, APB_SARADC_WORK_MODE_S);
-    SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL);
-    CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_SAR_SEL);
-    SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
-    SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_TO_I2S);
-#endif
+
     CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
     SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
     SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
@@ -177,7 +167,7 @@ void bootloader_random_disable(void)
 #if CONFIG_IDF_TARGET_ESP32
     CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
     CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
 #endif
 
@@ -187,9 +177,9 @@ void bootloader_random_disable(void)
     CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
                         | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
     SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
-    CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S);
+    CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
     SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
 #endif
 
@@ -205,9 +195,7 @@ void bootloader_random_disable(void)
     periph_module_reset(PERIPH_I2S0_MODULE);
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32
     /* Disable pull supply voltage to SAR ADC */
     CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
     SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S);
-#endif
 }

components/bootloader_support/src/bootloader_utility.c

@@ -29,18 +29,16 @@
 #include "esp32/rom/uart.h"
 #include "esp32/rom/gpio.h"
 #include "esp32/rom/secure_boot.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/cache.h"
-#include "esp32s2/rom/efuse.h"
-#include "esp32s2/rom/ets_sys.h"
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/crc.h"
-#include "esp32s2/rom/rtc.h"
-#include "esp32s2/rom/uart.h"
-#include "esp32s2/rom/gpio.h"
-#include "esp32s2/rom/secure_boot.h"
-#include "soc/extmem_reg.h"
-#include "soc/cache_memory.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/cache.h"
+#include "esp32s2beta/rom/efuse.h"
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/spi_flash.h"
+#include "esp32s2beta/rom/crc.h"
+#include "esp32s2beta/rom/rtc.h"
+#include "esp32s2beta/rom/uart.h"
+#include "esp32s2beta/rom/gpio.h"
+#include "esp32s2beta/rom/secure_boot.h"
 #else
 #error "Unsupported IDF_TARGET"
 #endif
@@ -378,7 +376,7 @@ int bootloader_utility_get_selected_boot_partition(const bootloader_state_t *bs)
 #endif // CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
 
 #ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
-            if (otadata[active_otadata].ota_state == ESP_OTA_IMG_VALID) {
+            if(otadata[active_otadata].ota_state == ESP_OTA_IMG_VALID) {
                 update_anti_rollback(&bs->ota[boot_index]);
             }
 #endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
@@ -441,7 +439,7 @@ static void set_actual_ota_seq(const bootloader_state_t *bs, int index)
 void bootloader_utility_load_boot_image_from_deep_sleep(void)
 {
     if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) {
-        esp_partition_pos_t *partition = bootloader_common_get_rtc_retain_mem_partition();
+        esp_partition_pos_t* partition = bootloader_common_get_rtc_retain_mem_partition();
         if (partition != NULL) {
             esp_image_metadata_t image_data;
             if (bootloader_load_image_no_verify(partition, &image_data) == ESP_OK) {
@@ -623,7 +621,9 @@ static void load_image(const esp_image_metadata_t *image_data)
 #endif
 
     ESP_LOGI(TAG, "Disabling RNG early entropy source...");
+#if !CONFIG_IDF_ENV_FPGA
     bootloader_random_disable();
+#endif
 
     // copy loaded segments to RAM, set up caches for mapped segments, and start application
     unpack_load_app(image_data);
@@ -687,7 +687,7 @@ static void set_cache_and_start_app(
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Disable(0);
     Cache_Flush(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     uint32_t autoload = Cache_Suspend_ICache();
     Cache_Invalidate_ICache_All();
 #endif
@@ -695,23 +695,19 @@ static void set_cache_and_start_app(
     /* Clear the MMU entries that are already set up,
        so the new app only has the mappings it creates.
     */
-#if CONFIG_IDF_TARGET_ESP32
     for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
         DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
     }
-#elif CONFIG_IDF_TARGET_ESP32S2
-    for (int i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
-        FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
-    }
-#endif
+
     uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
     uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr);
     ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d",
              drom_addr & MMU_FLASH_MASK, drom_load_addr_aligned, drom_size, drom_page_count);
 #if CONFIG_IDF_TARGET_ESP32
     rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000,
+                                64, drom_page_count, 0);
 #endif
     ESP_LOGV(TAG, "rc=%d", rc);
 #if CONFIG_IDF_TARGET_ESP32
@@ -724,17 +720,27 @@ static void set_cache_and_start_app(
              irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count);
 #if CONFIG_IDF_TARGET_ESP32
     rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count);
-#elif CONFIG_IDF_TARGET_ESP32S2
-    uint32_t iram1_used = 0;
+    ESP_LOGV(TAG, "rc=%d", rc);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    uint32_t iram1_used = 0, irom0_used = 0;
     if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
         iram1_used = 1;
     }
-    if (iram1_used) {
-        rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1);
-        rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
-        REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
+    if (irom_load_addr + irom_size > IROM0_ADDRESS_LOW) {
+        irom0_used = 1;
     }
-    rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
+    if (iram1_used || irom0_used) {
+        rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1);
+        rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
+        REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1);
+        REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_IRAM1);
+        if (irom0_used) {
+            rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IROM0_ADDRESS_LOW, 0, 64, 64, 1);
+            REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0);
+            REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_IROM0);
+        }
+    }
+    rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
 #endif
     ESP_LOGV(TAG, "rc=%d", rc);
 #if CONFIG_IDF_TARGET_ESP32
@@ -748,12 +754,12 @@ static void set_cache_and_start_app(
                        (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) |
                        (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 |
                        DPORT_APP_CACHE_MASK_DRAM1 );
-#elif CONFIG_IDF_TARGET_ESP32S2
-    REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0 );
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    DPORT_REG_CLR_BIT( DPORT_PRO_ICACHE_CTRL1_REG, (DPORT_PRO_ICACHE_MASK_IRAM0) | (DPORT_PRO_ICACHE_MASK_IRAM1 & 0) | (DPORT_PRO_ICACHE_MASK_IROM0 & 0) | DPORT_PRO_ICACHE_MASK_DROM0 );
 #endif
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Enable(0);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     Cache_Resume_ICache(autoload);
 #endif
     // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)

components/bootloader_support/src/esp32/bootloader_esp32.c

@@ -22,12 +22,10 @@
 #include "bootloader_clock.h"
 #include "bootloader_common.h"
 #include "bootloader_flash_config.h"
-#include "bootloader_mem.h"
 
 #include "soc/cpu.h"
 #include "soc/dport_reg.h"
 #include "soc/efuse_reg.h"
-#include "soc/gpio_periph.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/io_mux_reg.h"
 #include "soc/rtc.h"
@@ -364,6 +362,9 @@ static void wdt_reset_info_dump(int cpu)
         lsstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG);
         lsaddr = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG);
         lsdata = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG);
+#else
+        ESP_LOGE(TAG, "WDT reset info: &s CPU not support!\n", cpu_name);
+        return;
 #endif
     }
 
@@ -404,16 +405,14 @@ static void bootloader_check_wdt_reset(void)
     if (wdt_rst) {
         // if reset by WDT dump info from trace port
         wdt_reset_info_dump(0);
-#if !CONFIG_FREERTOS_UNICORE
         wdt_reset_info_dump(1);
-#endif
     }
     wdt_reset_cpu0_info_enable();
 }
 
 void abort(void)
 {
-#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
+#if !CONFIG_ESP32_PANIC_SILENT_REBOOT
     ets_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3);
 #endif
     if (esp_cpu_in_ocd_debug_mode()) {
@@ -426,9 +425,10 @@ void abort(void)
 esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
-
-    bootloader_init_mem();
-
+    // workaround for tensilica erratum572
+    cpu_init_memctl();
+    // protect memory region
+    cpu_configure_region_protection();
     // check that static RAM is after the stack
 #ifndef NDEBUG
     {

components/bootloader_support/src/esp32/flash_encrypt.c

@@ -22,7 +22,7 @@
 #include "esp_efuse.h"
 #include "esp_log.h"
 #include "esp32/rom/secure_boot.h"
-#include "hal/wdt_hal.h"
+#include "soc/rtc_wdt.h"
 
 #include "esp32/rom/cache.h"
 #include "esp32/rom/spi_flash.h"   /* TODO: Remove this */
@@ -359,11 +359,8 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length)
         return ESP_FAIL;
     }
 
-    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
     for (size_t i = 0; i < data_length; i += FLASH_SECTOR_SIZE) {
-        wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-        wdt_hal_feed(&rtc_wdt_ctx);
-        wdt_hal_write_protect_enable(&rtc_wdt_ctx);
+        rtc_wdt_feed();
         uint32_t sec_start = i + src_addr;
         err = bootloader_flash_read(sec_start, buf, FLASH_SECTOR_SIZE, false);
         if (err != ESP_OK) {

components/bootloader_support/src/esp32s2beta/bootloader_esp32s2beta.c

@@ -15,23 +15,21 @@
 #include "sdkconfig.h"
 #include "bootloader_common.h"
 #include "soc/efuse_reg.h"
-#include "soc/gpio_periph.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/io_mux_reg.h"
-#include "esp32s2/rom/efuse.h"
-#include "esp32s2/rom/gpio.h"
-#include "esp32s2/rom/spi_flash.h"
+#include "esp32s2beta/rom/efuse.h"
+#include "esp32s2beta/rom/gpio.h"
+#include "esp32s2beta/rom/spi_flash.h"
 
 #include "bootloader_init.h"
 #include "bootloader_clock.h"
 #include "bootloader_flash_config.h"
-#include "bootloader_mem.h"
 
-#include "esp32s2/rom/cache.h"
-#include "esp32s2/rom/ets_sys.h"
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/rtc.h"
-#include "esp32s2/rom/uart.h"
+#include "esp32s2beta/rom/cache.h"
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/rom/spi_flash.h"
+#include "esp32s2beta/rom/rtc.h"
+#include "esp32s2beta/rom/uart.h"
 #include "esp_attr.h"
 #include "esp_log.h"
 #include "esp_image_format.h"
@@ -39,41 +37,54 @@
 #include "soc/assist_debug_reg.h"
 #include "soc/cpu.h"
 #include "soc/dport_reg.h"
-#include "soc/extmem_reg.h"
 #include "soc/rtc.h"
 #include "soc/spi_periph.h"
-#include <string.h>
 
 static const char *TAG = "boot.esp32s2";
+
+#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
+#define FLASH_CS_IO SPI_CS0_GPIO_NUM
+#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
+#define FLASH_SPID_IO SPI_D_GPIO_NUM
+#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
+#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
+
 void bootloader_configure_spi_pins(int drv)
 {
     const uint32_t spiconfig = ets_efuse_get_spiconfig();
-    uint8_t wp_pin = ets_efuse_get_wp_pad();
-    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
-    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
-    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
-    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
-    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
-    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
-    if (spiconfig == 0) {
+    if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
+        gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
+        gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
+        gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
+        gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
+        gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
+        gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
+        gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
+        gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
+        gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
+        //select pin function gpio
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIHD_U, PIN_FUNC_GPIO);
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIWP_U, PIN_FUNC_GPIO);
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICS0_U, PIN_FUNC_GPIO);
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIQ_U, PIN_FUNC_GPIO);
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPID_U, PIN_FUNC_GPIO);
+        // flash clock signal should come from IO MUX.
+        // set drive ability for clock
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, drv, FUN_DRV_S);
 
-    } else {
-        clk_gpio_num = spiconfig         & 0x3f;
-        q_gpio_num = (spiconfig >> 6)    & 0x3f;
-        d_gpio_num = (spiconfig >> 12)   & 0x3f;
-        cs0_gpio_num = (spiconfig >> 18) & 0x3f;
-        hd_gpio_num = (spiconfig >> 24)  & 0x3f;
-        wp_gpio_num = wp_pin;
-    }
-    gpio_pad_set_drv(clk_gpio_num, drv);
-    gpio_pad_set_drv(q_gpio_num,   drv);
-    gpio_pad_set_drv(d_gpio_num,   drv);
-    gpio_pad_set_drv(cs0_gpio_num, drv);
-    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
-        gpio_pad_set_drv(hd_gpio_num, drv);
-    }
-    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
-        gpio_pad_set_drv(wp_gpio_num, drv);
+#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64
+        uint32_t flash_id = g_rom_flashchip.device_id;
+        if (flash_id == FLASH_ID_GD25LQ32C) {
+            // Set drive ability for 1.8v flash in 80Mhz.
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIHD_U, FUN_DRV, 3, FUN_DRV_S);
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIWP_U, FUN_DRV, 3, FUN_DRV_S);
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICS0_U, FUN_DRV, 3, FUN_DRV_S);
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, 3, FUN_DRV_S);
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIQ_U, FUN_DRV, 3, FUN_DRV_S);
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPID_U, FUN_DRV, 3, FUN_DRV_S);
+        }
+#endif
     }
 }
 
@@ -86,7 +97,7 @@ static void bootloader_reset_mmu(void)
 
     /* normal ROM boot exits with DROM0 cache unmasked,
     but serial bootloader exits with it masked. */
-    REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
+    DPORT_REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0);
 }
 
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
@@ -190,6 +201,7 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
 
 static void IRAM_ATTR bootloader_init_flash_configure(void)
 {
+    bootloader_flash_gpio_config(&bootloader_image_hdr);
     bootloader_flash_dummy_config(&bootloader_image_hdr);
     bootloader_flash_cs_timing_config();
 }
@@ -224,7 +236,7 @@ static void bootloader_init_uart_console(void)
 #else // CONFIG_ESP_CONSOLE_UART_NONE
     const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
 
-    uartAttach(NULL);
+    uartAttach();
     ets_install_uart_printf();
 
     // Wait for UART FIFO to be empty.
@@ -239,15 +251,15 @@ static void bootloader_init_uart_console(void)
     uart_tx_switch(uart_num);
     // If console is attached to UART1 or if non-default pins are used,
     // need to reconfigure pins using GPIO matrix
-    if (uart_num != 0 || uart_tx_gpio != 43 || uart_rx_gpio != 44) {
-        // Change pin mode UART to GPIO
-        PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_GPIO44);
-        PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_GPIO43);
+    if (uart_num != 0 || uart_tx_gpio != 1 || uart_rx_gpio != 3) {
+        // Change pin mode for GPIO1/3 from UART to GPIO
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_GPIO3);
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_GPIO1);
         // Route GPIO signals to/from pins
         // (arrays should be optimized away by the compiler)
-        const uint32_t tx_idx_list[2] = {U0TXD_OUT_IDX, U1TXD_OUT_IDX};
-        const uint32_t rx_idx_list[2] = {U0RXD_IN_IDX, U1RXD_IN_IDX};
-        const uint32_t uart_reset[2] = {DPORT_UART_RST, DPORT_UART1_RST};
+        const uint32_t tx_idx_list[3] = {U0TXD_OUT_IDX, U1TXD_OUT_IDX, U2TXD_OUT_IDX};
+        const uint32_t rx_idx_list[3] = {U0RXD_IN_IDX, U1RXD_IN_IDX, U2RXD_IN_IDX};
+        const uint32_t uart_reset[3] = {DPORT_UART_RST, DPORT_UART1_RST, DPORT_UART2_RST};
         const uint32_t tx_idx = tx_idx_list[uart_num];
         const uint32_t rx_idx = rx_idx_list[uart_num];
 
@@ -317,7 +329,7 @@ static void bootloader_check_wdt_reset(void)
 
     rst_reas[0] = rtc_get_reset_reason(0);
     if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
-        rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
+            rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
         ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
         wdt_rst = 1;
     }
@@ -330,7 +342,7 @@ static void bootloader_check_wdt_reset(void)
 
 void abort(void)
 {
-#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
+#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
     ets_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3);
 #endif
     if (esp_cpu_in_ocd_debug_mode()) {
@@ -340,19 +352,11 @@ void abort(void)
     }
 }
 
-static void bootloader_super_wdt_auto_feed(void)
-{
-    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
-}
-
 esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
-    bootloader_super_wdt_auto_feed();
     // protect memory region
-
-    bootloader_init_mem();
-
+    cpu_configure_region_protection();
     /* check that static RAM is after the stack */
 #ifndef NDEBUG
     {

components/bootloader_support/src/esp32s2beta/bootloader_sha.c

@@ -17,7 +17,7 @@
 #include <assert.h>
 #include <sys/param.h>
 
-#include "esp32s2/rom/sha.h"
+#include "esp32s2beta/rom/sha.h"
 
 static SHA_CTX ctx;
 

components/bootloader_support/src/esp32s2beta/flash_encrypt.c

@@ -22,103 +22,69 @@
 #include "esp_flash_partitions.h"
 #include "esp_secure_boot.h"
 #include "esp_log.h"
-#include "esp32s2/rom/secure_boot.h"
-#include "esp32s2/rom/cache.h"
-#include "esp32s2/rom/efuse.h"
-#include "esp_efuse.h"
-#include "esp_efuse_table.h"
-#include "hal/wdt_hal.h"
+#include "esp32s2beta/rom/secure_boot.h"
+#include "esp32s2beta/rom/cache.h"
+#include "esp32s2beta/rom/efuse.h"
 
 static const char *TAG = "flash_encrypt";
 
 /* Static functions for stages of flash encryption */
 static esp_err_t initialise_flash_encryption(void);
-static esp_err_t encrypt_flash_contents(uint32_t flash_crypt_cnt, bool flash_crypt_wr_dis) __attribute__((unused));
+static esp_err_t encrypt_flash_contents(uint32_t flash_crypt_cnt, bool flash_crypt_wr_dis);
 static esp_err_t encrypt_bootloader(void);
 static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partition_table, int *num_partitions);
 static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partition);
 
 esp_err_t esp_flash_encrypt_check_and_update(void)
 {
-    uint8_t flash_crypt_wr_dis = 0;
-    uint32_t flash_crypt_cnt = 0;
+    // TODO: not clear why this is read from DATA1 and written to PGM_DATA2
+    uint32_t cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT);
+    ESP_LOGV(TAG, "SPI_BOOT_CRYPT_CNT 0x%x", cnt);
 
-    esp_efuse_read_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &flash_crypt_cnt, 3);
-    esp_efuse_read_field_blob(ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT, &flash_crypt_wr_dis, 1);
-
-    ESP_LOGV(TAG, "SPI_BOOT_CRYPT_CNT 0x%x", flash_crypt_cnt);
-    ESP_LOGV(TAG, "EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT 0x%x", flash_crypt_wr_dis);
+    bool flash_crypt_wr_dis = false; // TODO: check if CRYPT_CNT is write disabled
 
     _Static_assert(EFUSE_SPI_BOOT_CRYPT_CNT == 0x7, "assuming CRYPT_CNT is only 3 bits wide");
 
-    if (__builtin_parity(flash_crypt_cnt) == 1) {
+    if (cnt == 1 || cnt == 3 || cnt == 7) {
         /* Flash is already encrypted */
-        int left = (flash_crypt_cnt == 1) ? 1 : 0;
-        if (flash_crypt_wr_dis) {
-            left = 0; /* can't update FLASH_CRYPT_CNT, no more flashes */
+        int left;
+        if (cnt == 7 /* || disabled */) {
+            left = 0;
+        } else if (cnt == 3) {
+            left = 1;
+        } else {
+            left = 2;
         }
         ESP_LOGI(TAG, "flash encryption is enabled (%d plaintext flashes left)", left);
         return ESP_OK;
-    } else {
-
-#ifndef CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED
+    }
+    else {
         /* Flash is not encrypted, so encrypt it! */
-        return encrypt_flash_contents(flash_crypt_cnt, flash_crypt_wr_dis);
-#else
-        ESP_LOGE(TAG, "flash encryption is not enabled, and SECURE_FLASH_REQUIRE_ALREADY_ENABLED "
-                      "is set, refusing to boot.");
-        return ESP_ERR_INVALID_STATE;
-#endif // CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED
-
+        return encrypt_flash_contents(cnt, flash_crypt_wr_dis);
     }
 }
 
-static bool s_key_dis_read(ets_efuse_block_t block)
+static esp_err_t initialise_flash_encryption(void)
 {
-    unsigned key_num = block - ETS_EFUSE_BLOCK_KEY0;
-    return REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG, EFUSE_RD_DIS) & (EFUSE_RD_DIS_KEY0 << key_num);
-}
+    /* Before first flash encryption pass, need to initialise key & crypto config */
 
-static bool s_key_dis_write(ets_efuse_block_t block)
-{
-    unsigned key_num = block - ETS_EFUSE_BLOCK_KEY0;
-    return REG_GET_FIELD(EFUSE_RD_WR_DIS_REG, EFUSE_WR_DIS) & (EFUSE_WR_DIS_KEY0 << key_num);
-}
+    /* Find out if a key is already set */
+    bool has_aes128 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, NULL);
+    bool has_aes256_1 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1, NULL);
+    bool has_aes256_2 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2, NULL);
 
-static esp_err_t check_and_generate_encryption_keys(void)
-{
-    esp_err_t err = ESP_ERR_INVALID_STATE;
-    ets_efuse_block_t aes_128_key_block;
-    ets_efuse_block_t aes_256_key_block_1;
-    ets_efuse_block_t aes_256_key_block_2;
-
-    bool has_aes128 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY, &aes_128_key_block);
-    bool has_aes256_1 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1, &aes_256_key_block_1);
-    bool has_aes256_2 = ets_efuse_find_purpose(ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2, &aes_256_key_block_2);
     bool has_key = has_aes128 || (has_aes256_1 && has_aes256_2);
-    bool dis_write = false;
-    bool dis_read = false;
-
-    // If there are keys set, they must be write and read protected!
-    if(has_key && has_aes128) {
-        dis_write = s_key_dis_write(aes_128_key_block);
-        dis_read = s_key_dis_read(aes_128_key_block);
-    } else if (has_key && has_aes256_1 && has_aes256_2) {
-        dis_write = s_key_dis_write(aes_256_key_block_1) && s_key_dis_write(aes_256_key_block_2);
-        dis_read = s_key_dis_read(aes_256_key_block_1) && s_key_dis_read(aes_256_key_block_2);
-    }
 
     if (!has_key && (has_aes256_1 || has_aes256_2)) {
         ESP_LOGE(TAG, "Invalid efuse key blocks: Both AES-256 key blocks must be set.");
         return ESP_ERR_INVALID_STATE;
     }
 
-    if(has_key && (!dis_read || !dis_write)) {
-        ESP_LOGE(TAG, "Invalid key state, a key was set but not read and write protected.");
-        return ESP_ERR_INVALID_STATE;
-    }
+    if (has_key) {
+        ESP_LOGI(TAG, "Using pre-existing key in efuse");
 
-    if(!has_key && !dis_write && !dis_read) {
+        ESP_LOGE(TAG, "TODO: Check key is read & write protected"); // TODO
+    } else {
         ESP_LOGI(TAG, "Generating new flash encryption key...");
 #ifdef CONFIG_SECURE_FLASH_ENCRYPTION_AES256
         const unsigned BLOCKS_NEEDED = 2;
@@ -136,84 +102,26 @@ static esp_err_t check_and_generate_encryption_keys(void)
         }
 
         for(ets_efuse_purpose_t purpose = PURPOSE_START; purpose <= PURPOSE_END; purpose++) {
-            uint32_t buf[8] = {0};
+            uint32_t buf[8];
             bootloader_fill_random(buf, sizeof(buf));
             ets_efuse_block_t block = ets_efuse_find_unused_key_block();
             ESP_LOGD(TAG, "Writing ETS_EFUSE_BLOCK_KEY%d with purpose %d",
                      block - ETS_EFUSE_BLOCK_KEY0, purpose);
-
-            /* Note: everything else in this function is deferred as a batch write, but we write the
-               key (and write protect it) immediately as it's too fiddly to manage unused key blocks, etc.
-               in bootloader size footprint otherwise. */
+            bootloader_debug_buffer(buf, sizeof(buf), "Key content");
             int r = ets_efuse_write_key(block, purpose, buf, sizeof(buf));
+            bzero(buf, sizeof(buf));
             if (r != 0) {
-                ESP_LOGE(TAG, "Failed to write efuse block %d with purpose %d. Can't continue.",
-                        block, purpose);
+                ESP_LOGE(TAG, "Failed to write efuse block %d with purpose %d. Can't continue.");
                 return ESP_FAIL;
             }
-
-            /* assuming numbering of esp_efuse_block_t matches ets_efuse_block_t */
-            _Static_assert((int)EFUSE_BLK_KEY0 == (int)ETS_EFUSE_BLOCK_KEY0, "esp_efuse_block_t doesn't match ets_efuse_block_t");
-            _Static_assert((int)EFUSE_BLK_KEY1 == (int)ETS_EFUSE_BLOCK_KEY1, "esp_efuse_block_t doesn't match ets_efuse_block_t");
-            _Static_assert((int)EFUSE_BLK_KEY2 == (int)ETS_EFUSE_BLOCK_KEY2, "esp_efuse_block_t doesn't match ets_efuse_block_t");
-            _Static_assert((int)EFUSE_BLK_KEY3 == (int)ETS_EFUSE_BLOCK_KEY3, "esp_efuse_block_t doesn't match ets_efuse_block_t");
-            _Static_assert((int)EFUSE_BLK_KEY4 == (int)ETS_EFUSE_BLOCK_KEY4, "esp_efuse_block_t doesn't match ets_efuse_block_t");
-            _Static_assert((int)EFUSE_BLK_KEY5 == (int)ETS_EFUSE_BLOCK_KEY5, "esp_efuse_block_t doesn't match ets_efuse_block_t");
-
-            // protect this block against reading after key is set (writing is done by ets_efuse_write_key)
-            err = esp_efuse_set_read_protect(block);
-            if(err != ESP_OK) {
-                ESP_LOGE(TAG, "Failed to set read protect to efuse block %d. Can't continue.", block);
-                return err;
-            }
         }
+
         ESP_LOGD(TAG, "Key generation complete");
-        return ESP_OK;
-
-    } else {
-        ESP_LOGI(TAG, "Using pre-existing key in efuse");
-        return ESP_OK;
-    }
-}
-
-static esp_err_t initialise_flash_encryption(void)
-{
-    esp_efuse_batch_write_begin(); /* Batch all efuse writes at the end of this function */
-
-    esp_err_t key_state = check_and_generate_encryption_keys();
-    if(key_state != ESP_OK) {
-        esp_efuse_batch_write_cancel();
-        return key_state;
     }
 
-#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
-    ESP_LOGI(TAG, "Disable UART bootloader encryption...");
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
-#else
-    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
-#endif
+    ESP_LOGE(TAG, "TODO: burn remaining security protection bits"); // TODO
 
-#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
-    ESP_LOGI(TAG, "Disable UART bootloader cache...");
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
-#else
-    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
-#endif
-
-#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
-    ESP_LOGI(TAG, "Disable JTAG...");
-    esp_efuse_write_field_bit(ESP_EFUSE_HARD_DIS_JTAG);
-#else
-    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
-#endif
-
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP);
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT);
-
-    esp_err_t err = esp_efuse_batch_write_commit();
-
-    return err;
+    return ESP_OK;
 }
 
 /* Encrypt all flash data that should be encrypted */
@@ -226,7 +134,7 @@ static esp_err_t encrypt_flash_contents(uint32_t spi_boot_crypt_cnt, bool flash_
     /* If the last spi_boot_crypt_cnt bit is burned or write-disabled, the
        device can't re-encrypt itself. */
     if (flash_crypt_wr_dis || spi_boot_crypt_cnt == EFUSE_SPI_BOOT_CRYPT_CNT) {
-        ESP_LOGE(TAG, "Cannot re-encrypt data SPI_BOOT_CRYPT_CNT 0x%02x write disabled %d", spi_boot_crypt_cnt, flash_crypt_wr_dis);
+        ESP_LOGE(TAG, "Cannot re-encrypt data (SPI_BOOT_CRYPT_CNT 0x%02x write disabled %d", spi_boot_crypt_cnt, flash_crypt_wr_dis);
         return ESP_FAIL;
     }
 
@@ -248,7 +156,10 @@ static esp_err_t encrypt_flash_contents(uint32_t spi_boot_crypt_cnt, bool flash_
         return err;
     }
 
-    /* Now iterate the just-loaded partition table, looking for entries to encrypt */
+    /* Now iterate the just-loaded partition table, looking for entries to encrypt
+     */
+
+    /* Go through each partition and encrypt if necessary */
     for (int i = 0; i < num_partitions; i++) {
         err = encrypt_partition(i, &partition_table[i]);
         if (err != ESP_OK) {
@@ -261,17 +172,13 @@ static esp_err_t encrypt_flash_contents(uint32_t spi_boot_crypt_cnt, bool flash_
     /* Set least significant 0-bit in spi_boot_crypt_cnt */
     int ffs_inv = __builtin_ffs((~spi_boot_crypt_cnt) & 0x7);
     /* ffs_inv shouldn't be zero, as zero implies spi_boot_crypt_cnt == 0xFF */
-    uint32_t new_spi_boot_crypt_cnt = (1 << (ffs_inv - 1));
-    ESP_LOGD(TAG, "SPI_BOOT_CRYPT_CNT 0x%x -> 0x%x", spi_boot_crypt_cnt, new_spi_boot_crypt_cnt + spi_boot_crypt_cnt);
+    uint32_t new_spi_boot_crypt_cnt = spi_boot_crypt_cnt + (1 << (ffs_inv - 1));
+    ESP_LOGD(TAG, "SPI_BOOT_CRYPT_CNT 0x%x -> 0x%x", spi_boot_crypt_cnt, new_spi_boot_crypt_cnt);
 
-    esp_efuse_write_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &new_spi_boot_crypt_cnt, 3);
+    ets_efuse_clear_program_registers();
+    REG_SET_FIELD(EFUSE_PGM_DATA2_REG, EFUSE_SPI_BOOT_CRYPT_CNT, new_spi_boot_crypt_cnt);
+    ets_efuse_program(ETS_EFUSE_BLOCK0);
 
-#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
-    //Secure SPI boot cnt after its update if needed.
-    const uint32_t spi_boot_cnt_wr_dis = 1;
-    ESP_LOGI(TAG, "Write protecting SPI_CRYPT_CNT eFuse");
-    esp_efuse_write_field_blob(ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT, &spi_boot_cnt_wr_dis, 1);
-#endif
     ESP_LOGI(TAG, "Flash encryption completed");
 
     return ESP_OK;
@@ -284,30 +191,21 @@ static esp_err_t encrypt_bootloader(void)
     /* Check for plaintext bootloader (verification will fail if it's already encrypted) */
     if (esp_image_verify_bootloader(&image_length) == ESP_OK) {
         ESP_LOGD(TAG, "bootloader is plaintext. Encrypting...");
-
-#if CONFIG_SECURE_BOOT_V2_ENABLED
-        // Account for the signature sector after the bootloader
-        image_length = (image_length + FLASH_SECTOR_SIZE - 1) & ~(FLASH_SECTOR_SIZE - 1);
-        image_length += FLASH_SECTOR_SIZE;
-        if (ESP_BOOTLOADER_OFFSET + image_length > ESP_PARTITION_TABLE_OFFSET) {
-            ESP_LOGE(TAG, "Bootloader is too large to fit Secure Boot V2 signature sector and partition table (configured offset 0x%x)", ESP_PARTITION_TABLE_OFFSET);
-            return ESP_ERR_INVALID_SIZE;
-        }
-#endif // CONFIG_SECURE_BOOT_V2_ENABLED
-
         err = esp_flash_encrypt_region(ESP_BOOTLOADER_OFFSET, image_length);
         if (err != ESP_OK) {
             ESP_LOGE(TAG, "Failed to encrypt bootloader in place: 0x%x", err);
             return err;
-        } 
-        
-        ESP_LOGI(TAG, "bootloader encrypted successfully");
-        return err;
+        }
+
+        if (esp_secure_boot_enabled()) {
+            // TODO: anything different for secure boot?
+        }
     }
     else {
         ESP_LOGW(TAG, "no valid bootloader was found");
-        return ESP_ERR_NOT_FOUND;
     }
+
+    return ESP_OK;
 }
 
 static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partition_table, int *num_partitions)
@@ -334,7 +232,6 @@ static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partitio
     }
 
     /* Valid partition table loded */
-    ESP_LOGI(TAG, "partition table encrypted and loaded successfully");
     return ESP_OK;
 }
 
@@ -383,13 +280,7 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length)
         return ESP_FAIL;
     }
 
-    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
     for (size_t i = 0; i < data_length; i += FLASH_SECTOR_SIZE) {
-
-        wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-        wdt_hal_feed(&rtc_wdt_ctx);
-        wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
         uint32_t sec_start = i + src_addr;
         err = bootloader_flash_read(sec_start, buf, FLASH_SECTOR_SIZE, false);
         if (err != ESP_OK) {

components/bootloader_support/src/esp32s2beta/secure_boot.c

@@ -13,7 +13,7 @@
 // limitations under the License.
 #include "esp_secure_boot.h"
 #include "esp_log.h"
-#include "esp32s2/rom/secure_boot.h"
+#include "esp32s2beta/rom/secure_boot.h"
 
 static const char *TAG = "secure_boot";
 
@@ -34,20 +34,12 @@ esp_err_t esp_secure_boot_permanently_enable(void)
         return r;
     }
 
-    esp_efuse_batch_write_begin(); /* Batch all efuse writes at the end of this function */
+    ets_efuse_clear_program_registers();
+    REG_SET_BIT(EFUSE_PGM_DATA3_REG, EFUSE_SECURE_BOOT_EN);
+    ets_efuse_program(ETS_EFUSE_BLOCK0);
 
-    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP);
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT);
-
-    // TODO: also disable JTAG here, etc
-
-    esp_err_t err = esp_efuse_batch_write_commit();
-
-    if (err == ESP_OK) {
-        assert(ets_efuse_secure_boot_enabled());
-        ESP_LOGI(TAG, "Secure boot permanently enabled");
-    }
+    assert(ets_efuse_secure_boot_enabled());
+    ESP_LOGI(TAG, "Secure boot permanently enabled");
 
     return ESP_OK;
 }

components/bootloader_support/src/esp32s2beta/secure_boot_signatures.c

@@ -17,7 +17,7 @@
 #include "bootloader_sha.h"
 #include "esp_log.h"
 #include "esp_image_format.h"
-#include "esp32s2/rom/secure_boot.h"
+#include "esp32s2beta/rom/secure_boot.h"
 
 static const char* TAG = "secure_boot";
 

components/bootloader_support/src/esp_image_format.c

@@ -27,11 +27,11 @@
 #include "bootloader_common.h"
 #include "soc/soc_memory_layout.h"
 #if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/rtc.h"
-#include "esp32/rom/secure_boot.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/rtc.h"
-#include "esp32s2/rom/secure_boot.h"
+#include <esp32/rom/rtc.h>
+#include <esp32/rom/secure_boot.h>
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include <esp32s2beta/rom/rtc.h>
+#include <esp32s2beta/rom/secure_boot.h>
 #endif
 
 /* Checking signatures as part of verifying images is necessary:
@@ -104,7 +104,7 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
     bool do_verify = (mode == ESP_IMAGE_LOAD) || (mode == ESP_IMAGE_VERIFY) || (mode == ESP_IMAGE_VERIFY_SILENT);
 #else
     bool do_load   = false; // Can't load the image in app mode
-    bool do_verify = true;  // In app mode is available only verify mode
+    bool do_verify = true;	// In app mode is avalible only verify mode
 #endif
     bool silent    = (mode == ESP_IMAGE_VERIFY_SILENT);
     esp_err_t err = ESP_OK;

components/bootloader_support/src/flash_encrypt.c

@@ -20,14 +20,6 @@
 #include "esp_flash_encrypt.h"
 #include "esp_secure_boot.h"
 
-#if CONFIG_IDF_TARGET_ESP32
-#define CRYPT_CNT ESP_EFUSE_FLASH_CRYPT_CNT
-#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT
-#elif CONFIG_IDF_TARGET_ESP32S2
-#define CRYPT_CNT ESP_EFUSE_SPI_BOOT_CRYPT_CNT
-#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT
-#endif
-
 #ifndef BOOTLOADER_BUILD
 static const char *TAG = "flash_encrypt";
 
@@ -41,16 +33,10 @@ void esp_flash_encryption_init_checks()
 #ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
 #ifdef CONFIG_SECURE_BOOT
     if (esp_secure_boot_enabled() && esp_flash_encryption_enabled()) {
-        bool flash_crypt_cnt_wr_dis = esp_efuse_read_field_bit(WR_DIS_CRYPT_CNT);
+        uint8_t flash_crypt_cnt_wr_dis = 0;
+        esp_efuse_read_field_blob(ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT, &flash_crypt_cnt_wr_dis, 1);
         if (!flash_crypt_cnt_wr_dis) {
-            uint8_t flash_crypt_cnt = 0;
-            esp_efuse_read_field_blob(CRYPT_CNT, &flash_crypt_cnt,  CRYPT_CNT[0]->bit_count);
-            if (flash_crypt_cnt == (1<<(CRYPT_CNT[0]->bit_count))-1) {
-                // If encryption counter is already max, no need to write protect it
-                // (this distinction is important on ESP32 ECO3 where write-procted FLASH_CRYPT_CNT also write-protects UART_DL_DIS)
-                return;
-            }
-            ESP_EARLY_LOGE(TAG, "Flash encryption & Secure Boot together requires FLASH_CRYPT_CNT efuse to be write protected. Fixing now...");
+            ESP_LOGE(TAG, "Flash encryption & Secure Boot together requires FLASH_CRYPT_CNT efuse to be write protected. Fixing now...");
             esp_flash_write_protect_crypt_cnt();
         }
     }
@@ -62,59 +48,43 @@ void esp_flash_encryption_init_checks()
     mode = esp_get_flash_encryption_mode();
     if (mode == ESP_FLASH_ENC_MODE_DEVELOPMENT) {
 #ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
-        ESP_EARLY_LOGE(TAG, "Flash encryption settings error: app is configured for RELEASE but efuses are set for DEVELOPMENT");
-        ESP_EARLY_LOGE(TAG, "Mismatch found in security options in bootloader menuconfig and efuse settings. Device is not secure.");
+        ESP_LOGE(TAG, "Flash encryption settings error: app is configured for RELEASE but efuses are set for DEVELOPMENT");
+        ESP_LOGE(TAG, "Mismatch found in security options in bootloader menuconfig and efuse settings. Device is not secure.");
 #else
-        ESP_EARLY_LOGW(TAG, "Flash encryption mode is DEVELOPMENT (not secure)");
+        ESP_LOGW(TAG, "Flash encryption mode is DEVELOPMENT (not secure)");
 #endif
     } else if (mode == ESP_FLASH_ENC_MODE_RELEASE) {
-        ESP_EARLY_LOGI(TAG, "Flash encryption mode is RELEASE");
+        ESP_LOGI(TAG, "Flash encryption mode is RELEASE");
     }
 }
 #endif
 
 void esp_flash_write_protect_crypt_cnt(void)
 {
-    esp_efuse_write_field_bit(WR_DIS_CRYPT_CNT);
+    uint8_t flash_crypt_cnt_wr_dis = 0;
+    esp_efuse_read_field_blob(ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT, &flash_crypt_cnt_wr_dis, 1);
+    if (!flash_crypt_cnt_wr_dis) {
+        esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT, 1);
+    }
 }
 
 esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
 {
     uint8_t efuse_flash_crypt_cnt_wr_protected = 0;
-#if CONFIG_IDF_TARGET_ESP32   
     uint8_t dis_dl_enc = 0, dis_dl_dec = 0, dis_dl_cache = 0;
-#elif CONFIG_IDF_TARGET_ESP32S2
-    uint8_t  dis_dl_enc = 0; 
-    uint8_t dis_dl_icache = 0; 
-    uint8_t dis_dl_dcache = 0; 
-
-#endif
-
     esp_flash_enc_mode_t mode = ESP_FLASH_ENC_MODE_DEVELOPMENT;
 
     if (esp_flash_encryption_enabled()) {
         /* Check if FLASH CRYPT CNT is write protected */
-        efuse_flash_crypt_cnt_wr_protected = esp_efuse_read_field_bit(WR_DIS_CRYPT_CNT);
-
+        esp_efuse_read_field_blob(ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT, &efuse_flash_crypt_cnt_wr_protected, 1);
         if (efuse_flash_crypt_cnt_wr_protected) {
-
-#if CONFIG_IDF_TARGET_ESP32
-            dis_dl_cache = esp_efuse_read_field_bit(ESP_EFUSE_DISABLE_DL_CACHE);
-            dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DISABLE_DL_ENCRYPT);
-            dis_dl_dec = esp_efuse_read_field_bit(ESP_EFUSE_DISABLE_DL_DECRYPT);
+            esp_efuse_read_field_blob(ESP_EFUSE_DISABLE_DL_CACHE, &dis_dl_cache, 1);
+            esp_efuse_read_field_blob(ESP_EFUSE_DISABLE_DL_ENCRYPT, &dis_dl_enc, 1);
+            esp_efuse_read_field_blob(ESP_EFUSE_DISABLE_DL_DECRYPT, &dis_dl_dec, 1);
             /* Check if DISABLE_DL_DECRYPT, DISABLE_DL_ENCRYPT & DISABLE_DL_CACHE are set */
             if ( dis_dl_cache && dis_dl_enc && dis_dl_dec ) {
                 mode = ESP_FLASH_ENC_MODE_RELEASE;
             }
-#elif CONFIG_IDF_TARGET_ESP32S2
-            dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
-            dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
-            dis_dl_dcache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
-
-            if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
-                mode = ESP_FLASH_ENC_MODE_RELEASE;
-            }
-#endif
         }
     } else {
         mode = ESP_FLASH_ENC_MODE_DISABLED;

components/bootloader_support/src/flash_qio_mode.c

@@ -19,9 +19,9 @@
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/spi_flash.h"
 #include "esp32/rom/efuse.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/efuse.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/spi_flash.h"
+#include "esp32s2beta/rom/efuse.h"
 #include "soc/spi_mem_struct.h"
 #endif
 #include "soc/spi_struct.h"
@@ -33,7 +33,7 @@
 /* SPI flash controller */
 #if CONFIG_IDF_TARGET_ESP32
 #define SPIFLASH SPI1
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
 #define SPIFLASH SPIMEM1
 #endif
 
@@ -141,7 +141,7 @@ uint32_t bootloader_read_flash_id(void)
     return id;
 }
 
-#if CONFIG_IDF_TARGET_ESP32S2
+#if CONFIG_IDF_TARGET_ESP32S2BETA
 #define FLASH_WRAP_CMD   0x77
 typedef enum {
     FLASH_WRAP_MODE_8B  = 0,
@@ -212,7 +212,7 @@ void bootloader_enable_qio_mode(void)
     enable_qio_mode(chip_data[i].read_status_fn,
                     chip_data[i].write_status_fn,
                     chip_data[i].status_qio_bit);
-#if CONFIG_IDF_TARGET_ESP32S2
+#if CONFIG_IDF_TARGET_ESP32S2BETA
     spi_flash_wrap_set(FLASH_WRAP_MODE_DISABLE);
 #endif
 }
@@ -277,7 +277,7 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
 
 #if CONFIG_IDF_TARGET_ESP32
     esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     if (ets_efuse_get_wp_pad() <= MAX_PAD_GPIO_NUM) {
         esp_rom_spiflash_select_qio_pins(ets_efuse_get_wp_pad(), spiconfig);
     } else {
@@ -340,7 +340,7 @@ static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8
     uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
 #if CONFIG_IDF_TARGET_ESP32
     SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
 #endif
     SPIFLASH.user.usr_dummy = 0;
@@ -352,13 +352,13 @@ static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8
     SPIFLASH.user.usr_miso = miso_len > 0;
 #if CONFIG_IDF_TARGET_ESP32
     SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
 #endif
     SPIFLASH.user.usr_mosi = mosi_len > 0;
 #if CONFIG_IDF_TARGET_ESP32
     SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
     SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
 #endif
     SPIFLASH.data_buf[0] = mosi_data;

components/bootloader_support/test/CMakeLists.txt

@@ -1,3 +1,3 @@
 idf_component_register(SRC_DIRS "."
-                    PRIV_INCLUDE_DIRS "."
-                    PRIV_REQUIRES unity bootloader_support app_update)
+                    INCLUDE_DIRS "."
+                    REQUIRES unity bootloader_support app_update)

components/bootloader_support/test/test_verify_image.c

@@ -33,7 +33,7 @@ TEST_CASE("Verify bootloader image in flash", "[bootloader_support]")
     TEST_ASSERT_EQUAL(data.image_len, bootloader_length);
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
 TEST_CASE("Verify unit test app image", "[bootloader_support]")
 {
     esp_image_metadata_t data = { 0 };

components/bt/CMakeLists.txt

@@ -47,7 +47,6 @@ if(CONFIG_BT_ENABLED)
             host/bluedroid/btc/profile/esp/blufi/include
             host/bluedroid/btc/profile/esp/include
             host/bluedroid/btc/profile/std/a2dp/include
-            host/bluedroid/btc/profile/std/hid/include
             host/bluedroid/btc/profile/std/include
             host/bluedroid/btc/include
             host/bluedroid/stack/btm/include
@@ -167,8 +166,6 @@ if(CONFIG_BT_ENABLED)
                    "host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c"
                    "host/bluedroid/btc/profile/std/hf_client/btc_hf_client.c"
                    "host/bluedroid/btc/profile/std/hf_client/bta_hf_client_co.c"
-                   "host/bluedroid/btc/profile/std/hid/hidh_api.c"
-                   "host/bluedroid/btc/profile/std/hid/hidh_conn.c"
                    "host/bluedroid/btc/profile/std/gap/btc_gap_ble.c"
                    "host/bluedroid/btc/profile/std/gap/btc_gap_bt.c"
                    "host/bluedroid/btc/profile/std/gap/bta_gap_bt_co.c"
@@ -539,15 +536,13 @@ if(CONFIG_BT_ENABLED)
 
         endif()
     endif()
-
 endif()
 
 # requirements can't depend on config
 idf_component_register(SRCS "${srcs}"
                 INCLUDE_DIRS "${include_dirs}"
                 PRIV_INCLUDE_DIRS "${priv_include_dirs}"
-                REQUIRES nvs_flash soc esp_timer
-                PRIV_REQUIRES esp_ipc)
+                REQUIRES nvs_flash soc)
 
 if(CONFIG_BT_ENABLED)
     target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-implicit-fallthrough -Wno-unused-const-variable)

components/bt/Kconfig

@@ -1,5 +1,4 @@
 menu "Bluetooth"
-    visible if IDF_TARGET_ESP32
 
     config BT_ENABLED
         bool "Bluetooth"
@@ -433,7 +432,6 @@ endmenu
 
 menuconfig BLE_MESH
     bool "ESP BLE Mesh Support"
-    depends on BT_ENABLED
     help
         This option enables ESP BLE Mesh support. The specific features that are
         available may depend on other features that have been enabled in the

components/bt/component.mk

@@ -45,7 +45,6 @@ COMPONENT_PRIV_INCLUDEDIRS +=   host/bluedroid/bta/include                   \
                                 host/bluedroid/btc/profile/std/gatt/include  \
                                 host/bluedroid/btc/profile/std/gap/include   \
                                 host/bluedroid/btc/profile/std/a2dp/include  \
-                                host/bluedroid/btc/profile/std/hid/include   \
                                 host/bluedroid/btc/profile/std/include       \
                                 host/bluedroid/btc/include                   \
                                 host/bluedroid/btif/include                  \
@@ -97,7 +96,6 @@ COMPONENT_SRCDIRS +=    host/bluedroid/bta/dm                      \
                         host/bluedroid/btc/profile/std/spp         \
                         host/bluedroid/btc/profile/std/hf_ag       \
                         host/bluedroid/btc/profile/std/hf_client   \
-                        host/bluedroid/btc/profile/std/hid         \
                         host/bluedroid/btc/profile                 \
                         host/bluedroid/stack/btm                   \
                         host/bluedroid/stack/btu                   \

components/bt/esp_ble_mesh/api/esp_ble_mesh_defs.h

@@ -458,11 +458,11 @@ typedef struct {
 struct esp_ble_mesh_model {
     /** Model ID */
     union {
-        const uint16_t model_id; /*!< 16-bit model identifier */
+        const uint16_t model_id;
         struct {
-            uint16_t company_id; /*!< 16-bit company identifier */
-            uint16_t model_id; /*!< 16-bit model identifier */
-        } vnd; /*!< Structure encapsulating a model ID with a company ID */
+            uint16_t company_id;
+            uint16_t model_id;
+        } vnd;
     };
 
     /** Internal information, mainly for persistent storage */
@@ -675,7 +675,7 @@ typedef struct {
 typedef struct {
     union {
         struct {
-            esp_ble_mesh_bd_addr_t addr;         /*!< Device address */
+            esp_ble_mesh_bd_addr_t addr;             /*!< Device address */
             esp_ble_mesh_addr_type_t addr_type;  /*!< Device address type */
         };
         uint8_t uuid[16];                   /*!< Device UUID */

components/bt/host/bluedroid/Kconfig.in

@@ -99,13 +99,6 @@ config BT_HFP_WBS_ENABLE
         This enables Wide Band Speech. Should disable it when SCO data path is PCM.
         Otherwise there will be no data transmited via GPIOs.
 
-config BT_HID_HOST_ENABLED
-    bool "Classic BT HID Host"
-    depends on BT_CLASSIC_ENABLED
-    default n
-    help
-        This enables the BT HID Host
-
 config BT_SSP_ENABLED
     bool "Secure Simple Pairing"
     depends on BT_CLASSIC_ENABLED

components/bt/host/bluedroid/api/esp_gatt_common_api.c

@@ -49,10 +49,35 @@ esp_err_t esp_ble_gatt_set_local_mtu (uint16_t mtu)
 }
 
 #if (BLE_INCLUDED == TRUE)
-extern uint16_t L2CA_GetFreePktBufferNum_LE(void);
+extern UINT16 L2CA_GetFreePktBufferNum_LE(void);
 
-uint16_t esp_ble_get_sendable_packets_num ()
+/**
+ * @brief           This function is called to get currently sendable packets number on controller,
+ *                  the function is called only in BLE running core and single connection now.
+ *
+ * @return
+ *                  sendable packets number on controller
+ *
+ */
+ 
+uint16_t esp_ble_get_sendable_packets_num (void)
 {
     return L2CA_GetFreePktBufferNum_LE();
 }
+
+/**
+ * @brief           This function is used to query the number of available buffers for the current connection.
+ *                  When you need to query the current available buffer number, it is recommended to use this API.
+ * @param[in]       conn_id: current connection id.
+ * 
+ * @return
+ *                  Number of available buffers for the current connection
+ *
+ */
+ 
+extern UINT16 L2CA_GetCurFreePktBufferNum_LE(UINT16 conn_id);
+uint16_t esp_ble_get_cur_sendable_packets_num (uint16_t connid)
+{
+    return L2CA_GetCurFreePktBufferNum_LE(connid);
+}
 #endif

components/bt/host/bluedroid/api/esp_gattc_api.c

@@ -431,7 +431,9 @@ esp_err_t esp_ble_gattc_write_char(esp_gatt_if_t gattc_if,
     arg.write_char.value = value;
     arg.write_char.write_type = write_type;
     arg.write_char.auth_req = auth_req;
-
+    if(write_type == ESP_GATT_WRITE_TYPE_NO_RSP){
+        l2ble_update_att_acl_pkt_num(L2CA_ADD_BTC_NUM, NULL);
+    }
     return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_gattc_args_t), btc_gattc_arg_deep_copy) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
 }
 
@@ -461,7 +463,9 @@ esp_err_t esp_ble_gattc_write_char_descr (esp_gatt_if_t gattc_if,
     arg.write_descr.value = value;
     arg.write_descr.write_type = write_type;
     arg.write_descr.auth_req = auth_req;
-
+    if(write_type == ESP_GATT_WRITE_TYPE_NO_RSP){
+        l2ble_update_att_acl_pkt_num(L2CA_ADD_BTC_NUM, NULL);
+    }
     return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_gattc_args_t), btc_gattc_arg_deep_copy) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
 }
 

components/bt/host/bluedroid/api/esp_gatts_api.c

@@ -273,7 +273,9 @@ esp_err_t esp_ble_gatts_send_indicate(esp_gatt_if_t gatts_if, uint16_t conn_id,
     arg.send_ind.need_confirm = need_confirm;
     arg.send_ind.value_len = value_len;
     arg.send_ind.value = value;
-
+    if(need_confirm == false){
+        l2ble_update_att_acl_pkt_num(L2CA_ADD_BTC_NUM, NULL);
+    }
     return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_gatts_args_t),
                                  btc_gatts_arg_deep_copy) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
 }

components/bt/host/bluedroid/api/include/api/esp_a2dp_api.h

@@ -31,8 +31,7 @@ extern "C" {
 
 typedef uint8_t esp_a2d_mct_t;
 
-/** A2DP media codec capabilities union
- */
+/// A2DP media codec capabilities union
 typedef struct {
     esp_a2d_mct_t type;                        /*!< A2DP media codec type */
 #define ESP_A2D_CIE_LEN_SBC          (4)
@@ -40,10 +39,10 @@ typedef struct {
 #define ESP_A2D_CIE_LEN_M24          (6)
 #define ESP_A2D_CIE_LEN_ATRAC        (7)
     union {
-        uint8_t sbc[ESP_A2D_CIE_LEN_SBC];      /*!< SBC codec capabilities */
-        uint8_t m12[ESP_A2D_CIE_LEN_M12];      /*!< MPEG-1,2 audio codec capabilities */
-        uint8_t m24[ESP_A2D_CIE_LEN_M24];      /*!< MPEG-2, 4 AAC audio codec capabilities */
-        uint8_t atrac[ESP_A2D_CIE_LEN_ATRAC];  /*!< ATRAC family codec capabilities */
+        uint8_t sbc[ESP_A2D_CIE_LEN_SBC];
+        uint8_t m12[ESP_A2D_CIE_LEN_M12];
+        uint8_t m24[ESP_A2D_CIE_LEN_M24];
+        uint8_t atrac[ESP_A2D_CIE_LEN_ATRAC];
     } cie;                                     /*!< A2DP codec information element */
 } __attribute__((packed)) esp_a2d_mcc_t;
 

components/bt/host/bluedroid/api/include/api/esp_blufi_api.h

@@ -83,6 +83,7 @@ typedef enum {
     ESP_BLUFI_DH_PARAM_ERROR,
     ESP_BLUFI_READ_PARAM_ERROR,
     ESP_BLUFI_MAKE_PUBLIC_ERROR,
+    ESP_BLUFI_DATA_FORMAT_ERROR,
 } esp_blufi_error_state_t;
 
 /**

components/bt/host/bluedroid/api/include/api/esp_bt_defs.h

@@ -86,9 +86,9 @@ typedef struct {
 #define ESP_UUID_LEN_128    16
     uint16_t len;							/*!< UUID length, 16bit, 32bit or 128bit */
     union {
-        uint16_t    uuid16;                 /*!< 16bit UUID */
-        uint32_t    uuid32;                 /*!< 32bit UUID */
-        uint8_t     uuid128[ESP_UUID_LEN_128]; /*!< 128bit UUID */
+        uint16_t    uuid16;
+        uint32_t    uuid32;
+        uint8_t     uuid128[ESP_UUID_LEN_128];
     } uuid;									/*!< UUID */
 } __attribute__((packed)) esp_bt_uuid_t;
 

components/bt/host/bluedroid/api/include/api/esp_gatt_common_api.h

@@ -46,6 +46,7 @@ extern esp_err_t esp_ble_gatt_set_local_mtu (uint16_t mtu);
 
 #if (BLE_INCLUDED == TRUE)
 extern uint16_t esp_ble_get_sendable_packets_num (void);
+extern uint16_t esp_ble_get_cur_sendable_packets_num (uint16_t connid);
 #endif
 
 #ifdef __cplusplus

components/bt/host/bluedroid/bta/gatt/bta_gattc_api.c

@@ -31,7 +31,7 @@
 #include "bta/bta_sys.h"
 #include "bta/bta_gatt_api.h"
 #include "bta_gattc_int.h"
-
+#include "stack/l2c_api.h"
 /*****************************************************************************
 **  Constants
 *****************************************************************************/
@@ -602,7 +602,10 @@ void BTA_GATTC_WriteCharValue ( UINT16 conn_id,
             p_buf->p_value = (UINT8 *)(p_buf + 1);
             memcpy(p_buf->p_value, p_value, len);
         }
-
+        if(write_type == BTA_GATTC_TYPE_WRITE_NO_RSP){
+            l2ble_update_att_acl_pkt_num(L2CA_DECREASE_BTC_NUM, NULL);
+            l2ble_update_att_acl_pkt_num(L2CA_ADD_BTU_NUM, NULL);
+        }
         bta_sys_sendmsg(p_buf);
     }
     return;
@@ -649,7 +652,10 @@ void BTA_GATTC_WriteCharDescr (UINT16 conn_id,
             /* pack the descr data */
             memcpy(p_buf->p_value, p_data->p_value, p_data->len);
         }
-
+        if(write_type == BTA_GATTC_TYPE_WRITE_NO_RSP){
+            l2ble_update_att_acl_pkt_num(L2CA_DECREASE_BTC_NUM, NULL);
+            l2ble_update_att_acl_pkt_num(L2CA_ADD_BTU_NUM, NULL);
+        }
         bta_sys_sendmsg(p_buf);
     }
     return;

components/bt/host/bluedroid/bta/gatt/bta_gatts_act.c

@@ -674,6 +674,7 @@ void bta_gatts_indicate_handle (tBTA_GATTS_CB *p_cb, tBTA_GATTS_DATA *p_msg)
                                                       p_msg->api_indicate.len,
                                                       p_msg->api_indicate.value);
             } else {
+                l2ble_update_att_acl_pkt_num(L2CA_DECREASE_BTU_NUM, NULL);
                 status = GATTS_HandleValueNotification (p_msg->api_indicate.hdr.layer_specific,
                                                         p_msg->api_indicate.attr_id,
                                                         p_msg->api_indicate.len,

components/bt/host/bluedroid/bta/gatt/bta_gatts_api.c

@@ -31,6 +31,7 @@
 #include "bta/bta_gatt_api.h"
 #include "bta_gatts_int.h"
 #include "osi/allocator.h"
+#include "stack/l2c_api.h"
 
 /*****************************************************************************
 **  Constants
@@ -426,6 +427,10 @@ void BTA_GATTS_HandleValueIndication (UINT16 conn_id, UINT16 attr_id, UINT16 dat
             memcpy(p_buf->value, p_data, data_len);
 
         }
+        if(need_confirm == false){
+            l2ble_update_att_acl_pkt_num(L2CA_DECREASE_BTC_NUM, NULL);
+            l2ble_update_att_acl_pkt_num(L2CA_ADD_BTU_NUM, NULL);
+        }
         bta_sys_sendmsg(p_buf);
     }
     return;

components/bt/host/bluedroid/bta/hh/bta_hh_act.c

@@ -34,7 +34,6 @@
 #include "bta_hh_int.h"
 #include "bta/bta_hh_co.h"
 #include "bta/utl.h"
-#include "osi/allocator.h"
 
 /*****************************************************************************
 **  Constants
@@ -197,7 +196,7 @@ static void bta_hh_sdp_cback(UINT16 result, UINT16 attr_mask,
         }
 
 #if BTA_HH_DEBUG
-        APPL_TRACE_EVENT("bta_hh_sdp_cback: p_cb: %p result 0x%02x, \
+        APPL_TRACE_EVENT("bta_hh_sdp_cback: p_cb: %d result 0x%02x, \
                             attr_mask 0x%02x, handle %x", \
                          p_cb, result, attr_mask, p_cb->hid_handle);
 #endif
@@ -262,7 +261,7 @@ static void bta_hh_di_sdp_cback(UINT16 result)
     tSDP_DI_GET_RECORD  di_rec;
     tHID_STATUS ret;
 #if BTA_HH_DEBUG
-    APPL_TRACE_EVENT("bta_hh_di_sdp_cback: p_cb: %p result 0x%02x", p_cb, result);
+    APPL_TRACE_EVENT("bta_hh_di_sdp_cback: p_cb: %d result 0x%02x", p_cb, result);
 #endif
 
     /* if DI record does not exist on remote device, vendor_id in tBTA_HH_DEV_DSCP_INFO will be

components/bt/host/bluedroid/bta/hh/bta_hh_api.c

@@ -35,7 +35,7 @@
 #include "stack/l2c_api.h"
 #include "bta/utl.h"
 
-#include "osi/allocator.h"
+#include "osi/include/log.h"
 
 /*****************************************************************************
 **  Constants

components/bt/host/bluedroid/bta/hh/bta_hh_main.c

@@ -30,7 +30,6 @@
 
 #include "bta/bta_hh_api.h"
 #include "bta_hh_int.h"
-#include "osi/allocator.h"
 
 /*****************************************************************************
 ** Constants and types

components/bt/host/bluedroid/bta/hh/bta_hh_utils.c

@@ -20,7 +20,7 @@
 #include "common/bt_target.h"
 #if defined(BTA_HH_INCLUDED) && (BTA_HH_INCLUDED == TRUE)
 
-#include "osi/allocator.h"
+
 #include "bta_hh_int.h"
 
 /* if SSR max latency is not defined by remote device, set the default value

components/bt/host/bluedroid/btc/profile/esp/blufi/blufi_prf.c

@@ -433,11 +433,19 @@ static void btc_blufi_recv_handler(uint8_t *data, int len)
             blufi_env.aggr_buf = osi_malloc(blufi_env.total_len);
             if (blufi_env.aggr_buf == NULL) {
                 BTC_TRACE_ERROR("%s no mem, len %d\n", __func__, blufi_env.total_len);
+                btc_blufi_report_error(ESP_BLUFI_DH_MALLOC_ERROR);
                 return;
             }
         }
-        memcpy(blufi_env.aggr_buf + blufi_env.offset, hdr->data + 2, hdr->data_len  - 2);
-        blufi_env.offset += (hdr->data_len - 2);
+        if (blufi_env.offset + hdr->data_len  - 2 <= blufi_env.total_len){
+            memcpy(blufi_env.aggr_buf + blufi_env.offset, hdr->data + 2, hdr->data_len  - 2);
+            blufi_env.offset += (hdr->data_len - 2);
+        } else {
+            BTC_TRACE_ERROR("%s payload is longer than packet length, len %d \n", __func__, blufi_env.total_len);
+            btc_blufi_report_error(ESP_BLUFI_DATA_FORMAT_ERROR);
+            return;
+        }
+
     } else {
         if (blufi_env.offset > 0) {   /* if previous pkt is frag */
             memcpy(blufi_env.aggr_buf + blufi_env.offset, hdr->data, hdr->data_len);

components/bt/host/bluedroid/btc/profile/std/hid/hidh_api.c

@@ -1,583 +0,0 @@
-/******************************************************************************
- *
- *  Copyright (C) 2002-2012 Broadcom Corporation
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at:
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- ******************************************************************************/
-
-/******************************************************************************
- *
- *  This file contains the HID HOST API entry points
- *
- ******************************************************************************/
-
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-
-#include "common/bt_target.h"
-#include "osi/allocator.h"
-#include "stack/bt_types.h"
-#include "stack/hiddefs.h"
-#include "stack/hidh_api.h"
-#include "hidh_int.h"
-#include "stack/btm_api.h"
-#include "stack/btu.h"
-#include "btm_int.h"
-
-#if (HID_HOST_INCLUDED == TRUE)
-
-#if HID_DYNAMIC_MEMORY == FALSE
-tHID_HOST_CTB   hh_cb;
-#endif
-
-static void hidh_search_callback (UINT16 sdp_result);
-
-/*******************************************************************************
-**
-** Function         HID_HostGetSDPRecord
-**
-** Description      This function reads the device SDP record
-**
-** Returns          tHID_STATUS
-**
-*******************************************************************************/
-tHID_STATUS HID_HostGetSDPRecord ( BD_ADDR addr, tSDP_DISCOVERY_DB *p_db, UINT32 db_len,
-                                   tHID_HOST_SDP_CALLBACK *sdp_cback )
-{
-    tSDP_UUID   uuid_list;
-
-    if ( hh_cb.sdp_busy ) {
-        return HID_ERR_SDP_BUSY;
-    }
-
-    uuid_list.len = 2;
-    uuid_list.uu.uuid16 = UUID_SERVCLASS_HUMAN_INTERFACE;
-
-    hh_cb.p_sdp_db = p_db;
-    SDP_InitDiscoveryDb (p_db, db_len, 1, &uuid_list, 0, NULL);
-
-    if (SDP_ServiceSearchRequest (addr, p_db, hidh_search_callback)) {
-        hh_cb.sdp_cback = sdp_cback ;
-        hh_cb.sdp_busy = TRUE;
-        return HID_SUCCESS;
-    } else {
-        return HID_ERR_NO_RESOURCES;
-    }
-}
-
-void hidh_get_str_attr( tSDP_DISC_REC *p_rec, UINT16 attr_id, UINT16 max_len, char *str )
-{
-    tSDP_DISC_ATTR          *p_attr;
-    UINT16                  name_len;
-
-    if ((p_attr = SDP_FindAttributeInRec(p_rec, attr_id)) != NULL) {
-        if ((name_len = SDP_DISC_ATTR_LEN(p_attr->attr_len_type)) < max_len ) {
-            memcpy( str, (char *) p_attr->attr_value.v.array, name_len );
-            str[name_len] = '\0';
-        } else {
-            memcpy( str, (char *) p_attr->attr_value.v.array, max_len - 1 );
-            str[max_len - 1] = '\0';
-        }
-    } else {
-        str[0] = '\0';
-    }
-}
-
-
-static void hidh_search_callback (UINT16 sdp_result)
-{
-    tSDP_DISCOVERY_DB       *p_db = hh_cb.p_sdp_db;
-    tSDP_DISC_REC           *p_rec;
-    tSDP_DISC_ATTR          *p_attr, *p_subattr1, *p_subattr2, *p_repdesc;
-    tBT_UUID                hid_uuid;
-    tHID_DEV_SDP_INFO       *p_nvi = &hh_cb.sdp_rec;
-    UINT16                  attr_mask = 0;
-
-    hid_uuid.len       = LEN_UUID_16;
-    hid_uuid.uu.uuid16 = UUID_SERVCLASS_HUMAN_INTERFACE;
-
-    hh_cb.sdp_busy = FALSE;
-
-    if (sdp_result != SDP_SUCCESS) {
-        hh_cb.sdp_cback(sdp_result, 0, NULL);
-        return;
-    }
-
-    if ((p_rec = SDP_FindServiceUUIDInDb (p_db, &hid_uuid, NULL)) == NULL) {
-        hh_cb.sdp_cback(HID_SDP_NO_SERV_UUID, 0, NULL);
-        return;
-    }
-
-    memset (&hh_cb.sdp_rec, 0, sizeof( tHID_DEV_SDP_INFO ));
-
-    /* First, verify the mandatory fields we care about */
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_DESCRIPTOR_LIST)) == NULL)
-            || (SDP_DISC_ATTR_TYPE(p_attr->attr_len_type) != DATA_ELE_SEQ_DESC_TYPE)
-            || ((p_subattr1 = p_attr->attr_value.v.p_sub_attr) == NULL)
-            || (SDP_DISC_ATTR_TYPE(p_subattr1->attr_len_type) != DATA_ELE_SEQ_DESC_TYPE)
-            || ((p_subattr2 = p_subattr1->attr_value.v.p_sub_attr) == NULL)
-            || ((p_repdesc = p_subattr2->p_next_attr) == NULL)
-            || (SDP_DISC_ATTR_TYPE(p_repdesc->attr_len_type) != TEXT_STR_DESC_TYPE)) {
-        hh_cb.sdp_cback(HID_SDP_MANDATORY_MISSING, 0, NULL);
-        return;
-    }
-
-    if ((p_nvi->dscp_info.dl_len = SDP_DISC_ATTR_LEN(p_repdesc->attr_len_type)) != 0) {
-        p_nvi->dscp_info.dsc_list = (UINT8 *) &p_repdesc->attr_value;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_VIRTUAL_CABLE)) != NULL) &&
-            (p_attr->attr_value.v.u8) ) {
-        attr_mask |= HID_VIRTUAL_CABLE;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_RECONNECT_INITIATE)) != NULL) &&
-            (p_attr->attr_value.v.u8) ) {
-        attr_mask |= HID_RECONN_INIT;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_NORMALLY_CONNECTABLE)) != NULL) &&
-            (p_attr->attr_value.v.u8) ) {
-        attr_mask |= HID_NORMALLY_CONNECTABLE;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_SDP_DISABLE)) != NULL) &&
-            (p_attr->attr_value.v.u8) ) {
-        attr_mask |= HID_SDP_DISABLE;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_BATTERY_POWER)) != NULL) &&
-            (p_attr->attr_value.v.u8) ) {
-        attr_mask |= HID_BATTERY_POWER;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_REMOTE_WAKE)) != NULL) &&
-            (p_attr->attr_value.v.u8) ) {
-        attr_mask |= HID_REMOTE_WAKE;
-    }
-
-    hidh_get_str_attr( p_rec, ATTR_ID_SERVICE_NAME, HID_MAX_SVC_NAME_LEN, p_nvi->svc_name );
-    hidh_get_str_attr( p_rec, ATTR_ID_SERVICE_DESCRIPTION, HID_MAX_SVC_DESCR_LEN, p_nvi->svc_descr );
-    hidh_get_str_attr( p_rec, ATTR_ID_PROVIDER_NAME, HID_MAX_PROV_NAME_LEN, p_nvi->prov_name );
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_DEVICE_RELNUM)) != NULL)) {
-        p_nvi->rel_num = p_attr->attr_value.v.u16;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_COUNTRY_CODE)) != NULL)) {
-        p_nvi->ctry_code = p_attr->attr_value.v.u8;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_DEVICE_SUBCLASS)) != NULL)) {
-        p_nvi->sub_class = p_attr->attr_value.v.u8;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_PARSER_VERSION)) != NULL)) {
-        p_nvi->hpars_ver = p_attr->attr_value.v.u16;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_LINK_SUPERVISION_TO)) != NULL)) {
-        attr_mask |= HID_SUP_TOUT_AVLBL;
-        p_nvi->sup_timeout = p_attr->attr_value.v.u16;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_SSR_HOST_MAX_LAT)) != NULL)) {
-        attr_mask |= HID_SSR_MAX_LATENCY;
-        p_nvi->ssr_max_latency = p_attr->attr_value.v.u16;
-    } else {
-        p_nvi->ssr_max_latency = HID_SSR_PARAM_INVALID;
-    }
-
-    if (((p_attr = SDP_FindAttributeInRec (p_rec, ATTR_ID_HID_SSR_HOST_MIN_TOUT)) != NULL)) {
-        attr_mask |= HID_SSR_MIN_TOUT;
-        p_nvi->ssr_min_tout = p_attr->attr_value.v.u16;
-    } else {
-        p_nvi->ssr_min_tout = HID_SSR_PARAM_INVALID;
-    }
-
-    hh_cb.sdp_rec.p_sdp_layer_rec = p_rec;
-    hh_cb.sdp_cback(SDP_SUCCESS, attr_mask, &hh_cb.sdp_rec);
-}
-
-
-/*******************************************************************************
-**
-** Function         HID_HostInit
-**
-** Description      This function initializes the control block and trace variable
-**
-** Returns          void
-**
-*******************************************************************************/
-void HID_HostInit (void)
-{
-    memset(&hh_cb, 0, sizeof(tHID_HOST_CTB));
-
-#if defined(HID_INITIAL_TRACE_LEVEL)
-    hh_cb.trace_level = HID_INITIAL_TRACE_LEVEL;
-#else
-    hh_cb.trace_level = BT_TRACE_LEVEL_NONE;
-#endif
-}
-
-/*******************************************************************************
-**
-** Function         HID_HostSetTraceLevel
-**
-** Description      This function sets the trace level for HID Host. If called with
-**                  a value of 0xFF, it simply reads the current trace level.
-**
-** Returns          the new (current) trace level
-**
-*******************************************************************************/
-UINT8 HID_HostSetTraceLevel (UINT8 new_level)
-{
-    if (new_level != 0xFF) {
-        hh_cb.trace_level = new_level;
-    }
-
-    return (hh_cb.trace_level);
-}
-
-/*******************************************************************************
-**
-** Function         HID_HostRegister
-**
-** Description      This function registers HID-Host with lower layers
-**
-** Returns          tHID_STATUS
-**
-*******************************************************************************/
-tHID_STATUS HID_HostRegister (tHID_HOST_DEV_CALLBACK *dev_cback)
-{
-    tHID_STATUS st;
-
-    if ( hh_cb.reg_flag ) {
-        return HID_ERR_ALREADY_REGISTERED;
-    }
-
-    if ( dev_cback == NULL ) {
-        return HID_ERR_INVALID_PARAM;
-    }
-
-    /* Register with L2CAP */
-    if ( (st = hidh_conn_reg()) != HID_SUCCESS ) {
-        return st;
-    }
-
-    hh_cb.callback = dev_cback ;
-    hh_cb.reg_flag = TRUE;
-
-    return (HID_SUCCESS);
-}
-
-/*******************************************************************************
-**
-** Function         HID_HostDeregister
-**
-** Description      This function is called when the host is about power down.
-**
-** Returns          tHID_STATUS
-**
-*******************************************************************************/
-tHID_STATUS HID_HostDeregister(void)
-{
-    UINT8 i;
-
-    if ( !hh_cb.reg_flag ) {
-        return (HID_ERR_NOT_REGISTERED);
-    }
-
-    for ( i = 0; i < HID_HOST_MAX_DEVICES; i++ ) {
-        HID_HostRemoveDev( i ) ;
-    }
-
-    hidh_conn_dereg();
-    hh_cb.reg_flag = FALSE;
-
-    return (HID_SUCCESS) ;
-}
-
-/*******************************************************************************
-**
-** Function         HID_HostAddDev
-**
-** Description      This is called so HID-host may manage this device.
-**
-** Returns          tHID_STATUS
-**
-*******************************************************************************/
-tHID_STATUS HID_HostAddDev ( BD_ADDR addr, UINT16 attr_mask, UINT8 *handle )
-{
-    int i;
-    /* Find an entry for this device in hh_cb.devices array */
-    if ( !hh_cb.reg_flag ) {
-        return (HID_ERR_NOT_REGISTERED);
-    }
-
-    for ( i = 0; i < HID_HOST_MAX_DEVICES; i++) {
-        if ((hh_cb.devices[i].in_use) &&
-                (!memcmp(addr, hh_cb.devices[i].addr, BD_ADDR_LEN))) {
-            break;
-        }
-    }
-
-    if (i == HID_HOST_MAX_DEVICES ) {
-        for ( i = 0; i < HID_HOST_MAX_DEVICES; i++) {
-            if ( !hh_cb.devices[i].in_use) {
-                break;
-            }
-        }
-    }
-
-    if ( i == HID_HOST_MAX_DEVICES ) {
-        return HID_ERR_NO_RESOURCES;
-    }
-
-    if (!hh_cb.devices[i].in_use) {
-        hh_cb.devices[i].in_use = TRUE;
-        memcpy( hh_cb.devices[i].addr, addr, sizeof( BD_ADDR ) ) ;
-        hh_cb.devices[i].state = HID_DEV_NO_CONN;
-        hh_cb.devices[i].conn_tries = 0 ;
-    }
-
-    if (attr_mask != HID_ATTR_MASK_IGNORE) {
-        hh_cb.devices[i].attr_mask = attr_mask;
-    }
-
-    *handle = i;
-
-    return (HID_SUCCESS);
-}
-
-
-/*******************************************************************************
-**
-** Function         HID_HostRemoveDev
-**
-** Description      This removes the device from list devices that host has to manage.
-**
-** Returns          tHID_STATUS
-**
-*******************************************************************************/
-tHID_STATUS HID_HostRemoveDev ( UINT8 dev_handle )
-{
-    if ( !hh_cb.reg_flag ) {
-        return (HID_ERR_NOT_REGISTERED);
-    }
-
-    if ( (dev_handle >= HID_HOST_MAX_DEVICES) || (!hh_cb.devices[dev_handle].in_use) ) {
-        return HID_ERR_INVALID_PARAM;
-    }
-
-    HID_HostCloseDev( dev_handle ) ;
-    hh_cb.devices[dev_handle].in_use = FALSE;
-    hh_cb.devices[dev_handle].conn.conn_state = HID_CONN_STATE_UNUSED;
-    hh_cb.devices[dev_handle].conn.ctrl_cid = hh_cb.devices[dev_handle].conn.intr_cid = 0;
-    hh_cb.devices[dev_handle].attr_mask = 0;
-    return HID_SUCCESS;
-}
-
-/*******************************************************************************
-**
-** Function         HID_HostOpenDev
-**
-** Description      This function is called when the user wants to initiate a
-**                  connection attempt to a device.
-**
-** Returns          void
-**
-*******************************************************************************/
-tHID_STATUS HID_HostOpenDev ( UINT8 dev_handle )
-{
-    if ( !hh_cb.reg_flag ) {
-        return (HID_ERR_NOT_REGISTERED);
-    }
-
-    if ( (dev_handle >= HID_HOST_MAX_DEVICES) || (!hh_cb.devices[dev_handle].in_use) ) {
-        return HID_ERR_INVALID_PARAM;
-    }
-
-    if ( hh_cb.devices[dev_handle].state != HID_DEV_NO_CONN ) {
-        return HID_ERR_ALREADY_CONN;
-    }
-
-    hh_cb.devices[dev_handle].conn_tries = 1;
-    return hidh_conn_initiate( dev_handle );
-}
-
-/*******************************************************************************
-**
-** Function         HID_HostWriteDev
-**
-** Description      This function is called when the host has a report to send.
-**
-**                  report_id: is only used on GET_REPORT transaction if is specified.
-**                              only valid when it's a non-zero value.
-**
-** Returns          void
-**
-*******************************************************************************/
-tHID_STATUS HID_HostWriteDev( UINT8 dev_handle, UINT8 t_type,
-                              UINT8 param, UINT16 data, UINT8 report_id, BT_HDR *pbuf  )
-{
-    tHID_STATUS status = HID_SUCCESS;
-
-    if ( !hh_cb.reg_flag ) {
-        HIDH_TRACE_ERROR("HID_ERR_NOT_REGISTERED");
-        status = HID_ERR_NOT_REGISTERED;
-    }
-
-    if ( (dev_handle >= HID_HOST_MAX_DEVICES) || (!hh_cb.devices[dev_handle].in_use) ) {
-        HIDH_TRACE_ERROR("HID_ERR_INVALID_PARAM");
-        status = HID_ERR_INVALID_PARAM;
-    }
-
-    else if ( hh_cb.devices[dev_handle].state != HID_DEV_CONNECTED ) {
-        HIDH_TRACE_ERROR("HID_ERR_NO_CONNECTION dev_handle %d", dev_handle);
-        status = HID_ERR_NO_CONNECTION;
-    }
-
-    if (status != HID_SUCCESS) {
-        if (pbuf) {
-            osi_free ((void *)pbuf);
-        }
-    } else {
-        status = hidh_conn_snd_data( dev_handle, t_type, param, data, report_id, pbuf ) ;
-    }
-
-    return status;
-}
-
-/*******************************************************************************
-**
-** Function         HID_HostCloseDev
-**
-** Description      This function disconnects the device.
-**
-** Returns          void
-**
-*******************************************************************************/
-tHID_STATUS HID_HostCloseDev( UINT8 dev_handle )
-{
-    if ( !hh_cb.reg_flag ) {
-        return (HID_ERR_NOT_REGISTERED);
-    }
-
-    if ( (dev_handle >= HID_HOST_MAX_DEVICES) || (!hh_cb.devices[dev_handle].in_use) ) {
-        return HID_ERR_INVALID_PARAM;
-    }
-
-    hh_cb.devices[dev_handle].conn_tries = HID_HOST_MAX_CONN_RETRY + 1;
-    btu_stop_timer( &(hh_cb.devices[dev_handle].conn.timer_entry) ) ;
-
-    if ( hh_cb.devices[dev_handle].state != HID_DEV_CONNECTED ) {
-        return HID_ERR_NO_CONNECTION;
-    }
-
-    hh_cb.devices[dev_handle].conn_tries = HID_HOST_MAX_CONN_RETRY + 1;
-    return hidh_conn_disconnect( dev_handle );
-}
-
-tHID_STATUS HID_HostSetSecurityLevel( char serv_name[], UINT8 sec_lvl )
-{
-    if (!BTM_SetSecurityLevel (FALSE, serv_name, BTM_SEC_SERVICE_HIDH_SEC_CTRL,
-                               sec_lvl, HID_PSM_CONTROL, BTM_SEC_PROTO_HID, HID_SEC_CHN)) {
-        HIDH_TRACE_ERROR ("Security Registration 1 failed");
-        return (HID_ERR_NO_RESOURCES);
-    }
-
-    if (!BTM_SetSecurityLevel (TRUE, serv_name, BTM_SEC_SERVICE_HIDH_SEC_CTRL,
-                               sec_lvl, HID_PSM_CONTROL, BTM_SEC_PROTO_HID, HID_SEC_CHN)) {
-        HIDH_TRACE_ERROR ("Security Registration 2 failed");
-        return (HID_ERR_NO_RESOURCES);
-    }
-
-    if (!BTM_SetSecurityLevel (FALSE, serv_name, BTM_SEC_SERVICE_HIDH_NOSEC_CTRL,
-                               BTM_SEC_NONE, HID_PSM_CONTROL, BTM_SEC_PROTO_HID, HID_NOSEC_CHN)) {
-        HIDH_TRACE_ERROR ("Security Registration 3 failed");
-        return (HID_ERR_NO_RESOURCES);
-    }
-
-    if (!BTM_SetSecurityLevel (TRUE, serv_name, BTM_SEC_SERVICE_HIDH_NOSEC_CTRL,
-                               BTM_SEC_NONE, HID_PSM_CONTROL, BTM_SEC_PROTO_HID, HID_NOSEC_CHN)) {
-        HIDH_TRACE_ERROR ("Security Registration 4 failed");
-        return (HID_ERR_NO_RESOURCES);
-    }
-
-    if (!BTM_SetSecurityLevel (TRUE, serv_name, BTM_SEC_SERVICE_HIDH_INTR,
-                               BTM_SEC_NONE, HID_PSM_INTERRUPT, BTM_SEC_PROTO_HID, 0)) {
-        HIDH_TRACE_ERROR ("Security Registration 5 failed");
-        return (HID_ERR_NO_RESOURCES);
-    }
-
-    if (!BTM_SetSecurityLevel (FALSE, serv_name, BTM_SEC_SERVICE_HIDH_INTR,
-                               BTM_SEC_NONE, HID_PSM_INTERRUPT, BTM_SEC_PROTO_HID, 0)) {
-        HIDH_TRACE_ERROR ("Security Registration 6 failed");
-        return (HID_ERR_NO_RESOURCES);
-    }
-
-    return ( HID_SUCCESS );
-}
-
-/******************************************************************************
-**
-** Function         hid_known_hid_device
-**
-** Description      check if this device is  of type HID Device
-**
-** Returns          TRUE if device is HID Device else FALSE
-**
-*******************************************************************************/
-BOOLEAN hid_known_hid_device (BD_ADDR bd_addr)
-{
-    UINT8 i;
-    tBTM_INQ_INFO *p_inq_info = BTM_InqDbRead(bd_addr);
-
-    if ( !hh_cb.reg_flag ) {
-        return FALSE;
-    }
-
-    /* First  check for class of device , if Inq DB has information about this device*/
-    if (p_inq_info != NULL) {
-        /* Check if remote major device class is of type BTM_COD_MAJOR_PERIPHERAL */
-        if ((p_inq_info->results.dev_class[1] & BTM_COD_MAJOR_CLASS_MASK)
-                == BTM_COD_MAJOR_PERIPHERAL ) {
-            HIDH_TRACE_DEBUG("hid_known_hid_device:dev found in InqDB & COD matches HID dev");
-            return TRUE;
-        }
-    } else {
-        /* Look for this device in security device DB */
-        tBTM_SEC_DEV_REC  *p_dev_rec = btm_find_dev (bd_addr);
-        if ((p_dev_rec != NULL) &&
-                ((p_dev_rec->dev_class[1] & BTM_COD_MAJOR_CLASS_MASK) == BTM_COD_MAJOR_PERIPHERAL )) {
-            HIDH_TRACE_DEBUG("hid_known_hid_device:dev found in SecDevDB & COD matches HID dev");
-            return TRUE;
-        }
-    }
-
-    /* Find an entry for this device in hh_cb.devices array */
-    for ( i = 0; i < HID_HOST_MAX_DEVICES; i++) {
-        if ((hh_cb.devices[i].in_use) &&
-                (memcmp(bd_addr, hh_cb.devices[i].addr, BD_ADDR_LEN) == 0)) {
-            return TRUE;
-        }
-    }
-    /* Check if this device is marked as HID Device in IOP Dev */
-    HIDH_TRACE_DEBUG("hid_known_hid_device:remote is not HID device");
-    return FALSE;
-}
-
-#endif //HID_HOST_INCLUDED

components/bt/host/bluedroid/btc/profile/std/hid/include/hid_conn.h

@@ -25,9 +25,7 @@
 #ifndef HID_CONN_H
 #define HID_CONN_H
 
-#include "common/bt_defs.h"
 #if (HID_HOST_INCLUDED == TRUE)
-
 /* Define the HID Connection Block
 */
 typedef struct hid_conn {
@@ -58,6 +56,7 @@ typedef struct hid_conn {
     UINT16            rem_mtu_size;
     UINT16            disc_reason;                       /* Reason for disconnecting (for HID_HDEV_EVT_CLOSE) */
     TIMER_LIST_ENT    timer_entry;
+
 } tHID_CONN;
 
 #define HID_SEC_CHN   1

components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h

@@ -67,13 +67,6 @@
 #define UC_BT_HFP_CLIENT_ENABLED            FALSE
 #endif
 
-//HID HOST(BT)
-#ifdef CONFIG_BT_HID_HOST_ENABLED
-#define UC_BT_HID_HOST_ENABLED           	CONFIG_BT_HID_HOST_ENABLED
-#else
-#define UC_BT_HID_HOST_ENABLED           	FALSE
-#endif
-
 //SSP
 #ifdef CONFIG_BT_SSP_ENABLED
 #define UC_BT_SSP_ENABLED                   CONFIG_BT_SSP_ENABLED
@@ -299,10 +292,10 @@
 #define UC_BT_LOG_MCA_TRACE_LEVEL           UC_TRACE_LEVEL_WARNING
 #endif
 
-#ifdef CONFIG_BT_LOG_HIDH_TRACE_LEVEL
-#define UC_BT_LOG_HIDH_TRACE_LEVEL           CONFIG_BT_LOG_HIDH_TRACE_LEVEL
+#ifdef CONFIG_BT_LOG_HID_TRACE_LEVEL
+#define UC_BT_LOG_HID_TRACE_LEVEL           CONFIG_BT_LOG_HID_TRACE_LEVEL
 #else
-#define UC_BT_LOG_HIDH_TRACE_LEVEL           UC_TRACE_LEVEL_WARNING
+#define UC_BT_LOG_HID_TRACE_LEVEL           UC_TRACE_LEVEL_WARNING
 #endif
 
 #ifdef CONFIG_BT_LOG_APPL_TRACE_LEVEL

components/bt/host/bluedroid/common/include/common/bt_target.h

@@ -127,11 +127,6 @@
 #define BT_SSP_INCLUDED             TRUE
 #endif /* UC_BT_SSP_ENABLED */
 
-#if UC_BT_HID_HOST_ENABLED
-#define HID_HOST_INCLUDED           TRUE
-#define BTA_HH_INCLUDED             TRUE
-#endif /* UC_BT_HID_HOST_ENABLED */
-
 #endif /* UC_BT_CLASSIC_ENABLED */
 
 #ifndef CLASSIC_BT_INCLUDED

components/bt/host/bluedroid/common/include/common/bt_trace.h

@@ -198,7 +198,7 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l
 #define AVCT_INITIAL_TRACE_LEVEL            UC_BT_LOG_AVCT_TRACE_LEVEL
 #define AVRC_INITIAL_TRACE_LEVEL            UC_BT_LOG_AVRC_TRACE_LEVEL
 #define MCA_INITIAL_TRACE_LEVEL             UC_BT_LOG_MCA_TRACE_LEVEL
-#define HIDH_INITIAL_TRACE_LEVEL            UC_BT_LOG_HIDH_TRACE_LEVEL
+#define HID_INITIAL_TRACE_LEVEL             UC_BT_LOG_HID_TRACE_LEVEL
 #define APPL_INITIAL_TRACE_LEVEL            UC_BT_LOG_APPL_TRACE_LEVEL
 #define GATT_INITIAL_TRACE_LEVEL            UC_BT_LOG_GATT_TRACE_LEVEL
 #define SMP_INITIAL_TRACE_LEVEL             UC_BT_LOG_SMP_TRACE_LEVEL

components/bt/host/bluedroid/stack/gatt/gatt_cl.c

@@ -219,6 +219,7 @@ void gatt_act_write (tGATT_CLCB *p_clcb, UINT8 sec_act)
     if (p_attr) {
         switch (p_clcb->op_subtype) {
         case GATT_WRITE_NO_RSP:
+            l2ble_update_att_acl_pkt_num(L2CA_DECREASE_BTU_NUM, NULL);
             p_clcb->s_handle = p_attr->handle;
             op_code = (sec_act == GATT_SEC_SIGN_DATA) ? GATT_SIGN_CMD_WRITE : GATT_CMD_WRITE;
             rt = gatt_send_write_msg(p_tcb,

components/bt/host/bluedroid/stack/include/stack/l2c_api.h

@@ -29,6 +29,7 @@
 #include "common/bt_target.h"
 #include "stack/l2cdefs.h"
 #include "stack/hcidefs.h"
+#include "osi/fixed_queue.h"
 
 /*****************************************************************************
 **  Constants
@@ -1228,7 +1229,21 @@ extern UINT16 L2CA_GetDisconnectReason (BD_ADDR remote_bda, tBT_TRANSPORT transp
 
 extern BOOLEAN L2CA_CheckIsCongest(UINT16 fixed_cid, UINT16 handle);
 
+#define  L2CA_GET_ATT_NUM      0
+#define  L2CA_ADD_BTC_NUM      1
+#define  L2CA_DECREASE_BTC_NUM 2
+#define  L2CA_ADD_BTU_NUM      3
+#define  L2CA_DECREASE_BTU_NUM 4
+#define  L2CA_BUFF_INI         5
+#define  L2CA_BUFF_DEINIT      6
 
+typedef struct {
+    UINT16 conn_id;
+    UINT16 * get_num;
+} tl2c_buff_param_t;
+
+
+extern void l2ble_update_att_acl_pkt_num(UINT8 type, tl2c_buff_param_t *param);
 
 #ifdef __cplusplus
 }

components/bt/host/bluedroid/stack/l2cap/include/l2c_int.h

@@ -74,6 +74,8 @@
 #define L2CAP_DEFAULT_MONITOR_TOUT   12000        /* 12000 milliseconds */
 #define L2CAP_FCR_ACK_TOUT           200          /* 200 milliseconds */
 
+#define L2CAP_CACHE_ATT_ACL_NUM      10
+
 /* Define the possible L2CAP channel states. The names of
 ** the states may seem a bit strange, but they are taken from
 ** the Bluetooth specification.
@@ -165,6 +167,9 @@ typedef enum {
 
 #define L2CAP_MAX_FCR_CFG_TRIES         2       /* Config attempts before disconnecting */
 
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
 typedef uint8_t tL2C_BLE_FIXED_CHNLS_MASK;
 
 typedef struct {

components/bt/host/bluedroid/stack/l2cap/l2c_api.c

@@ -36,7 +36,7 @@
 #include "stack/btu.h"
 #include "stack/btm_api.h"
 #include "osi/allocator.h"
-
+#include "gatt_int.h"
 #if (CLASSIC_BT_INCLUDED == TRUE)
 /*******************************************************************************
 **
@@ -1877,6 +1877,15 @@ UINT16 L2CA_GetFreePktBufferNum_LE(void)
 {
     return l2cb.controller_le_xmit_window;
 }
+UINT16 L2CA_GetCurFreePktBufferNum_LE(UINT16 conn_id)
+{
+    uint16_t num = 0;
+    tl2c_buff_param_t param;
+    param.conn_id = conn_id;
+    param.get_num = #
+    l2ble_update_att_acl_pkt_num(L2CA_GET_ATT_NUM, &param);
+    return num;
+}
 #endif
 
 /*******************************************************************************
@@ -2265,3 +2274,108 @@ UINT16 L2CA_FlushChannel (UINT16 lcid, UINT16 num_to_flush)
     return (num_left);
 }
 
+/******************************************************************************
+**
+** Function         update_acl_pkt_num
+**
+** Description      Update the number of att acl packets to be sent in xmit_hold_q.
+**
+** Returns          None
+**
+*******************************************************************************/
+#if BLE_INCLUDED == TRUE
+void l2ble_update_att_acl_pkt_num(UINT8 type, tl2c_buff_param_t *param)
+{
+    static SemaphoreHandle_t buff_semaphore = NULL ;
+    static INT16 btc_buf;
+    static INT16 btu_buf;
+
+    if(buff_semaphore == NULL && type != L2CA_BUFF_INI){
+        L2CAP_TRACE_ERROR("%s buff_semaphore not init", __func__);
+        return;
+    }
+    switch (type)
+    {
+    case L2CA_ADD_BTC_NUM:{
+        xSemaphoreTake(buff_semaphore, portMAX_DELAY);
+        btc_buf ++;
+        xSemaphoreGive(buff_semaphore);
+        break;
+    }
+    case L2CA_DECREASE_BTC_NUM:{
+        xSemaphoreTake(buff_semaphore, portMAX_DELAY);
+        btc_buf --;
+        xSemaphoreGive(buff_semaphore);
+        break;
+    }
+    case L2CA_ADD_BTU_NUM:{
+        xSemaphoreTake(buff_semaphore, portMAX_DELAY);
+        btu_buf ++;
+        xSemaphoreGive(buff_semaphore);
+        break;
+    }
+    case L2CA_DECREASE_BTU_NUM:{
+        xSemaphoreTake(buff_semaphore, portMAX_DELAY);
+        btu_buf --;
+        xSemaphoreGive(buff_semaphore);
+        break;
+    }
+    case L2CA_GET_ATT_NUM:{
+        xSemaphoreTake(buff_semaphore, portMAX_DELAY);
+        INT16 att_acl_pkt_num = 0;
+        INT16 att_max_num = 0;
+        *(param->get_num) = 0;
+        UINT8 tcb_idx = param->conn_id;
+        tGATT_TCB * p_tcb = gatt_get_tcb_by_idx(tcb_idx);
+        if (p_tcb == NULL){
+            L2CAP_TRACE_ERROR("%s not found p_tcb", __func__);
+            xSemaphoreGive(buff_semaphore);
+            break;
+        }
+        tL2C_LCB * p_lcb = l2cu_find_lcb_by_bd_addr (p_tcb->peer_bda, BT_TRANSPORT_LE);
+        if (p_lcb == NULL){
+            L2CAP_TRACE_ERROR("%s not found p_lcb", __func__);
+            xSemaphoreGive(buff_semaphore);
+            break;
+        }
+        fixed_queue_t * queue = p_lcb->p_fixed_ccbs[L2CAP_ATT_CID - L2CAP_FIRST_FIXED_CHNL]->xmit_hold_q;
+        att_max_num = MIN(p_lcb->link_xmit_quota, L2CAP_CACHE_ATT_ACL_NUM);
+        if (queue == NULL){
+            L2CAP_TRACE_ERROR("%s not found queue", __func__);
+            xSemaphoreGive(buff_semaphore);
+            break;
+        }
+        att_acl_pkt_num = fixed_queue_length(queue);
+        if(att_acl_pkt_num < att_max_num){
+            if(btc_buf + btu_buf < att_max_num - att_acl_pkt_num){
+                *(param->get_num) = att_max_num - att_acl_pkt_num - (btc_buf + btu_buf);
+            }
+        }
+        xSemaphoreGive(buff_semaphore);
+        break;
+    }
+    case L2CA_BUFF_INI:{
+        btc_buf = 0;
+        btu_buf = 0;
+        buff_semaphore = xSemaphoreCreateBinary();
+        if (buff_semaphore == NULL) {
+            L2CAP_TRACE_ERROR("%s NO MEMORY", __func__);
+            break;
+        }
+        xSemaphoreGive(buff_semaphore);
+        break;
+    }
+    case L2CA_BUFF_DEINIT:{
+        xSemaphoreTake(buff_semaphore, portMAX_DELAY);
+        btc_buf = 0;
+        btu_buf = 0;
+        xSemaphoreGive(buff_semaphore);
+        vSemaphoreDelete(buff_semaphore);
+        buff_semaphore = NULL;
+        break;
+    }
+    default:
+        break;
+    }
+}
+#endif

components/bt/host/bluedroid/stack/l2cap/l2c_link.c

@@ -1131,6 +1131,12 @@ void l2c_link_check_send_pkts (tL2C_LCB *p_lcb, tL2C_CCB *p_ccb, BT_HDR *p_buf)
             while ((l2cb.controller_xmit_window != 0) && (p_lcb->sent_not_acked < p_lcb->link_xmit_quota))
 #endif
             {
+                //need check flag: partial_segment_being_sent
+                if ( (p_lcb->partial_segment_being_sent)
+                        || (p_lcb->link_state != LST_CONNECTED)
+                        || (L2C_LINK_CHECK_POWER_MODE (p_lcb)) ) {
+                    break;
+                }
                 //L2CAP_TRACE_DEBUG("l2cu_get_next_buffer_to_send = %p",l2cu_get_next_buffer_to_send(p_lcb));
                 if ((p_buf = l2cu_get_next_buffer_to_send (p_lcb)) == NULL) {
                     break;

components/bt/host/bluedroid/stack/l2cap/l2c_main.c

@@ -883,6 +883,9 @@ void l2c_init (void)
     if (l2cb.rcv_pending_q == NULL) {
         L2CAP_TRACE_ERROR("%s unable to allocate memory for link layer control block", __func__);
     }
+#if BLE_INCLUDED == TRUE
+    l2ble_update_att_acl_pkt_num(L2CA_BUFF_INI, NULL);
+#endif
 }
 
 void l2c_free(void)
@@ -892,6 +895,9 @@ void l2c_free(void)
 #if L2C_DYNAMIC_MEMORY
     FREE_AND_RESET(l2c_cb_ptr);
 #endif
+#if BLE_INCLUDED == TRUE
+    l2ble_update_att_acl_pkt_num(L2CA_BUFF_DEINIT, NULL);
+#endif
 }
 
 /*******************************************************************************

components/bt/host/bluedroid/stack/l2cap/l2c_utils.c

@@ -3662,7 +3662,7 @@ void l2cu_check_channel_congestion (tL2C_CCB *p_ccb)
         } else {
             tL2C_LCB *p_lcb = p_ccb->p_lcb;
             /* If this channel was not congested but it is congested now, tell the app */
-            if ((q_count > p_ccb->buff_quota) || (p_lcb && (p_ccb->local_cid == L2CAP_ATT_CID) && (p_lcb->link_xmit_quota > 0) && (p_lcb->link_xmit_quota <= p_lcb->sent_not_acked))) {
+            if (q_count > p_ccb->buff_quota || (p_lcb && (p_lcb->link_xmit_data_q) && (list_length(p_lcb->link_xmit_data_q) + q_count) > p_ccb->buff_quota)) {
                 p_ccb->cong_sent = TRUE;
                 if (p_ccb->p_rcb && p_ccb->p_rcb->api.pL2CA_CongestionStatus_Cb) {
                     L2CAP_TRACE_DEBUG ("L2CAP - Calling CongestionStatus_Cb (TRUE),CID:0x%04x,XmitQ:%u,Quota:%u",

components/bt/host/nimble/Kconfig.in

@@ -10,7 +10,6 @@ choice BT_NIMBLE_MEM_ALLOC_MODE
         - External SPIRAM memory only
         - Either internal or external memory based on default malloc()
           behavior in ESP-IDF
-        - Internal IRAM memory wherever applicable else internal DRAM
 
         Recommended mode here is always internal, since that is most preferred
         from security perspective. But if application requirement does not
@@ -27,16 +26,7 @@ choice BT_NIMBLE_MEM_ALLOC_MODE
     config BT_NIMBLE_MEM_ALLOC_MODE_DEFAULT
         bool "Default alloc mode"
 
-    config BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT
-        bool "Internal IRAM"
-        depends on ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
-        help
-            Allows to use IRAM memory region as 8bit accessible region.
-
-            Every unaligned (8bit or 16bit) access will result in an exception
-            and incur penalty of certain clock cycles per unaligned read/write.
-
-endchoice #BT_NIMBLE_MEM_ALLOC_MODE
+endchoice
 
 config BT_NIMBLE_MAX_CONNECTIONS
     int "Maximum number of concurrent connections"

components/bt/host/nimble/port/src/esp_nimble_mem.c

@@ -30,8 +30,6 @@ IRAM_ATTR void *nimble_platform_mem_malloc(size_t size)
     return heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
 #elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_EXTERNAL
     return heap_caps_malloc(size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT);
-#elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT
-    return heap_caps_malloc_prefer(size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
 #else
     return malloc(size);
 #endif
@@ -43,8 +41,6 @@ IRAM_ATTR void *nimble_platform_mem_calloc(size_t n, size_t size)
     return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
 #elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_EXTERNAL
     return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT);
-#elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT
-    return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
 #else
     return calloc(n, size);
 #endif

components/bt/test/CMakeLists.txt

@@ -1,5 +1,5 @@
 if(CONFIG_BT_ENABLED OR CMAKE_BUILD_EARLY_EXPANSION)
     idf_component_register(SRC_DIRS "."
-                        PRIV_INCLUDE_DIRS "."
-                        PRIV_REQUIRES unity nvs_flash bt)
+                        INCLUDE_DIRS "."
+                        REQUIRES unity nvs_flash bt)
 endif()

components/console/CMakeLists.txt

@@ -1,5 +1,4 @@
 idf_component_register(SRCS "commands.c"
-                            "esp_console_repl.c"
                             "split_argv.c"
                             "argtable3/argtable3.c"
                             "linenoise/linenoise.c"

components/console/argtable3/argtable3.c

@@ -3007,7 +3007,7 @@ static int trex_newnode(TRex *exp, TRexNodeType type)
 		exp->_nallocated *= 2;
 		exp->_nodes = (TRexNode *)realloc(exp->_nodes, exp->_nallocated * sizeof(TRexNode));
 	}
-	exp->_nodes[exp->_nsize++] = n; // NOLINT(clang-analyzer-unix.Malloc)
+	exp->_nodes[exp->_nsize++] = n;
 	newid = exp->_nsize - 1;
 	return (int)newid;
 }

components/console/commands.c

@@ -1,4 +1,4 @@
-// Copyright 2016-2019 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -18,7 +18,6 @@
 #include <sys/param.h>
 #include "esp_log.h"
 #include "esp_console.h"
-#include "esp_system.h"
 #include "linenoise/linenoise.h"
 #include "argtable3/argtable3.h"
 #include "sys/queue.h"
@@ -57,9 +56,6 @@ static const cmd_item_t *find_command_by_name(const char *name);
 
 esp_err_t esp_console_init(const esp_console_config_t *config)
 {
-    if (!config) {
-        return ESP_ERR_INVALID_ARG;
-    }
     if (s_tmp_line_buf) {
         return ESP_ERR_INVALID_STATE;
     }
@@ -80,10 +76,8 @@ esp_err_t esp_console_deinit(void)
         return ESP_ERR_INVALID_STATE;
     }
     free(s_tmp_line_buf);
-    s_tmp_line_buf = NULL;
     cmd_item_t *it, *tmp;
     SLIST_FOREACH_SAFE(it, &s_cmd_list, next, tmp) {
-        SLIST_REMOVE(&s_cmd_list, it, cmd_item_, next);
         free(it->hint);
         free(it);
     }
@@ -92,25 +86,18 @@ esp_err_t esp_console_deinit(void)
 
 esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd)
 {
-    cmd_item_t *item = NULL;
-    if (!cmd || cmd->command == NULL) {
+    cmd_item_t *item = (cmd_item_t *) calloc(1, sizeof(*item));
+    if (item == NULL) {
+        return ESP_ERR_NO_MEM;
+    }
+    if (cmd->command == NULL) {
+        free(item);
         return ESP_ERR_INVALID_ARG;
     }
     if (strchr(cmd->command, ' ') != NULL) {
+        free(item);
         return ESP_ERR_INVALID_ARG;
     }
-    item = (cmd_item_t *)find_command_by_name(cmd->command);
-    if (!item) {
-        // not registered before
-        item = calloc(1, sizeof(*item));
-        if (item == NULL) {
-            return ESP_ERR_NO_MEM;
-        }
-    } else {
-        // remove from list and free the old hint, because we will alloc new hint for the command
-        SLIST_REMOVE(&s_cmd_list, item, cmd_item_, next);
-        free(item->hint);
-    }
     item->command = cmd->command;
     item->help = cmd->help;
     if (cmd->hint) {
@@ -179,10 +166,8 @@ static const cmd_item_t *find_command_by_name(const char *name)
 {
     const cmd_item_t *cmd = NULL;
     cmd_item_t *it;
-    int len = strlen(name);
     SLIST_FOREACH(it, &s_cmd_list, next) {
-        if (strlen(it->command) == len &&
-                strcmp(name, it->command) == 0) {
+        if (strcmp(name, it->command) == 0) {
             cmd = it;
             break;
         }
@@ -246,6 +231,7 @@ static int help_command(int argc, char **argv)
     return 0;
 }
 
+
 esp_err_t esp_console_register_help_command(void)
 {
     esp_console_cmd_t command = {