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Added special register decoding for wsr and rsr

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This commit is contained in:
Olof Astrand
2020-06-12 16:11:39 +02:00
parent 9266d6b8d8
commit 302174465a
3 changed files with 51 additions and 8 deletions
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31
data/languages/xtensa.sinc
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@@ -3,6 +3,7 @@ define alignment=1;
define space ram type=ram_space size=4 default;
define space register type=register_space size=4;
define space special_register type=ram_space size=4;
# Address registers (AR).
define register offset=0x0000 size=4 [
@@ -27,6 +28,32 @@ define register offset=0x1000 size=4 [ pc ];
# Shift amount register. (TODO: other special registers)
define register offset=0x2000 size=1 [ sar ];
#not all registers are 32Bit but for sake of simplicity they are here
define special_register offset=0 size=4 [ LBEG LEND LCOUNT SAR BR LITBASE ];
define special_register offset=48 size=4 [ SCOMPARE1 ];
define special_register offset=64 size=4 [ ACCLO ACCHI ];
define special_register offset=128 size=4 [ M0 M1 M2 M3 ];
define special_register offset=288 size=4 [ WindowBase WindowStart ];
define special_register offset=332 size=4 [ PTEVADDR ];
define special_register offset=356 size=4 [ MMID RASID ITLBCFG DTLBCFG ];
define special_register offset=384 size=4 [ IBREAKENABLE ];
define special_register offset=392 size=4 [ CACHEATTR ATOMCTL ];
define special_register offset=416 size=4 [ DDR ];
define special_register offset=424 size=4 [ MEPC MEPS MESAVE MESR MECR MEVADDR ];
define special_register offset=512 size=4 [ IBREAKA0 IBREAKA1 ];
define special_register offset=576 size=4 [ DBREAKA0 DBREAKA1 ];
define special_register offset=640 size=4 [ DBREAKC0 DBREAKC1 ];
define special_register offset=708 size=4 [ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 ];
define special_register offset=768 size=4 [ DEPC ];
define special_register offset=776 size=4 [ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 ];
define special_register offset=836 size=4 [ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 ];
define special_register offset=896 size=4 [ CPENABLE ];
define special_register offset=900 size=4 [ INTERRUPT INTSET INTCLEAR INTENABLE ];# assuming it's a typo in the manual and INTERRUPT has number 225
define special_register offset=920 size=4 [ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR ];
define special_register offset=960 size=4 [ CCOMPARE0 CCOMPARE1 CCOMPARE2 ];
define special_register offset=976 size=4 [ MISC0 MISC1 MISC2 MISC3 ];
# Regular 24-bit instruction.
define token insn(24)
# Named opcode/register fields.
@@ -37,6 +64,7 @@ define token insn(24)
as = (8,11)
fs = (8,11)
bs = (8,11)
sr = (8,15)
at = (4,7)
ft = (4,7)
bt = (4,7)
@@ -106,6 +134,9 @@ attach variables [ br bs bt ] [
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
];
attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ];
# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive
# bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least
# singificant operand half, LM the most significant bits of the least significant operand half, etc.

20
data/languages/xtensaInstructions.sinc
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@@ -1002,9 +1002,10 @@ macro extract_bit(val, bit, result) {
at = rsil(u4_8.11:1);
}
# RSR - Read Special Register, pg. 500.
:rsr at, u8_8.15 is op0 = 0 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
at = rsr(u8_8.15:1);
# RSR - Read Special Register, pg. 500. u8_8.15
:rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 {
#at = rsr(u8_8.15:1);
at = *[special_register]sr;
}
# RSYNC - Register Read Synchronize, pg. 502.
@@ -1276,9 +1277,11 @@ macro extract_bit(val, bit, result) {
witlb(as, at);
}
# WSR - Write Special Register, pg. 561.
:wsr at, u8_8.15 is op2 = 0b0001 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
wsr(u8_8.15:1, at);
#WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0
# WSR - Write Special Register, pg. 561. u8_8.15
:wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 {
#wsr(u8_8.15:1, at);
*[special_register]:4 sr = at;
}
# WUR - Write User Register, pg. 563.
@@ -1296,7 +1299,10 @@ macro extract_bit(val, bit, result) {
br = bs ^^ bt;
}
# XSR - Exchange Special Register, pg. 566.
# XSR - Exchange Special Register, pg. 566. u8_8.15
:xsr at, u8_8.15 is op2 = 0b0110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 {
at = xsr(u8_8.15:1, at);
#tmp = *[special_register]sr;
#*[special_register]:4 sr = at;
#at = tmp;
}

8
data/languages/xtensaTodo.sinc
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@@ -122,7 +122,13 @@
# RETW.N - Narrow Windowed Return, pg. 482.
:retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 {
return [a0];
a10=a2;
a11=a3;
a12=a4;
a13=a5;
a14=a6;
a15=a7;
return [a0];
}
# ROTW - Rotate Window, pg. 496.