Add fake iX and oX registers to get a better decompilation for esp32 binaries

build.gradle

@@ -0,0 +1,10 @@
+apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
+apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
+apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
+apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
+apply plugin: 'eclipse'
+eclipse.project.name = 'Processors Xtensa'
+
+dependencies {
+	compile project(':Base')
+}

data/languages/xtensa.cspec

@@ -30,22 +30,22 @@
     <prototype name="__stdcall" extrapop="0" stackshift="0">
       <input>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a2"/>
+          <register name="i2"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a3"/>
+          <register name="i3"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a4"/>
+          <register name="i4"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a5"/>
+          <register name="i5"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a6"/>
+          <register name="i6"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a7"/>
+          <register name="i7"/>
         </pentry>
         <pentry minsize="1" maxsize="500" align="4">
           <addr offset="0" space="stack"/>
@@ -53,16 +53,16 @@
       </input>
       <output>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a2"/>
+          <register name="o2"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a3"/>
+          <register name="o3"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a4"/>
+          <register name="o4"/>
         </pentry>
         <pentry minsize="1" maxsize="4" extension="inttype">
-          <register name="a5"/>
+          <register name="o5"/>
         </pentry>
     </output>
     <returnaddress>
@@ -70,6 +70,15 @@
     </returnaddress>
     <unaffected>
       <register name="a1"/>
+      <register name="a3"/>
+      <register name="a4"/>
+      <register name="a5"/>
+      <register name="a6"/>
+      <register name="a7"/>
+      <register name="a8"/>
+      <register name="a9"/>
+      <register name="a10"/>
+      <register name="a11"/>                        
       <register name="a12"/>
       <register name="a13"/>
       <register name="a14"/>

data/languages/xtensa.sinc

@@ -15,6 +15,8 @@ define save_register offset=0x0000 size=4 [
 # Address registers (AR).
 define register offset=0x0000 size=4 [
     a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
+    i2 i3 i4 i5 i6 i7
+    o2 o3 o4 o5 o6 o7
 ];
 
 # Floating Point registers (FR + FCR (control) + FSR (status)).

data/languages/xtensaInstructions.sinc

@@ -303,15 +303,29 @@ macro extract_bit(val, bit, result) {
 
 # CALL0 - Non-windowed Call, pg. 297.
 :call0 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0 & op0 = 0b0101 {
+    i2 = a2;
+    i3 = a3;
+    i4 = a4;
+    i5 = a5;
+    i6 = a6;
+    i7 = a7;     
     a0 = inst_start + 3;
     call srel_6.23_sb2;
+    a2=o2;
 }
 
 # CALLX0 - Non-windowed Call Register, pg. 304.
 :callx0 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0 & op0 = 0 {
     local dst = as;
+    i2 = a2;
+    i3 = a3;
+    i4 = a4;
+    i5 = a5;
+    i6 = a6;
+    i7 = a7;      
     a0 = inst_start + 3;
     call [dst];
+    a2=o2;
 }
 
 # CEIL.S - Ceiling Single to Fixed, pg. 311.
@@ -931,6 +945,7 @@ macro extract_bit(val, bit, result) {
 # RET.N - Narrow Non-Windowed Return, pg. 479.
 :ret.n is n_ar = 0b1111 & n_as = 0 & n_at = 0 & n_op0 = 0b1101 {
     return [a0];
+    o2=a2;
 }
 
 # RFDD - Return from Debug and Dispatch, pg. 484.

data/languages/xtensaTodo.sinc

@@ -33,130 +33,92 @@ macro restore() {
 # CALL4 - Call PC-relative, Rotate Window by 4, pg. 298.
 :call4 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b01 & op0 = 0b0101 {
     local dst = srel_6.23_sb2;
-    a2=a6;
+    i2=a6;
-    a3=a7;
+    i3=a7;
-    a4=a8;
+    i4=a8;
-    a5=a9;
+    i5=a9;
     a0 = inst_start + 3;
     call [dst];
+    a6=o2;
 }
 
 # CALL8 - Call PC-relative, Rotate Window by 8, pg. 300.
 :call8 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b10 & op0 = 0b0101 {
     local dst = srel_6.23_sb2;
-    save();
+    i2=a10;
-    #s2=a2;
+    i3=a11;
-    #s3=a3;
+    i4=a12;
-    #s4=a4;
+    i5=a13;
-    #s5=a5;
+    i6=a14;
-    #s6=a6;
+    i7=a15;    
-    #s7=a7;
-    a2=a10;
-    a3=a11;
-    a4=a12;
-    a5=a13;
-    a6=a14;
-    a7=a15;    
     a0 = inst_start + 3;
     call [dst];
-    restore();
+    a10=o2;
 }
 
 # CALL12 - Call PC-relative, Rotate Window by 12, pg. 302.
 :call12 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b11 & op0 = 0b0101 {
     local dst = srel_6.23_sb2;
-    a2=a14;
+    i2=a14;
-    a3=a15;
+    i3=a15;
     a0 = inst_start + 3;
     call [dst];
+    a14=o2;
 }
 
 # ENTRY - Subroutine Entry, pg. 340.
 :entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 {
     local amn = sext(u15_12.23_sb3);
+    a2=i2;
+    a3=i3;
+    a4=i4;
+    a5=i5;
+    a6=i6;
+    a7=i7;        
     #as = as + amn;
     WindowBase    = amn;
     a1 = a1 - amn;
 }
 
-#    if (u15_12.23_sb3 ==4)
-#        goto <shift4>;
-#    if (u15_12.23_sb3 ==8)
-#        goto <shift8>;
-#    if (u15_12.23_sb3 ==12)
-#        goto <shift12>;
-#    <shift4>
-#        a2=a6;
-#        a3=a7;
-#        a4=a8;
-#        a5=a9;
-#        a6=a10;
-#        a7=a11;
-#        a8=a12;
-#        a9=a13;
-#        a10=a14;
-#        a11=a15;
-#        goto <end>;
-#    <shift8>
-#        a2=a10;
-#        a3=a11;
-#        a4=a12;
-#        a5=a13;
-#        a6=a14;
-#        a7=a15;
-#        goto <end>;
-#    <shift12>
-#        a2=a14;
-#        a3=a15;
-#    <end>
-
-
 
 
 
 # CALLX4 - Call Register, Rotate Window by 4, pg. 305.
 :callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b01 & op0 = 0 {
     local dst = as;
-    a2=a6;
+    i2=a6;
-    a3=a7;
+    i3=a7;
-    a4=a8;
+    i4=a8;
-    a5=a9;
+    i5=a9;
-    a6=a10;
+    i6=a10;
-    a7=a11;
+    i7=a11;
-    a8=a12;
-    a9=a13;
-    a10=a14;
-    a11=a15;
     a0 = inst_start + 3;
     call [dst];
+    a6=o2;
 }
 
 # CALLX8 - Call Register, Rotate Window by 8, pg. 307.
 :callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b10 & op0 = 0 {
     local dst = as;
-    #s2=a2;
+    i2=a10;
-    #s3=a3;
+    i3=a11;
-    #s4=a4;
+    i4=a12;
-    #s5=a5;
+    i5=a13;
-    #s6=a6;
+    i6=a14;
-    #s7=a7;
+    i7=a15;        
-    a2=a10;
-    a3=a11;
-    a4=a12;
-    a5=a13;
-    a6=a14;
-    a7=a15;        
     a0 = inst_start + 3;
     call [dst];
+    a10=o2;    
 }
 
 # CALLX12 - Call Register, Rotate Window by 12, pg. 308.
 :callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b11 & op0 = 0 {
     local dst = as;
-    a2=a14;
+    i2=a14;
-    a3=a15;
+    i3=a15;
     a0 = inst_start + 3;
     call [dst];
+    a14=o2;
 }
 
 
@@ -170,30 +132,23 @@ macro restore() {
 # RETW - Windowed Return, pg. 480.
 :retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6.7 = 0b10 & u2_4.5 = 0b01 & op0 = 0 {
 # Assume call8
-    a10=a2;
+    o2=a2;
-    a11=a3;
+    o3=a3;
-    a12=a4;
+    o4=a4;
-    a13=a5;
+    a10=a2;    
-    a14=a6;
-    a15=a7;
-    #a2=s2;
-    #a3=s3;
-    #a4=s4;
-    #a5=s5;
-    #a6=s6;
-    #a7=s7;                        
     a1 = a1 + WindowBase;
     return [a0];
 }
 
 # RETW.N - Narrow Windowed Return, pg. 482.
 :retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 {
+    o2=a2;
+    o3=a3;
+    o4=a4;
+    o5=a5;
+    o6=a6;
+    o7=a7;
     a10=a2;
-    a11=a3;
-    a12=a4;
-    a13=a5;
-    a14=a6;
-    a15=a7;
     a1 = a1 + WindowBase;
     return [a0];
 }