sr register varnode issue

This commit is contained in:
Olof Astrand
2020-07-14 11:27:40 +02:00
parent fb191336c8
commit f471375e24
3 changed files with 14 additions and 17 deletions

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@@ -64,7 +64,6 @@ define token insn(24)
as = (8,11)
fs = (8,11)
bs = (8,11)
sr = (8,15)
at = (4,7)
ft = (4,7)
bt = (4,7)
@@ -142,7 +141,7 @@ attach variables [ br bs bt ] [
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
];
attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ];
#attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ];
# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive

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@@ -1004,10 +1004,9 @@ macro extract_bit(val, bit, result) {
at = rsil(u4_8.11:1);
}
# RSR - Read Special Register, pg. 500. u8_8.15
:rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 {
#at = rsr(u8_8.15:1);
at = *[special_register]sr;
# RSR - Read Special Register, pg. 500.
:rsr at, u8_8.15 is op0 = 0 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
at = rsr(u8_8.15:1);
}
# RSYNC - Register Read Synchronize, pg. 502.
@@ -1279,12 +1278,14 @@ macro extract_bit(val, bit, result) {
witlb(as, at);
}
#WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0
# WSR - Write Special Register, pg. 561. u8_8.15
:wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 {
#wsr(u8_8.15:1, at);
*[special_register]:4 sr = at;
# WSR - Write Special Register, pg. 561.
:wsr at, u8_8.15 is op2 = 0b0001 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
wsr(u8_8.15:1, at);
}
#:WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0
#{
# *[special_register]:4 sr = at;
#}
# WUR - Write User Register, pg. 563.
:wur at, u8_8.15 is op2 = 0b1111 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
@@ -1301,12 +1302,9 @@ macro extract_bit(val, bit, result) {
br = bs ^^ bt;
}
# XSR - Exchange Special Register, pg. 566. u8_8.15
# XSR - Exchange Special Register, pg. 566.
:xsr at, u8_8.15 is op2 = 0b0110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 {
at = xsr(u8_8.15:1, at);
#tmp = *[special_register]sr;
#*[special_register]:4 sr = at;
#at = tmp;
}
# PAD, dummy

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@@ -164,7 +164,7 @@ macro popVal(val32) {
#a5=s5;
#a6=s6;
#a7=s7;
a1 = a1 + WindowBase;
#a1 = a1 + WindowBase;
return [a0];
}
@@ -176,7 +176,7 @@ macro popVal(val32) {
a13=a5;
a14=a6;
a15=a7;
a1 = a1 + WindowBase;
#a1 = a1 + WindowBase;
return [a0];
}