forked from yath/ghidra-xtensa
sr register varnode issue
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@@ -64,7 +64,6 @@ define token insn(24)
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as = (8,11)
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fs = (8,11)
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bs = (8,11)
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sr = (8,15)
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at = (4,7)
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ft = (4,7)
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bt = (4,7)
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@@ -142,7 +141,7 @@ attach variables [ br bs bt ] [
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b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
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];
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attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ];
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#attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ];
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# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive
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@@ -1004,10 +1004,9 @@ macro extract_bit(val, bit, result) {
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at = rsil(u4_8.11:1);
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}
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# RSR - Read Special Register, pg. 500. u8_8.15
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:rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 {
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#at = rsr(u8_8.15:1);
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at = *[special_register]sr;
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# RSR - Read Special Register, pg. 500.
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:rsr at, u8_8.15 is op0 = 0 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
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at = rsr(u8_8.15:1);
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}
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# RSYNC - Register Read Synchronize, pg. 502.
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@@ -1279,12 +1278,14 @@ macro extract_bit(val, bit, result) {
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witlb(as, at);
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}
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#WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0
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# WSR - Write Special Register, pg. 561. u8_8.15
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:wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 {
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#wsr(u8_8.15:1, at);
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*[special_register]:4 sr = at;
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# WSR - Write Special Register, pg. 561.
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:wsr at, u8_8.15 is op2 = 0b0001 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
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wsr(u8_8.15:1, at);
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}
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#:WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0
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#{
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# *[special_register]:4 sr = at;
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#}
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# WUR - Write User Register, pg. 563.
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:wur at, u8_8.15 is op2 = 0b1111 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 {
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@@ -1301,12 +1302,9 @@ macro extract_bit(val, bit, result) {
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br = bs ^^ bt;
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}
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# XSR - Exchange Special Register, pg. 566. u8_8.15
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# XSR - Exchange Special Register, pg. 566.
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:xsr at, u8_8.15 is op2 = 0b0110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 {
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at = xsr(u8_8.15:1, at);
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#tmp = *[special_register]sr;
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#*[special_register]:4 sr = at;
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#at = tmp;
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}
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# PAD, dummy
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@@ -164,7 +164,7 @@ macro popVal(val32) {
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#a5=s5;
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#a6=s6;
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#a7=s7;
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a1 = a1 + WindowBase;
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#a1 = a1 + WindowBase;
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return [a0];
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}
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@@ -176,7 +176,7 @@ macro popVal(val32) {
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a13=a5;
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a14=a6;
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a15=a7;
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a1 = a1 + WindowBase;
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#a1 = a1 + WindowBase;
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return [a0];
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}
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