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feedc0de/ghidra-xtensa
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forked from yath/ghidra-xtensa
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302174465a743c8eb36d3e3cba074296ce4cb058
ghidra-xtensa/data/languages
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History
Olof Astrand 302174465a Added special register decoding for wsr and rsr
2020-06-12 16:11:39 +02:00
..
xtensa.cspec
Fix compiler spec
2019-06-22 22:04:43 +02:00
xtensa.dwarf
Updated with upstream manual merge
2020-05-16 12:21:28 +02:00
xtensa.ldefs
Updated with upstream manual merge
2020-05-16 12:21:28 +02:00
xtensa.opinion
Add opinion file for ELF and titlecase the processor name
2019-06-26 16:28:50 +02:00
xtensa.pspec
Initial commit
2019-06-22 15:04:45 +02:00
xtensa.sinc
Added special register decoding for wsr and rsr
2020-06-12 16:11:39 +02:00
xtensa.slaspec
Initial commit
2019-06-22 15:04:45 +02:00
xtensaInstructions.sinc
Added special register decoding for wsr and rsr
2020-06-12 16:11:39 +02:00
xtensaTodo.sinc
Added special register decoding for wsr and rsr
2020-06-12 16:11:39 +02:00
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