Merge pull request #3994 from miyazakh/esp_rsa_hw

Fixed esp32 RSA hw accelerator initialization issue
This commit is contained in:
Chris Conlon
2021-04-30 13:58:24 -06:00
committed by GitHub
3 changed files with 9 additions and 8 deletions

View File

@ -51,10 +51,10 @@ static void set_time()
time_t now; time_t now;
struct tm timeinfo; struct tm timeinfo;
char strftime_buf[64]; char strftime_buf[64];
/* please update the time if seeing unknown failure. */ /* please update the time if seeing unknown failure when loading cert. */
/* this could cause TLS communication failure due to time expiration */ /* this could cause TLS communication failure due to time expiration */
/* incleasing 31536000 seconds is close to spend 356 days. */ /* incleasing 31536000 seconds is close to spend 356 days. */
utctime.tv_sec = 1598661910; /* dummy time: Fri Aug 29 09:45:00 2020 */ utctime.tv_sec = 1619650800; /* dummy time: Wed April 28 23:00:00 2021 */
utctime.tv_usec = 0; utctime.tv_usec = 0;
tz.tz_minuteswest = 0; tz.tz_minuteswest = 0;
tz.tz_dsttime = 0; tz.tz_dsttime = 0;

View File

@ -48,10 +48,10 @@ static void set_time()
time_t now; time_t now;
struct tm timeinfo; struct tm timeinfo;
char strftime_buf[64]; char strftime_buf[64];
/* please update the time if seeing unknown failure. */ /* please update the time if seeing unknown failure when loading cert. */
/* this could cause TLS communication failure due to time expiration */ /* this could cause TLS communication failure due to time expiration */
/* incleasing 31536000 seconds is close to spend 356 days. */ /* incleasing 31536000 seconds is close to spend 356 days. */
utctime.tv_sec = 1598661910; /* dummy time: Fri Aug 29 09:45:00 2020 */ utctime.tv_sec = 1619650800; /* dummy time: Wed April 28 23:00:00 2021 */
utctime.tv_usec = 0; utctime.tv_usec = 0;
tz.tz_minuteswest = 0; tz.tz_minuteswest = 0;
tz.tz_dsttime = 0; tz.tz_dsttime = 0;

View File

@ -94,6 +94,7 @@ static int esp_mp_hw_lock()
/* Enable RSA hardware */ /* Enable RSA hardware */
periph_module_enable(PERIPH_RSA_MODULE); periph_module_enable(PERIPH_RSA_MODULE);
DPORT_REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD);
return ret; return ret;
} }
/* /*