clear PROT_RSA_PD bit in PORT_RSA_PD_CTRL_REG to be initialization and activate RSA accelerator

This commit is contained in:
Hideki Miyazaki
2021-04-29 09:20:16 +09:00
parent 385e0bedaa
commit f4935f52b5
3 changed files with 9 additions and 8 deletions

View File

@@ -51,10 +51,10 @@ static void set_time()
time_t now;
struct tm timeinfo;
char strftime_buf[64];
/* please update the time if seeing unknown failure. */
/* this could cause TLS communication failure due to time expiration */
/* incleasing 31536000 seconds is close to spend 356 days. */
utctime.tv_sec = 1598661910; /* dummy time: Fri Aug 29 09:45:00 2020 */
/* please update the time if seeing unknown failure when loading cert. */
/* this could cause TLS communication failure due to time expiration */
/* incleasing 31536000 seconds is close to spend 356 days. */
utctime.tv_sec = 1619650800; /* dummy time: Wed April 28 23:00:00 2021 */
utctime.tv_usec = 0;
tz.tz_minuteswest = 0;
tz.tz_dsttime = 0;

View File

@@ -48,10 +48,10 @@ static void set_time()
time_t now;
struct tm timeinfo;
char strftime_buf[64];
/* please update the time if seeing unknown failure. */
/* this could cause TLS communication failure due to time expiration */
/* incleasing 31536000 seconds is close to spend 356 days. */
utctime.tv_sec = 1598661910; /* dummy time: Fri Aug 29 09:45:00 2020 */
/* please update the time if seeing unknown failure when loading cert. */
/* this could cause TLS communication failure due to time expiration */
/* incleasing 31536000 seconds is close to spend 356 days. */
utctime.tv_sec = 1619650800; /* dummy time: Wed April 28 23:00:00 2021 */
utctime.tv_usec = 0;
tz.tz_minuteswest = 0;
tz.tz_dsttime = 0;

View File

@@ -94,6 +94,7 @@ static int esp_mp_hw_lock()
/* Enable RSA hardware */
periph_module_enable(PERIPH_RSA_MODULE);
DPORT_REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD);
return ret;
}
/*