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Fix Poly1305 on Intel AVX2

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Fix define checks for other x86_64 assembly code files
This commit is contained in:
Sean Parkinson
2019-08-16 17:42:19 +10:00
parent cb33ada380
commit 8454bd1077
5 changed files with 10 additions and 9 deletions
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4
wolfcrypt/src/aes_gcm_asm.S
View File

@@ -22,9 +22,9 @@
#ifndef HAVE_INTEL_AVX1
#define HAVE_INTEL_AVX1
#endif /* HAVE_INTEL_AVX1 */
#ifndef HAVE_INTEL_AVX2
#ifndef NO_AVX2_SUPPORT
#define HAVE_INTEL_AVX2
#endif /* HAVE_INTEL_AVX2 */
#endif /* NO_AVX2_SUPPORT */
#ifndef __APPLE__
.data

2
wolfcrypt/src/fe_x25519_asm.S
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@@ -1,6 +1,6 @@
/* fe_x25519_asm
*
* Copyright (C) 2006-2018 wolfSSL Inc.
* Copyright (C) 2006-2019 wolfSSL Inc.
*
* This file is part of wolfSSL.
*

5
wolfcrypt/src/poly1305_asm.S
View File

@@ -22,9 +22,9 @@
#ifndef HAVE_INTEL_AVX1
#define HAVE_INTEL_AVX1
#endif /* HAVE_INTEL_AVX1 */
#ifndef HAVE_INTEL_AVX2
#ifndef NO_AVX2_SUPPORT
#define HAVE_INTEL_AVX2
#endif /* HAVE_INTEL_AVX2 */
#endif /* NO_AVX2_SUPPORT */
#ifdef HAVE_INTEL_AVX1
#ifndef __APPLE__
@@ -418,6 +418,7 @@ _poly1305_calc_powers_avx2:
movq %r12, %rax
shrq $2, %rax
leaq 0(%rax,%rax,4), %rax
andq $3, %r12
addq %rax, %r10
adcq $0x00, %r11
adcq $0x00, %r12

4
wolfcrypt/src/sha256_asm.S
View File

@@ -22,9 +22,9 @@
#ifndef HAVE_INTEL_AVX1
#define HAVE_INTEL_AVX1
#endif /* HAVE_INTEL_AVX1 */
#ifndef HAVE_INTEL_AVX2
#ifndef NO_AVX2_SUPPORT
#define HAVE_INTEL_AVX2
#endif /* HAVE_INTEL_AVX2 */
#endif /* NO_AVX2_SUPPORT */
#ifdef HAVE_INTEL_AVX1
#ifndef __APPLE__

4
wolfcrypt/src/sha512_asm.S
View File

@@ -22,9 +22,9 @@
#ifndef HAVE_INTEL_AVX1
#define HAVE_INTEL_AVX1
#endif /* HAVE_INTEL_AVX1 */
#ifndef HAVE_INTEL_AVX2
#ifndef NO_AVX2_SUPPORT
#define HAVE_INTEL_AVX2
#endif /* HAVE_INTEL_AVX2 */
#endif /* NO_AVX2_SUPPORT */
#ifdef HAVE_INTEL_AVX1
#ifndef __APPLE__