version 2.9.2 release

the signature if it exists.

.gitignore

@@ -30,6 +30,8 @@ tags
 .tags*
 cyassl-config
 cyassl.sublime*
+fips.c
+fips_test.c
 ctaocrypt/benchmark/benchmark
 ctaocrypt/test/testctaocrypt
 examples/client/client
@@ -41,15 +43,24 @@ output
 mcapi/test
 testsuite/testsuite
 tests/unit
+testsuite/testsuite.test
+tests/unit.test
 testsuite/*.der
 testsuite/*.pem
 testsuite/*.raw
 cert.der
 cert.pem
+certecc.der
+certecc.pem
 othercert.der
 othercert.pem
 key.der
 key.pem
+certreq.der
+certreq.pem
+pkcs7cert.der
+pkcs7signedData.der
+pkcs7envelopedData.der
 diff
 sslSniffer/sslSnifferTest/tracefile.txt
 *.gz
@@ -68,7 +79,7 @@ cyassl*rc*
 autoscan.log
 TAGS
 .DS_Store
-support/libcyassl.pc
+support/cyassl.pc
 cyassl/ctaocrypt/stamp-h1
 swig/_cyassl.so
 swig/cyassl.py
@@ -81,3 +92,28 @@ cov-int
 cyassl.tgz
 *.log
 *.trs
+IDE\MDK-ARM\Projects/
+IDE\MDK-ARM\STM32F2xx_StdPeriph_Lib/inc
+IDE\MDK-ARM\STM32F2xx_StdPeriph_Lib/src
+IDE\MDK-ARM\LPC43xx\Drivers/
+IDE\MDK-ARM\LPC43xx\LPC43xx/
+*.gcno
+*.gcda
+*.gcov
+
+# MPLAB Generated Files (OS X)
+mcapi/ctaocrypt_mcapi.X/nbproject/Makefile-*
+mcapi/ctaocrypt_mcapi.X/nbproject/Package-default.bash
+mcapi/ctaocrypt_test.X/nbproject/Makefile-*
+mcapi/ctaocrypt_test.X/nbproject/Package-default.bash
+mcapi/cyassl.X/nbproject/Makefile-*
+mcapi/cyassl.X/nbproject/Package-default.bash
+mcapi/zlib.X/nbproject/Makefile-*
+mcapi/zlib.X/nbproject/Package-default.bash
+mplabx/ctaocrypt_benchmark.X/nbproject/Makefile-*
+mplabx/ctaocrypt_benchmark.X/nbproject/Package-default.bash
+mplabx/ctaocrypt_test.X/nbproject/Makefile-*
+mplabx/ctaocrypt_test.X/nbproject/Package-default.bash
+mplabx/cyassl.X/nbproject/Makefile-*
+mplabx/cyassl.X/nbproject/Package-default.bash
+

IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s

@@ -0,0 +1,338 @@
+;/***********************************************************************
+; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
+; *
+; * Project: LPC43xx CMSIS Package
+; *
+; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00003000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x0000a000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp              ; 0 Top of Stack
+                DCD     Reset_Handler             ; 1 Reset Handler
+                DCD     NMI_Handler               ; 2 NMI Handler
+                DCD     HardFault_Handler         ; 3 Hard Fault Handler
+                DCD     MemManage_Handler         ; 4 MPU Fault Handler
+                DCD     BusFault_Handler          ; 5 Bus Fault Handler
+                DCD     UsageFault_Handler        ; 6 Usage Fault Handler
+                DCD     Sign_Value                ; 7 Reserved
+                DCD     0                         ; 8 Reserved
+                DCD     0                         ; 9 Reserved
+                DCD     0                         ; 10 Reserved
+                DCD     SVC_Handler               ; 11 SVCall Handler
+                DCD     DebugMon_Handler          ; 12 Debug Monitor Handler
+                DCD     0                         ; 13 Reserved
+                DCD     PendSV_Handler            ; 14 PendSV Handler
+                DCD     SysTick_Handler           ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     DAC_IRQHandler            ; 16 D/A Converter
+                DCD     M0CORE_IRQHandler         ; 17 M0 Core
+                DCD     DMA_IRQHandler            ; 18 General Purpose DMA
+                DCD     EZH_IRQHandler            ; 19 EZH/EDM
+                DCD     FLASH_EEPROM_IRQHandler   ; 20 Reserved for Typhoon
+                DCD     ETH_IRQHandler            ; 21 Ethernet
+                DCD     SDIO_IRQHandler           ; 22 SD/MMC
+                DCD     LCD_IRQHandler            ; 23 LCD
+                DCD     USB0_IRQHandler           ; 24 USB0
+                DCD     USB1_IRQHandler           ; 25 USB1
+                DCD     SCT_IRQHandler            ; 26 State Configurable Timer
+                DCD     RIT_IRQHandler            ; 27 Repetitive Interrupt Timer
+                DCD     TIMER0_IRQHandler         ; 28 Timer0
+                DCD     TIMER1_IRQHandler         ; 29 Timer1
+                DCD     TIMER2_IRQHandler         ; 30 Timer2
+                DCD     TIMER3_IRQHandler         ; 31 Timer3
+                DCD     MCPWM_IRQHandler          ; 32 Motor Control PWM
+                DCD     ADC0_IRQHandler           ; 33 A/D Converter 0
+                DCD     I2C0_IRQHandler           ; 34 I2C0
+                DCD     I2C1_IRQHandler           ; 35 I2C1
+                DCD     SPI_IRQHandler            ; 36 SPI
+                DCD     ADC1_IRQHandler           ; 37 A/D Converter 1
+                DCD     SSP0_IRQHandler           ; 38 SSP0
+                DCD     SSP1_IRQHandler           ; 39 SSP1
+                DCD     UART0_IRQHandler          ; 40 UART0
+                DCD     UART1_IRQHandler          ; 41 UART1
+                DCD     UART2_IRQHandler          ; 42 UART2
+                DCD     UART3_IRQHandler          ; 43 UART3
+                DCD     I2S0_IRQHandler           ; 44 I2S0
+                DCD     I2S1_IRQHandler           ; 45 I2S1
+                DCD     SPIFI_IRQHandler          ; 46 SPI Flash Interface
+                DCD     SGPIO_IRQHandler          ; 47 SGPIO
+                DCD     GPIO0_IRQHandler          ; 48 GPIO0
+                DCD     GPIO1_IRQHandler          ; 49 GPIO1
+                DCD     GPIO2_IRQHandler          ; 50 GPIO2
+                DCD     GPIO3_IRQHandler          ; 51 GPIO3
+                DCD     GPIO4_IRQHandler          ; 52 GPIO4
+                DCD     GPIO5_IRQHandler          ; 53 GPIO5
+                DCD     GPIO6_IRQHandler          ; 54 GPIO6
+                DCD     GPIO7_IRQHandler          ; 55 GPIO7
+                DCD     GINT0_IRQHandler          ; 56 GINT0
+                DCD     GINT1_IRQHandler          ; 57 GINT1
+                DCD     EVRT_IRQHandler           ; 58 Event Router
+                DCD     CAN1_IRQHandler           ; 59 C_CAN1
+                DCD     0                         ; 60 Reserved
+                DCD     VADC_IRQHandler           ; 61 VADC
+                DCD     ATIMER_IRQHandler         ; 62 ATIMER
+                DCD     RTC_IRQHandler            ; 63 RTC
+                DCD     0                         ; 64 Reserved
+                DCD     WDT_IRQHandler            ; 65 WDT
+                DCD     M0s_IRQHandler            ; 66 M0s
+                DCD     CAN0_IRQHandler           ; 67 C_CAN0
+                DCD     QEI_IRQHandler            ; 68 QEI
+
+
+;CRP address at offset 0x2FC relative to the BOOT Bank address
+                IF      :LNOT::DEF:NO_CRP
+                SPACE   (0x2FC - (. - __Vectors))
+;                EXPORT  CRP_Key
+CRP_Key         DCD     0xFFFFFFFF
+;                       0xFFFFFFFF => CRP Disabled
+;                       0x12345678 => CRP Level 1
+;                       0x87654321 => CRP Level 2
+;                       0x43218765 => CRP Level 3 (ARE YOU SURE?)
+;                       0x4E697370 => NO ISP      (ARE YOU SURE?)
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  DAC_IRQHandler          [WEAK]
+                EXPORT  M0CORE_IRQHandler       [WEAK]
+                EXPORT  DMA_IRQHandler          [WEAK]
+                EXPORT  EZH_IRQHandler          [WEAK]
+                EXPORT  FLASH_EEPROM_IRQHandler [WEAK]
+                EXPORT  ETH_IRQHandler          [WEAK]
+                EXPORT  SDIO_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler          [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  USB1_IRQHandler         [WEAK]
+                EXPORT  SCT_IRQHandler          [WEAK]
+                EXPORT  RIT_IRQHandler          [WEAK]
+                EXPORT  TIMER0_IRQHandler       [WEAK]
+                EXPORT  TIMER1_IRQHandler       [WEAK]
+                EXPORT  TIMER2_IRQHandler       [WEAK]
+                EXPORT  TIMER3_IRQHandler       [WEAK]
+                EXPORT  MCPWM_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  SPI_IRQHandler          [WEAK]
+                EXPORT  ADC1_IRQHandler         [WEAK]
+                EXPORT  SSP0_IRQHandler         [WEAK]
+                EXPORT  SSP1_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler        [WEAK]
+                EXPORT  UART1_IRQHandler        [WEAK]
+                EXPORT  UART2_IRQHandler        [WEAK]
+                EXPORT  UART3_IRQHandler        [WEAK]
+                EXPORT  I2S0_IRQHandler         [WEAK]
+                EXPORT  I2S1_IRQHandler         [WEAK]
+                EXPORT  SPIFI_IRQHandler        [WEAK]
+                EXPORT  SGPIO_IRQHandler        [WEAK]
+                EXPORT  GPIO0_IRQHandler        [WEAK]
+                EXPORT  GPIO1_IRQHandler        [WEAK]
+                EXPORT  GPIO2_IRQHandler        [WEAK]
+                EXPORT  GPIO3_IRQHandler        [WEAK]
+                EXPORT  GPIO4_IRQHandler        [WEAK]
+                EXPORT  GPIO5_IRQHandler        [WEAK]
+                EXPORT  GPIO6_IRQHandler        [WEAK]
+                EXPORT  GPIO7_IRQHandler        [WEAK]
+                EXPORT  GINT0_IRQHandler        [WEAK]
+                EXPORT  GINT1_IRQHandler        [WEAK]
+                EXPORT  EVRT_IRQHandler         [WEAK]
+                EXPORT  CAN1_IRQHandler         [WEAK]
+                EXPORT  VADC_IRQHandler         [WEAK]
+                EXPORT  ATIMER_IRQHandler       [WEAK]
+                EXPORT  RTC_IRQHandler          [WEAK]
+                EXPORT  WDT_IRQHandler          [WEAK]
+                EXPORT  M0s_IRQHandler          [WEAK]
+                EXPORT  CAN0_IRQHandler         [WEAK]
+                EXPORT  QEI_IRQHandler          [WEAK]
+
+DAC_IRQHandler
+M0CORE_IRQHandler
+DMA_IRQHandler
+EZH_IRQHandler
+FLASH_EEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+VADC_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+M0s_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

IDE/MDK-ARM/LPC43xx/time-LCP43xx.c

@@ -0,0 +1,166 @@
+/* time.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+
+/*-----------------------------------------------------------------------------
+ *        initialize RTC 
+ *----------------------------------------------------------------------------*/
+#include <stdio.h>
+#include "lpc43xx_rtc.h"
+#include "lpc43xx_cgu.h"
+
+static void init_RTC() 
+{	
+		/* Enable GPIO register interface clock                                     */
+		LPC_CCU1->CLK_M4_GPIO_CFG     |= 1;
+		while (!(LPC_CCU1->CLK_M4_GPIO_STAT   & 1)) ;
+	
+    /* RTC Block section ------------------------------------------------------ */
+    /* Init RTC module */
+    RTC_Init(LPC_RTC);
+
+    /* Set ALARM time for second */
+    RTC_SetAlarmTime (LPC_RTC, RTC_TIMETYPE_SECOND, 30);
+
+    /* Set the AMR for 30s match alarm interrupt */
+    RTC_AlarmIntConfig (LPC_RTC, RTC_TIMETYPE_SECOND, ENABLE);
+
+    /* Set the CIIR for minute counter interrupt*/
+    RTC_CntIncrIntConfig (LPC_RTC, RTC_TIMETYPE_MINUTE, ENABLE);
+
+    /* Enable rtc (starts increase the tick counter and second counter register) */
+    RTC_Cmd(LPC_RTC, ENABLE);
+				
+}
+
+/*-----------------------------------------------------------------------------
+ *        initialize TIM
+ *----------------------------------------------------------------------------*/
+ 
+#include "lpc43xx_timer.h"
+
+static void init_TIM()
+{
+    TIM_TIMERCFG_Type TIM_ConfigStruct;
+    /* Initialize timer 0, prescale count time of 1uS */
+    TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_TICKVAL;
+    TIM_ConfigStruct.PrescaleValue  = 204;  /* 204MHz */
+    /* Set configuration for Tim_config and Tim_MatchConfig */
+    TIM_Init(LPC_TIMER2, TIM_TIMER_MODE,&TIM_ConfigStruct);
+    TIM_ResetCounter(LPC_TIMER2);
+    /* To start timer 2 */
+    TIM_Cmd(LPC_TIMER2,ENABLE);
+}
+
+double current_time() 
+{
+    return (double)LPC_TIMER2->TC/1000000.0; 
+}
+
+
+void init_time(void) {
+	  init_RTC() ;
+    init_TIM() ;
+}
+
+#include <time.h>
+
+struct tm *Cyassl_MDK_gmtime(const time_t *c) 
+{ 
+    static struct tm date ; 
+
+  	RTC_TIME_Type RTCFullTime;
+	  RTC_GetFullTime (LPC_RTC, &RTCFullTime);
+
+    date.tm_year = RTCFullTime.YEAR + 100 ;
+    date.tm_mon = RTCFullTime.MONTH - 1 ;
+    date.tm_mday = RTCFullTime.DOM ;
+    date.tm_hour = RTCFullTime.HOUR ;
+    date.tm_min = RTCFullTime.MIN ;
+    date.tm_sec = RTCFullTime.SEC ;
+
+    #if defined(DEBUG_CYASSL) 
+    {
+			  extern void CYASSL_MSG(char *msg) ;
+        char msg[100] ;
+        sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n",
+        RTCFullTime.YEAR+2000,  RTCFullTime.MONTH, RTCFullTime.DOM,
+        RTCFullTime.HOUR,  RTCFullTime.MIN,  RTCFullTime.SEC) ; 
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+    
+    return(&date) ;
+}
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+
+#include <stdio.h>
+
+void time_main(void *args) 
+{
+    char * datetime ;
+	  int year ;
+  	RTC_TIME_Type RTCFullTime;
+
+    if( args == NULL || ((func_args *)args)->argc == 1) {  
+		    RTC_GetFullTime (LPC_RTC, &RTCFullTime);
+        printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", 
+             RTCFullTime.MONTH, RTCFullTime.DOM, RTCFullTime.YEAR+2000,  
+             RTCFullTime.HOUR,  RTCFullTime.MIN,  RTCFullTime.SEC) ;              
+    } else if(((func_args *)args)->argc == 3 && 
+              ((func_args *)args)->argv[1][0] == '-' && 
+              ((func_args *)args)->argv[1][1] == 'd' ) {
+
+								datetime = ((func_args *)args)->argv[2];
+        sscanf(datetime, "%d/%d/%d", 
+             (int *)&RTCFullTime.MONTH, (int *)&RTCFullTime.DOM, &year) ;
+        RTCFullTime.YEAR = year - 2000 ;   
+				RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MONTH, RTCFullTime.MONTH);
+        RTC_SetTime (LPC_RTC, RTC_TIMETYPE_YEAR, RTCFullTime.YEAR);
+        RTC_SetTime (LPC_RTC, RTC_TIMETYPE_DAYOFMONTH, RTCFullTime.DOM);       
+    } else if(((func_args *)args)->argc == 3 && 
+              ((func_args *)args)->argv[1][0] == '-' && 
+              ((func_args *)args)->argv[1][1] == 't' ) {
+		    RTC_GetFullTime (LPC_RTC, &RTCFullTime);
+								datetime = ((func_args *)args)->argv[2];
+        sscanf(datetime, "%d:%d:%d",            
+            (int *)&RTCFullTime.HOUR, 
+            (int *)&RTCFullTime.MIN, 
+            (int *)&RTCFullTime.SEC
+        ) ;
+        RTC_SetTime (LPC_RTC, RTC_TIMETYPE_SECOND, RTCFullTime.SEC);
+        RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MINUTE, RTCFullTime.MIN);
+        RTC_SetTime (LPC_RTC, RTC_TIMETYPE_HOUR, RTCFullTime.HOUR);
+    } else printf("Invalid argument\n") ; 
+}
+
+
+
+

IDE/MDK-ARM/MDK-ARM/CyaSSL/Retarget.c

@@ -0,0 +1,261 @@
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+ 
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <rt_sys.h>
+
+
+#include <File_Config.h>
+
+#pragma import(__use_no_semihosting_swi)
+
+/* The following macro definitions may be used to translate this file:
+
+  STDIO - use standard Input/Output device
+          (default is NOT used)
+ */
+
+/* Standard IO device handles. */
+#define STDIN   0x8001
+#define STDOUT  0x8002
+#define STDERR  0x8003
+
+/* Standard IO device name defines. */
+const char __stdin_name[]  = "STDIN";
+const char __stdout_name[] = "STDOUT";
+const char __stderr_name[] = "STDERR";
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+
+#ifdef STDIO
+extern int  SER_GetChar   (void);
+extern int  SER_PutChar   (int ch);
+
+/*-----------------------------------------------------------------------------
+  Write character to the Serial Port
+ *----------------------------------------------------------------------------*/
+int sendchar (int c) 
+{
+    if (c == '\n')  {
+        SER_PutChar ('\r');
+    }
+    SER_PutChar (c);
+    return (c);
+}
+
+
+/*-----------------------------------------------------------------------------
+  Read character from the Serial Port
+ *----------------------------------------------------------------------------*/
+int getkey (void) 
+{
+    int ch = SER_GetChar();
+
+    if (ch < 0) {
+        return 0;
+    }
+    return ch;
+}
+#endif
+
+/*--------------------------- _ttywrch ---------------------------------------*/
+
+void _ttywrch (int ch) 
+{
+#ifdef STDIO
+    sendchar (ch);
+#endif
+}
+
+/*--------------------------- _sys_open --------------------------------------*/
+#ifndef NO_FILESYSTEM
+static int KEIL_FS_open(const char *name, int openmode) 
+{
+    int i ;  int ret ;
+    #define PATHSIZE 100
+    char path[PATHSIZE] ; char *p ;
+    
+    if(strlen(name) > PATHSIZE)return(-1) ;
+    
+    for(i = 0; i<= strlen(name); i++) {
+        if(name[i] == '/')path[i] = '\\' ;
+        else              path[i] = name[i] ;
+    }       
+    if(path[0] == '.' && path[1] == '\\') p = path + 2 ;
+    else                                  p = path ;
+
+    ret = __sys_open (p, openmode) ;
+    
+    return(ret) ;
+}
+#endif
+
+FILEHANDLE _sys_open (const char *name, int openmode) 
+{
+    /* Register standard Input Output devices. */
+    if (strcmp(name, "STDIN") == 0) {
+        return (STDIN);
+    }
+    if (strcmp(name, "STDOUT") == 0) {
+        return (STDOUT);
+    }
+    if (strcmp(name, "STDERR") == 0) {
+        return (STDERR);
+    }
+    #ifndef NO_FILESYSTEM
+    return (KEIL_FS_open(name, openmode));
+    #else
+    return(0) ;
+    #endif
+}
+
+/*--------------------------- _sys_close -------------------------------------*/
+
+int _sys_close (FILEHANDLE fh) 
+{
+    if (fh > 0x8000) {
+        return (0);
+    }
+    #ifndef NO_FILESYSTEM
+    return (__sys_close (fh));
+    #else
+    return(0) ;
+    #endif
+}
+
+/*--------------------------- _sys_write -------------------------------------*/
+
+int _sys_write (FILEHANDLE fh, const U8 *buf, U32 len, int mode) 
+{
+#ifdef STDIO
+    if (fh == STDOUT) {
+        /* Standard Output device. */
+        for (  ; len; len--) {
+            sendchar (*buf++);
+        }
+        return (0);
+    }
+#endif
+    if (fh > 0x8000) {
+        return (-1);
+    }
+    #ifndef NO_FILESYSTEM
+    return (__sys_write (fh, buf, len));
+    #else
+    return(0) ;
+    #endif
+}
+
+/*--------------------------- _sys_read --------------------------------------*/
+
+int _sys_read (FILEHANDLE fh, U8 *buf, U32 len, int mode) 
+{
+#ifdef STDIO
+    if (fh == STDIN) {
+    /* Standard Input device. */
+        int sz ;
+        while((buf[0] = getkey()) == 0) ;
+           ;
+        for (sz = 0 ; sz <= len ; sz ++ ) {
+            if(buf[sz] == 0) break ;
+            else sz++ ;
+            buf[sz] = getkey ();
+        }
+        return (sz);
+    }
+#endif
+    if (fh > 0x8000) {
+        return (-1);
+    }
+    #ifndef NO_FILESYSTEM
+    return (__sys_read (fh, buf, len));
+    #else
+    return(0) ;
+    #endif
+}
+
+/*--------------------------- _sys_istty -------------------------------------*/
+
+int _sys_istty (FILEHANDLE fh) 
+{
+    if (fh > 0x8000) {
+        return (1);
+    }
+    return (0);
+}
+
+/*--------------------------- _sys_seek --------------------------------------*/
+
+int _sys_seek (FILEHANDLE fh, long pos) 
+{
+    if (fh > 0x8000) {
+        return (-1);
+    }
+    #ifndef NO_FILESYSTEM
+    return (__sys_seek (fh, pos));
+    #else
+    return(0) ;
+    #endif
+}
+
+/*--------------------------- _sys_ensure ------------------------------------*/
+
+int _sys_ensure (FILEHANDLE fh) 
+{
+    if (fh > 0x8000) {
+        return (-1);
+    }
+    #ifndef NO_FILESYSTEM
+    return (__sys_ensure (fh));
+    #else
+    return(0) ;
+    #endif
+}
+
+/*--------------------------- _sys_flen --------------------------------------*/
+
+long _sys_flen (FILEHANDLE fh) 
+{
+    if (fh > 0x8000) {
+        return (0);
+    }
+    #ifndef NO_FILESYSTEM
+    return (__sys_flen (fh));
+    #else
+    return(0) ;
+    #endif
+}
+
+
+/*--------------------------- _sys_tmpnam ------------------------------------*/
+
+int _sys_tmpnam (char *name, int sig, unsigned maxlen) 
+{
+    return (1);
+}
+
+/*--------------------------- _sys_command_string ----------------------------*/
+
+char *_sys_command_string (char *cmd, int len) 
+{
+    return (cmd);
+}
+
+/*--------------------------- _sys_exit --------------------------------------*/
+
+void _sys_exit (int return_code) 
+{
+#ifdef CYASSL_MDK_SHELL
+    return ;
+#else
+    /* Endless loop. */
+    while (1);
+#endif
+    
+}
+

IDE/MDK-ARM/MDK-ARM/CyaSSL/cert_data.c

@@ -0,0 +1,28 @@
+/* certs_test.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+/* Define initial data for cert buffers */
+#include <cyassl/certs_test.h>
+

IDE/MDK-ARM/MDK-ARM/CyaSSL/cert_data.h

@@ -0,0 +1,39 @@
+#ifndef CYASSL_CERT_DATA_H
+#define CYASSL_CERT_DATA_H
+
+#ifdef USE_CERT_BUFFERS_1024
+extern const unsigned char client_key_der_1024[]  ;
+extern int sizeof_client_key_der_1024 ;
+/* ./certs/1024/client-cert.der, 1024-bit */
+extern const unsigned char client_cert_der_1024[] ;
+extern int sizeof_client_cert_der_1024 ;
+/* ./certs/1024/dh1024.der, 1024-bit */
+extern const unsigned char dh_key_der_1024[] ; 
+extern int sizeof_dh_key_der_1024 ; 
+/* ./certs/1024/dsa1024.der, 1024-bit */
+extern const unsigned char dsa_key_der_1024[] ;
+extern int sizeof_dsa_key_der_1024 ;
+/* ./certs/1024/rsa1024.der, 1024-bit */
+extern const unsigned char rsa_key_der_1024[] ;
+extern int sizeof_rsa_key_der_1024 ;
+
+#elif defined(USE_CERT_BUFFERS_2048)
+/* ./certs/client-key.der, 2048-bit */
+extern const unsigned char client_key_der_2048[] ;
+extern int sizeof_client_key_der_2048 ;
+/* ./certs/client-cert.der, 2048-bit */
+extern const unsigned char client_cert_der_2048[] ;
+extern int sizeof_client_cert_der_2048 ;
+/* ./certs/dh2048.der, 2048-bit */
+extern const unsigned char dh_key_der_2048[] ;
+extern int sizeof_dh_key_der_2048 ;
+/* ./certs/dsa2048.der, 2048-bit */
+extern const unsigned char dsa_key_der_2048[] ;
+extern int sizeof_dsa_key_der_2048;
+/* ./certs/rsa2048.der, 2048-bit */
+extern const unsigned char rsa_key_der_2048[] ;
+extern int sizeof_rsa_key_der_2048 ;
+#endif
+
+#endif
+

IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h

@@ -0,0 +1,291 @@
+/* config-BEREFOOT.h
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+
+/**** CyaSSL for KEIL-RL Configuration ****/
+
+#define __CORTEX_M3__
+#define CYASSL_MDK_ARM
+#define NO_WRITEV
+#define NO_CYASSL_DIR
+#define NO_MAIN_DRIVER
+
+#define CYASSL_DER_LOAD
+#define HAVE_NULL_CIPHER
+
+#define SINGLE_THREADED
+#define NO_FILESYSTEM
+#define NO_TLS
+
+#define NO_ECHOSERVER
+#define NO_ECHOCLIENT
+#define NO_SIMPLE_SERVER
+#define NO_SIMPLE_CLIENT
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Build Target: KEIL-BAREFOOT
+//  <h> Single Threaded, No File System, No TCP-net
+//   </h>
+//      <e>Command Shell
+#define MDK_CONF_SHELL 1
+#if MDK_CONF_SHELL  == 1
+#define CYASSL_MDK_SHELL
+#endif
+//  </e>
+//  <h>CyaSSL Apps
+//  <h>Crypt/Cipher
+//        <o>Cert Storage <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
+#define MDK_CONF_CERT_BUFF 1
+#if MDK_CONF_CERT_BUFF == 1
+#define USE_CERT_BUFFERS_1024
+#elif MDK_CONF_CERT_BUFF == 2
+#define USE_CERT_BUFFERS_2048
+#endif
+
+//      <e>Crypt/Cipher Test Suite
+#define MDK_CONF_CTaoCryptTest 1
+#if MDK_CONF_CTaoCryptTest  == 0
+#define NO_CRYPT_TEST
+#endif
+//  </e>
+//      <e>Crypt/Cipher Benchmark
+#define MDK_CONF_CTaoCryptBenchmark 1
+#if MDK_CONF_CTaoCryptBenchmark == 0
+#define NO_CRYPT_BENCHMARK 
+#define BENCH_EMBEDDED
+#endif
+//  </e>
+//   </h>
+
+//  <h>STM32 Hardware Crypt
+//      <e>STM32F2 Hardware RNG
+#define MDK_CONF_STM32F2_RNG 0
+#if MDK_CONF_STM32F2_RNG == 1
+#define STM32F2_RNG
+#else
+#define NO_DEV_RANDOM
+#endif
+//  </e>
+//      <e>STM32F2 Hardware Crypt
+#define MDK_CONF_STM32F2_CRYPTO 0
+#if MDK_CONF_STM32F2_CRYPTO == 1
+#define STM32F2_CRYPTO
+#endif
+//  </e>
+
+// </h>
+
+
+//  <h>CTaoCrypt Library
+
+//       <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
+//        </h>
+//      <e>MD2
+#define MDK_CONF_MD2 0
+#if MDK_CONF_MD2 == 1
+#define CYASSL_MD2
+#endif
+//  </e>
+//      <e>MD4
+#define MDK_CONF_MD4 1
+#if MDK_CONF_MD4 == 0
+#define NO_MD4
+#endif
+//  </e>
+//      <e>SHA-384
+//          <i>This has to be with SHA512
+#define MDK_CONF_SHA384 0
+#if MDK_CONF_SHA384 == 1
+#define CYASSL_SHA384
+#endif
+//  </e>
+//      <e>SHA-512          
+#define MDK_CONF_SHA512     0
+#if MDK_CONF_SHA512     == 1
+#define CYASSL_SHA512   
+#endif
+//  </e>
+//      <e>RIPEMD
+#define MDK_CONF_RIPEMD 0
+#if MDK_CONF_RIPEMD == 1
+#define CYASSL_RIPEMD
+#endif
+//  </e>
+//      <e>HMAC
+#define MDK_CONF_HMAC 1
+#if MDK_CONF_HMAC == 0
+#define NO_HMAC
+#endif
+//  </e>
+//      <e>HC128
+#define MDK_CONF_HC128 0
+#if MDK_CONF_HC128 == 1
+#define HAVE_HC128
+#endif
+//  </e>
+//  <e>RABBIT
+#define MDK_CONF_RABBIT 1
+#if MDK_CONF_RABBI == 0
+#define NO_RABBIT
+#endif
+//  </e>
+
+//      <e>AEAD     
+#define MDK_CONF_AEAD 0
+#if MDK_CONF_AEAD == 1
+#define HAVE_AEAD
+#endif
+//  </e>
+//      <e>DES3
+#define MDK_CONF_DES3 1
+#if MDK_CONF_DES3 == 0
+#define NO_DES3
+#endif
+//  </e>
+//      <e>CAMELLIA
+#define MDK_CONF_CAMELLIA 0
+#if MDK_CONF_CAMELLIA == 1
+#define HAVE_CAMELLIA
+#endif
+//  </e>
+
+//      <e>DH
+//              <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
+#define MDK_CONF_DH 1
+#if MDK_CONF_DH == 0
+#define NO_DH
+#endif
+//  </e>
+//      <e>DSA
+#define MDK_CONF_DSA 1 
+#if MDK_CONF_DSA == 0
+#define NO_DSA
+#endif
+//  </e>
+//      <e>PWDBASED
+#define MDK_CONF_PWDBASED 1
+#if MDK_CONF_PWDBASED == 0
+#define NO_PWDBASED
+#endif
+//  </e>
+
+//      <e>ECC
+#define MDK_CONF_ECC 0
+#if MDK_CONF_ECC == 1
+#define HAVE_ECC
+#endif
+//  </e>
+//      <e>PSK
+#define MDK_CONF_PSK 1
+#if MDK_CONF_PSK == 0
+#define NO_PSK
+#endif
+//  </e>
+//      <e>AESCCM (Turn off Hardware Crypt)
+#define MDK_CONF_AESCCM 0
+#if MDK_CONF_AESCCM == 1
+#define HAVE_AESCCM
+#endif
+//  </e>
+//      <e>AESGCM (Turn off Hardware Crypt)
+#define MDK_CONF_AESGCM 0
+#if MDK_CONF_AESGCM == 1
+#define HAVE_AESGCM
+#define BUILD_AESGCM
+#endif
+//  </e>
+//      <e>NTRU (need License, "crypto_ntru.h")
+#define MDK_CONF_NTRU 0
+#if MDK_CONF_NTRU == 1
+#define HAVE_NTRU
+#endif
+//  </e>
+//  </h>
+
+//  <h>Others
+
+//      <e>Inline
+#define MDK_CONF_INLINE 0
+#if MDK_CONF_INLINE == 0
+#define NO_INLINE
+#endif
+//  </e>
+//      <h>Debug
+//              <e>Debug Message
+#define MDK_CONF_DebugMessage 0
+#if MDK_CONF_DebugMessage == 1
+#define DEBUG_CYASSL
+#endif
+//         </e>
+//              <e>Check malloc
+#define MDK_CONF_CheckMalloc 1
+#if MDK_CONF_CheckMalloc == 1
+#define CYASSL_MALLOC_CHECK
+#endif
+//         </e>
+
+
+//  </h>
+//      <e>ErrNo.h
+#define MDK_CONF_ErrNo 0
+#if MDK_CONF_ErrNo == 1
+#define HAVE_ERRNO
+#endif
+//  </e>
+//      <e>zlib (need "zlib.h")
+#define MDK_CONF_LIBZ 0
+#if MDK_CONF_LIBZ == 1
+#define HAVE_LIBZ
+#endif
+//  </e>
+//      <e>CAVIUM (need CAVIUM headers)
+#define MDK_CONF_CAVIUM 0
+#if MDK_CONF_CAVIUM == 1
+#define HAVE_CAVIUM
+#endif
+//  </e>
+
+//      <e>Error Strings
+#define MDK_CONF_ErrorStrings 1
+#if MDK_CONF_ErrorStrings == 0
+#define NO_ERROR_STRINGS
+#endif
+//  </e>
+
+//      <e>Small Stack
+#define MDK_CONF_SmallStack 1
+#if MDK_CONF_SmallStack == 0
+#define NO_CYASSL_SMALL_STACK
+#endif
+//  </e>
+//      <e>Use Fast Math
+#define MDK_CONF_FASTMATH 0
+#if MDK_CONF_FASTMATH == 1
+#define USE_FAST_MATH
+#endif
+//  </e>
+
+
+//  </h>
+
+//</h>
+// <<< end of configuration section >>>

IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h

@@ -0,0 +1,329 @@
+/* config-FS.h
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+
+/**** CyaSSL for KEIL-RL Configuration ****/
+
+#define __CORTEX_M3__
+#define CYASSL_KEIL_RL
+#define NO_WRITEV
+#define NO_CYASSL_DIR
+#define NO_MAIN_DRIVER
+
+
+#define CYASSL_DER_LOAD
+#define HAVE_NULL_CIPHER
+
+#define SINGLE_THREADED
+
+#define NO_ECHOSERVER
+#define NO_ECHOCLIENT
+#define NO_SIMPLE_SERVER
+#define NO_SIMPLE_CLIENT
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Build Target: KEIL-FS
+//  <h> Single Threaded, With File System, No TCP-net
+//   </h>
+//      <e>Command Shell
+#define MDK_CONF_SHELL 1
+#if MDK_CONF_SHELL  == 1
+#define CYASSL_MDK_SHELL
+#endif
+//  </e>
+//  <h>CyaSSL Apps
+//  <h>Crypt/Cipher
+//        <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
+#define MDK_CONF_CERT_BUFF 0
+#if MDK_CONF_CERT_BUFF== 1
+#define USE_CERT_BUFFERS_1024
+#elif MDK_CONF_CERT_BUFF == 2
+#define USE_CERT_BUFFERS_2048
+#endif
+
+//      <e>Crypt/Cipher Test Suite
+#define MDK_CONF_CTaoCryptTest 1
+#if MDK_CONF_CTaoCryptTest  == 0
+#define NO_CRYPT_TEST
+#endif
+//  </e>
+//      <e>Crypt/Cipher Benchmark
+#define MDK_CONF_CTaoCryptBenchmark 1
+#if MDK_CONF_CTaoCryptBenchmark == 0
+#define NO_CRYPT_BENCHMARK 
+#endif
+//  </e>
+//   </h>
+
+//  <h>STM32 Hardware Crypt
+//      <e>STM32F2 Hardware RNG
+#define MDK_CONF_STM32F2_RNG 0
+#if MDK_CONF_STM32F2_RNG == 1
+#define STM32F2_RNG
+#else
+#define NO_DEV_RANDOM
+#endif
+//  </e>
+//      <e>STM32F2 Hardware Crypt
+#define MDK_CONF_STM32F2_CRYPTO 0
+#if MDK_CONF_STM32F2_CRYPTO == 1
+#define STM32F2_CRYPTO
+#endif
+//  </e>
+
+// </h>
+
+//  <h>CyaSSL Library
+//     <h>SSL (Included by default)
+//     </h>
+
+//      <e>TLS 
+#define MDK_CONF_TLS 1
+#if MDK_CONF_TLS == 0
+#define NO_TLS
+#endif
+//  </e>
+
+//      <e>CertGen
+#define MDK_CONF_CERT_GEN 0
+#if MDK_CONF_CERT_GEN == 1
+#define CYASSL_CERT_GEN
+#endif
+//  </e>
+//      <e>KeyGen
+#define MDK_CONF_KEY_GEN 0
+#if MDK_CONF_KEY_GEN == 1
+#define CYASSL_KEY_GEN
+#endif
+//  </e>
+//      <e>CRL
+#define MDK_CONF_DER_LOAD 0
+#if MDK_CONF_DER_LOAD == 1
+#define CYASSL_DER_LOAD
+#endif
+//  </e>
+//      <e>OpenSSL Extra
+#define MDK_CONF_OPENSSL_EXTRA 0
+#if MDK_CONF_OPENSSL_EXTRA == 1
+#define OPENSSL_EXTRA
+#endif
+//  </e>
+//      <h>CRL Monitor, OCSP (not supported with KEIL)
+//     </h>
+
+// </h>
+
+//  <h>CTaoCrypt Library
+
+//       <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
+//        </h>
+
+//      <e>MD2
+#define MDK_CONF_MD2 0
+#if MDK_CONF_MD2 == 1
+#define CYASSL_MD2
+#endif
+//  </e>
+//      <e>MD4
+#define MDK_CONF_MD4 1
+#if MDK_CONF_MD4 == 0
+#define NO_MD4
+#endif
+//  </e>
+//      <e>SHA-384
+//          <i>This has to be with SHA512
+#define MDK_CONF_SHA384 0
+#if MDK_CONF_SHA384 == 1
+#define CYASSL_SHA384
+#endif
+//  </e>
+//      <e>SHA-512          
+#define MDK_CONF_SHA512     0
+#if MDK_CONF_SHA512     == 1
+#define CYASSL_SHA512   
+#endif
+//  </e>
+//      <e>RIPEMD
+#define MDK_CONF_RIPEMD 0
+#if MDK_CONF_RIPEMD == 1
+#define CYASSL_RIPEMD
+#endif
+//  </e>
+//      <e>HMAC
+#define MDK_CONF_HMAC 1
+#if MDK_CONF_HMAC == 0
+#define NO_HMAC
+#endif
+//  </e>
+//      <e>HC128
+#define MDK_CONF_HC128 0
+#if MDK_CONF_HC128 == 1
+#define HAVE_HC128
+#endif
+//  </e>
+//  <e>RABBIT
+#define MDK_CONF_RABBIT 1
+#if MDK_CONF_RABBI == 0
+#define NO_RABBIT
+#endif
+//  </e>
+
+//      <e>AEAD     
+#define MDK_CONF_AEAD 0
+#if MDK_CONF_AEAD == 1
+#define HAVE_AEAD
+#endif
+//  </e>
+//      <e>DES3
+#define MDK_CONF_DES3 1
+#if MDK_CONF_DES3 == 0
+#define NO_DES3
+#endif
+//  </e>
+//      <e>CAMELLIA
+#define MDK_CONF_CAMELLIA 0
+#if MDK_CONF_CAMELLIA == 1
+#define HAVE_CAMELLIA
+#endif
+//  </e>
+
+//      <e>DH
+//              <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
+#define MDK_CONF_DH 1
+#if MDK_CONF_DH == 0
+#define NO_DH
+#endif
+//  </e>
+//      <e>DSA
+#define MDK_CONF_DSA 1 
+#if MDK_CONF_DSA == 0
+#define NO_DSA
+#endif
+//  </e>
+//      <e>PWDBASED
+#define MDK_CONF_PWDBASED 1
+#if MDK_CONF_PWDBASED == 0
+#define NO_PWDBASED
+#endif
+//  </e>
+
+//      <e>ECC
+#define MDK_CONF_ECC 0
+#if MDK_CONF_ECC == 1
+#define HAVE_ECC
+#endif
+//  </e>
+//      <e>PSK
+#define MDK_CONF_PSK 1
+#if MDK_CONF_PSK == 0
+#define NO_PSK
+#endif
+//  </e>
+//      <e>AESCCM (Turn off Hardware Crypt)
+#define MDK_CONF_AESCCM 0
+#if MDK_CONF_AESCCM == 1
+#define HAVE_AESCCM
+#endif
+//  </e>
+//      <e>AESGCM (Turn off Hardware Crypt)
+#define MDK_CONF_AESGCM 0
+#if MDK_CONF_AESGCM == 1
+#define HAVE_AESGCM
+#define BUILD_AESGCM
+#endif
+//  </e>
+//      <e>NTRU (need License, "crypto_ntru.h")
+#define MDK_CONF_NTRU 0
+#if MDK_CONF_NTRU == 1
+#define HAVE_NTRU
+#endif
+//  </e>
+//  </h>
+
+//  <h>Others
+
+//      <e>Inline
+#define MDK_CONF_INLINE 0
+#if MDK_CONF_INLINE == 0
+#define NO_INLINE
+#endif
+//  </e>
+//      <h>Debug
+//              <e>Debug Message
+#define MDK_CONF_DebugMessage 0
+#if MDK_CONF_DebugMessage == 1
+#define DEBUG_CYASSL
+#endif
+//         </e>
+//              <e>Check malloc
+#define MDK_CONF_CheckMalloc 1
+#if MDK_CONF_CheckMalloc == 1
+#define CYASSL_MALLOC_CHECK
+#endif
+//         </e>
+
+
+//  </h>
+//      <e>ErrNo.h
+#define MDK_CONF_ErrNo 0
+#if MDK_CONF_ErrNo == 1
+#define HAVE_ERRNO
+#endif
+//  </e>
+//      <e>zlib (need "zlib.h")
+#define MDK_CONF_LIBZ 0
+#if MDK_CONF_LIBZ == 1
+#define HAVE_LIBZ
+#endif
+//  </e>
+//      <e>CAVIUM (need CAVIUM headers)
+#define MDK_CONF_CAVIUM 0
+#if MDK_CONF_CAVIUM == 1
+#define HAVE_CAVIUM
+#endif
+//  </e>
+
+//      <e>Error Strings
+#define MDK_CONF_ErrorStrings 1
+#if MDK_CONF_ErrorStrings == 0
+#define NO_ERROR_STRINGS
+#endif
+//  </e>
+
+//      <e>Small Stack
+#define MDK_CONF_SmallStack 1
+#if MDK_CONF_SmallStack == 0
+#define NO_CYASSL_SMALL_STACK
+#endif
+//  </e>
+//      <e>Use Fast Math
+#define MDK_CONF_FASTMATH 0
+#if MDK_CONF_FASTMATH == 1
+#define USE_FAST_MATH
+#endif
+//  </e>
+
+
+//  </h>
+
+//</h>
+// <<< end of configuration section >>>

IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h

@@ -0,0 +1,351 @@
+/* config-RTX-TCP-FS.h
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+
+/**** CyaSSL for KEIL-RL Configuration ****/
+
+#define __CORTEX_M3__
+#define CYASSL_MDK_ARM
+#define NO_WRITEV
+#define NO_CYASSL_DIR
+#define NO_MAIN_DRIVER
+
+
+#define CYASSL_DER_LOAD
+#define HAVE_NULL_CIPHER
+
+#define HAVE_KEIL_RTX
+#define CYASSL_KEIL_TCP_NET
+
+
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Build Target: KEIL-RTX-TCP-FS
+//  <h> RTOS, File System and TCP-net
+//  </h>
+//      <e>Command Shell
+#define MDK_CONF_SHELL 1
+#if MDK_CONF_SHELL  == 1
+#define CYASSL_MDK_SHELL
+#endif
+//  </e>
+//  <h>CyaSSL Apps
+//  <h>Crypt/Cipher
+//        <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
+#define MDK_CONF_CERT_BUFF 0
+#if MDK_CONF_CERT_BUFF== 1
+#define USE_CERT_BUFFERS_1024
+#elif MDK_CONF_CERT_BUFF == 2
+#define USE_CERT_BUFFERS_2048
+#endif
+
+//      <e>Crypt/Cipher Test Suite
+#define MDK_CONF_CTaoCryptTest 1
+#if MDK_CONF_CTaoCryptTest  == 0
+#define NO_CRYPT_TEST
+#endif
+//  </e>
+//      <e>Crypt/Cipher Benchmark
+#define MDK_CONF_CTaoCryptBenchmark 1
+#if MDK_CONF_CTaoCryptBenchmark == 0
+#define NO_CRYPT_BENCHMARK 
+#define BENCH_EMBEDDED
+#endif
+//  </e>
+//   </h>
+//   <h>SSL/TLS Server/Client
+//      <e>echoServer
+#define MDK_CONF_echoServer 1
+#if MDK_CONF_echoServer == 0
+#define NO_ECHOSERVER
+#endif
+//  </e>
+//      <e>echoClient
+#define MDK_CONF_echoClient 1
+#if MDK_CONF_echoClient == 0
+#define NO_ECHOCLIENT
+#endif
+//  </e>
+//      <e>SimpleServer
+#define MDK_CONF_simpleServer 1
+#if MDK_CONF_simpleServer == 0
+#define NO_SIMPLE_SERVER
+#endif
+//  </e>
+//      <e>SimpleCliet
+#define MDK_CONF_simpleClient 1
+#if MDK_CONF_simpleClient == 0
+#define NO_SIMPLE_CLIENT
+#endif
+//  </e>
+// </h>
+// </h>
+//  <h>STM32 Hardware Crypt
+//      <e>STM32F2 Hardware RNG
+#define MDK_CONF_STM32F2_RNG 0
+#if MDK_CONF_STM32F2_RNG == 1
+#define STM32F2_RNG
+#else
+#define NO_DEV_RANDOM
+#endif
+//  </e>
+//      <e>STM32F2 Hardware Crypt
+#define MDK_CONF_STM32F2_CRYPTO 0
+#if MDK_CONF_STM32F2_CRYPTO == 1
+#define STM32F2_CRYPTO
+#endif
+//  </e>
+
+// </h>
+
+//  <h>CyaSSL Library
+//     <h>SSL (Included by default)
+//     </h>
+
+//      <e>TLS 
+#define MDK_CONF_TLS 1
+#if MDK_CONF_TLS == 0
+#define NO_TLS
+#endif
+//  </e>
+
+//      <e>CertGen
+#define MDK_CONF_CERT_GEN 0
+#if MDK_CONF_CERT_GEN == 1
+#define CYASSL_CERT_GEN
+#endif
+//  </e>
+//      <e>KeyGen
+#define MDK_CONF_KEY_GEN 0
+#if MDK_CONF_KEY_GEN == 1
+#define CYASSL_KEY_GEN
+#endif
+//  </e>
+//      <e>CRL
+#define MDK_CONF_DER_LOAD 0
+#if MDK_CONF_DER_LOAD == 1
+#define CYASSL_DER_LOAD
+#endif
+//  </e>
+//      <e>OpenSSL Extra
+#define MDK_CONF_OPENSSL_EXTRA 1
+#if MDK_CONF_OPENSSL_EXTRA == 1
+#define OPENSSL_EXTRA
+#endif
+//  </e>
+//      <h>CRL Monitor, OCSP (not supported with KEIL)
+//     </h>
+
+// </h>
+
+//  <h>CTaoCrypt Library
+
+//       <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
+//        </h>
+//      <e>MD2
+#define MDK_CONF_MD2 0
+#if MDK_CONF_MD2 == 1
+#define CYASSL_MD2
+#endif
+//  </e>
+//      <e>MD4
+#define MDK_CONF_MD4 1
+#if MDK_CONF_MD4 == 0
+#define NO_MD4
+#endif
+//  </e>
+//      <e>SHA-384
+//          <i>This has to be with SHA512
+#define MDK_CONF_SHA384 0
+#if MDK_CONF_SHA384 == 1
+#define CYASSL_SHA384
+#endif
+//  </e>
+//      <e>SHA-512          
+#define MDK_CONF_SHA512     0
+#if MDK_CONF_SHA512     == 1
+#define CYASSL_SHA512   
+#endif
+//  </e>
+//      <e>RIPEMD
+#define MDK_CONF_RIPEMD 1
+#if MDK_CONF_RIPEMD == 1
+#define CYASSL_RIPEMD
+#endif
+//  </e>
+//      <e>HMAC
+#define MDK_CONF_HMAC 1
+#if MDK_CONF_HMAC == 0
+#define NO_HMAC
+#endif
+//  </e>
+//      <e>HC128
+#define MDK_CONF_HC128 0
+#if MDK_CONF_HC128 == 1
+#define HAVE_HC128
+#endif
+//  </e>
+//  <e>RABBIT
+#define MDK_CONF_RABBIT 1
+#if MDK_CONF_RABBI == 0
+#define NO_RABBIT
+#endif
+//  </e>
+
+//      <e>AEAD     
+#define MDK_CONF_AEAD 0
+#if MDK_CONF_AEAD == 1
+#define HAVE_AEAD
+#endif
+//  </e>
+//      <e>DES3
+#define MDK_CONF_DES3 1
+#if MDK_CONF_DES3 == 0
+#define NO_DES3
+#endif
+//  </e>
+//      <e>CAMELLIA
+#define MDK_CONF_CAMELLIA 0
+#if MDK_CONF_CAMELLIA == 1
+#define HAVE_CAMELLIA
+#endif
+//  </e>
+
+//      <e>DH
+//              <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
+#define MDK_CONF_DH 1
+#if MDK_CONF_DH == 0
+#define NO_DH
+#endif
+//  </e>
+//      <e>DSA
+#define MDK_CONF_DSA 1 
+#if MDK_CONF_DSA == 0
+#define NO_DSA
+#endif
+//  </e>
+//      <e>PWDBASED
+#define MDK_CONF_PWDBASED 1
+#if MDK_CONF_PWDBASED == 0
+#define NO_PWDBASED
+#endif
+//  </e>
+
+//      <e>ECC
+#define MDK_CONF_ECC 1
+#if MDK_CONF_ECC == 1
+#define HAVE_ECC
+#endif
+//  </e>
+//      <e>PSK
+#define MDK_CONF_PSK 1
+#if MDK_CONF_PSK == 0
+#define NO_PSK
+#endif
+//  </e>
+//      <e>AESCCM (Turn off Hardware Crypt)
+#define MDK_CONF_AESCCM 0
+#if MDK_CONF_AESCCM == 1
+#define HAVE_AESCCM
+#endif
+//  </e>
+//      <e>AESGCM (Turn off Hardware Crypt)
+#define MDK_CONF_AESGCM 0
+#if MDK_CONF_AESGCM == 1
+#define HAVE_AESGCM
+#define BUILD_AESGCM
+#endif
+//  </e>
+//      <e>NTRU (need License, "crypto_ntru.h")
+#define MDK_CONF_NTRU 0
+#if MDK_CONF_NTRU == 1
+#define HAVE_NTRU
+#endif
+//  </e>
+//  </h>
+
+//  <h>Others
+
+//      <e>Inline
+#define MDK_CONF_INLINE 0
+#if MDK_CONF_INLINE == 0
+#define NO_INLINE
+#endif
+//  </e>
+//      <h>Debug
+//              <e>Debug Message
+#define MDK_CONF_DEBUG_MSG 0
+#if MDK_CONF_DEBUG_MSG == 1
+#define DEBUG_CYASSL
+#endif
+//         </e>
+//              <e>Check malloc
+#define MDK_CONF_CHECK_MALLOC 1
+#if MDK_CONF_CHECK_MALLOC == 1
+#define CYASSL_MALLOC_CHECK
+#endif
+//         </e>
+
+
+//  </h>
+//      <e>ErrNo.h
+#define MDK_CONF_ERR_NO 0
+#if MDK_CONF_ERR_NO == 1
+#define HAVE_ERRNO
+#endif
+//  </e>
+//      <e>zlib (need "zlib.h")
+#define MDK_CONF_LIBZ 0
+#if MDK_CONF_LIBZ == 1
+#define HAVE_LIBZ
+#endif
+//  </e>
+//      <e>CAVIUM (need CAVIUM headers)
+#define MDK_CONF_CAVIUM 0
+#if MDK_CONF_CAVIUM == 1
+#define HAVE_CAVIUM
+#endif
+//  </e>
+
+//      <e>Error Strings
+#define MDK_CONF_ErrorStrings 1
+#if MDK_CONF_ErrorStrings == 0
+#define NO_ERROR_STRINGS
+#endif
+//  </e>
+
+//      <e>Small Stack
+#define MDK_CONF_SMALL_STACK 1
+#if MDK_CONF_SMALL_STACK == 0
+#define NO_CYASSL_SMALL_STACK
+#endif
+//  </e>
+//      <e>Use Fast Math
+#define MDK_CONF_FASTMATH 0
+#if MDK_CONF_FASTMATH == 1
+#define USE_FAST_MATH
+#endif
+//  </e>
+
+
+//  </h>
+
+//</h>
+// <<< end of configuration section >>>

IDE/MDK-ARM/MDK-ARM/CyaSSL/config.h

@@ -0,0 +1,46 @@
+/* config.h
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+
+/**** CyaSSL for KEIL-RL Configuration ****/
+
+#define __CORTEX_M3__
+#define CYASSL_MDK_ARM
+#define NO_WRITEV
+#define NO_CYASSL_DIR
+
+/* for Retarget.c */
+#define  STDIO
+#define BENCH_EMBEDDED
+
+#define CYASSL_DER_LOAD
+#define HAVE_NULL_CIPHER
+
+#if    defined(MDK_CONF_RTX_TCP_FS)
+#include "config-RTX-TCP-FS.h"
+#elif  defined(MDK_CONF_TCP_FS)
+#include "config-TCP-FS.h"
+#elif  defined(MDK_CONF_FS)
+#include "config-FS.h"
+#elif  defined(MDK_CONF_BARE_METAL)
+#include "config-BARE-METAL.h"
+#endif
+

IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c

@@ -0,0 +1,249 @@
+/* cyassl_MDK_ARM.c
+    *
+    * Copyright (C) 2006-2013 wolfSSL Inc.
+    *
+    * This file is part of CyaSSL.
+    *
+    * CyaSSL is free software; you can redistribute it and/or modify
+    * it under the terms of the GNU General Public License as published by
+    * the Free Software Foundation; either version 2 of the License, or
+    * (at your option) any later version.
+    *
+    * CyaSSL is distributed in the hope that it will be useful,
+    * but WITHOUT ANY WARRANTY; without even the implied warranty of
+    * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    * GNU General Public License for more details.
+    *
+    * You should have received a copy of the GNU General Public License
+    * along with this program; if not, write to the Free Software
+    * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+    */
+
+
+/***************************************************************************************/
+/**   This file is for defining functions for specific to KEIL-RL.                **/
+/***************************************************************************************/
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <stdio.h>
+#if defined (CYASSL_MDK5)
+    #include "cmsis_os.h"
+    #if defined(CYASSL_KEIL_TCP_NET)
+        #include "rl_net.h"
+    #endif
+#else
+    #include <rtl.h>
+#endif
+
+#include "cyassl_MDK_ARM.h"
+
+#include <cyassl/ctaocrypt/visibility.h>
+#include <cyassl/ctaocrypt/logging.h>
+
+#if defined (CYASSL_CMSIS_RTOS)
+        #define os_dly_wait(t)    osDelay(10*t)
+#endif
+
+
+/** KEIL-RL TCPnet ****/
+/** TCPnet BSD socket does not have following functions. **/
+
+#if defined(CYASSL_KEIL_TCP_NET)
+char *inet_ntoa(struct in_addr in) 
+{
+    #define NAMESIZE 16
+    static char name[NAMESIZE] ;
+    sprintf(name, "%d.%d.%d.%d", (in.s_addr>>24)&0xff, (in.s_addr>>16)&0xff, (in.s_addr>>8)&0xff, in.s_addr&0xff) ;
+    return name ;
+}
+
+unsigned long inet_addr(const char *cp)
+{
+    unsigned int a[4] ; unsigned long ret ;
+    sscanf(cp, "%d.%d.%d.%d", &a[0], &a[1], &a[2], &a[3]) ;
+    ret = ((a[3]<<24) + (a[2]<<16) + (a[1]<<8) + a[0]) ;
+    return(ret) ;
+}
+
+
+/*** tcp_connect is actually associated with following syassl_tcp_connect. ***/
+int Cyassl_connect(int sd, const  struct sockaddr* sa, int sz) 
+{
+    int ret = 0 ;
+    #if defined(CYASSL_KEIL_TCP_NET)  
+    
+    SOCKADDR_IN addr ;
+
+    addr = *(SOCKADDR_IN *)sa ;
+
+    do {
+        #undef connect  /* Go to KEIL TCPnet connect */
+        ret = connect(sd, (SOCKADDR *)&addr, sizeof(addr)) ;
+        os_dly_wait(50);
+    } while(ret == SCK_EWOULDBLOCK) ;
+    #ifdef DEBUG_CYASSL
+    { 
+        char msg[50] ;
+        sprintf(msg, "BSD Connect return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;
+    }
+    #endif
+    
+    #endif /* CYASSL_KEIL_TCP_NET */
+    return(ret ) ;
+}
+
+
+int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen) 
+{
+    int ret = 0 ;
+
+    #if defined(CYASSL_KEIL_TCP_NET)
+    while(1) {
+        #undef accept  /* Go to KEIL TCPnet accept */
+        ret = accept(sd, addr,  addrlen) ;
+        if(ret != SCK_EWOULDBLOCK) break ;
+        os_dly_wait(1);
+    } 
+    #ifdef DEBUG_CYASSL
+    {
+        char msg[50] ;
+        sprintf(msg, "BSD Accept return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+    
+    #endif /* CYASSL_KEIL_TCP_NET */
+    return(ret ) ;
+
+}
+    
+int Cyassl_recv(int sd, void *buf, size_t len, int flags) 
+{
+    int ret  = 0;
+    #if defined(CYASSL_KEIL_TCP_NET)  
+    while(1) {
+        #undef recv  /* Go to KEIL TCPnet recv */
+        ret = recv(sd, buf, len,  flags) ;
+        if((ret != SCK_EWOULDBLOCK) &&( ret != SCK_ETIMEOUT)) break ;
+        os_dly_wait(1);
+    }
+    #ifdef DEBUG_CYASSL
+    {       
+        char msg[50] ;
+        sprintf(msg, "BSD Recv return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+
+    #endif  /* CYASSL_KEIL_TCP_NET */
+    return(ret ) ;
+}
+
+int Cyassl_send(int sd, const void *buf, size_t len, int flags) 
+{
+    int  ret = 0 ;
+
+    #if defined(CYASSL_KEIL_TCP_NET)  
+    while(1) {
+    #undef send  /* Go to KEIL TCPnet send */
+        ret = send(sd, buf, len,  flags) ;
+        if(ret != SCK_EWOULDBLOCK) break ;
+        os_dly_wait(1);
+    } 
+    #ifdef DEBUG_CYASSL
+    {
+        char msg[50] ;
+        sprintf(msg, "BSD Send return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+
+#endif  /* CYASSL_KEIL_TCP_NET */
+    return(ret) ;
+
+}
+
+#endif /* CYASSL_KEIL_TCP_NET */
+
+#if defined(CYASSL_KEIL_TCP_NET)  
+void Cyassl_sleep(int t) 
+{
+    #if defined(HAVE_KEIL_RTX)
+    os_dly_wait(t/1000+1) ;
+    #endif
+}
+
+int Cyassl_tcp_select(int sd, int timeout) 
+{
+    
+    return 0 ;
+    
+}
+#endif
+
+extern int strlen(const char *s) ;
+
+FILE * CyaSSL_fopen(const char *name, const char *openmode) 
+{
+    int i ;  FILE * ret ;
+    #define PATHSIZE 100
+    char path[PATHSIZE] ; char *p ;
+    
+    if(strlen(name) > PATHSIZE)return(NULL) ;
+    
+    for(i = 0; i<= strlen(name); i++) {
+        if(name[i] == '/')path[i] = '\\' ;
+        else              path[i] = name[i] ;
+    }       
+    if(path[0] == '.' && path[1] == '\\') p = path + 2 ;
+    else                                  p = path ;
+
+    ret = fopen (p, openmode) ;
+    
+    return(ret) ;
+}
+
+#if defined (CYASSL_MDK5)
+#define getkey getchar
+#define sendchar putchar
+#else
+extern int getkey(void) ;
+extern int sendchar(int c) ;
+#endif
+
+char * Cyassl_fgets ( char * str, int num, FILE * f ) 
+{
+    int i ;
+    
+    for(i = 0 ; i< num ; i++) {
+            while((str[i] = getkey()) == 0) {
+            #if defined (HAVE_KEIL_RTX) 
+						    #if !defined(CYASSL_CMSIS_RTOS)
+                    os_tsk_pass ();
+					      #else 
+                    osThreadYield ();
+                #endif
+				    #endif
+        }
+        if(str[i] == '\n' || str[i] == '\012' || str[i] == '\015')  {
+            sendchar('\n') ;    
+            str[i++] = '\n' ; 
+            str[i] = '\0' ; 
+            break ;
+        } else if(str[i] == '\010') { /* BS */
+            if(i) { /* erace one char */
+                sendchar('\010') ; sendchar(' ') ; sendchar('\010') ; 
+                i = (i>0 ? (i-2) : -1 ) ;
+                continue ;
+            } 
+        } else if(str[i] == '\033'  || str[i] == '\004' ) {  /* ESC or ^D */
+            str[i] = '\0' ;
+            return(0) ;
+        }
+        sendchar(str[i]) ;
+    }
+    return(str) ;
+}

IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h

@@ -0,0 +1,103 @@
+/* cyassl_KEIL_RL.h
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/******************************************************************************/
+/**   This file is for defining types, values for specific to KEIL-MDK-ARM.  **/
+/******************************************************************************/
+#ifndef CYASSL_KEIL_RL_H
+#define CYASSL_KEIL_RL_H
+
+
+
+#include <stdio.h>
+
+/* Go to STDIN */
+#define fgets(buff, sz, fd)   Cyassl_fgets(buff, sz, fd) 
+extern char * Cyassl_fgets ( char * str, int num, FILE * f ) ;
+
+#define SOCKET_T int
+
+/*** #include <socket.h> ***/
+#define  NUMBITSPERBYTE 8
+#define FD_SETSIZE 10
+
+typedef long fd_mask;
+#define NFDBITS   (sizeof(fd_mask) * NUMBITSPERBYTE)  /* bits per mask */
+
+typedef struct fd_set {
+  fd_mask fds_bits[(FD_SETSIZE + NFDBITS - 1) / NFDBITS];
+} fd_set;
+
+/*** #include <sys/types.h> ***/
+struct timeval {
+   long tv_sec;     /* seconds      */
+   long tv_usec;    /* microseconds */
+};
+
+
+/***  #include <unistd.h>  **/
+/*
+ int select(int nfds, fd_set *readfds, fd_set *writefds,
+            fd_set *exceptfds, const struct timeval *timeout);
+  void FD_CLR(int fd, fd_set *set);
+  int  FD_ISSET(int fd, fd_set *set);
+  void FD_SET(int fd, fd_set *set);
+  void FD_ZERO(fd_set *set);
+*/
+typedef int socklen_t ;
+
+/* for avoiding conflict with KEIL-TCPnet BSD socket */
+/* Bodies are in cyassl_KEIL_RL.c                    */
+#define connect             Cyassl_connect
+#define accept              Cyassl_accept
+#define recv                Cyassl_recv
+#define send                Cyassl_send
+#define sleep               Cyassl_sleep
+
+/* for avoiding conflicting with KEIL-TCPnet TCP socket */
+/* Bodies are in test.h */
+#define tcp_connect Cyassl_tcp_connect    
+#define tcp_socket    Cyassl_tcp_soket
+#define tcp_listen      Cyassl_tcp_listen
+#define tcp_select     Cyassl_tcp_select
+
+extern int Cyassl_connect(int sd, const struct sockaddr * sa, int sz) ;
+extern int Cyassl_accept(int sd, struct sockaddr *addr, socklen_t *addrlen);
+extern int Cyassl_recv(int sd, void *buf, size_t len, int flags);
+extern int Cyassl_send(int sd, const void *buf, size_t len, int flags);
+extern void Cyassl_sleep(int sec) ;
+extern int Cyassl_tcp_select(int sd, int timeout) ;
+
+/** KEIL-RL TCPnet ****/
+/* TCPnet BSD socket does not have following functions. */
+extern char *inet_ntoa(struct in_addr in);
+extern unsigned long inet_addr(const char *cp);
+extern int setsockopt(int sockfd, int level, int optname, 
+                                      const void *optval, socklen_t optlen);
+extern int select(int nfds, fd_set *readfds, fd_set *writefds,
+                          fd_set *exceptfds, const struct timeval *timeout);
+
+/* CyaSSL MDK-ARM time functions */
+#include <time.h>
+struct tm *Cyassl_MDK_gmtime(const time_t *c) ;
+extern double current_time(void) ;
+
+#endif /* CYASSL_KEIL_RL_H */

IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c

@@ -0,0 +1,172 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ctaocrypt/visibility.h>
+#include <cyassl/ctaocrypt/logging.h>
+
+#include <RTL.h>
+#include <stdio.h>
+#include "cyassl_MDK_ARM.h"
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+#if !defined(NO_FILESYSTEM)
+static void init_card (void) 
+{
+    U32 retv;
+
+    while ((retv = finit (NULL)) != 0) {     /* Wait until the Card is ready */
+        if (retv == 1) {
+            printf ("\nSD/MMC Init Failed");
+            printf ("\nInsert Memory card and press key...\n");
+        } else {
+            printf ("\nSD/MMC Card is Unformatted");
+        }
+     }
+}
+#endif
+
+
+/*-----------------------------------------------------------------------------
+ *        TCP/IP tasks
+ *----------------------------------------------------------------------------*/
+#ifdef CYASSL_KEIL_TCP_NET
+__task void tcp_tick (void) 
+{
+    
+    CYASSL_MSG("Time tick started.") ;
+    #if defined (HAVE_KEIL_RTX)
+    os_itv_set (10);
+    #endif
+  
+    while (1) {
+        #if defined (HAVE_KEIL_RTX)
+        os_itv_wait ();
+        #endif
+        /* Timer tick every 100 ms */
+        timer_tick ();
+    }
+}
+
+__task void tcp_poll (void)
+{
+    CYASSL_MSG("TCP polling started.\n") ;
+    while (1) {
+        main_TcpNet ();
+        #if defined (HAVE_KEIL_RTX)
+        os_tsk_pass ();
+        #endif
+    }
+}
+#endif
+
+#if defined(HAVE_KEIL_RTX) && defined(CYASSL_MDK_SHELL)
+#define SHELL_STACKSIZE 1000
+static unsigned char Shell_stack[SHELL_STACKSIZE] ;
+#endif
+
+
+#if  defined(CYASSL_MDK_SHELL)
+extern void shell_main(void) ;
+#endif
+
+extern void time_main(int) ;
+extern void benchmark_test(void) ;
+extern void SER_Init(void) ;
+
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+
+/*** This is the parent task entry ***/
+void main_task (void) 
+{
+    #ifdef CYASSL_KEIL_TCP_NET
+    init_TcpNet ();
+
+    os_tsk_create (tcp_tick, 2);
+    os_tsk_create (tcp_poll, 1);
+    #endif
+    
+    #ifdef CYASSL_MDK_SHELL 
+        #ifdef  HAVE_KEIL_RTX
+           os_tsk_create_user(shell_main, 1, Shell_stack, SHELL_STACKSIZE) ;
+       #else
+           shell_main() ;
+       #endif
+    #else
+
+    /************************************/
+    /*** USER APPLICATION HERE        ***/
+    /************************************/
+    printf("USER LOGIC STARTED\n") ;
+	
+    #endif 
+
+    #ifdef   HAVE_KEIL_RTX
+    CYASSL_MSG("Terminating tcp_main\n") ;
+    os_tsk_delete_self ();
+    #endif
+
+}
+
+
+    int myoptind = 0;
+    char* myoptarg = NULL;
+
+#if defined(DEBUG_CYASSL)
+    extern void CyaSSL_Debugging_ON(void) ;
+#endif
+
+
+/*** main entry ***/
+extern void init_time(void) ;
+extern void 	SystemInit(void);
+
+int main() {
+
+    SystemInit();  
+    SER_Init() ;
+    #if !defined(NO_FILESYSTEM)
+    init_card () ;     /* initializing SD card */
+    #endif
+
+    init_time() ;
+
+    #if defined(DEBUG_CYASSL)
+         printf("Turning ON Debug message\n") ;
+         CyaSSL_Debugging_ON() ;
+    #endif
+    
+    #ifdef   HAVE_KEIL_RTX
+        os_sys_init (main_task) ;
+    #else
+        main_task() ;
+    #endif
+
+    return 0 ; /* There should be no return here */
+
+}

IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c

@@ -0,0 +1,595 @@
+/*shell.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+ /*** tiny Shell for CyaSSL apps ***/
+ 
+ #ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include "cyassl/internal.h"
+#undef RNG
+#include <cyassl/ctaocrypt/logging.h>
+
+#if defined(CYASSL_MDK_ARM)
+    #include <stdio.h>
+    #include <string.h>
+    #include <stdlib.h>
+    #include <rtl.h>
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#ifdef CYASSL_KEIL_NET
+#include "cyassl/test.h"
+#else
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+#endif
+
+#ifdef NO_ECHOCLIENT
+#define echoclient_test command_not_found
+#endif
+#ifdef NO_ECHOSERVER
+#define echoserver_test command_not_found
+#endif
+#ifdef NO_SIMPLE_CLIENT
+#define client_test command_not_found
+#endif
+#ifdef NO_SIMPLE_SERVER
+#define server_test command_not_found
+#endif
+#ifdef NO_CRYPT_BENCHMARK
+#define benchmark_test command_not_found
+#endif
+#ifdef NO_CRYPT_TEST
+#define ctaocrypt_test command_not_found
+#endif
+
+#ifndef CYASSL_KEIL_NET
+#define ipaddr_comm command_not_found
+#endif
+
+#if !defined(HAVE_KEIL_RTX)
+#define stack_comm command_not_found
+#endif
+
+
+#if !defined(DEBUG_CYASSL)
+#define dbg_comm command_not_found
+#endif
+
+
+void command_not_found(void *argv) {
+        printf("Command not found\n") ;
+}
+
+extern void echoclient_test(void *args) ;
+extern void echoserver_test(void *args) ;
+extern void benchmark_test(void *args) ;
+extern void ctaocrypt_test(void *args) ;
+extern void client_test(void *args) ;
+extern void server_test(void *args) ;
+extern void kill_task(void *args) ;
+extern void time_main(void *args) ;
+extern void ipaddr_comm(void *args) ;
+extern void stack_comm(void *args) ;
+extern void for_command(void *args) ;
+extern void dbg_comm(void *arg) ;
+extern void help_comm(void *arg) ;
+
+#if !defined(NO_CRYPT_TEST)
+
+#ifndef NO_MD5
+extern void md5_test(void *arg) ;
+#endif
+#ifdef CYASSL_MD2
+extern void md2_test(void *arg) ;
+#endif
+#ifndef NO_MD4
+extern void md4_test(void *arg) ;
+#endif
+
+extern void sha_test(void *arg) ;
+
+#ifndef NO_SHA256
+extern void sha256_test(void *arg) ;
+#endif
+#ifdef CYASSL_SHA384
+extern void sha384_test(void *arg) ;
+#endif
+
+#ifdef CYASSL_SHA512
+extern void sha512_test(void *arg) ;
+#endif
+
+#ifdef CYASSL_RIPEMD
+extern void ripemd_test(void *arg) ;
+#endif
+#ifndef NO_HMAC
+    #ifndef NO_MD5
+extern void hmac_md5_test(void *arg) ;
+    #endif
+extern void hmac_sha_test(void *arg) ;
+
+    #ifndef NO_SHA256
+extern void hmac_sha256_test(void *arg) ;
+    #endif
+
+    #ifdef CYASSL_SHA384
+extern void hmac_sha384_test(void *arg) ;
+    #endif
+#endif
+#ifndef NO_RC4
+extern void arc4_test(void *arg) ;
+#endif
+
+#ifndef NO_HC128
+extern void hc128_test(void *arg) ;
+#endif
+
+#ifndef NO_RABBIT
+extern void rabbit_test(void *arg) ;
+#endif
+
+#ifndef NO_DES3
+extern void des_test(void *arg) ;
+extern void des3_test(void *arg) ;
+#endif
+
+#ifndef NO_AES
+extern void aes_test(void *arg) ;
+#ifdef HAVE_AESGCM
+extern void aesgcm_test(void *arg) ;
+#endif
+
+#ifdef HAVE_AESCCM
+extern void aesccm_test(void *arg) ;
+#endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+extern void camellia_test(void *arg) ;
+#endif
+extern void random_test(void *arg) ;
+
+#ifndef NO_RSA
+extern void rsa_test(void *arg) ;
+#endif
+
+#ifndef NO_DH
+extern void dh_test(void *arg) ;
+#endif
+
+#ifndef NO_DSA
+extern void dsa_test(void *arg) ;
+#endif
+    
+#ifndef NO_PWDBASED
+extern void pwdbased_test(void *arg) ;
+#endif
+
+#ifdef HAVE_ECC
+extern void openssl_test(void *arg) ;
+#endif
+
+#ifdef HAVE_ECC
+extern void ecc_test(void *arg) ;
+#endif
+
+#endif /* NO_CRYPT_TEST */
+
+static struct {
+  const char *command ;
+    void (*func)(void *args) ;
+}   commandTable[] = {
+    "echoclient", echoclient_test,
+    "echoserver", echoserver_test,
+    "benchmark", benchmark_test,
+    "test", ctaocrypt_test,
+    "client", client_test,
+    "server", server_test,
+    "time", time_main,          /* get/set RTC:  [-d yy/mm/dd] [-t hh:mm:ss]*/
+    "ipaddr", ipaddr_comm,      /* TBD */
+    "stack", stack_comm,        /* On/Off check stack size */
+    "for", for_command,         /* iterate next command X times */
+    "debug", dbg_comm,          /* On/Off debug message  */
+    "help", help_comm,          /* Breif description about the commands */
+
+    /** short name **/
+    "ec", echoclient_test,
+    "es", echoserver_test,
+    "bm", benchmark_test,
+    "te", ctaocrypt_test,
+    "cl", client_test,
+    "sv", server_test,
+    "ip", ipaddr_comm,
+    "st", stack_comm,
+  "dbg", dbg_comm,
+    "?",    help_comm,
+
+/*** test suites ****/
+#if !defined(NO_CRYPT_TEST)
+#ifndef NO_MD5
+  "md5",  md5_test,
+#endif
+#ifdef CYASSL_MD2
+  "md2",  md2_test,
+#endif
+#ifndef NO_MD4
+  "md4",  md4_test,
+#endif
+  "sha",  sha_test,
+#ifndef NO_SHA256
+  "sha256",  sha256_test,
+#endif
+#ifdef CYASSL_SHA384
+  "sha384",  sha384_test,
+#endif
+#ifdef CYASSL_SHA512
+  "sha512",  sha512_test,
+#endif
+#ifdef CYASSL_RIPEMD
+  "ripemd",  ripemd_test,
+#endif
+#ifndef NO_HMAC
+  #ifndef NO_MD5
+  "hmac_md5",  hmac_md5_test,
+    #endif
+  "hmac_sha",  hmac_sha_test,
+    #ifndef NO_SHA256
+  "hmac_sha256",  hmac_sha256_test,
+    #endif
+    #ifdef CYASSL_SHA384
+  "hmac_sha384",  hmac_sha384_test,
+  #endif
+#endif
+#ifndef NO_RC4
+    "arc4",  arc4_test,
+#endif
+#ifndef NO_HC128
+  "hc128",  hc128_test,
+#endif
+#ifndef NO_RABBIT
+  "rabbit",  rabbit_test,
+#endif
+#ifndef NO_DES3
+  "des",  des_test,
+  "des3",  des3_test,
+#endif  
+#ifndef NO_AES  
+  "aes",  aes_test,
+    #ifdef HAVE_AESGCM
+  "aesgcm",  aesgcm_test,
+    #endif
+    #ifdef HAVE_AESCCM
+  "aesccm",  aesccm_test,
+    #endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+  "camellia",  camellia_test,
+#endif
+  "random",  random_test,
+#ifndef NO_RSA
+  "rsa",  rsa_test,
+#endif
+#ifndef NO_DH
+  "dh",  dh_test,
+#endif
+#ifndef NO_DSA
+    "dsa",  dsa_test,
+#endif 
+#ifndef NO_PWDBASED
+  "pwdbased",  pwdbased_test,
+#endif  
+#ifdef OPENSSL_EXTRA
+  "openssl",  openssl_test,
+#endif
+#ifdef HAVE_ECC
+  "ecc",  ecc_test,
+#endif
+
+#endif /* NO_CRYPT_TEST */
+
+    "",  NULL
+} ;
+
+enum jobtype { FORGROUND, BACKGROUND }  ;
+
+#define IF_DELIMITER(ch) ((ch) == ' ' || (ch) == '\n')
+
+/*******  Get Command Line *****************************/
+static int getline(char * line, int sz, func_args *args, int*bf_flg) 
+{
+    char * ret ;
+    int i ;
+    
+    #define MAXARGS 10
+    #define MAXARGLEN 30
+    static char *argv[MAXARGS] ;
+    args->argv = argv ;
+    
+    putchar('>') ;
+    fflush(stdout) ;
+    ret = fgets(line, sz, stdin) ;
+    #define SHELL_ERROR_FGETS -102
+    if(ret != line) return(SHELL_ERROR_FGETS) ;
+    
+    if(line[strlen(line)-2] == '&') {
+        (*bf_flg) = BACKGROUND ;
+        line[strlen(line)-2] = '\n' ;
+    } else {
+        (*bf_flg) = FORGROUND ;
+    }
+    args->argc = 0 ;
+    for(i=0; i<sz; i++) {
+        args->argv[args->argc] = &(line[i]) ;
+        while(!IF_DELIMITER(line[i])) i++ ;
+        args->argc++ ;
+        if(line[i] == '\n') {
+            line[i]  = '\0' ;
+            break ;
+        } else {
+            line[i]  = '\0' ;
+        }
+    }
+    return i ;
+}
+
+static int BackGround = 0 ; /* 1: background job is running */
+
+/************* Embedded Shell Commands **********************************/
+#define IP_SIZE 16
+
+#ifdef CYASSL_KEIL_NET
+static void ipaddr_comm(void *args) 
+{
+    if(((func_args *)args)->argc == 1) {
+            printf("IP addr: %s, port %d\n", yasslIP, yasslPort) ;
+    } else {
+        if(BackGround != 0) {
+        printf("Cannot change IP addr while background server is running\n") ;
+        } else if(((func_args *)args)->argc == 3 && 
+                  ((func_args *)args)->argv[1][0] == '-'&& 
+                  ((func_args *)args)->argv[1][1] == 'a' ) {
+/*          strcpy(yasslIP, ((func_args *)args)->argv[2]) ; */
+        } else if(((func_args *)args)->argc == 3 && 
+                  ((func_args *)args)->argv[1][0] == '-' && 
+                  ((func_args *)args)->argv[1][1] == 'p' ) {
+/*          yasslPort = atoi(((func_args *)args)->argv[2]) ; */
+        } else printf("Invalid argument\n") ; 
+    }
+}
+
+#endif
+
+
+
+#if defined(HAVE_KEIL_RTX)
+static int stack_ck = 0 ;
+
+static void stack_comm(void *args) 
+{
+    if(stack_ck) {
+        printf("Stack Check: Off\n") ;
+        stack_ck = 0 ;
+    } else {
+        printf("Stack Check: On\n") ;
+        stack_ck = 1 ;
+    }
+}
+    
+#define FILL_PATTERN 0xa596695a
+void stack_fill(char * stack, int size)
+{
+    int i ;
+
+    if(stack_ck == 0)return ;
+    for(i=1; i<size/4-10; i++)
+        ((int *)stack)[i] = FILL_PATTERN ;
+}
+
+void stack_check(char * stack, int size) 
+{
+    int i ;
+    
+    if(stack_ck == 0)return ;
+    if(stack_ck == 1) {
+        stack_ck ++ ; return ; 
+    }
+    for(i=1; i<size/4 ; i++) {
+        if(((int *)stack)[i] != FILL_PATTERN) break ;
+    }
+    if(i < size/4) {
+        printf("Stack is used %d bytes out of %d\n", size - i*4, size) ;
+    } else {
+        printf("Stack overflow. Stack size: %d\n", size) ;
+    }
+}
+
+#endif /* HAVE_KEIL_RTX */
+
+static int for_iteration = 1 ;
+
+static void for_command(void *args) 
+{
+    if( args == NULL || ((func_args *)args)->argc == 1) {
+        printf("For %d times\n", for_iteration) ;
+    } else if( args == NULL || ((func_args *)args)->argc == 2) {
+        for_iteration = atoi(((func_args *)args)->argv[1]) ;
+    } else printf("Invalid argument\n") ;
+}
+
+
+#if defined(DEBUG_CYASSL)
+
+static int CyasslDebug = 1 ;
+
+static void dbg_comm(void *args) 
+{
+    if(CyasslDebug == 1) {
+        CyasslDebug = 0 ;
+        printf("Turning OFF Debug message\n") ;
+        CyaSSL_Debugging_OFF() ;
+    } else {
+        CyasslDebug = 1 ;
+        printf("Turning ON Debug message\n") ;
+        CyaSSL_Debugging_ON() ;
+    }
+}
+#endif
+
+static void help_comm(void *args) 
+{
+    
+}
+
+
+
+#define BG_JOB_STACK_SIZE 12000
+#if (!defined(NO_SIMPLE_SERVER) && !defined(NO_ECHOSERVER)) && \
+                                                   defined(HAVE_KEIL_RTX)
+static char bg_job_stack[BG_JOB_STACK_SIZE] ;
+#endif
+
+#define COMMAND_STACK_SIZE 12000
+#if defined(HAVE_KEIL_RTX)
+static char command_stack[COMMAND_STACK_SIZE] ;
+#endif
+
+
+#ifdef  HAVE_KEIL_RTX
+static   CyaSSL_Mutex command_mutex ;
+#endif
+
+/***********    Invoke Forground Command  *********************/
+static void command_invoke(void *args) 
+{
+    void (*func)(void * ) ;
+    int i,iteration ;
+
+    func = (void(*)(void *))((func_args *)args)->argv[0] ; 
+    #ifdef  HAVE_KEIL_RTX
+    LockMutex((CyaSSL_Mutex *)&command_mutex) ;
+    #endif
+    iteration = for_iteration ;
+    for(i=0; i< iteration; i++) {
+        if(iteration > 1) printf("--- Start for %d ---->\n", i) ;
+        #if defined(HAVE_KEIL_RTX)
+        stack_fill(command_stack, COMMAND_STACK_SIZE) ;
+        #endif
+                
+        func(args) ;        /* invoke command */
+                
+        #if defined(HAVE_KEIL_RTX)
+        stack_check(command_stack, COMMAND_STACK_SIZE) ;
+        #endif
+    }
+    if(iteration > 1) 
+        for_iteration = 1 ;
+    #ifdef HAVE_KEIL_RTX
+    UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+    os_tsk_delete_self() ;
+    #endif
+}
+
+#if (!defined(NO_SIMPLE_SERVER) && !defined(NO_ECHOSERVER)) && \
+                                                      defined(HAVE_KEIL_RTX)
+/*******  Invoke Background Job   *******************************/
+static void bg_job_invoke(void *args) 
+{
+    void (*func)(void * ) ;
+    BackGround = 1 ; 
+    stack_fill(bg_job_stack, BG_JOB_STACK_SIZE) ;
+    func = (void(*)(void *))((func_args *)args)->argv[0] ; 
+    func(args) ;        /* invoke command */
+    stack_check(bg_job_stack, BG_JOB_STACK_SIZE) ;
+    #ifdef CYASSL_KEIL_NET
+    init_TcpNet ();
+    #endif
+    BackGround = 0 ;
+    os_tsk_delete_self() ; ;
+}
+#endif
+
+#define LINESIZE 100
+static char line[LINESIZE] ;
+
+
+/********* SHEULL MAIN LOOP ***********************************/
+void shell_main(void) {
+    int i ; 
+    func_args args ;
+    int bf_flg ;
+   
+    i = BackGround ; 
+        /* Dummy for avoiding warning: BackGround is defined but not used. */
+    
+    
+ #if defined(HAVE_KEIL_RTX)
+    InitMutex(&command_mutex) ;
+#endif
+    time_main(NULL) ;
+    printf("Starting Shell\n") ;
+    while(1) {
+        if(getline(line,  LINESIZE, &args, &bf_flg) > 0) {
+        for(i=0; commandTable[i].func != NULL; i++) {
+            if(strcmp(commandTable[i].command, args.argv[0]) == 0) {
+            args.argv[0] = (char *) commandTable[i].func ;
+                if(bf_flg == FORGROUND) {
+                    #ifdef  HAVE_KEIL_RTX
+                    UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                    os_tsk_create_user_ex( (void(*)(void *))&command_invoke, 7,
+                            command_stack, COMMAND_STACK_SIZE, &args) ;
+                    #else
+                    command_invoke(&args) ;
+                    #endif
+                    #ifdef  HAVE_KEIL_RTX
+                    LockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                    #endif
+                } else {
+                    #if (!defined(NO_SIMPLE_SERVER) && \
+                         !defined(NO_ECHOSERVER)) && \
+                         defined(HAVE_KEIL_RTX)
+                    if(BackGround != 0) {
+                        printf("Multiple background servers not supported.\n") ;
+                    } else {
+                        printf("\"%s\" is running with the background mode.\n", 
+                                                     commandTable[i].command) ;
+                        os_tsk_create_user_ex( (void(*)(void *))&bg_job_invoke, 
+                                   6, bg_job_stack, BG_JOB_STACK_SIZE, &args) ;
+                    }
+                    #else
+                    printf("Invalid Command: no background job\n") ;
+                    #endif
+                }
+                break ;
+            }
+        }
+        if(commandTable[i].func == NULL)
+            printf("Command not found\n") ;
+        }
+    }
+}
+

IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c

@@ -0,0 +1,53 @@
+/* ssl-dummy.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ssl.h>
+#include <cyassl/internal.h>
+#include <cyassl/error-ssl.h>
+#include <cyassl/ctaocrypt/coding.h>
+
+Signer* GetCA(void* vp, byte* hash) 
+{ 
+    Signer*s ;
+    return  s ;
+}
+
+int CyaSSL_dtls(CYASSL* ssl)
+{
+    return ssl->options.dtls;
+}
+
+int CyaSSL_get_using_nonblock(CYASSL* ssl)
+{
+    CYASSL_ENTER("CyaSSL_get_using_nonblock");
+    CYASSL_LEAVE("CyaSSL_get_using_nonblock", ssl->options.usingNonblock);
+    return ssl->options.usingNonblock;
+}
+
+Signer* GetCAByName(void* vp, byte* hash)
+{
+    Signer * ca ;
+    return(ca) ;
+}

IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini

@@ -0,0 +1,22 @@
+/******************************************************************************/
+/* Dbg_Flash.ini Initialization File for Debugging from Internal              */
+/*               Flash for NXP LPC18xx/LPC43xx                                */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2012 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+FUNC void Per_Reset (void) {
+  // Reset peripherals: LCD, USB0, USB1, DMA, SDIO, ETHERNET
+  _WDWORD(0x40053100, 0x005F0000);   // Issue reset
+  _sleep_(1);
+}
+
+Per_Reset();                                     // Reset some peripherals
+
+KILL BUTTON *                                    // Kill all buttons
+DEFINE BUTTON "Reset Peripherals", "Per_Reset()" // Create peripheral reset button
+

IDE/MDK-ARM/MDK-ARM/config/File_Config.c

@@ -0,0 +1,401 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - FlashFS
+ *----------------------------------------------------------------------------
+ *      Name:    FILE_CONFIG.C
+ *      Purpose: Configuration of RL FlashFS by user
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *      This code is part of the RealView Run-Time Library.
+ *      Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+ 
+#include <File_Config.h>
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>File System
+// ==============
+// <i> Define File System global parameters
+
+//   <o>Number of open files <4-16>
+//   <i>Define number of files that can be
+//   <i>opened at the same time.
+//   <i>Default: 8
+#define N_FILES     6
+
+//   <o>FAT Name Cache Size <0-1000000>
+//   <i>Define number of cached FAT file or directory names.
+//   <i>48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACNT   0
+
+//   <e>Relocate FAT Name Cache Buffer
+//   <i>Locate Cache Buffer at a specific address.
+#define FAT_NAME_RELOC   0
+
+//   <o>Base address <0x0000-0xFFFFFE00:0x200>
+//   <i>Define the Cache buffer base address.
+#define FAT_NAME_CADR    0x60000000
+
+//   </e>
+//   <o>CPU Clock Frequency [Hz]<0-1000000000>
+//   <i>Define the CPU Clock frequency used for
+//   <i>flash programming and erasing.
+#define CPU_CLK     180000000
+
+// </h>
+// <e>Flash Drive
+// ==============
+// <i>Enable Embedded Flash Drive [F:]
+#define FL0_EN      0
+
+//   <o>Base address <0x0-0xFFFFF000:0x1000>
+//   <i>Define the target device Base address
+//   <i>Default: 0x80000000
+#define FL0_BADR    0x80000000
+
+//   <o>Device Size <0x4000-0xFFFFF000:0x4000>
+//   <i>Define the size of Flash device in bytes
+//   <i>Default: 0x100000 (1MB)
+#define FL0_SIZE    0x0200000
+
+//   <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
+//   <i>Define the initial value for erased Flash data
+//   <i>Default: 0xFF
+#define FL0_INITV   0xFF
+
+//   <s.80>Device Description file
+//   <i>Specify a file name with a relative path
+//   <i>Default: FS_FlashDev.h
+#define FL0_HFILE   "FS_FlashDev.h"
+
+//   <q>Default Drive [F:]
+//   <i>Used when Drive letter not specified
+#define FL0_DEF     1
+
+// </e>
+// <e>SPI Flash Drive
+// ==================
+// <i>Enable SPI Flash Drive [S:]
+#define SF0_EN      0
+
+//   <o>Device Size <0x10000-0xFFFFF000:0x8000>
+//   <i>Define the size of SPI Flash device in bytes
+//   <i>Default: 0x100000 (1MB)
+#define SF0_SIZE    0x0200000
+
+//   <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
+//   <i>Define the initial value for erased Flash data
+//   <i>Default: 0xFF
+#define SF0_INITV   0xFF
+
+//   <s.80>Device Description file
+//   <i>Specify a file name with a relative path
+//   <i>Default: FS_SPI_FlashDev.h
+#define SF0_HFILE   "FS_SPI_FlashDev.h"
+
+//   <q>Default Drive [S:]
+//   <i>Used when Drive letter not specified
+#define SF0_DEF     0
+
+// </e>
+// <e>RAM Drive
+// ============
+// <i>Enable Embedded RAM Drive  [R:]
+#define RAM0_EN     0
+
+//   <o>Device Size <0x4000-0xFFFFF000:0x4000>
+//   <i>Define the size of RAM device in bytes
+//   <i>Default: 0x40000
+#define RAM0_SIZE   0x004000
+
+//   <o>Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128
+//   <i>Define number of virtual sectors for RAM device
+//   <i>Default: 32
+#define RAM0_NSECT  64
+
+//   <e>Relocate Device Buffer
+//   <i>Locate RAM Device Buffer at a specific address.
+//   <i>If not enabled, the linker selects base address.
+#define RAM0_RELOC  1
+
+//   <o>Base address <0x0-0xFFFFF000:0x1000>
+//   <i>Define the target device Base address.
+//   <i>Default: 0x81000000
+#define RAM0_BADR   0x81010000
+
+//   </e>
+//   <q>Default Drive [R:]
+//   <i>Used when Drive letter not specified
+#define RAM0_DEF    0
+
+// </e>
+// <e>Memory Card Drive 0
+// ======================
+// <i>Enable Memory Card Drive  [M0:]
+#define MC0_EN      1
+
+//   <o>Bus Mode <0=>SD-Native <1=>SPI
+//   <i>Define Memory Card bus interface mode.
+//   <i>SD-Native mode needs MCI peripheral.
+//   <i>SPI mode uses SD Card in SPI mode.
+#define MC0_SPI     0
+          
+//   <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                        <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Define System Cache buffer size for file IO. 
+//   <i>Increase this number for faster r/w access.
+//   <i>Default: 4 kB
+#define MC0_CASZ    4
+
+//   <e>Relocate Cache Buffer
+//   <i>Locate Cache Buffer at a specific address.
+//   <i>Some devices like NXP LPC23xx require a Cache buffer
+//   <i>for DMA transfer located at specific address.
+#define MC0_RELOC   0
+
+//   <o>Base address <0x0000-0xFFFFFE00:0x200>
+//   <i>Define the Cache buffer base address.
+//   <i>For LPC23xx/24xx devices this is USB RAM
+//   <i>starting at 0x7FD00000.
+#define MC0_CADR    0x7FD00000
+
+//   </e>
+//   <q>FAT Journal
+//   <i>Enable FAT Journal in order to guarantee
+//   <i>fail-safe FAT file system operation.
+#define MC0_FSJ     0
+
+//   <q>Default Drive [M0:]
+//   <i>Used when Drive letter not specified
+#define MC0_DEF     1
+
+// </e>
+// <e>Memory Card Drive 1
+// ======================
+// <i>Enable Memory Card Drive  [M1:]
+#define MC1_EN      0
+
+//   <o>Bus Mode <0=>SD-Native <1=>SPI
+//   <i>Define Memory Card bus interface mode.
+//   <i>SD-Native mode needs MCI peripheral.
+//   <i>SPI mode uses SD Card in SPI mode.
+#define MC1_SPI     1
+          
+//   <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                        <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Define System Cache buffer size for file IO. 
+//   <i>Increase this number for faster r/w access.
+//   <i>Default: 4 kB
+#define MC1_CASZ    0
+
+//   <e>Relocate Cache Buffer
+//   <i>Locate Cache Buffer at a specific address.
+//   <i>Some devices like NXP LPC23xx require a Cache buffer
+//   <i>for DMA transfer located at specific address.
+#define MC1_RELOC   0
+
+//   <o>Base address <0x0000-0xFFFFFE00:0x200>
+//   <i>Define the Cache buffer base address.
+//   <i>For LPC23xx/24xx devices this is USB RAM
+//   <i>starting at 0x7FD00000.
+#define MC1_CADR    0x7FD00000
+
+//   </e>
+//   <q>FAT Journal
+//   <i>Enable FAT Journal in order to guarantee
+//   <i>fail-safe FAT file system operation.
+#define MC1_FSJ     0
+
+//   <q>Default Drive [M1:]
+//   <i>Used when Drive letter not specified
+#define MC1_DEF     0
+
+// </e>
+// <e>USB Flash Drive 0
+// ====================
+// <i>Enable USB Flash Drive  [U0:]
+#define USB0_EN     0
+
+//   <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                        <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Define System Cache buffer size for file IO. 
+//   <i>Increase this number for faster r/w access.
+//   <i>Default: 4 kB
+#define USB0_CASZ   8
+
+//   <q>FAT Journal
+//   <i>Enable FAT Journal in order to guarantee
+//   <i>fail-safe FAT file system operation.
+#define USB0_FSJ    0
+
+//   <q>Default Drive [U0:]
+//   <i>Used when Drive letter not specified
+#define USB0_DEF    0
+
+// </e>
+// <e>USB Flash Drive 1
+// ====================
+// <i>Enable USB Flash Drive  [U1:]
+#define USB1_EN     0
+
+//   <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                        <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Define System Cache buffer size for file IO. 
+//   <i>Increase this number for faster r/w access.
+//   <i>Default: 4 kB
+#define USB1_CASZ   8
+
+//   <q>FAT Journal
+//   <i>Enable FAT Journal in order to guarantee
+//   <i>fail-safe FAT file system operation.
+#define USB1_FSJ    0
+
+//   <q>Default Drive [U1:]
+//   <i>Used when Drive letter not specified
+#define USB1_DEF    0
+
+// </e>
+// <e>NAND Flash Drive 0
+// ===================
+// <i>Enable NAND Flash Drive  [N0:]
+#define NAND0_EN    0
+
+//   <o>Page size  <528=> 512 + 16 bytes
+//                 <2112=>2048 + 64 bytes
+//                 <4224=>4096 + 128 bytes
+//                 <8448=>8192 + 256 bytes
+//   <i>Define program Page size in bytes (User + Spare area).
+#define NAND0_PGSZ  2112
+
+//   <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
+//                 <64=>64 pages <128=>128 pages <256=>256 pages
+//   <i>Define number of pages in a block.
+#define NAND0_PGCNT 64
+
+//   <o>Device Size [blocks] <512-32768>
+//   <i>Define number of blocks in NAND Flash device.
+#define NAND0_BLCNT 4096
+
+//   <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
+//                   <8=>8 pages <16=>16 pages <32=>32 pages
+//   <i>Define number of cached Pages.
+//   <i>Default: 4 pages
+#define NAND0_CAPG  2
+
+//   <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
+//                     <8=>8 blocks <16=>16 blocks <32=>32 blocks
+//                     <64=>64 blocks <128=>128 blocks <256=>256 blocks
+//   <i>Define number of indexed Flash Blocks.
+//   <i>Increase this number for better performance.
+//   <i>Default: 16 blocks
+#define NAND0_CABL  16
+
+//   <o>Software ECC <0=>None <1=>Hamming (SLC)
+//   <i>Enable software ECC calculation only,
+//   <i>if not supported by hardware.
+#define NAND0_SWECC 1
+
+//   <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                        <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Define System Cache buffer size for file IO. 
+//   <i>Increase this number for faster r/w access.
+//   <i>Default: 4 kB
+#define NAND0_CASZ  4
+
+//   <e>Relocate Cache Buffers
+//   <i>Use this option to locate Cache buffers 
+//   <i>at specific address in RAM or SDRAM.
+#define NAND0_RELOC 0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Define base address for Cache Buffers.
+#define NAND0_CADR  0x80000000
+
+//   </e>
+//   <q>FAT Journal
+//   <i>Enable FAT Journal in order to guarantee
+//   <i>fail-safe FAT file system operation.
+#define NAND0_FSJ     0
+
+//   <q>Default Drive [N0:]
+//   <i>Used when Drive letter not specified
+#define NAND0_DEF   0
+
+// </e>
+// <e>NAND Flash Drive 1
+// ===================
+// <i>Enable NAND Flash Drive  [N1:]
+#define NAND1_EN    0
+
+//   <o>Page size  <528=> 512 + 16 bytes
+//                 <2112=>2048 + 64 bytes
+//                 <4224=>4096 + 128 bytes
+//                 <8448=>8192 + 256 bytes
+//   <i>Define program Page size in bytes (User + Spare area).
+#define NAND1_PGSZ  2112
+
+//   <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
+//                 <64=>64 pages <128=>128 pages <256=>256 pages
+//   <i>Define number of pages in a block.
+#define NAND1_PGCNT 32
+
+//   <o>Device Size [blocks] <512-32768>
+//   <i>Define number of blocks in NAND Flash device.
+#define NAND1_BLCNT 512
+
+//   <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
+//                   <8=>8 pages <16=>16 pages <32=>32 pages
+//   <i>Define number of cached Pages.
+//   <i>Default: 4 pages
+#define NAND1_CAPG  4
+
+//   <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
+//                     <8=>8 blocks <16=>16 blocks <32=>32 blocks
+//                     <64=>64 blocks <128=>128 blocks <256=>256 blocks
+//   <i>Define number of indexed Flash Blocks.
+//   <i>Increase this number for better performance.
+//   <i>Default: 16 blocks
+#define NAND1_CABL  16
+
+//   <o>Software ECC <0=>None <1=>Hamming (SLC)
+//   <i>Enable software ECC calculation only,
+//   <i>if not supported by hardware.
+#define NAND1_SWECC 0
+
+//   <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                        <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Define System Cache buffer size for file IO.
+//   <i>Increase this number for faster r/w access.
+//   <i>Default: 4 kB
+#define NAND1_CASZ  4
+
+//   <e>Relocate Cache Buffers
+//   <i>Use this option to locate Cache buffers
+//   <i>at specific address in RAM or SDRAM.
+#define NAND1_RELOC 0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Define base address for Cache Buffers.
+#define NAND1_CADR  0x80000000
+
+//   </e>
+//   <q>FAT Journal
+//   <i>Enable FAT Journal in order to guarantee
+//   <i>fail-safe FAT file system operation.
+#define NAND1_FSJ     0
+
+//   <q>Default Drive [N1:]
+//   <i>Used when Drive letter not specified
+#define NAND1_DEF   0
+
+// </e>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+#ifndef  __NO_FILE_LIB_C
+#include <File_lib.c>
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK-ARM/MDK-ARM/config/Net_Config.c

@@ -0,0 +1,892 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - TCPnet
+ *----------------------------------------------------------------------------
+ *      Name:    NET_CONFIG.C
+ *      Purpose: Configuration of RL TCPnet by user.
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *      This code is part of the RealView Run-Time Library.
+ *      Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include <Net_Config.h>
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>System Definitions
+// =====================
+// <i> Global TCPnet System definitions
+//   <s.15>Local Host Name
+//   <i> This is the name under which embedded host can be
+//   <i> accessed on a local area network.
+//   <i> Default: "mcb2300"
+#define LHOST_NAME     "mcb2300"
+
+//   <o>Memory Pool size <1500-64000:4><#/4>
+//   <i> This is the size of a memory pool in bytes. Buffers for
+//   <i> TCPnet packets are allocated from this memory pool.
+//   <i> Default: 8000 bytes
+#define MEM_SIZE       4000
+
+//   <o>Tick Timer interval <10=> 10 ms <20=> 20 ms <25=> 25 ms
+//                          <40=> 40 ms <50=> 50 ms <100=> 100 ms 
+//                          <200=> 200 ms
+//   <i> System Tick Timer interval for software timers
+//   <i> Default: 100 ms
+#define TICK_INTERVAL  10
+
+// </h>
+// <e>Ethernet Network Interface
+// =============================
+// <i> Enable or disable Ethernet Network Interface
+#define ETH_ENABLE     1
+
+//   <h>MAC Address
+//   ==============
+//   <i> Local Ethernet MAC Address
+//   <i> Value FF:FF:FF:FF:FF:FF is not allowed.
+//   <i> It is an ethernet Broadcast MAC address.
+//     <o>Address byte 1 <0x00-0xff:2>
+//     <i> LSB is an ethernet Multicast bit.
+//     <i> Must be 0 for local MAC address.
+//     <i> Default: 0x00
+#define _MAC1          0x30
+
+//     <o>Address byte 2 <0x00-0xff>
+//     <i> Default: 0x30
+#define _MAC2          0x06
+
+//     <o>Address byte 3 <0x00-0xff>
+//     <i> Default: 0x6C
+#define _MAC3          0x6C
+
+//     <o>Address byte 4 <0x00-0xff>
+//     <i> Default: 0x00
+#define _MAC4          0x00
+
+//     <o>Address byte 5 <0x00-0xff>
+//     <i> Default: 0x00
+#define _MAC5          0x00
+
+//     <o>Address byte 6 <0x00-0xff>
+//     <i> Default: 0x01
+#define _MAC6          0x01
+
+//   </h>
+//   <h>IP Address
+//   =============
+//   <i> Local Static IP Address
+//   <i> Value 255.255.255.255 is not allowed.
+//   <i> It is a Broadcast IP address.
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 192
+#define _IP1           192
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 168
+#define _IP2           168
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 0
+#define _IP3           0
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 100
+#define _IP4           100
+
+//   </h>
+//   <h>Subnet mask
+//   ==============
+//   <i> Local Subnet mask
+//     <o>Mask byte 1 <0-255>
+//     <i> Default: 255
+#define _MSK1          255
+
+//     <o>Mask byte 2 <0-255>
+//     <i> Default: 255
+#define _MSK2          255
+
+//     <o>Mask byte 3 <0-255>
+//     <i> Default: 255
+#define _MSK3          255
+
+//     <o>Mask byte 4 <0-255>
+//     <i> Default: 0
+#define _MSK4          0
+
+//   </h>
+//   <h>Default Gateway
+//   ==================
+//   <i> Default Gateway IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 192
+#define _GW1           192
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 168
+#define _GW2           168
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 0
+#define _GW3           0
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 254
+#define _GW4           254
+
+//   </h>
+//   <h>Primary DNS Server
+//   =====================
+//   <i> Primary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define _pDNS1         194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define _pDNS2         25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define _pDNS3         2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 129
+#define _pDNS4         129
+
+//   </h>
+//   <h>Secondary DNS Server
+//   =======================
+//   <i> Secondary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define _sDNS1         194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define _sDNS2         25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define _sDNS3         2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 130
+#define _sDNS4         130
+
+//   </h>
+//   <h>ARP Definitions
+//   ==================
+//   <i> Address Resolution Protocol Definitions
+//     <o>Cache Table size <5-100>
+//     <i> Number of cached hardware/IP addresses
+//     <i> Default: 10
+#define ARP_TABSIZE    10
+
+//     <o>Cache Timeout in seconds <5-255>
+//     <i> A timeout for a cached hardware/IP addresses
+//     <i> Default: 150
+#define ARP_TIMEOUT    150
+
+//     <o>Number of Retries <0-20>
+//     <i> Number of Retries to resolve an IP address
+//     <i> before ARP module gives up
+//     <i> Default: 4
+#define ARP_MAXRETRY   4
+
+//     <o>Resend Timeout in seconds <1-10>
+//     <i> A timeout to resend the ARP Request
+//     <i> Default: 2
+#define ARP_RESEND     10
+
+//     <q>Send Notification on Address changes
+//     <i> When this option is enabled, the embedded host
+//     <i> will send a Gratuitous ARP notification at startup,
+//     <i> or when the device IP address has changed.
+//     <i> Default: Disabled
+#define ARP_NOTIFY     1
+
+//   </h>
+//   <e>IGMP Group Management
+//   ========================
+//   <i> Enable or disable Internet Group Management Protocol
+#define IGMP_ENABLE    0
+
+//     <o>Membership Table size <2-50>
+//     <i> Number of Groups this host can join
+//     <i> Default: 5
+#define IGMP_TABSIZE   5
+
+//   </e>
+//   <q>NetBIOS Name Service
+//   =======================
+//   <i> When this option is enabled, the embedded host can be
+//   <i> accessed by his name on the local LAN using NBNS protocol.
+//   <i> You need to modify also the number of UDP Sockets,
+//   <i> because NBNS protocol uses one UDP socket to run.
+#define NBNS_ENABLE    0
+
+//   <e>Dynamic Host Configuration
+//   =============================
+//   <i> When this option is enabled, local IP address, Net Mask
+//   <i> and Default Gateway are obtained automatically from
+//   <i> the DHCP Server on local LAN.
+//   <i> You need to modify also the number of UDP Sockets,
+//   <i> because DHCP protocol uses one UDP socket to run.
+#define DHCP_ENABLE    1
+
+//     <s.40>Vendor Class Identifier
+//     <i> This value is optional. If specified, it is added
+//     <i> to DHCP request message, identifying vendor type.
+//     <i> Default: ""
+#define DHCP_VCID      ""
+
+//     <q>Bootfile Name
+//     <i> This value is optional. If enabled, the Bootfile Name
+//     <i> (option 67) is also requested from DHCP server.
+//     <i> Default: disabled
+#define DHCP_BOOTF     1
+
+//   </e>
+// </e>
+
+// <e>PPP Network Interface
+// ========================
+// <i> Enable or disable PPP Network Interface
+#define PPP_ENABLE     0
+
+//   <h>IP Address
+//   =============
+//   <i> Local Static IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 192
+#define _IP1P          192
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 168
+#define _IP2P          168
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 125
+#define _IP3P          125
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 1
+#define _IP4P          1
+
+//   </h>
+//   <h>Subnet mask
+//   ==============
+//   <i> Local Subnet mask
+//     <o>Mask byte 1 <0-255>
+//     <i> Default: 255
+#define _MSK1P         255
+
+//     <o>Mask byte 2 <0-255>
+//     <i> Default: 255
+#define _MSK2P         255
+
+//     <o>Mask byte 3 <0-255>
+//     <i> Default: 255
+#define _MSK3P         255
+
+//     <o>Mask byte 4 <0-255>
+//     <i> Default: 0
+#define _MSK4P         0
+
+//   </h>
+//   <h>Primary DNS Server
+//   =====================
+//   <i> Primary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define _pDNS1P        194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define _pDNS2P        25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define _pDNS3P        2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 129
+#define _pDNS4P        129
+
+//   </h>
+//   <h>Secondary DNS Server
+//   =======================
+//   <i> Secondary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define _sDNS1P        194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define _sDNS2P        25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define _sDNS3P        2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 130
+#define _sDNS4P        130
+
+//   </h>
+//   <e>Logon Authentication
+//   =======================
+//   <i> Enable or disable user authentication
+#define PPP_AUTHEN     1
+
+//     <q>Unsecured password (PAP)
+//     <i>Allow or use Password Authentication Protocol.
+#define PPP_PAPEN      1
+
+//     <q>Secured password (CHAP-MD5)
+//     <i>Request or use Challenge Handshake Authentication
+//     <i>Protocol with MD5 digest algorithm.
+#define PPP_CHAPEN     1
+
+//   </e>
+//   <q>Obtain Client IP address automatically
+//   =========================================
+//   <i> This option only applies when PPP Dial-up is used to dial
+//   <i> to remote PPP Server. If checked, network connection
+//   <i> dynamically obtains an IP address from remote PPP Server.
+#define PPP_GETIP      1
+
+//   <q>Use Default Gateway on remote Network
+//   ========================================
+//   <i> This option only applies when both Ethernet and PPP Dial-up
+//   <i> are used. If checked, data that cannot be sent to local LAN
+//   <i> is forwarded to Dial-up network instead.
+#define PPP_DEFGW      1
+
+//   <o>Async Control Character Map <0x0-0xffffffff>
+//   <i> A bit-map of control characters 0-31, which are
+//   <i> transmitted escaped as a 2 byte sequence.
+//   <i> For XON/XOFF set this value to: 0x000A 0000
+//   <i> Default: 0x00000000
+#define PPP_ACCM       0x00000000
+
+//   <o>LCP Echo Interval in seconds <0-3600>
+//   <i> If no frames are received within this interval, PPP sends an
+//   <i> Echo Request and expects an Echo Response from the peer.
+//   <i> If the response is not received, the link is terminated.
+//   <i> A value of 0 disables the LCP Echo test.
+//   <i> Default: 30
+#define PPP_ECHOTOUT   30
+
+//   <o>Number of Retries <0-20>
+//   <i> How many times PPP will try to retransmit data
+//   <i> before giving up. Increase this value for links
+//   <i> with low baud rates or high latency.
+//   <i> Default: 3
+#define PPP_MAXRETRY   3
+
+//   <o>Retry Timeout in seconds <1-10>
+//   <i> If no response received within this time frame,
+//   <i> PPP module will try to resend the data again.
+//   <i> Default: 2
+#define PPP_RETRYTOUT  2
+
+// </e>
+// <e>SLIP Network Interface
+// ========================
+// <i> Enable or disable SLIP Network Interface
+#define SLIP_ENABLE    0
+
+//   <h>IP Address
+//   =============
+//   <i> Local Static IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 192
+#define _IP1S          192
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 168
+#define _IP2S          168
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 225
+#define _IP3S          225
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 1
+#define _IP4S          1
+
+//   </h>
+//   <h>Subnet mask
+//   ==============
+//   <i> Local Subnet mask
+//     <o>Mask byte 1 <0-255>
+//     <i> Default: 255
+#define _MSK1S         255
+
+//     <o>Mask byte 2 <0-255>
+//     <i> Default: 255
+#define _MSK2S         255
+
+//     <o>Mask byte 3 <0-255>
+//     <i> Default: 255
+#define _MSK3S         255
+
+//     <o>Mask byte 4 <0-255>
+//     <i> Default: 0
+#define _MSK4S         0
+
+//   </h>
+//   <h>Primary DNS Server
+//   =====================
+//   <i> Primary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define _pDNS1S        194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define _pDNS2S        25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define _pDNS3S        2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 129
+#define _pDNS4S        129
+
+//   </h>
+//   <h>Secondary DNS Server
+//   =======================
+//   <i> Secondary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define _sDNS1S        194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define _sDNS2S        25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define _sDNS3S        2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 130
+#define _sDNS4S        130
+
+//   </h>
+//   <q>Use Default Gateway on remote Network
+//   ========================================
+//   <i> This option only applies when both Ethernet and SLIP Dial-up
+//   <i> are used. If checked, data that cannot be sent to local LAN
+//   <i> is forwarded to Dial-up network instead.
+#define SLIP_DEFGW     1
+
+// </e>
+// <e>UDP Sockets
+// ==============
+// <i> Enable or disable UDP Sockets
+#define UDP_ENABLE     1
+
+//   <o>Number of UDP Sockets <1-20>
+//   <i> Number of available UDP sockets
+//   <i> Default: 5
+#define UDP_NUMSOCKS   20
+
+// </e>
+// <e>TCP Sockets
+// ==============
+// <i> Enable or disable TCP Sockets
+#define TCP_ENABLE     1
+
+//   <o>Number of TCP Sockets <1-20>
+//   <i> Number of available TCP sockets
+//   <i> Default: 5
+#define TCP_NUMSOCKS   10
+
+//   <o>Number of Retries <0-20>
+//   <i> How many times TCP module will try to retransmit data
+//   <i> before giving up. Increase this value for high-latency
+//   <i> and low_throughput networks.
+//   <i> Default: 5
+#define TCP_MAXRETRY   20
+
+//   <o>Retry Timeout in seconds <1-10>
+//   <i> If data frame not acknowledged within this time frame,
+//   <i> TCP module will try to resend the data again.
+//   <i> Default: 4
+#define TCP_RETRYTOUT  4
+
+//   <o>Default Connect Timeout in seconds <1-600>
+//   <i> Default TCP Socket Keep Alive timeout. When it expires
+//   <i> with no TCP data frame send, TCP Connection is closed.
+//   <i> Default: 120
+#define TCP_DEFTOUT    120
+
+//   <o>Maximum Segment Size <536-1460>
+//   <i> The Maximum Segment Size specifies the maximum
+//   <i> number of bytes in the TCP segment's Data field.
+//   <i> Default: 1460
+#define TCP_MAXSEGSZ   1460
+
+/* TCP fixed timeouts */
+#define TCP_INIT_RETRY_TOUT 1     /* TCP initial Retransmit period in sec.   */
+#define TCP_SYN_RETRY_TOUT  2     /* TCP SYN frame retransmit period in sec. */
+#define TCP_CONRETRY        7     /* Number of retries to establish a conn.  */
+
+// </e>
+// <e>HTTP Server
+// ==============
+// <i> Enable or disable HTTP Server
+#define HTTP_ENABLE    0
+
+//   <o>Number of HTTP Sessions <1-10>
+//   <i> Number of simultaneously active HTTP Sessions.
+//   <i> Default: 3
+#define HTTP_NUMSESS   3
+
+//   <o>Port Number <1-65535>
+//   <i> Listening port number.
+//   <i> Default: 80
+#define HTTP_PORTNUM   80
+
+//   <s.50>Server-Id header
+//   <i> This value is optional. If specified, it overrides 
+//   <i> the default HTTP Server header from the library.
+//   <i> Default: ""
+#define HTTP_SRVID     ""
+
+//   <e>Enable User Authentication
+//     <i> When enabled, the user will have to authenticate
+//     <i> himself by username and password before accessing
+//     <i> any page on this Embedded WEB server.
+#define HTTP_ENAUTH    1
+
+//     <s.20>Authentication Realm
+//     <i> Default: "Embedded WEB Server"
+#define HTTP_AUTHREALM "Embedded WEB Server"
+
+//     <s.15>Authentication Username
+//     <i> Default: "admin"
+#define HTTP_AUTHUSER  "admin"
+
+//     <s.15>Authentication Password
+//     <i> Default: ""
+#define HTTP_AUTHPASSW ""
+
+//   </e>
+// </e>
+// <e>Telnet Server
+// ================
+// <i> Enable or disable Telnet Server
+#define TNET_ENABLE    0
+
+//   <o>Number of Telnet Connections <1-10>
+//   <i> Number of simultaneously active Telnet Connections.
+//   <i> Default: 1
+#define TNET_NUMSESS   1
+
+//   <o>Port Number <1-65535>
+//   <i> Listening port number.
+//   <i> Default: 23
+#define TNET_PORTNUM   23
+
+//   <o>Idle Connection Timeout in seconds <0-3600>
+//   <i> When timeout expires, the connection is closed.
+//   <i> A value of 0 disables disconnection on timeout.
+//   <i> Default: 120
+#define TNET_IDLETOUT  120
+
+//   <q>Disable Echo
+//   <i> When disabled, the server will not echo
+//   <i> characters it receives.
+//   <i> Default: Not disabled
+#define TNET_NOECHO    0
+
+//   <e>Enable User Authentication
+//   <i> When enabled, the user will have to authenticate
+//   <i> himself by username and password before access
+//   <i> to the system is allowed.
+#define TNET_ENAUTH    1
+
+//     <s.15>Authentication Username
+//     <i> Default: "admin"
+#define TNET_AUTHUSER  "admin"
+
+//     <s.15>Authentication Password
+//     <i> Default: ""
+#define TNET_AUTHPASSW ""
+
+//   </e>
+// </e>
+// <e>TFTP Server
+// ==============
+// <i> Enable or disable TFTP Server
+#define TFTP_ENABLE    0
+
+//   <o>Number of TFTP Sessions <1-10>
+//   <i> Number of simultaneously active TFTP Sessions
+//   <i> Default: 1
+#define TFTP_NUMSESS   1
+
+//   <o>Port Number <1-65535>
+//   <i> Listening port number.
+//   <i> Default: 69
+#define TFTP_PORTNUM   69
+
+//   <q>Enable Firewall Support
+//   <i> Use the same Port Number to receive
+//   <i> requests and send answers to clients.
+//   <i> Default: Not Enabled
+#define TFTP_ENFWALL   0
+
+//   <o>Inactive Session Timeout in seconds <5-120>
+//   <i> When timeout expires TFTP Session is closed.
+//   <i> Default: 15
+#define TFTP_DEFTOUT   15
+
+//   <o>Number of Retries <1-10>
+//   <i> How many times TFTP Server will try to
+//   <i> retransmit the data before giving up.
+//   <i> Default: 4
+#define TFTP_MAXRETRY  4
+
+// </e>
+// <e>TFTP Client
+// ==============
+// <i> Enable or disable TFTP Client
+#define TFTPC_ENABLE   0
+
+//   <o>Block Size <128=>128   <256=>256   <512=>512
+//                 <1024=>1024 <1428=>1428
+//   <i> Size of transfer block in bytes.
+//   <i> Default: 512
+#define TFTPC_BLOCKSZ  512
+
+//   <o>Number of Retries <1-10>
+//   <i> How many times TFTP Client will try to
+//   <i> retransmit the data before giving up.
+//   <i> Default: 4
+#define TFTPC_MAXRETRY 4
+
+//   <o>Retry Timeout <2=>200 ms <5=>500 ms <10=>1 sec
+//                    <20=>2 sec <50=>5 sec <100=>10 sec
+//   <i> If data frame not acknowledged within this time frame,
+//   <i> TFTP Client will try to resend the data again.
+//   <i> Default: 500 ms
+#define TFTPC_RETRYTO  5
+
+// </e>
+// <e>FTP Server
+// ==============
+// <i> Enable or disable FTP Server
+#define FTP_ENABLE     0
+
+//   <o>Number of FTP Sessions <1-10>
+//   <i> Number of simultaneously active FTP Sessions
+//   <i> Default: 1
+#define FTP_NUMSESS    1
+
+//   <o>Port Number <1-65535>
+//   <i> Listening port number.
+//   <i> Default: 21
+#define FTP_PORTNUM    21
+
+//   <s.50>Welcome Message
+//   <i> This value is optional. If specified,
+//   <i> it overrides the default welcome message.
+//   <i> Default: ""
+#define FTP_WELMSG     ""
+
+//   <o>Idle Session Timeout in seconds <0-3600>
+//   <i> When timeout expires, the connection is closed.
+//   <i> A value of 0 disables disconnection on timeout.
+//   <i> Default: 120
+#define FTP_IDLETOUT   120
+
+//   <e>Enable User Authentication
+//   <i> When enabled, the user will have to authenticate
+//   <i> himself by username and password before access
+//   <i> to the system is allowed.
+#define FTP_ENAUTH     1
+
+//     <s.15>Authentication Username
+//     <i> Default: "admin"
+#define FTP_AUTHUSER   "admin"
+
+//     <s.15>Authentication Password
+//     <i> Default: ""
+#define FTP_AUTHPASSW  ""
+
+//   </e>
+// </e>
+// <e>FTP Client
+// =============
+// <i> Enable or disable FTP Client
+#define FTPC_ENABLE    0
+
+//     <o>Response Timeout in seconds <1-120>
+//     <i> This is a time for FTP Client to wait for a response from
+//     <i> the Server. If timeout expires, Client aborts operation.
+//     <i> Default: 10
+#define FTPC_DEFTOUT   10
+
+//     <q>Passive mode (PASV)
+//     <i> The client initiates a data connection to the server.
+//     <i> Default: Not passive (Active)
+#define FTPC_PASVMODE  0
+
+// </e>
+// <e>DNS Client
+// =============
+// <i> Enable or disable DNS Client
+#define DNS_ENABLE     1
+
+//     <o>Cache Table size <5-100>
+//     <i> Number of cached DNS host names/IP addresses
+//     <i> Default: 20
+#define DNS_TABSIZE    20
+
+// </e>
+// <e>SMTP Client
+// ==============
+// <i> Enable or disable SMTP Client
+#define SMTP_ENABLE    0
+
+//     <o>Response Timeout in seconds <5-120>
+//     <i> This is a time for SMTP Client to wait for a response from
+//     <i> SMTP Server. If timeout expires, Client aborts operation.
+//     <i> Default: 20
+#define SMTP_DEFTOUT   20
+
+// </e>
+// <e>SNMP Agent
+// =============
+// <i> Enable or disable SNMP Agent
+#define SNMP_ENABLE    0
+
+//   <s.15>Community Name
+//   <i> Defines where an SNMP message is destined for.
+//   <i> Default: "public"
+#define SNMP_COMMUNITY "public"
+
+//   <o>Port Number <1-65535>
+//   <i> Listening port number.
+//   <i> Default: 161
+#define SNMP_PORTNUM   161
+
+//   <o>Trap Port Number <1-65535>
+//   <i> Port number for Trap operations.
+//   <i> Default: 162
+#define SNMP_TRAPPORT  162
+
+//   <h>Trap Server
+//   ==============
+//   <i> Trap Server IP Address
+//   <o>Address byte 1 <0-255>
+//   <i> Default: 192
+#define SNMP_TRAPIP1   192
+
+//   <o>Address byte 2 <0-255>
+//   <i> Default: 168
+#define SNMP_TRAPIP2   168
+
+//   <o>Address byte 3 <0-255>
+//   <i> Default: 0
+#define SNMP_TRAPIP3   0
+
+//   <o>Address byte 4 <0-255>
+//   <i> Default: 100
+#define SNMP_TRAPIP4   100
+
+//   </h>
+// </e>
+// <e>BSD Socket Interface
+// =======================
+// <i> Enable or disable Berkeley Socket Programming Interface
+#define BSD_ENABLE     1
+
+//   <o>Number of BSD Sockets <1-20>
+//   <i> Number of available Berkeley Sockets
+//   <i> Default: 2
+#define BSD_NUMSOCKS   10
+
+//   <o>Number of Streaming Server Sockets <0-20>
+//   <i> Defines a number of Streaming (TCP) Server sockets,
+//   <i> that listen for an incoming connection from the client.
+//   <i> Default: 1
+#define BSD_SRVSOCKS   2
+
+//   <o>Receive Timeout in seconds <0-600>
+//   <i> A timeout for socket receive in blocking mode.
+//   <i> Timeout value of 0 means indefinite timeout.
+//   <i> Default: 20
+#define BSD_RCVTOUT    20
+
+//   <q>Hostname Resolver
+//   <i> Enable or disable Berkeley style hostname resolver.
+#define BSD_GETHOSTEN  1
+
+// </e>
+//------------- <<< end of configuration section >>> -----------------------
+
+/*----------------------------------------------------------------------------
+ *      Fatal Error Handler
+ *---------------------------------------------------------------------------*/
+
+void sys_error (ERROR_CODE code) {
+  /* This function is called when a fatal error is encountered. The normal */
+  /* program execution is not possible anymore. Add your crytical error   .*/
+  /* handler code here.                                                    */
+
+  switch (code) {
+    case ERR_MEM_ALLOC:
+      /* Out of memory. */
+      break;
+
+    case ERR_MEM_FREE:
+      /* Trying to release non existing memory block. */
+      break;
+
+    case ERR_MEM_CORRUPT:
+      /* Memory Link pointer is Corrupted. */
+      /* More data written than the size of allocated mem block. */
+      break;
+
+    case ERR_MEM_LOCK:
+      /* Locked Memory management function (alloc/free) re-entered. */
+      /* RTX multithread protection malfunctioning, not implemented */
+      /* or interrupt disable is not functioning correctly. */
+      break;
+
+    case ERR_UDP_ALLOC:
+      /* Out of UDP Sockets. */
+      break;
+
+    case ERR_TCP_ALLOC:
+      /* Out of TCP Sockets. */
+      break;
+
+    case ERR_TCP_STATE:
+      /* TCP State machine in undefined state. */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+
+/*----------------------------------------------------------------------------
+ *      TCPnet Config Functions
+ *---------------------------------------------------------------------------*/
+
+#define  __NET_CONFIG__
+
+#include <Net_lib.c>
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK-ARM/MDK-ARM/config/Net_Debug.c

@@ -0,0 +1,139 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - TCPnet
+ *----------------------------------------------------------------------------
+ *      Name:    NET_DEBUG.C
+ *      Purpose: Debug Module
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *      This code is part of the RealView Run-Time Library.
+ *      Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include <Net_Config.h>
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+
+// <q>Print Time Stamp
+// ===================
+//   <i> Enable printing the time-info in debug messages
+#define DBG_TIME       1
+
+// <h>TCPnet Debug Definitions
+// ===========================
+//   <o>Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Dynamic Memory debug messages
+#define DBG_MEM        1
+
+//   <o>Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Ethernet debug messages
+#define DBG_ETH        1
+
+//   <o>PPP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off PPP debug messages
+#define DBG_PPP        0
+
+//   <o>SLIP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off SLIP debug messages
+#define DBG_SLIP       0
+
+//   <o>ARP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off ARP debug messages
+#define DBG_ARP        1
+
+//   <o>IP Debug    <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off IP debug messages
+#define DBG_IP         1
+
+//   <o>ICMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off ICMP debug messages
+#define DBG_ICMP       1
+
+//   <o>IGMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off IGMP debug messages
+#define DBG_IGMP       1
+
+//   <o>UDP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off UDP debug messages
+#define DBG_UDP        1
+
+//   <o>TCP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off TCP debug messages
+#define DBG_TCP        2
+
+//   <o>NBNS Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off NetBIOS Name Service debug messages
+#define DBG_NBNS       1
+
+//   <o>DHCP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Dynamic Host Configuration debug messages
+#define DBG_DHCP       2
+
+//   <o>DNS Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Domain Name Service debug messages
+#define DBG_DNS        1
+
+//   <o>SNMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Simple Network Management debug messages
+#define DBG_SNMP       1
+
+//   <o>BSD Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off BSD Interface debug messages
+#define DBG_BSD        2
+
+// </h>
+// <h>Application Debug Definitions
+// ================================
+//   <o>HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Web Server debug messages
+#define DBG_HTTP       1
+
+//   <o>FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off FTP Server debug messages
+#define DBG_FTP        1
+
+//   <o>FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off FTP Client debug messages
+#define DBG_FTPC       1
+
+//   <o>Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Telnet Server debug messages
+#define DBG_TNET       1
+
+//   <o>TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off TFTP Server debug messages
+#define DBG_TFTP       1
+
+//   <o>TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off TFTP Client debug messages
+#define DBG_TFTPC      1
+
+//   <o>SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off SMTP Client debug messages
+#define DBG_SMTP       1
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+
+/*--------------------------- init_debug ------------------------------------*/
+
+void init_debug (void) {
+  /* Add your code to initialize the Debug output. This is usually the  */
+  /* serial interface. The function is called at TCPnet system startup. */
+  /* You may need to customize also the 'putchar()' function.           */
+
+}
+
+
+/*----------------------------------------------------------------------------
+ *      TCPnet Debug Functions
+ *---------------------------------------------------------------------------*/
+
+#define  __NET_DEBUG__
+
+#include <Net_lib.c>
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c

@@ -0,0 +1,205 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_CONFIG.C
+ *      Purpose: Configuration of RTX Kernel for Cortex-M
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *      This code is part of the RealView Run-Time Library.
+ *      Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include <RTL.h>
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Task Configuration
+// =====================
+//
+//   <o>Number of concurrent running tasks <0-250>
+//   <i> Define max. number of tasks that will run at the same time.
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     6
+#endif
+
+//   <o>Number of tasks with user-provided stack <0-250>
+//   <i> Define the number of tasks that will use a bigger stack.
+//   <i> The memory space for the stack is provided by the user.
+//   <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     2
+#endif
+
+//   <o>Task stack size [bytes] <20-4096:8><#/4>
+//   <i> Set the stack size for tasks which is assigned by the system.
+//   <i> Default: 512
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     499
+#endif
+
+// <q>Check for the stack overflow
+// ===============================
+// <i> Include the stack checking code for a stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// <q>Run in privileged mode
+// =========================
+// <i> Run all Tasks in privileged mode.
+// <i> Default: Unprivileged
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// </h>
+// <h>Tick Timer Configuration
+// =============================
+//   <o>Hardware timer <0=> Core SysTick <1=> Peripheral Timer
+//   <i> Define the on-chip timer used as a time-base for RTX.
+//   <i> Default: Core SysTick
+#ifndef OS_TIMER
+ #define OS_TIMER       0
+#endif
+
+//   <o>Timer clock value [Hz] <1-1000000000>
+//   <i> Set the timer clock value for selected timer.
+//   <i> Default: 6000000  (6MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       120000000
+#endif
+
+//   <o>Timer tick value [us] <1-1000000>
+//   <i> Set the timer tick value for selected timer.
+//   <i> Default: 10000  (10ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+// <e>Round-Robin Task switching
+// =============================
+// <i> Enable Round-Robin Task switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Define how long a task will execute before a task switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// </e>
+
+//   <o>Number of user timers <0-250>
+//   <i> Define max. number of user timers that will run at the same time.
+//   <i> Default: 0  (User timers disabled)
+#ifndef OS_TIMERCNT
+ #define OS_TIMERCNT    1
+#endif
+
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the iterrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+__task void os_idle_demon (void) {
+  /* The idle demon is a system task, running when no other task is ready */
+  /* to run. The 'os_xxx' function calls are not allowed from this task.  */
+
+  for (;;) {
+  /* HERE: include optional user code to be executed when no task runs.*/
+  }
+}
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+#if (OS_TIMER != 0)
+int os_tick_init (void) {
+  /* Initialize hardware timer as system tick timer. */
+  /* ... */
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+#endif
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+#if (OS_TIMER != 0)
+void os_tick_irqack (void) {
+  /* Acknowledge timer interrupt. */
+  /* ... */
+}
+#endif
+
+/*--------------------------- os_tmr_call -----------------------------------*/
+
+void os_tmr_call (U16 info) {
+  /* This function is called when the user timer has expired. Parameter   */
+  /* 'info' holds the value, defined when the timer was created.          */
+
+  /* HERE: include optional user code to be executed on timeout. */
+}
+
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (U32 err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include <RTX_lib.c>
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK-ARM/MDK-ARM/config/STM32_SWO.ini

@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2009 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+// <h> Debug MCU Configuration
+//   <o1.0>    DBG_SLEEP     <i> Debug Sleep Mode
+//   <o1.1>    DBG_STOP      <i> Debug Stop Mode
+//   <o1.2>    DBG_STANDBY   <i> Debug Standby Mode
+//   <o1.5>    TRACE_IOEN    <i> Trace I/O Enable 
+//   <o1.6..7> TRACE_MODE    <i> Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//   <o1.8>    DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
+//   <o1.9>    DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
+//   <o1.10>   DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
+//   <o1.11>   DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
+//   <o1.12>   DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
+//   <o1.13>   DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
+//   <o1.14>   DBG_CAN_STOP  <i> CAN Stopped when Core is halted
+// </h>
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup

IDE/MDK-ARM/MDK-ARM/config/startup_stm32f2xx.s

@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00001000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00009000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c

@@ -0,0 +1,299 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include "time.h"
+
+#define PERIPH_BASE           ((uint32_t)0x40000000) 
+/*-----------------------------------------------------------------------------
+ *        initialize RTC 
+ *----------------------------------------------------------------------------*/
+#include "stm32f2xx.h"
+
+#define assert_param(a)
+
+#define RTC_RSF_MASK         ((uint32_t)0xFFFFFF5F)
+#define SYNCHRO_TIMEOUT      ((uint32_t) 0x00008000)
+#define Bcd2ToByte(v) \
+   ((((uint8_t)(v & (uint8_t)0xF0) >> (uint8_t)0x4) * 10) + (v & (uint8_t)0x0F))
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_TR_MNT           ((uint32_t)0x00007000)
+#define RTC_TR_MNU           ((uint32_t)0x00000F00)
+
+#define PWR_OFFSET           (PWR_BASE - PERIPH_BASE)
+#define CR_OFFSET            (PWR_OFFSET + 0x00)
+#define DBP_BitNumber        0x08
+#define CR_DBP_BB     (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+#define RTC_INIT_MASK        ((uint32_t)0xFFFFFFFF)  
+#define INITMODE_TIMEOUT     ((uint32_t) 0x00010000)
+
+static void init_RTC() 
+{
+    __IO uint32_t initcounter =  0x00 ;
+    uint32_t initstatus = 0x00;    /* Enable the PWR clock : RCC_APB1Periph_PWR  */       
+    ((uint32_t *)RCC)[0x10] |= ((uint32_t)0x10000000) ;
+    
+    /* Allow access to RTC */
+    *(__IO uint32_t *) CR_DBP_BB = ENABLE ;
+      /* RCC_LSEConfig(RCC_LSE_ON) */
+    *(__IO uint8_t *) (RCC_BASE + 0x70) =  ((uint8_t)0x00);
+    /* Reset LSEBYP bit */
+    *(__IO uint8_t *) (RCC_BASE + 0x70) =  ((uint8_t)0x00);
+    *(__IO uint8_t *) (RCC_BASE + 0x70) =  ((uint8_t)0x01);
+    /* Wait till LSE is ready */  
+        while((RCC->BDCR << 0x2) == 0x0) { }
+      /* Select the RTC clock source: RCC_RTCCLKSource_LSE */
+    ((RCC_TypeDef *)RCC)->BDCR |= (uint32_t)0x00000100;
+
+    /* Enable the RTC Clock */
+    *(__IO uint32_t *)  (PERIPH_BB_BASE + (((RCC_BASE - PERIPH_BASE)+ 0x70) * 32) + (0x0F* 4)) = (uint32_t)ENABLE;
+
+    *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 
+    RTC->ISR = (uint32_t) RTC_INIT_MASK;
+    do {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));   /* Clear RTC CR FMT Bit */
+    /* Set RTC_CR register */
+    RTC->CR |=   ((uint32_t)0x00000000) ;   /* RTC_HourFormat_24 */
+
+    /* Configure the RTC PRER */
+    RTC->PRER = 0x7f ; 
+    RTC->PRER |= (uint32_t)(0xff << 16);
+
+    /* Exit Initialization mode */
+    RTC->ISR &= (uint32_t)~RTC_ISR_INIT; 
+
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF; 
+}
+
+/*-----------------------------------------------------------------------------
+ *        initialize TIM
+ *----------------------------------------------------------------------------*/
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+
+static void init_TIM()
+{
+      uint16_t tmpcr1 = 0;
+
+    ((uint32_t *)RCC)[0x10] |= RCC_APB1Periph_TIM2 ;
+
+    tmpcr1 = TIM2->CR1 ;
+    tmpcr1 &=   (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) )); 
+                                     /* CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS) */
+    tmpcr1 |= (uint16_t)0x0000  ;    /* CR1 |= TIM_CounterMode_Up */
+    TIM2->CR1=  tmpcr1 ;
+
+    TIM2->ARR = 0xffffffff ;         /* ARR= TIM_Period */
+    TIM2->PSC = 60 ;                 /* PSC = TIM_Prescaler */
+    TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */      
+
+    *(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ; 
+                                     /* TIM_Cmd(TIM2, ENABLE) ; */
+}
+
+void init_time(void) {
+      init_RTC() ;
+    init_TIM() ;
+}
+
+static void GetTime(uint8_t *h, uint8_t *m, uint8_t *s)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+    *h = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16));
+    *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8));
+    *s = (uint8_t)Bcd2ToByte((tmpreg & (RTC_TR_ST | RTC_TR_SU))); 
+}
+
+static uint32_t ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  while (Value >= 10)  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+static void SetTime(uint8_t h, uint8_t m, uint8_t s)
+{
+     __IO uint32_t synchrocounter = 0;
+     uint32_t synchrostatus = 0x00;
+     __IO uint32_t initcounter = 0;
+     uint32_t initstatus = 0x00;
+     uint32_t tmpreg ;  
+
+     tmpreg = ((ByteToBcd2(h) << 16) | (ByteToBcd2(m) << 8) |  ByteToBcd2(s)) ;
+     /* Disable the write protection for RTC registers */
+     RTC->WPR = 0xCA;
+     RTC->WPR = 0x53;
+     RTC->ISR &= (uint32_t)~RTC_ISR_INIT; 
+
+     RTC->ISR = (uint32_t)RTC_INIT_MASK;
+
+     /* Wait till RTC is in INIT state and if Time out is reached exit */
+     do {
+         initstatus = RTC->ISR & RTC_ISR_INITF;
+         initcounter++;  
+     } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+     RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+    
+     RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+     /* Wait the registers to be synchronised */
+     do {
+         synchrostatus = RTC->ISR & RTC_ISR_RSF;
+         synchrocounter++;  
+     } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+     RTC->WPR = 0xFF;
+}
+
+static void GetDate(uint8_t *y, uint8_t *m, uint8_t *d)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = (uint32_t)(RTC->DR & RTC_TR_RESERVED_MASK); 
+    *y = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_YT|RTC_DR_YU)) >>16));
+    *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_MT|RTC_DR_MU)) >> 8));
+    *d = (uint8_t)Bcd2ToByte((uint8_t)(tmpreg & (RTC_DR_DT |RTC_DR_DU)));
+}
+
+static void SetDate(uint8_t y, uint8_t m, uint8_t d)
+{
+     __IO uint32_t synchrocounter = 0;
+     uint32_t synchrostatus = 0x00;
+     __IO uint32_t initcounter = 0;
+     uint32_t initstatus = 0x00;
+     uint32_t tmpreg = 0 ;  
+    
+    tmpreg = ((ByteToBcd2(y) << 16) | (ByteToBcd2(m) << 8) |  ByteToBcd2(d)) ;
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+    RTC->ISR &= (uint32_t)~RTC_ISR_INIT; 
+
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do {
+        initstatus = RTC->ISR & RTC_ISR_INITF;
+        initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+    RTC->DR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+    /* Wait the registers to be synchronised */
+    do {
+        synchrostatus = RTC->ISR & RTC_ISR_RSF;
+        synchrocounter++;  
+    } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+    RTC->WPR = 0xFF;
+}
+
+
+#include <stdio.h>
+void CYASSL_MSG(const char *msg) ;
+
+struct tm *Cyassl_MDK_gmtime(const time_t *c) 
+{ 
+    uint8_t h, m, s ;
+    uint8_t y, mo, d ;
+    static struct tm date ; 
+
+    GetTime(&h, &m, &s) ;
+    GetDate(&y, &mo, &d) ;
+
+    date.tm_year = y + 100 ;
+    date.tm_mon = mo - 1 ;
+    date.tm_mday = d ;
+    date.tm_hour = h ;
+    date.tm_min = m ;
+    date.tm_sec = s ;
+
+    #if defined(DEBUG_CYASSL) 
+    {
+        char msg[100] ;
+        sprintf(msg, 
+        "Debug::Cyassl_KEIL_gmtime(DATE=/%2d/%02d/%04d TIME=%02d:%02d:%02d)\n",
+                d,  mo,  y+2000, h,  m,  s) ; 
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+    
+    return(&date) ;
+}
+
+double current_time() 
+{
+      return ((double)TIM2->CNT/1000000.0) ;
+}
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+
+void time_main(void *args) 
+{
+    char * datetime ;
+    uint8_t h, m, s ;
+    uint8_t y, mo, d ;
+    
+    if( args == NULL || ((func_args *)args)->argc == 1) {
+        GetTime(&h, &m, &s) ;
+        GetDate(&y, &mo, &d) ;
+        printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", 
+             mo, d, y+2000, h, m, s) ;              
+    } else if(((func_args *)args)->argc == 3 && 
+              ((func_args *)args)->argv[1][0] == '-' && 
+              ((func_args *)args)->argv[1][1] == 'd' ) {
+        datetime = ((func_args *)args)->argv[2];
+        sscanf(datetime, "%d/%d/%d", (int *)&mo, (int *)&d, (int *) &y) ;
+        SetDate(y-2000, mo, d) ;        
+    } else if(((func_args *)args)->argc == 3 && 
+              ((func_args *)args)->argv[1][0] == '-' && 
+              ((func_args *)args)->argv[1][1] == 't' ) {
+        datetime = ((func_args *)args)->argv[2];
+        sscanf(datetime, "%d:%d:%d",            
+            (int *)&h, (int *)&m, (int *)&s) ;
+        SetTime(h, m, s) ;
+    } else printf("Invalid argument\n") ; 
+}
+
+
+/*******************************************************************
+      time()                                                                      
+********************************************************************/
+time_t time(time_t * t) { return 0 ; }

IDE/MDK5-ARM/Docs/CyaSSL-Licnese.txt

@@ -0,0 +1,107 @@
+LICENSE AGREEMENT
+
+The wolfSSL source code is subject to the U.S. Export Administration Regulations and other U.S. law, and may not be exported or re-exported to certain countries (currently Afghanistan, Cuba, Iran, Iraq, Libya, North Korea, Sudan and Syria) or to persons or entities prohibited from receiving U.S. exports (including Denied Parties, entities on the Bureau of Export Administration Entity List, and Specially Designated Nationals).
+
+---
+
+GNU GENERAL PUBLIC LICENSE
+Version 2, June 1991
+
+============================================================
+
+Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
+
+=========================================================
+
+Preamble
+
+The licenses for most software are designed to take away your freedom to share and change it.  By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users.  This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it.  (Some other Free Software Foundation software is covered by the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+When we speak of free software, we are referring to freedom, not price.  Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. 
+
+To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it.
+
+For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have.  You must make sure that they, too, receive or can get the source code.  And you must show them these terms so they know their rights.
+
+We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software.
+
+Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software.  If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations.
+
+Finally, any free program is threatened constantly by software patents.  We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary.  To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all.
+
+The precise terms and conditions for copying, distribution and modification follow.
+
+GNU GENERAL PUBLIC LICENSE
+
+TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License.  The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language.  (Hereinafter, translation is included without limitation in the term "modification".)  Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not covered by this License; they are outside its scope.  The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). 
+
+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee.
+
+  2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions:
+
+    a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change.
+
+    b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License.
+
+    c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License.  (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole.  If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works.  But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License.
+
+  3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following:
+
+    a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
+
+    b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
+
+    c) Accompany it with the information you received as to the offer to distribute corresponding source code.  (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for making modifications to it.  For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable.  However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable.
+
+If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License.  Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.
+
+  5. You are not required to accept this License, since you have not signed it.  However, nothing else grants you permission to modify or distribute the Program or its derivative works.  These actions are prohibited by law if you do not accept this License.  Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions.  You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License.
+
+  7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License.  If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all.  For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices.  Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice.
+
+This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded.  In such case, this License incorporates the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time.  Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation.  If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission.  For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this.  Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.
+
+NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+END OF TERMS AND CONDITIONS

IDE/MDK5-ARM/Docs/CyaSSLManual-TableofContents.htm

@@ -0,0 +1 @@
+<meta http-equiv="Refresh" content="0; URL=http://wolfssl.com/yaSSL/Docs-cyassl-manual-toc.html">

IDE/MDK5-ARM/Docs/CyaSSLManual-wolfCryptUsageReference.htm

@@ -0,0 +1 @@
+<meta http-equiv="Refresh" content="0; URL=http://wolfssl.com/yaSSL/Docs-cyassl-manual-10-ctaocrypt-usage-reference.html">

IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.c

@@ -0,0 +1,28 @@
+/* certs_test.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+/* Define initial data for cert buffers */
+#include <cyassl/certs_test.h>
+

IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.h

@@ -0,0 +1,39 @@
+#ifndef CYASSL_CERT_DATA_H
+#define CYASSL_CERT_DATA_H
+
+#ifdef USE_CERT_BUFFERS_1024
+extern const unsigned char client_key_der_1024[]  ;
+extern int sizeof_client_key_der_1024 ;
+/* ./certs/1024/client-cert.der, 1024-bit */
+extern const unsigned char client_cert_der_1024[] ;
+extern int sizeof_client_cert_der_1024 ;
+/* ./certs/1024/dh1024.der, 1024-bit */
+extern const unsigned char dh_key_der_1024[] ; 
+extern int sizeof_dh_key_der_1024 ; 
+/* ./certs/1024/dsa1024.der, 1024-bit */
+extern const unsigned char dsa_key_der_1024[] ;
+extern int sizeof_dsa_key_der_1024 ;
+/* ./certs/1024/rsa1024.der, 1024-bit */
+extern const unsigned char rsa_key_der_1024[] ;
+extern int sizeof_rsa_key_der_1024 ;
+
+#elif defined(USE_CERT_BUFFERS_2048)
+/* ./certs/client-key.der, 2048-bit */
+extern const unsigned char client_key_der_2048[] ;
+extern int sizeof_client_key_der_2048 ;
+/* ./certs/client-cert.der, 2048-bit */
+extern const unsigned char client_cert_der_2048[] ;
+extern int sizeof_client_cert_der_2048 ;
+/* ./certs/dh2048.der, 2048-bit */
+extern const unsigned char dh_key_der_2048[] ;
+extern int sizeof_dh_key_der_2048 ;
+/* ./certs/dsa2048.der, 2048-bit */
+extern const unsigned char dsa_key_der_2048[] ;
+extern int sizeof_dsa_key_der_2048;
+/* ./certs/rsa2048.der, 2048-bit */
+extern const unsigned char rsa_key_der_2048[] ;
+extern int sizeof_rsa_key_der_2048 ;
+#endif
+
+#endif
+

IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c

@@ -0,0 +1,247 @@
+/* cyassl_KEIL_RL.c
+    *
+    * Copyright (C) 2006-2013 wolfSSL Inc.
+    *
+    * This file is part of CyaSSL.
+    *
+    * CyaSSL is free software; you can redistribute it and/or modify
+    * it under the terms of the GNU General Public License as published by
+    * the Free Software Foundation; either version 2 of the License, or
+    * (at your option) any later version.
+    *
+    * CyaSSL is distributed in the hope that it will be useful,
+    * but WITHOUT ANY WARRANTY; without even the implied warranty of
+    * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    * GNU General Public License for more details.
+    *
+    * You should have received a copy of the GNU General Public License
+    * along with this program; if not, write to the Free Software
+    * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+    */
+
+
+/***************************************************************************************/
+/**   This file is for defining functions for specific to KEIL-RL.                **/
+/***************************************************************************************/
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <stdio.h>
+#if defined (CYASSL_MDK5)
+    #include "cmsis_os.h"
+    #if defined(CYASSL_KEIL_TCP_NET)
+        #include "rl_net.h"
+    #endif
+#else
+    #include <rtl.h>
+#endif
+
+#include "cyassl_MDK_ARM.h"
+
+#include <cyassl/ctaocrypt/visibility.h>
+#include <cyassl/ctaocrypt/logging.h>
+
+#if defined (CYASSL_CMSIS_RTOS)
+        #define os_dly_wait(t)    osDelay(10*t)
+#endif
+
+
+/** KEIL-RL TCPnet ****/
+/** TCPnet BSD socket does not have following functions. **/
+
+#if defined(CYASSL_KEIL_TCP_NET)
+char *inet_ntoa(struct in_addr in) 
+{
+    #define NAMESIZE 16
+    static char name[NAMESIZE] ;
+    sprintf(name, "%d.%d.%d.%d", (in.s_addr>>24)&0xff, (in.s_addr>>16)&0xff, (in.s_addr>>8)&0xff, in.s_addr&0xff) ;
+    return name ;
+}
+
+unsigned long inet_addr(const char *cp)
+{
+    unsigned int a[4] ; unsigned long ret ;
+    sscanf(cp, "%d.%d.%d.%d", &a[0], &a[1], &a[2], &a[3]) ;
+    ret = ((a[3]<<24) + (a[2]<<16) + (a[1]<<8) + a[0]) ;
+    return(ret) ;
+}
+
+
+/*** tcp_connect is actually associated with following syassl_tcp_connect. ***/
+int Cyassl_connect(int sd, const  struct sockaddr* sa, int sz) 
+{
+    int ret = 0 ;
+    #if defined(CYASSL_KEIL_TCP_NET)  
+    
+    SOCKADDR_IN addr ;
+
+    addr = *(SOCKADDR_IN *)sa ;
+
+    do {
+        #undef connect  /* Go to KEIL TCPnet connect */
+        ret = connect(sd, (SOCKADDR *)&addr, sizeof(addr)) ;
+        os_dly_wait(50);
+    } while(ret == SCK_EWOULDBLOCK) ;
+    #ifdef DEBUG_CYASSL
+    { 
+        char msg[50] ;
+        sprintf(msg, "BSD Connect return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;
+    }
+    #endif
+    
+    #endif /* CYASSL_KEIL_TCP_NET */
+    return(ret ) ;
+}
+
+
+int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen) 
+{
+    int ret = 0 ;
+
+    #if defined(CYASSL_KEIL_TCP_NET)
+    while(1) {
+        #undef accept  /* Go to KEIL TCPnet accept */
+        ret = accept(sd, addr,  addrlen) ;
+        if(ret != SCK_EWOULDBLOCK) break ;
+        os_dly_wait(1);
+    } 
+    #ifdef DEBUG_CYASSL
+    {
+        char msg[50] ;
+        sprintf(msg, "BSD Accept return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+    
+    #endif /* CYASSL_KEIL_TCP_NET */
+    return(ret ) ;
+
+}
+    
+int Cyassl_recv(int sd, void *buf, size_t len, int flags) 
+{
+    int ret  = 0;
+    #if defined(CYASSL_KEIL_TCP_NET)  
+    while(1) {
+        #undef recv  /* Go to KEIL TCPnet recv */
+        ret = recv(sd, buf, len,  flags) ;
+        if((ret != SCK_EWOULDBLOCK) &&( ret != SCK_ETIMEOUT)) break ;
+        os_dly_wait(1);
+    }
+    #ifdef DEBUG_CYASSL
+    {       
+        char msg[50] ;
+        sprintf(msg, "BSD Recv return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+
+    #endif  /* CYASSL_KEIL_TCP_NET */
+    return(ret ) ;
+}
+
+int Cyassl_send(int sd, const void *buf, size_t len, int flags) 
+{
+    int  ret = 0 ;
+
+    #if defined(CYASSL_KEIL_TCP_NET)  
+    while(1) {
+    #undef send  /* Go to KEIL TCPnet send */
+        ret = send(sd, buf, len,  flags) ;
+        if(ret != SCK_EWOULDBLOCK) break ;
+        os_dly_wait(1);
+    } 
+    #ifdef DEBUG_CYASSL
+    {
+        char msg[50] ;
+        sprintf(msg, "BSD Send return code: %d\n", ret) ;
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+
+#endif  /* CYASSL_KEIL_TCP_NET */
+    return(ret) ;
+
+}
+
+#endif /* CYASSL_KEIL_TCP_NET */
+
+#if defined(CYASSL_KEIL_TCP_NET)  
+void Cyassl_sleep(int t) 
+{
+    #if defined(HAVE_KEIL_RTX)
+    os_dly_wait(t/1000+1) ;
+    #endif
+}
+
+int Cyassl_tcp_select(int sd, int timeout) 
+{
+    
+    return 0 ;
+    
+}
+#endif
+
+extern int strlen(const char *s) ;
+
+FILE * CyaSSL_fopen(const char *name, const char *openmode) 
+{
+    int i ;  FILE * ret ;
+    #define PATHSIZE 100
+    char path[PATHSIZE] ; char *p ;
+    
+    if(strlen(name) > PATHSIZE)return(NULL) ;
+    
+    for(i = 0; i<= strlen(name); i++) {
+        if(name[i] == '/')path[i] = '\\' ;
+        else              path[i] = name[i] ;
+    }       
+    if(path[0] == '.' && path[1] == '\\') p = path + 2 ;
+    else                                  p = path ;
+
+    ret = fopen (p, openmode) ;
+    
+    return(ret) ;
+}
+
+#if defined (CYASSL_MDK5)
+#define getkey getchar
+#define sendchar putchar
+#else
+extern int getkey(void) ;
+extern int sendchar(int c) ;
+#endif
+
+char * Cyassl_fgets ( char * str, int num, FILE * f ) 
+{
+    int i ;
+    
+    for(i = 0 ; i< num ; i++) {
+            while((str[i] = getkey()) == 0) {
+            #if defined (HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+                os_tsk_pass ();
+            #else 
+                osThreadYield ();
+            #endif
+        }
+        if(str[i] == '\n' || str[i] == '\012' || str[i] == '\015')  {
+            sendchar('\n') ;
+            str[i++] = '\n' ; 
+            str[i] = '\0' ; 
+            break ;
+        } else if(str[i] == '\010') { /* BS */
+            if(i) { /* erace one char */
+                sendchar('\010') ; sendchar(' ') ; sendchar('\010') ; 
+                i = (i>0 ? (i-2) : -1 ) ;
+                continue ;
+            } 
+        } else if(str[i] == '\033'  || str[i] == '\004' ) {  /* ESC or ^D */
+            str[i] = '\0' ;
+            return(0) ;
+        }
+        sendchar(str[i]) ;
+    }
+    return(str) ;
+}

IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h

@@ -0,0 +1,106 @@
+/* cyassl_KEIL_RL.h
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/******************************************************************************/
+/**   This file is for defining types, values for specific to KEIL-MDK-ARM.  **/
+/******************************************************************************/
+#ifndef CYASSL_KEIL_RL_H
+#define CYASSL_KEIL_RL_H
+
+
+
+#include <stdio.h>
+
+/* Go to STDIN */
+#define fgets(buff, sz, fd)   Cyassl_fgets(buff, sz, fd) 
+extern char * Cyassl_fgets ( char * str, int num, FILE * f ) ;
+
+#define SOCKET_T int
+
+/*** #include <socket.h> ***/
+#define  NUMBITSPERBYTE 8
+#define FD_SETSIZE 10
+
+typedef long fd_mask;
+#define NFDBITS   (sizeof(fd_mask) * NUMBITSPERBYTE)  /* bits per mask */
+
+typedef struct fd_set {
+    fd_mask fds_bits[(FD_SETSIZE + NFDBITS - 1) / NFDBITS];
+} fd_set;
+
+/*** #include <sys/types.h> ***/
+struct timeval {
+   long tv_sec;     /* seconds      */
+   long tv_usec;    /* microseconds */
+};
+
+
+#if defined(CYASSL_KEIL_TCP_NET) 
+
+
+#if defined(CYASSL_MDK5)
+#define SCK_EWOULDBLOCK     BSD_ERROR_WOULDBLOCK
+#define SCK_ETIMEOUT        BSD_ERROR_TIMEOUT
+#include "rl_net.h" 
+#endif
+ 
+typedef int socklen_t ;
+
+/* for avoiding conflict with KEIL-TCPnet BSD socket */
+/* Bodies are in cyassl_KEIL_RL.c                    */
+#define connect             Cyassl_connect
+#define accept              Cyassl_accept
+#define recv                Cyassl_recv
+#define send                Cyassl_send
+#define sleep               Cyassl_sleep
+
+/* for avoiding conflicting with KEIL-TCPnet TCP socket */
+/* Bodies are in test.h */
+#define tcp_connect Cyassl_tcp_connect    
+#define tcp_socket    Cyassl_tcp_soket
+#define tcp_listen      Cyassl_tcp_listen
+#define tcp_select     Cyassl_tcp_select
+
+extern int Cyassl_connect(int sd, const struct sockaddr * sa, int sz) ;
+extern int Cyassl_accept(int sd, struct sockaddr *addr, socklen_t *addrlen);
+extern int Cyassl_recv(int sd, void *buf, size_t len, int flags);
+extern int Cyassl_send(int sd, const void *buf, size_t len, int flags);
+extern void Cyassl_sleep(int sec) ;
+extern int Cyassl_tcp_select(int sd, int timeout) ;
+
+/** KEIL-RL TCPnet ****/
+/* TCPnet BSD socket does not have following functions. */
+extern char *inet_ntoa(struct in_addr in);
+extern unsigned long inet_addr(const char *cp);
+extern int setsockopt(int sockfd, int level, int optname, 
+                                      const void *optval, socklen_t optlen);
+extern int select(int nfds, fd_set *readfds, fd_set *writefds,
+                          fd_set *exceptfds, const struct timeval *timeout);
+
+#endif /* CYASSL_KEIL_TCP_NET */
+
+
+/* CyaSSL MDK-ARM time functions */
+#include <time.h>
+struct tm *Cyassl_MDK_gmtime(const time_t *c) ;
+extern double current_time(void) ;
+
+#endif /* CYASSL_KEIL_RL_H */

IDE/MDK5-ARM/MDK-ARM/CyaSSL/ssl-dummy.c

@@ -0,0 +1,52 @@
+/* ssl-dummy.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ssl.h>
+#include <cyassl/internal.h>
+
+Signer* GetCA(void* vp, byte* hash) 
+{ 
+    return NULL  ;
+}
+
+int CyaSSL_dtls(CYASSL* ssl)
+{
+    return NULL ;
+}
+
+int CyaSSL_get_using_nonblock(CYASSL* ssl)
+{
+    return NULL ;
+}
+
+Signer* GetCAByName(void* vp, byte* hash)
+{
+    return NULL ;
+}
+
+int CyaSSL_PemCertToDer(const char* fileName, unsigned char* derBuf, int derSz) 
+{
+        return NULL ;
+}

IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt

@@ -0,0 +1,15 @@
+This program is a simple benchmark of wolfCrypt library.
+
+In order to run this benchmark, copy 
+{PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+
+For benchmark configuration, refer config-Crypt.h.
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+Support
+-------
+Please send questions or comments to support@wolfssl.com

IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx

@@ -0,0 +1,917 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>CryptBenchmark</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F207IG</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32F207IG$Device\Include\stm32f2xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32F207IG$SVD\STM32F20x.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Object\</OutputDirectory>
+          <OutputName>CryptBenchmark</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Object\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>8</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\STM32_SWO.ini</InitializationFile>
+            <Driver>BIN\ULP2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4100</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\ULP2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>HAVE_CONFIG_H   MDK_CONF_Benchmark  CYASSL_STM32F2xx</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>benchmark.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\benchmark.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Configuration</GroupName>
+          <Files>
+            <File>
+              <FileName>config-Crypt.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\RTE\wolfSSL\config-Crypt.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>RTX_CM3.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib</FilePath>
+            </File>
+            <File>
+              <FileName>RTX_Conf_CM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>RTE\CMSIS\RTX_Conf_CM.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+          <Files>
+            <File>
+              <FileName>DMA_STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>GPIO_STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>RTE_Device.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>RTE\Device\STM32F207IG\RTE_Device.h</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32f2xx.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>RTE\Device\STM32F207IG\startup_stm32f2xx.s</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32f2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>RTE\Device\STM32F207IG\system_stm32f2xx.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>MCI_STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::File System</GroupName>
+          <Files>
+            <File>
+              <FileName>FS_LFN_CM3_L.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib</FilePath>
+            </File>
+            <File>
+              <FileName>FS_Config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>RTE\File_System\FS_Config.c</FilePath>
+            </File>
+            <File>
+              <FileName>FS_Config_MC_0.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>RTE\File_System\FS_Config_MC_0.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::wolfSSL</GroupName>
+          <Files>
+            <File>
+              <FileName>config-Crypt.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>RTE\wolfSSL\config-Crypt.h</FilePath>
+            </File>
+            <File>
+              <FileName>cyassl_MDK_ARM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c</FilePath>
+            </File>
+            <File>
+              <FileName>ssl-dummy.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c</FilePath>
+            </File>
+            <File>
+              <FileName>time-STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>aes.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\aes.c</FilePath>
+            </File>
+            <File>
+              <FileName>arc4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\arc4.c</FilePath>
+            </File>
+            <File>
+              <FileName>asm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asm.c</FilePath>
+            </File>
+            <File>
+              <FileName>asn.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asn.c</FilePath>
+            </File>
+            <File>
+              <FileName>blake2b.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\blake2b.c</FilePath>
+            </File>
+            <File>
+              <FileName>camellia.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\camellia.c</FilePath>
+            </File>
+            <File>
+              <FileName>coding.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\coding.c</FilePath>
+            </File>
+            <File>
+              <FileName>compress.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\compress.c</FilePath>
+            </File>
+            <File>
+              <FileName>des3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\des3.c</FilePath>
+            </File>
+            <File>
+              <FileName>dh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dh.c</FilePath>
+            </File>
+            <File>
+              <FileName>dsa.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dsa.c</FilePath>
+            </File>
+            <File>
+              <FileName>ecc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc.c</FilePath>
+            </File>
+            <File>
+              <FileName>ecc_fp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc_fp.c</FilePath>
+            </File>
+            <File>
+              <FileName>error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\error.c</FilePath>
+            </File>
+            <File>
+              <FileName>hc128.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hc128.c</FilePath>
+            </File>
+            <File>
+              <FileName>hmac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hmac.c</FilePath>
+            </File>
+            <File>
+              <FileName>integer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\integer.c</FilePath>
+            </File>
+            <File>
+              <FileName>logging.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\logging.c</FilePath>
+            </File>
+            <File>
+              <FileName>md2.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md2.c</FilePath>
+            </File>
+            <File>
+              <FileName>md4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md4.c</FilePath>
+            </File>
+            <File>
+              <FileName>md5.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md5.c</FilePath>
+            </File>
+            <File>
+              <FileName>memory.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\memory.c</FilePath>
+            </File>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>port.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c</FilePath>
+            </File>
+            <File>
+              <FileName>pwdbased.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c</FilePath>
+            </File>
+            <File>
+              <FileName>rabbit.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c</FilePath>
+            </File>
+            <File>
+              <FileName>random.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c</FilePath>
+            </File>
+            <File>
+              <FileName>ripemd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c</FilePath>
+            </File>
+            <File>
+              <FileName>rsa.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c</FilePath>
+            </File>
+            <File>
+              <FileName>sha.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c</FilePath>
+            </File>
+            <File>
+              <FileName>sha256.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c</FilePath>
+            </File>
+            <File>
+              <FileName>sha512.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c</FilePath>
+            </File>
+            <File>
+              <FileName>tfm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis>
+      <api Cclass="CMSIS" Cgroup="RTOS" Cvendor="ARM" exclusive="0">
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.1"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </api>
+      <api Cclass="Drivers" Cgroup="MCI" Cvendor="Keil" exclusive="0">
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.20.0" condition="CMSIS Core">
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.1"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.73.0" condition="CMSIS Core">
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.3"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="5.0.4" condition="CMSIS Core with RTOS">
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="Drive" Csub="Memory Card" Cvendor="Keil" Cversion="5.0.4" condition="File System and MCI Driver" maxInstances="2">
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="DMA" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.3"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="GPIO" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.3"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.3"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Drivers" Cgroup="MCI" Cvendor="Keil" Cversion="1.01.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS RTOS GPIO DMA">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="Device" Csub="Timer" Cvendor="wolfSSL" Cversion="2.8.1" condition="wolfCrypt-Core">
+        <package license="cyassl\IDE\MDK5-ARM\Docs\CyaSSL-Licnese.txt" name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.1"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.8.1" condition="wolfCrypt-Core">
+        <package license="cyassl\IDE\MDK5-ARM\Docs\CyaSSL-Licnese.txt" name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.1"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="Dummy" Cvendor="wolfSSL" Cversion="2.8.1" condition="wolfCrypt-Core">
+        <package license="cyassl\IDE\MDK5-ARM\Docs\CyaSSL-Licnese.txt" name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.1"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="CMSIS_RTX\Templates\RTX_Conf_CM.c">
+        <instance index="0">RTE\CMSIS\RTX_Conf_CM.c</instance>
+        <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.73.0" condition="CMSIS Core"/>
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.3"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h">
+        <instance index="0">RTE\Device\STM32F207IG\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device"/>
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\ARM\startup_stm32f2xx.s">
+        <instance index="0">RTE\Device\STM32F207IG\startup_stm32f2xx.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device"/>
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_stm32f2xx.c">
+        <instance index="0">RTE\Device\STM32F207IG\system_stm32f2xx.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device"/>
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="FileSystem\Config\FS_Config.c">
+        <instance index="0">RTE\File_System\FS_Config.c</instance>
+        <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="5.0.4" condition="CMSIS Core with RTOS"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="FileSystem\Config\FS_Config_MC.h">
+        <instance index="0">RTE\File_System\FS_Config_MC_0.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="Drive" Csub="Memory Card" Cvendor="Keil" Cversion="5.0.4" condition="File System and MCI Driver" maxInstances="2"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config.c">
+        <instance index="0" removed="1">RTE\Network\Net_Config.c</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="CORE" Cvariant="Debug" Cvendor="Keil" Cversion="5.0.2" condition="CMSIS Core with RTOS"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_BSD.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_BSD.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Socket" Csub="BSD" Cvendor="Keil" Cversion="5.0.2" condition="Network UDP/TCP"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_DNS_Client.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_DNS_Client.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Service" Csub="DNS Client" Cvendor="Keil" Cversion="5.0.2" condition="Network UDP"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_ETH.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_ETH_0.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Interface" Csub="ETH" Cvendor="Keil" Cversion="5.0.2" condition="Network Driver ETH" maxInstances="1"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_TCP.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_TCP.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Socket" Csub="TCP" Cvendor="Keil" Cversion="5.0.2" condition="Network Interface"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_UDP.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_UDP.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Socket" Csub="UDP" Cvendor="Keil" Cversion="5.0.2" condition="Network Interface"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Debug.c">
+        <instance index="0" removed="1">RTE\Network\Net_Debug.c</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="CORE" Cvariant="Debug" Cvendor="Keil" Cversion="5.0.2" condition="CMSIS Core with RTOS"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-Crypt.h">
+        <instance index="0" removed="1">RTE\Other\config-Crypt.h</instance>
+        <component Cclass="Other" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.7.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-FS.h">
+        <instance index="0" removed="1">RTE\Other\config-FS.h</instance>
+        <component Cclass="Other" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.7.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-RTX-TCP-FS.h">
+        <instance index="0" removed="1">RTE\Other\config-RTX-TCP-FS.h</instance>
+        <component Cclass="Other" Cgroup="CyaSSL" Csub="RTX,TCP,FS" Cvendor="wolfSSL" Cversion="2.7.0" condition="CyaSSL-RTX,TCP,FS"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config.h">
+        <instance index="0" removed="1">RTE\Other\config.h</instance>
+        <component Cclass="Other" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.7.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-Crypt.h">
+        <instance index="0">RTE\wolfSSL\config-Crypt.h</instance>
+        <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.8.1" condition="wolfCrypt-Core"/>
+        <package license="cyassl\IDE\MDK5-ARM\Docs\CyaSSL-Licnese.txt" name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.1"/>
+        <targetInfos>
+          <targetInfo name="CryptBenchmark"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config.h">
+        <instance index="0" removed="1">RTE\wolfSSL\config.h</instance>
+        <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.8.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.0"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/CMSIS/RTX_Conf_CM.c

@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+//   <o>Number of concurrent running threads <0-250>
+//   <i> Defines max. number of threads that will run at the same time.
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     6
+#endif
+
+//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
+//   <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     50
+#endif
+
+//   <o>Main Thread stack size [bytes] <64-10000:8><#/4>
+//   <i> Defines stack size for main thread.
+//   <i> Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 1500
+#endif
+
+//   <o>Number of threads with user-provided stack size <0-250>
+//   <i> Defines the number of threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     0
+#endif
+
+//   <o>Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4>
+//   <i> Defines the combined stack size for threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 0
+#endif
+
+// <q>Check for stack overflow
+// <i> Includes the stack checking code for stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// <o>Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// </h>
+
+// <h>RTX Kernel Timer Tick Configuration
+// ======================================
+// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
+// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   <o>Timer clock value [Hz] <1-1000000000>
+//   <i> Defines the timer clock value.
+//   <i> Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   <o>Timer tick value [us] <1-1000000>
+//   <i> Defines the timer tick value.
+//   <i> Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Defines how long a thread will execute before a thread switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// </e>
+
+// <e>User Timers
+// ==============
+//   <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   <o>Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//   <i> Defines priority for Timer Thread
+//   <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines stack size for Timer thread.
+//   <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   <o>Timer Callback Queue size <1-32>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// </e>
+
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the interrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/startup_stm32f2xx.s

@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00002000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00009000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/system_stm32f2xx.c

@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config.c

@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>File System
+// <i>Define File System global parameters
+
+//   <o>Number of open files <4-16>
+//   <i>Define number of files that can be
+//   <i>opened at the same time.
+//   <i>Default: 8
+#define NUM_FILES               8
+
+//   <o>FAT Name Cache Size <0-1000000>
+//   <i>Define number of cached FAT file or directory names.
+//   <i>48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   <e>Relocate FAT Name Cache Buffer
+//   <i>Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   </e>
+
+// </h>
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"

IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config_MC_0.h

@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Memory Card Drive 0
+// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   <o>Connect to hardware via Driver_MCI# <0-255>
+//   <i>Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   <o>Connect to hardware via Driver_SPI# <0-255>
+//   <i>Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   <o>Memory Card Interface Mode <0=>Native <1=>SPI
+//   <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   <i>since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Drive Cache stores data sectors and may be increased to speed-up
+//   <i>file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   <e>Locate Drive Cache and Drive Buffer
+//   <i>Some microcontrollers support DMA only in specific memory areas and
+//   <i>require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   </e>
+
+//   <q>Use FAT Journal
+//   <i>Protect File Allocation Table and Directory Entries for
+//   <i>fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   <q>Default Drive "M0:"
+//   <i>Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// </h>

IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/RTE_Components.h

@@ -0,0 +1,19 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CryptBenchmark' 
+ * Target:  'CryptBenchmark' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_STM32F2xx    /* Device Startup for STM32F2 */
+#define RTE_Drivers_MCI0                /* Driver MCI0 */
+#define RTE_FileSystem_Core             /* File System Core */
+          #define RTE_FileSystem_LFN              /* File System with Long Filename support */
+#define RTE_FileSystem_Drive_MC_0       /* File System Memory Card Drive 0 */
+
+#endif /* RTE_COMPONENTS_H */

IDE/MDK5-ARM/Projects/CryptBenchmark/STM32_SWO.ini

@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2004-2013 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+// <h> Debug MCU Configuration
+//   <o1.0>    DBG_SLEEP     <i> Debug Sleep Mode
+//   <o1.1>    DBG_STOP      <i> Debug Stop Mode
+//   <o1.2>    DBG_STANDBY   <i> Debug Standby Mode
+//   <o1.5>    TRACE_IOEN    <i> Trace I/O Enable 
+//   <o1.6..7> TRACE_MODE    <i> Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//   <o1.8>    DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
+//   <o1.9>    DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
+//   <o1.10>   DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
+//   <o1.11>   DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
+//   <o1.12>   DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
+//   <o1.13>   DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
+//   <o1.14>   DBG_CAN_STOP  <i> CAN Stopped when Core is halted
+// </h>
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup

IDE/MDK5-ARM/Projects/CryptBenchmark/main.c

@@ -0,0 +1,71 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ctaocrypt/visibility.h>
+#include <cyassl/ctaocrypt/logging.h>
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+ 
+#include <stdio.h>
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+  int32_t retv;
+
+  retv = finit ("M0:");
+  if (retv == 0) {
+    retv = fmount ("M0:");
+    if (retv == 0) {
+      printf ("Drive M0 ready!\n");
+    }
+    else {
+      printf ("Drive M0 mount failed!\n");
+    }
+  }
+  else {
+    printf ("Drive M0 initialization failed!\n");
+  }
+}
+extern void benchmark_test(void * arg) ;
+extern void init_time(void) ;
+
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+
+int main() 
+{
+    void * arg = NULL ;
+
+    init_time() ;
+    init_filesystem ();
+    printf("=== Start: Crypt Benchmark ===\n") ;
+        benchmark_test(arg) ;
+    printf("=== End: Crypt Benchmark  ===\n") ;   
+    
+}

IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt

@@ -0,0 +1,16 @@
+This program is a simple test suite of wolfCrypt library.
+
+In order to run this test suite, copy 
+{PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+
+For test configuration, refer config-Crypt.h.
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+
+ Support
+-------
+Please send questions or comments to support@wolfssl.com

IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx

@@ -0,0 +1,919 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>CryptTest</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F207IG</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32F207IG$Device\Include\stm32f2xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32F207IG$SVD\STM32F20x.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Object\</OutputDirectory>
+          <OutputName>CryptTest</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Object\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>8</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\STM32_SWO.ini</InitializationFile>
+            <Driver>BIN\ULP2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4100</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\ULP2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>HAVE_CONFIG_H   MDK_CONF_CryptTest CYASSL_STM32F2xx __DBG_ITM</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>test.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\test.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Configuration</GroupName>
+          <Files>
+            <File>
+              <FileName>config-Crypt.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\RTE\wolfSSL\config-Crypt.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>RTX_CM3.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib</FilePath>
+            </File>
+            <File>
+              <FileName>RTX_Conf_CM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>RTE\CMSIS\RTX_Conf_CM.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+          <Files>
+            <File>
+              <FileName>DMA_STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>GPIO_STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>RTE_Device.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>RTE\Device\STM32F207IG\RTE_Device.h</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32f2xx.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>RTE\Device\STM32F207IG\startup_stm32f2xx.s</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32f2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>RTE\Device\STM32F207IG\system_stm32f2xx.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>MCI_STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::File System</GroupName>
+          <Files>
+            <File>
+              <FileName>FS_LFN_CM3_L.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib</FilePath>
+            </File>
+            <File>
+              <FileName>FS_Config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>RTE\File_System\FS_Config.c</FilePath>
+            </File>
+            <File>
+              <FileName>FS_Config_MC_0.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>RTE\File_System\FS_Config_MC_0.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::wolfSSL</GroupName>
+          <Files>
+            <File>
+              <FileName>cyassl_MDK_ARM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c</FilePath>
+            </File>
+            <File>
+              <FileName>ssl-dummy.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c</FilePath>
+            </File>
+            <File>
+              <FileName>time-STM32F2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>aes.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c</FilePath>
+            </File>
+            <File>
+              <FileName>arc4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c</FilePath>
+            </File>
+            <File>
+              <FileName>asm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c</FilePath>
+            </File>
+            <File>
+              <FileName>asn.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c</FilePath>
+            </File>
+            <File>
+              <FileName>blake2b.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c</FilePath>
+            </File>
+            <File>
+              <FileName>camellia.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c</FilePath>
+            </File>
+            <File>
+              <FileName>coding.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c</FilePath>
+            </File>
+            <File>
+              <FileName>compress.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c</FilePath>
+            </File>
+            <File>
+              <FileName>des3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c</FilePath>
+            </File>
+            <File>
+              <FileName>dh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c</FilePath>
+            </File>
+            <File>
+              <FileName>dsa.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c</FilePath>
+            </File>
+            <File>
+              <FileName>ecc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c</FilePath>
+            </File>
+            <File>
+              <FileName>ecc_fp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c</FilePath>
+            </File>
+            <File>
+              <FileName>error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c</FilePath>
+            </File>
+            <File>
+              <FileName>hc128.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c</FilePath>
+            </File>
+            <File>
+              <FileName>hmac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c</FilePath>
+            </File>
+            <File>
+              <FileName>integer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c</FilePath>
+            </File>
+            <File>
+              <FileName>logging.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c</FilePath>
+            </File>
+            <File>
+              <FileName>md2.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c</FilePath>
+            </File>
+            <File>
+              <FileName>md4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c</FilePath>
+            </File>
+            <File>
+              <FileName>md5.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c</FilePath>
+            </File>
+            <File>
+              <FileName>memory.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c</FilePath>
+            </File>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>pwdbased.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c</FilePath>
+            </File>
+            <File>
+              <FileName>rabbit.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c</FilePath>
+            </File>
+            <File>
+              <FileName>random.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c</FilePath>
+            </File>
+            <File>
+              <FileName>ripemd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c</FilePath>
+            </File>
+            <File>
+              <FileName>rsa.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c</FilePath>
+            </File>
+            <File>
+              <FileName>sha.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c</FilePath>
+            </File>
+            <File>
+              <FileName>sha256.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c</FilePath>
+            </File>
+            <File>
+              <FileName>sha512.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c</FilePath>
+            </File>
+            <File>
+              <FileName>tfm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c</FilePath>
+            </File>
+            <File>
+              <FileName>config-Crypt.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>RTE\wolfSSL\config-Crypt.h</FilePath>
+            </File>
+            <File>
+              <FileName>config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>RTE\wolfSSL\config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis>
+      <api Cclass="CMSIS" Cgroup="RTOS" exclusive="0">
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.1"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </api>
+      <api Cclass="Drivers" Cgroup="MCI" exclusive="0">
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.20.0" condition="CMSIS Core">
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.1"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.73.0" condition="CMSIS Core">
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.3"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="5.0.4" condition="CMSIS Core with RTOS">
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="Drive" Csub="Memory Card" Cvendor="Keil" Cversion="5.0.4" condition="File System and MCI Driver" maxInstances="2">
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="DMA" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.3"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="GPIO" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.3"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.3"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Drivers" Cgroup="MCI" Cvendor="Keil" Cversion="1.01.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS RTOS GPIO DMA">
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="Device" Csub="Timer" Cvendor="wolfSSL" Cversion="2.8.0" condition="wolfCrypt-Core">
+        <package name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.0"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.8.0" condition="wolfCrypt-Core">
+        <package name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.0"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="Dummy" Cvendor="wolfSSL" Cversion="2.8.0" condition="wolfCrypt-Core">
+        <package name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.0"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="CMSIS_RTX\Templates\RTX_Conf_CM.c">
+        <instance index="0">RTE\CMSIS\RTX_Conf_CM.c</instance>
+        <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.73.0" condition="CMSIS Core"/>
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.3"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h">
+        <instance index="0">RTE\Device\STM32F207IG\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device"/>
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\ARM\startup_stm32f2xx.s">
+        <instance index="0">RTE\Device\STM32F207IG\startup_stm32f2xx.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device"/>
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_stm32f2xx.c">
+        <instance index="0">RTE\Device\STM32F207IG\system_stm32f2xx.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="STM32F207IG" condition="STM32F2xx CMSIS Device"/>
+        <package name="STM32F2xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="1.0.4"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="FileSystem\Config\FS_Config.c">
+        <instance index="0">RTE\File_System\FS_Config.c</instance>
+        <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="5.0.4" condition="CMSIS Core with RTOS"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="FileSystem\Config\FS_Config_MC.h">
+        <instance index="0">RTE\File_System\FS_Config_MC_0.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="File System" Cgroup="Drive" Csub="Memory Card" Cvendor="Keil" Cversion="5.0.4" condition="File System and MCI Driver" maxInstances="2"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.2"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config.c">
+        <instance index="0" removed="1">RTE\Network\Net_Config.c</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="CORE" Cvariant="Debug" Cvendor="Keil" Cversion="5.0.2" condition="CMSIS Core with RTOS"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_BSD.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_BSD.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Socket" Csub="BSD" Cvendor="Keil" Cversion="5.0.2" condition="Network UDP/TCP"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_DNS_Client.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_DNS_Client.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Service" Csub="DNS Client" Cvendor="Keil" Cversion="5.0.2" condition="Network UDP"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_ETH.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_ETH_0.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Interface" Csub="ETH" Cvendor="Keil" Cversion="5.0.2" condition="Network Driver ETH" maxInstances="1"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_TCP.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_TCP.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Socket" Csub="TCP" Cvendor="Keil" Cversion="5.0.2" condition="Network Interface"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Config_UDP.h">
+        <instance index="0" removed="1">RTE\Network\Net_Config_UDP.h</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="Socket" Csub="UDP" Cvendor="Keil" Cversion="5.0.2" condition="Network Interface"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Network\Config\Net_Debug.c">
+        <instance index="0" removed="1">RTE\Network\Net_Debug.c</instance>
+        <component Cbundle="MDK-Pro" Cclass="Network" Cgroup="CORE" Cvariant="Debug" Cvendor="Keil" Cversion="5.0.2" condition="CMSIS Core with RTOS"/>
+        <package name="MDK-Middleware" url="http://www.keil.com/pack/" vendor="Keil" version="5.1.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-Crypt.h">
+        <instance index="0" removed="1">RTE\Other\config-Crypt.h</instance>
+        <component Cclass="Other" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.7.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-FS.h">
+        <instance index="0" removed="1">RTE\Other\config-FS.h</instance>
+        <component Cclass="Other" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.7.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-RTX-TCP-FS.h">
+        <instance index="0" removed="1">RTE\Other\config-RTX-TCP-FS.h</instance>
+        <component Cclass="Other" Cgroup="CyaSSL" Csub="RTX,TCP,FS" Cvendor="wolfSSL" Cversion="2.7.0" condition="CyaSSL-RTX,TCP,FS"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config.h">
+        <instance index="0" removed="1">RTE\Other\config.h</instance>
+        <component Cclass="Other" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.7.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/keil/pack/" vendor="wolfSSL" version="2.7.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config-Crypt.h">
+        <instance index="0">RTE\wolfSSL\config-Crypt.h</instance>
+        <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.8.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.0"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\config.h">
+        <instance index="0">RTE\wolfSSL\config.h</instance>
+        <component Cbundle="wolfSSL" Cclass="wolfSSL" Cgroup="wolfCrypt" Csub="CORE" Cvendor="wolfSSL" Cversion="2.8.0" condition="wolfCrypt-Core"/>
+        <package name="CyaSSL" url="http://www.wolfSSL.com/files/ide" vendor="wolfSSL" version="2.8.0"/>
+        <targetInfos>
+          <targetInfo name="CryptTest"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

IDE/MDK5-ARM/Projects/CryptTest/RTE/CMSIS/RTX_Conf_CM.c

@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+//   <o>Number of concurrent running threads <0-250>
+//   <i> Defines max. number of threads that will run at the same time.
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     6
+#endif
+
+//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
+//   <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     50
+#endif
+
+//   <o>Main Thread stack size [bytes] <64-10000:8><#/4>
+//   <i> Defines stack size for main thread.
+//   <i> Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 2000
+#endif
+
+//   <o>Number of threads with user-provided stack size <0-250>
+//   <i> Defines the number of threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     0
+#endif
+
+//   <o>Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4>
+//   <i> Defines the combined stack size for threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 0
+#endif
+
+// <q>Check for stack overflow
+// <i> Includes the stack checking code for stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// <o>Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// </h>
+
+// <h>RTX Kernel Timer Tick Configuration
+// ======================================
+// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
+// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   <o>Timer clock value [Hz] <1-1000000000>
+//   <i> Defines the timer clock value.
+//   <i> Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   <o>Timer tick value [us] <1-1000000>
+//   <i> Defines the timer tick value.
+//   <i> Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Defines how long a thread will execute before a thread switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// </e>
+
+// <e>User Timers
+// ==============
+//   <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   <o>Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//   <i> Defines priority for Timer Thread
+//   <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines stack size for Timer thread.
+//   <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   <o>Timer Callback Queue size <1-32>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// </e>
+
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the interrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/startup_stm32f2xx.s

@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00001000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00009000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/system_stm32f2xx.c

@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config.c

@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>File System
+// <i>Define File System global parameters
+
+//   <o>Number of open files <4-16>
+//   <i>Define number of files that can be
+//   <i>opened at the same time.
+//   <i>Default: 8
+#define NUM_FILES               8
+
+//   <o>FAT Name Cache Size <0-1000000>
+//   <i>Define number of cached FAT file or directory names.
+//   <i>48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   <e>Relocate FAT Name Cache Buffer
+//   <i>Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   </e>
+
+// </h>
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"

IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config_MC_0.h

@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Memory Card Drive 0
+// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   <o>Connect to hardware via Driver_MCI# <0-255>
+//   <i>Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   <o>Connect to hardware via Driver_SPI# <0-255>
+//   <i>Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   <o>Memory Card Interface Mode <0=>Native <1=>SPI
+//   <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   <i>since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Drive Cache stores data sectors and may be increased to speed-up
+//   <i>file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   <e>Locate Drive Cache and Drive Buffer
+//   <i>Some microcontrollers support DMA only in specific memory areas and
+//   <i>require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   </e>
+
+//   <q>Use FAT Journal
+//   <i>Protect File Allocation Table and Directory Entries for
+//   <i>fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   <q>Default Drive "M0:"
+//   <i>Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// </h>

IDE/MDK5-ARM/Projects/CryptTest/RTE/RTE_Components.h

@@ -0,0 +1,19 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CryptTest' 
+ * Target:  'CryptTest' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_STM32F2xx    /* Device Startup for STM32F2 */
+#define RTE_Drivers_MCI0                /* Driver MCI0 */
+#define RTE_FileSystem_Core             /* File System Core */
+          #define RTE_FileSystem_LFN              /* File System with Long Filename support */
+#define RTE_FileSystem_Drive_MC_0       /* File System Memory Card Drive 0 */
+
+#endif /* RTE_COMPONENTS_H */

IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini

@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2004-2013 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+// <h> Debug MCU Configuration
+//   <o1.0>    DBG_SLEEP     <i> Debug Sleep Mode
+//   <o1.1>    DBG_STOP      <i> Debug Stop Mode
+//   <o1.2>    DBG_STANDBY   <i> Debug Standby Mode
+//   <o1.5>    TRACE_IOEN    <i> Trace I/O Enable 
+//   <o1.6..7> TRACE_MODE    <i> Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//   <o1.8>    DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
+//   <o1.9>    DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
+//   <o1.10>   DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
+//   <o1.11>   DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
+//   <o1.12>   DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
+//   <o1.13>   DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
+//   <o1.14>   DBG_CAN_STOP  <i> CAN Stopped when Core is halted
+// </h>
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup

IDE/MDK5-ARM/Projects/CryptTest/main.c

@@ -0,0 +1,71 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ctaocrypt/visibility.h>
+#include <cyassl/ctaocrypt/logging.h>
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+ 
+#include <stdio.h>
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+  int32_t retv;
+
+  retv = finit ("M0:");
+  if (retv == 0) {
+    retv = fmount ("M0:");
+    if (retv == 0) {
+      printf ("Drive M0 ready!\n");
+    }
+    else {
+      printf ("Drive M0 mount failed!\n");
+    }
+  }
+  else {
+    printf ("Drive M0 initialization failed!\n");
+  }
+}
+extern void ctaocrypt_test(void * arg) ;
+extern void init_time(void) ;
+
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+
+int main() 
+{
+    void * arg = NULL ;
+
+    init_time() ;
+    init_filesystem ();
+    printf("=== Start: Crypt test ===\n") ;
+        ctaocrypt_test(arg) ;
+    printf("=== End: Crypt test  ===\n") ;    
+    
+}

IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt

@@ -0,0 +1,89 @@
+This program gives  wolfCrypt and CyaSSL library demo.
+
+In order to run the demo,
+Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+For demo configuration, refer config-Crypt.h and config-CyaSSL.h.
+
+After download and start the execution, you can type in commands through the
+Debug(printf) viewer. 
+
+time [-d date][-t time]      Set/Get RTC: The time is used for certificate validation.
+test                                wolfCrypt Simple test suite
+benchmark                      wolfCrypt Simple benchmark
+server&                          simple server in background mode
+client                             simple client
+echoserver&                   echo server in background mode
+echoclient                      echo client
+server/client -h              help for server/client command
+
+
+=== Typical Command Usage Scenario ===
+
+Starting Shell
+>time -d 9/23/2013
+>time
+Date: 9/23/2013, Time: 00:38:31
+>test
+MD5      test passed!
+MD4      test passed!
+SHA      test passed!
+...
+
+>benchmark
+AES      25 kB took 0.025 seconds,   0.96 MB/s
+ARC4     25 kB took 0.006 seconds,   3.83 MB/s
+...
+
+DH  2048 key agreement   685.93 milliseconds, avg over 1 iterations
+
+>echoserver&
+"echoserver" is running with the background mode.
+
+>echoclient
+ABCDEFG
+ABCDEFG
+WXYZ
+WXYZ
+quit
+sending server shutdown command: quit!
+client sent quit command: shutting down!
+
+>server&
+"server" is running with the background mode.
+
+>client
+peer's cert info:
+ issuer : /C=...
+ subject: /C=...
+ serial number:02 
+SSL version is TLSv1.2
+SSL cipher suite is TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+peer's cert info:
+ issuer : /C=...
+ subject: /C=...
+ serial number:... 
+SSL version is TLSv1.2
+SSL cipher suite is TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+Client message: hello cyassl!
+Server response: I hear you fa shizzle!
+
+>client -h 192.168.2.100 -p 443 -g -v 0
+peer's cert info:
+ issuer : /CN=...
+ subject: /CN=...
+ serial number:44:39:... 
+SSL version is SSLv3
+SSL cipher suite is SSL_RSA_WITH_RC4_128_SHA
+SSL connect ok, sending GET...
+...
+===
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+
+Support
+-------
+Please send questions or comments to support@wolfssl.com

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c

@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+//   <o>Number of concurrent running threads <0-250>
+//   <i> Defines max. number of threads that will run at the same time.
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     6
+#endif
+
+//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
+//   <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     250
+#endif
+
+//   <o>Main Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines stack size for main thread.
+//   <i> Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 250
+#endif
+
+//   <o>Number of threads with user-provided stack size <0-250>
+//   <i> Defines the number of threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     2
+#endif
+
+//   <o>Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4>
+//   <i> Defines the combined stack size for threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 4500
+#endif
+
+// <q>Check for stack overflow
+// <i> Includes the stack checking code for stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// <o>Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// </h>
+
+// <h>RTX Kernel Timer Tick Configuration
+// ======================================
+// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
+// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   <o>Timer clock value [Hz] <1-1000000000>
+//   <i> Defines the timer clock value.
+//   <i> Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   <o>Timer tick value [us] <1-1000000>
+//   <i> Defines the timer tick value.
+//   <i> Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Defines how long a thread will execute before a thread switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// </e>
+
+// <e>User Timers
+// ==============
+//   <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   <o>Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//   <i> Defines priority for Timer Thread
+//   <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   <o>Timer Thread stack size [bytes] <64-64000:8><#/4>
+//   <i> Defines stack size for Timer thread.
+//   <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   <o>Timer Callback Queue size <1-32>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// </e>
+
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the interrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/startup_stm32f2xx.s

@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00001000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x0000F000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/system_stm32f2xx.c

@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config.c

@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>File System
+// <i>Define File System global parameters
+
+//   <o>Number of open files <4-16>
+//   <i>Define number of files that can be
+//   <i>opened at the same time.
+//   <i>Default: 8
+#define NUM_FILES               8
+
+//   <o>FAT Name Cache Size <0-1000000>
+//   <i>Define number of cached FAT file or directory names.
+//   <i>48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   <e>Relocate FAT Name Cache Buffer
+//   <i>Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   </e>
+
+// </h>
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config_MC_0.h

@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Memory Card Drive 0
+// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   <o>Connect to hardware via Driver_MCI# <0-255>
+//   <i>Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   <o>Connect to hardware via Driver_SPI# <0-255>
+//   <i>Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   <o>Memory Card Interface Mode <0=>Native <1=>SPI
+//   <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   <i>since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Drive Cache stores data sectors and may be increased to speed-up
+//   <i>file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   <e>Locate Drive Cache and Drive Buffer
+//   <i>Some microcontrollers support DMA only in specific memory areas and
+//   <i>require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   </e>
+
+//   <q>Use FAT Journal
+//   <i>Protect File Allocation Table and Directory Entries for
+//   <i>fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   <q>Default Drive "M0:"
+//   <i>Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// </h>

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config.c

@@ -0,0 +1,153 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>System Definitions
+// <i> Global Network System definitions
+//   <s.15>Local Host Name
+//   <i> This is the name under which embedded host can be
+//   <i> accessed on a local area network.
+//   <i> Default: "my_host"
+#define NET_HOST_NAME           "my_host"
+
+//   <o>Memory Pool size <1536-262144:4><#/4>
+//   <i> This is the size of a memory pool in bytes. Buffers for
+//   <i> Network packets are allocated from this memory pool.
+//   <i> Default: 12000 bytes
+#define NET_MEM_SIZE            3000
+
+// </h>
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef  RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_PPP_0
+#include "Net_Config_PPP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_PPP_1
+#include "Net_Config_PPP_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_SLIP_0
+#include "Net_Config_SLIP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_SLIP_1
+#include "Net_Config_SLIP_1.h"
+#endif
+
+#ifdef  RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef  RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef  RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef  RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef  RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef  RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef  RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef  RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef  RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef  RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef  RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+  \fn          void net_sys_error (ERROR_CODE error)
+  \ingroup     net_cores
+  \brief       Network system error handler.
+*/
+void net_sys_error (ERROR_CODE error) {
+  /* This function is called when a fatal error is encountered. */
+  /* The normal program execution is not possible anymore.      */
+
+  switch (error) {
+    case ERR_MEM_ALLOC:
+      /* Out of memory */
+      break;
+
+    case ERR_MEM_FREE:
+      /* Trying to release non existing memory block */
+      break;
+
+    case ERR_MEM_CORRUPT:
+      /* Memory Link pointer Corrupted */
+      /* More data written than the size of allocated mem block */
+      break;
+
+    case ERR_MEM_LOCK:
+      /* Locked Memory management function (alloc/free) re-entered */
+      break;
+
+    case ERR_UDP_ALLOC:
+      /* Out of UDP Sockets */
+      break;
+
+    case ERR_TCP_ALLOC:
+      /* Out of TCP Sockets */
+      break;
+
+    case ERR_TCP_STATE:
+      /* TCP State machine in undefined state */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+/**
+@}
+*/

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_BSD.h

@@ -0,0 +1,36 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_BSD.h
+ * Purpose: Network Configuration BSD Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Berkley (BSD) Sockets
+#define BSD_ENABLE              1
+
+//   <o>Number of BSD Sockets <1-20>
+//   <i> Number of available Berkeley Sockets
+//   <i> Default: 2
+#define BSD_NUM_SOCKS           10
+
+//   <o>Number of Streaming Server Sockets <0-20>
+//   <i> Defines a number of Streaming (TCP) Server sockets,
+//   <i> that listen for an incoming connection from the client.
+//   <i> Default: 1
+#define BSD_SERVER_SOCKS        1
+
+//   <o>Receive Timeout in seconds <0-600>
+//   <i> A timeout for socket receive in blocking mode.
+//   <i> Timeout value of 0 means indefinite timeout.
+//   <i> Default: 20
+#define BSD_RECEIVE_TOUT        20
+
+//   <q>Hostname Resolver
+//   <i> Enable or disable Berkeley style hostname resolver.
+#define BSD_HOSTNAME_ENABLE     0
+
+// </h>

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_DNS_Client.h

@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Service
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_DNS_Client.h
+ * Purpose: Network Configuration DNS Client
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>DNS Client
+#define DNS_CLIENT_ENABLE       1
+
+//     <o>Cache Table size <5-100>
+//     <i> Number of cached DNS host names/IP addresses
+//     <i> Default: 20
+#define DNS_CLIENT_TAB_SIZE     20
+
+// </h>

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_ETH_0.h

@@ -0,0 +1,222 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Interface
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_ETH_0.h
+ * Purpose: Network Configuration ETH Interface
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Ethernet Network Interface 0
+#define ETH0_ENABLE             1
+
+//   <o>Connect to hardware via Driver_ETH# <0-255>
+//   <i>Select driver control block for MAC and PHY interface
+#define ETH0_DRIVER             1
+
+//   <h>MAC Address
+//   <i> Local Ethernet MAC Address
+//   <i> Value FF:FF:FF:FF:FF:FF is not allowed.
+//   <i> It is an ethernet Broadcast MAC address.
+//     <o>Address byte 1 <0x00-0xff:2>
+//     <i> LSB is an ethernet Multicast bit.
+//     <i> Must be 0 for local MAC address.
+//     <i> Default: 0x1E
+#define ETH0_MAC1               0x1E
+
+//     <o>Address byte 2 <0x00-0xff>
+//     <i> Default: 0x30
+#define ETH0_MAC2               0x30
+
+//     <o>Address byte 3 <0x00-0xff>
+//     <i> Default: 0x6C
+#define ETH0_MAC3               0x6C
+
+//     <o>Address byte 4 <0x00-0xff>
+//     <i> Default: 0xA2
+#define ETH0_MAC4               0xA2
+
+//     <o>Address byte 5 <0x00-0xff>
+//     <i> Default: 0x45
+#define ETH0_MAC5               0x45
+
+//     <o>Address byte 6 <0x00-0xff>
+//     <i> Default: 0x5E
+#define ETH0_MAC6               0x5E
+//   </h>
+
+//   <h>IP Address
+//   <i> Local Static IP Address
+//   <i> Value 255.255.255.255 is not allowed.
+//   <i> It is a Broadcast IP address.
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 192
+#define ETH0_IP1                192
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 168
+#define ETH0_IP2                168
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 0
+#define ETH0_IP3                0
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 100
+#define ETH0_IP4                100
+//   </h>
+
+//   <h>Subnet mask
+//   <i> Local Subnet mask
+//     <o>Mask byte 1 <0-255>
+//     <i> Default: 255
+#define ETH0_MASK1              255
+
+//     <o>Mask byte 2 <0-255>
+//     <i> Default: 255
+#define ETH0_MASK2              255
+
+//     <o>Mask byte 3 <0-255>
+//     <i> Default: 255
+#define ETH0_MASK3              255
+
+//     <o>Mask byte 4 <0-255>
+//     <i> Default: 0
+#define ETH0_MASK4              0
+//   </h>
+
+//   <h>Default Gateway
+//   <i> Default Gateway IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 192
+#define ETH0_GW1                192
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 168
+#define ETH0_GW2                168
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 0
+#define ETH0_GW3                0
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 254
+#define ETH0_GW4                254
+//   </h>
+
+//   <h>Primary DNS Server
+//   <i> Primary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define ETH0_PRI_DNS1           194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define ETH0_PRI_DNS2           25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define ETH0_PRI_DNS3           2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 129
+#define ETH0_PRI_DNS4           129
+//   </h>
+
+//   <h>Secondary DNS Server
+//   <i> Secondary DNS Server IP Address
+//     <o>Address byte 1 <0-255>
+//     <i> Default: 194
+#define ETH0_SEC_DNS1           194
+
+//     <o>Address byte 2 <0-255>
+//     <i> Default: 25
+#define ETH0_SEC_DNS2           25
+
+//     <o>Address byte 3 <0-255>
+//     <i> Default: 2
+#define ETH0_SEC_DNS3           2
+
+//     <o>Address byte 4 <0-255>
+//     <i> Default: 130
+#define ETH0_SEC_DNS4           130
+//   </h>
+
+//   <h>ARP Definitions
+//   <i> Address Resolution Protocol Definitions
+//     <o>Cache Table size <5-100>
+//     <i> Number of cached hardware/IP addresses
+//     <i> Default: 10
+#define ETH0_ARP_TAB_SIZE       10
+
+//     <o>Cache Timeout in seconds <5-255>
+//     <i> A timeout for a cached hardware/IP addresses
+//     <i> Default: 150
+#define ETH0_ARP_CACHE_TOUT     150
+
+//     <o>Number of Retries <0-20>
+//     <i> Number of Retries to resolve an IP address
+//     <i> before ARP module gives up
+//     <i> Default: 4
+#define ETH0_ARP_MAX_RETRY      4
+
+//     <o>Resend Timeout in seconds <1-10>
+//     <i> A timeout to resend the ARP Request
+//     <i> Default: 2
+#define ETH0_ARP_RESEND_TOUT    2
+
+//     <q>Send Notification on Address changes
+//     <i> When this option is enabled, the embedded host
+//     <i> will send a Gratuitous ARP notification at startup,
+//     <i> or when the device IP address has changed.
+//     <i> Default: Disabled
+#define ETH0_ARP_NOTIFY         0
+//   </h>
+
+//   <e>IGMP Group Management
+//   <i> Enable or disable Internet Group Management Protocol
+#define ETH0_IGMP_ENABLE        0
+
+//     <o>Membership Table size <2-50>
+//     <i> Number of Groups this host can join
+//     <i> Default: 5
+#define ETH0_IGMP_TAB_SIZE      5
+//   </e>
+
+//   <q>NetBIOS Name Service
+//   <i> When this option is enabled, the embedded host can be
+//   <i> accessed by his name on the local LAN using NBNS protocol.
+//   <i> You need to modify also the number of UDP Sockets,
+//   <i> because NBNS protocol uses one UDP socket to run.
+#define ETH0_NBNS_ENABLE        1
+
+//   <e>Dynamic Host Configuration
+//   <i> When this option is enabled, local IP address, Net Mask
+//   <i> and Default Gateway are obtained automatically from
+//   <i> the DHCP Server on local LAN.
+//   <i> You need to modify also the number of UDP Sockets,
+//   <i> because DHCP protocol uses one UDP socket to run.
+#define ETH0_DHCP_ENABLE        1
+
+//     <s.40>Vendor Class Identifier
+//     <i> This value is optional. If specified, it is added
+//     <i> to DHCP request message, identifying vendor type.
+//     <i> Default: ""
+#define ETH0_DHCP_VCID          ""
+
+//     <q>Bootfile Name
+//     <i> This value is optional. If enabled, the Bootfile Name
+//     <i> (option 67) is also requested from DHCP server.
+//     <i> Default: disabled
+#define ETH0_DHCP_BOOTFILE      0
+
+//     <q>NTP Servers
+//     <i> This value is optional. If enabled, a list of NTP Servers
+//     <i> (option 42) is also requested from DHCP server.
+//     <i> Default: disabled
+#define ETH0_DHCP_NTP_SERVERS   0
+//   </e>
+
+// </h>

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_TCP.h

@@ -0,0 +1,61 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_TCP.h
+ * Purpose: Network Configuration TCP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>TCP Sockets
+#define TCP_ENABLE              1
+
+//   <o>Number of TCP Sockets <1-20>
+//   <i> Number of available TCP sockets
+//   <i> Default: 5
+#define TCP_NUM_SOCKS           10
+
+//   <o>Number of Retries <0-20>
+//   <i> How many times TCP module will try to retransmit data
+//   <i> before giving up. Increase this value for high-latency
+//   <i> and low_throughput networks.
+//   <i> Default: 5
+#define TCP_MAX_RETRY           5
+
+//   <o>Retry Timeout in seconds <1-10>
+//   <i> If data frame not acknowledged within this time frame,
+//   <i> TCP module will try to resend the data again.
+//   <i> Default: 4
+#define TCP_RETRY_TOUT          4
+
+//   <o>Default Connect Timeout in seconds <1-600>
+//   <i> Default TCP Socket Keep Alive timeout. When it expires
+//   <i> with no TCP data frame send, TCP Connection is closed.
+//   <i> Default: 120
+#define TCP_DEFAULT_TOUT        120
+
+//   <o>Maximum Segment Size <536-1460>
+//   <i> The Maximum Segment Size specifies the maximum
+//   <i> number of bytes in the TCP segment's Data field.
+//   <i> Default: 1460
+#define TCP_MAX_SEG_SIZE        1460
+
+//   <o>Receive Window Size <536-65535>
+//   <i> Receive Window Size specifies the size of data, 
+//   <i> that the socket is able to buffer in flow-control mode.
+//   <i> Default: 4380
+#define TCP_RECEIVE_WIN_SIZE    4380
+
+// </h>
+
+// TCP Initial Retransmit period in seconds
+#define TCP_INITIAL_RETRY_TOUT  1
+
+// TCP SYN frame retransmit period in seconds
+#define TCP_SYN_RETRY_TOUT      2
+
+// Number of retries to establish a connection
+#define TCP_CONNECT_RETRY       7
+

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_UDP.h

@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_UDP.h
+ * Purpose: Network Configuration UDP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>UDP Sockets
+#define UDP_ENABLE              1
+
+//   <o>Number of UDP Sockets <1-30>
+//   <i> Number of available UDP sockets
+//   <i> Default: 5
+#define UDP_NUM_SOCKS           15
+
+// </h>

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Debug.c

@@ -0,0 +1,125 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Debug.c
+ * Purpose: Network Debug Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <q>Print Time Stamp
+//   <i> Enable printing the time-info in debug messages
+#define DBG_TIME                1
+
+// <h>TCPnet Debug Definitions
+//   <o>Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Dynamic Memory debug messages
+#define DBG_MEM                 1
+
+//   <o>Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Ethernet debug messages
+#define DBG_ETH                 0
+
+//   <o>PPP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off PPP debug messages
+#define DBG_PPP                 0
+
+//   <o>SLIP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off SLIP debug messages
+#define DBG_SLIP                0
+
+//   <o>ARP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off ARP debug messages
+#define DBG_ARP                 0
+
+//   <o>IP Debug    <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off IP debug messages
+#define DBG_IP                  1
+
+//   <o>ICMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off ICMP debug messages
+#define DBG_ICMP                1
+
+//   <o>IGMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off IGMP debug messages
+#define DBG_IGMP                1
+
+//   <o>UDP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off UDP debug messages
+#define DBG_UDP                 1
+
+//   <o>TCP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off TCP debug messages
+#define DBG_TCP                 1
+
+//   <o>NBNS Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off NetBIOS Name Service debug messages
+#define DBG_NBNS                1
+
+//   <o>DHCP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Dynamic Host Configuration debug messages
+#define DBG_DHCP                1
+
+//   <o>DNS Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Domain Name Service debug messages
+#define DBG_DNS                 1
+
+//   <o>SNMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Simple Network Management debug messages
+#define DBG_SNMP                1
+
+//   <o>SNTP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Simple Network Time debug messages
+#define DBG_SNTP                1
+
+//   <o>BSD Debug   <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off BSD Interface debug messages
+#define DBG_BSD                 1
+// </h>
+
+// <h>Application Debug Definitions
+//   <o>HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Web Server debug messages
+#define DBG_HTTP_SERVER         1
+
+//   <o>FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off FTP Server debug messages
+#define DBG_FTP_SERVER          1
+
+//   <o>FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off FTP Client debug messages
+#define DBG_FTP_CLIENT          1
+
+//   <o>Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off Telnet Server debug messages
+#define DBG_TELNET_SERVER       1
+
+//   <o>TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off TFTP Server debug messages
+#define DBG_TFTP_SERVER         1
+
+//   <o>TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off TFTP Client debug messages
+#define DBG_TFTP_CLIENT         1
+
+//   <o>SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//   <i> Turn On/Off SMTP Client debug messages
+#define DBG_SMTP_CLIENT         1
+// </h>
+
+
+#include "net_debug.h"
+
+
+/**
+  \fn          void net_debug_init (void)
+  \brief       Initialize Network Debug Interface.
+*/
+void net_debug_init (void) {
+  /* Add your code to initialize the Debug output. This is usually the  */
+  /* serial interface. The function is called at TCPnet system startup. */
+  /* You may need to customize also the 'putchar()' function.           */
+
+}

IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/RTE_Components.h

@@ -0,0 +1,28 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CyaSSL-Full' 
+ * Target:  'CyaSSL-Full' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_STM32F2xx    /* Device Startup for STM32F2 */
+#define RTE_Drivers_ETH_MAC0            /* Driver ETH_MAC0 */
+#define RTE_Drivers_MCI0                /* Driver MCI0 */
+#define RTE_Drivers_PHY_ST802RT1        /* Driver PHY ST802RT1 */
+#define RTE_FileSystem_Core             /* File System Core */
+          #define RTE_FileSystem_LFN              /* File System with Long Filename support */
+#define RTE_FileSystem_Drive_MC_0       /* File System Memory Card Drive 0 */
+#define RTE_Network_Core                /* Network Core */
+          #define RTE_Network_Debug               /* Network Debug Version */
+#define RTE_Network_DNS_Client          /* Network DNS Client */
+#define RTE_Network_Interface_ETH_0     /* Network Interface ETH 0 */
+#define RTE_Network_Socket_BSD          /* Network Socket BSD */
+#define RTE_Network_Socket_TCP          /* Network Socket TCP */
+#define RTE_Network_Socket_UDP          /* Network Socket UDP */
+
+#endif /* RTE_COMPONENTS_H */

IDE/MDK5-ARM/Projects/CyaSSL-Full/STM32_SWO.ini

@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2004-2013 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+// <h> Debug MCU Configuration
+//   <o1.0>    DBG_SLEEP     <i> Debug Sleep Mode
+//   <o1.1>    DBG_STOP      <i> Debug Stop Mode
+//   <o1.2>    DBG_STANDBY   <i> Debug Standby Mode
+//   <o1.5>    TRACE_IOEN    <i> Trace I/O Enable 
+//   <o1.6..7> TRACE_MODE    <i> Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//   <o1.8>    DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
+//   <o1.9>    DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
+//   <o1.10>   DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
+//   <o1.11>   DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
+//   <o1.12>   DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
+//   <o1.13>   DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
+//   <o1.14>   DBG_CAN_STOP  <i> CAN Stopped when Core is halted
+// </h>
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup

IDE/MDK5-ARM/Projects/CyaSSL-Full/cert_data.c

@@ -0,0 +1,28 @@
+/* certs_test.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+/* Define initial data for cert buffers */
+#include <cyassl/certs_test.h>
+

IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c

@@ -0,0 +1,756 @@
+/* client.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+        #include <config.h>
+#endif
+ #define CYASSL_MDK_ARM
+#if defined(CYASSL_MDK_ARM)
+        #include <stdio.h>
+        #include <string.h>
+
+        #if defined(CYASSL_MDK5)
+            #include "cmsis_os.h"
+            #include "rl_fs.h" 
+            #include "rl_net.h" 
+        #else
+            #include "rtl.h"
+        #endif
+
+        #include "cyassl_MDK_ARM.h"
+#endif
+
+#include <cyassl/ctaocrypt/settings.h>
+
+#if !defined(CYASSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER)
+    /* in case memory tracker wants stats */
+    #define CYASSL_TRACK_MEMORY
+#endif
+
+#include <cyassl/ssl.h>
+
+#ifdef CYASSL_MDK_SHELL
+extern void exit_command(void) ;
+#define exit(code) exit_command() 
+#endif
+
+#include <cyassl/test.h>
+
+#include "examples/client/client.h"
+
+#define USE_CYASSL_MEMORY
+
+#ifdef CYASSL_CALLBACKS
+    int handShakeCB(HandShakeInfo*);
+    int timeoutCB(TimeoutInfo*);
+    Timeval timeout;
+#endif
+
+
+static void NonBlockingSSL_Connect(CYASSL* ssl)
+{
+#ifndef CYASSL_CALLBACKS
+    int ret = CyaSSL_connect(ssl);
+#else
+    int ret = CyaSSL_connect_ex(ssl, handShakeCB, timeoutCB, timeout);
+#endif
+    int error = CyaSSL_get_error(ssl, 0);
+    SOCKET_T sockfd = (SOCKET_T)CyaSSL_get_fd(ssl);
+    int select_ret;
+
+    while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ ||
+                                  error == SSL_ERROR_WANT_WRITE)) {
+        int currTimeout = 1;
+
+        if (error == SSL_ERROR_WANT_READ)
+            printf("... client would read block\n");
+        else
+            printf("... client would write block\n");
+
+#ifdef CYASSL_DTLS
+        currTimeout = CyaSSL_dtls_get_current_timeout(ssl);
+#endif
+        select_ret = tcp_select(sockfd, currTimeout);
+
+        if ((select_ret == TEST_RECV_READY) ||
+                                        (select_ret == TEST_ERROR_READY)) {
+            #ifndef CYASSL_CALLBACKS
+                    ret = CyaSSL_connect(ssl);
+            #else
+                ret = CyaSSL_connect_ex(ssl,handShakeCB,timeoutCB,timeout);
+            #endif
+            error = CyaSSL_get_error(ssl, 0);
+        }
+        else if (select_ret == TEST_TIMEOUT && !CyaSSL_dtls(ssl)) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#ifdef CYASSL_DTLS
+        else if (select_ret == TEST_TIMEOUT && CyaSSL_dtls(ssl) &&
+                                            CyaSSL_dtls_got_timeout(ssl) >= 0) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#endif
+        else {
+            error = SSL_FATAL_ERROR;
+        }
+    }
+    if (ret != SSL_SUCCESS)
+        err_sys("SSL_connect failed");
+}
+
+
+static void Usage(void)
+{
+    printf("client "    LIBCYASSL_VERSION_STRING
+           " NOTE: All files relative to CyaSSL home dir\n");
+    printf("-?          Help, print this usage\n");
+    printf("-h <host>   Host to connect to, default %s\n", yasslIP);
+    printf("-p <num>    Port to connect on, not 0, default %d\n", yasslPort);
+    printf("-v <num>    SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n",
+                                 CLIENT_DEFAULT_VERSION);
+    printf("-l <str>    Cipher list\n");
+    printf("-c <file>   Certificate file,           default %s\n", cliCert);
+    printf("-k <file>   Key file,                   default %s\n", cliKey);
+    printf("-A <file>   Certificate Authority file, default %s\n", caCert);
+    printf("-b <num>    Benchmark <num> connections and print stats\n");
+    printf("-s          Use pre Shared keys\n");
+    printf("-t          Track CyaSSL memory use\n");
+    printf("-d          Disable peer checks\n");
+    printf("-g          Send server HTTP GET\n");
+    printf("-u          Use UDP DTLS,"
+           " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n");
+    printf("-m          Match domain name in cert\n");
+    printf("-N          Use Non-blocking sockets\n");
+    printf("-r          Resume session\n");
+    printf("-f          Fewer packets/group messages\n");
+    printf("-x          Disable client cert/key loading\n");
+#ifdef SHOW_SIZES
+    printf("-z          Print structure sizes\n");
+#endif
+    printf("-S <str>    Use Host Name Indication\n");
+}
+
+
+THREAD_RETURN CYASSL_THREAD client_test(void* args)
+{
+    SOCKET_T sockfd = 0;
+
+    CYASSL_METHOD*  method  = 0;
+    CYASSL_CTX*     ctx     = 0;
+    CYASSL*         ssl     = 0;
+    
+    CYASSL*         sslResume = 0;
+    CYASSL_SESSION* session = 0;
+    char         resumeMsg[] = "resuming cyassl!";
+    int          resumeSz    = sizeof(resumeMsg);
+
+    char msg[32] = "hello cyassl!";   /* GET may make bigger */
+    char reply[80];
+    int  input;
+    int  msgSz = (int)strlen(msg);
+
+    int   port   = yasslPort;
+    char* host   = (char*)yasslIP;
+    char* domain = (char*)"www.yassl.com";
+
+    int    ch;
+    int    version = CLIENT_INVALID_VERSION;
+    int    usePsk   = 0;
+    int    sendGET  = 0;
+    int    benchmark = 0;
+    int    doDTLS    = 0;
+    int    matchName = 0;
+    int    doPeerCheck = 1;
+    int    nonBlocking = 0;
+    int    resumeSession = 0;
+    int    trackMemory   = 0;
+    int    useClientCert = 1;
+    int    fewerPackets  = 0;
+    char*  cipherList = NULL;
+    char*  verifyCert = (char*)caCert;
+    char*  ourCert    = (char*)cliCert;
+    char*  ourKey     = (char*)cliKey;
+
+#ifdef HAVE_SNI
+    char*  sniHostName = NULL;
+#endif
+
+    int     argc = ((func_args*)args)->argc;
+    char**  argv = ((func_args*)args)->argv;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef NO_RSA
+    verifyCert = (char*)eccCert;
+    ourCert    = (char*)cliEccCert;
+    ourKey     = (char*)cliEccKey;
+#endif
+    (void)resumeSz;
+    (void)session;
+    (void)sslResume;
+    (void)trackMemory;
+
+    while ((ch = mygetopt(argc, argv, "?gdusmNrtfxh:p:v:l:A:c:k:b:zS:")) != -1){
+        switch (ch) {
+            case '?' :
+                Usage();
+                exit(EXIT_SUCCESS);
+
+            case 'g' :
+                sendGET = 1;
+                break;
+
+            case 'd' :
+                doPeerCheck = 0;
+                break;
+
+            case 'u' :
+                doDTLS  = 1;
+                break;
+
+            case 's' :
+                usePsk = 1;
+                break;
+
+            case 't' :
+            #ifdef USE_CYASSL_MEMORY
+                trackMemory = 1;
+            #endif
+                break;
+
+            case 'm' :
+                matchName = 1;
+                break;
+
+            case 'x' :
+                useClientCert = 0;
+                break;
+
+            case 'f' :
+                fewerPackets = 1;
+                break;
+
+            case 'h' :
+                host   = myoptarg;
+                domain = myoptarg;
+                break;
+
+            case 'p' :
+                port = atoi(myoptarg);
+                #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API)
+                    if (port == 0)
+                        err_sys("port number cannot be 0");
+                #endif
+                break;
+
+            case 'v' :
+                version = atoi(myoptarg);
+                if (version < 0 || version > 3) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'l' :
+                cipherList = myoptarg;
+                break;
+
+            case 'A' :
+                verifyCert = myoptarg;
+                break;
+
+            case 'c' :
+                ourCert = myoptarg;
+                break;
+
+            case 'k' :
+                ourKey = myoptarg;
+                break;
+
+            case 'b' :
+                benchmark = atoi(myoptarg);
+                if (benchmark < 0 || benchmark > 1000000) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'N' :
+                nonBlocking = 1;
+                break;
+
+            case 'r' :
+                resumeSession = 1;
+                break;
+
+            case 'z' :
+                #ifndef CYASSL_LEANPSK
+                    CyaSSL_GetObjectSize();
+                #endif
+                break;
+
+            case 'S' :
+                #ifdef HAVE_SNI
+                    sniHostName = myoptarg;
+                #endif
+                break;
+
+            default:
+                Usage();
+                exit(MY_EX_USAGE);
+        }
+    }
+
+    myoptind = 0;      /* reset for test cases */
+
+    /* sort out DTLS versus TLS versions */
+    if (version == CLIENT_INVALID_VERSION) {
+        if (doDTLS)
+            version = CLIENT_DTLS_DEFAULT_VERSION;
+        else
+            version = CLIENT_DEFAULT_VERSION;
+    }
+    else {
+        if (doDTLS) {
+            if (version == 3)
+                version = -2;
+            else
+                version = -1;
+        }
+    }
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        InitMemoryTracker(); 
+#endif
+
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case 0:
+            method = CyaSSLv3_client_method();
+            break;
+                
+                
+    #ifndef NO_TLS
+        case 1:
+            method = CyaTLSv1_client_method();
+            break;
+
+        case 2:
+            method = CyaTLSv1_1_client_method();
+            break;
+    #endif /* NO_TLS */
+                
+#endif  /* NO_OLD_TLS */
+                
+#ifndef NO_TLS
+        case 3:
+            method = CyaTLSv1_2_client_method();
+            break;
+#endif
+
+#ifdef CYASSL_DTLS
+        case -1:
+            method = CyaDTLSv1_client_method();
+            break;
+
+        case -2:
+            method = CyaDTLSv1_2_client_method();
+            break;
+#endif
+
+        default:
+            err_sys("Bad SSL version");
+            break;
+    }
+
+    if (method == NULL)
+        err_sys("unable to get method");
+
+    ctx = CyaSSL_CTX_new(method);
+    if (ctx == NULL)
+        err_sys("unable to get ctx");
+        
+    if (cipherList)
+        if (CyaSSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS)
+            err_sys("client can't set cipher list 1");
+
+#ifdef CYASSL_LEANPSK
+    usePsk = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    usePsk = 1;
+#endif
+
+    if (fewerPackets)
+        CyaSSL_CTX_set_group_messages(ctx);
+
+    if (usePsk) {
+#ifndef NO_PSK
+        CyaSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb);
+        if (cipherList == NULL) {
+            const char *defaultCipherList;
+            #ifdef HAVE_NULL_CIPHER
+                defaultCipherList = "PSK-NULL-SHA256";
+            #else
+                defaultCipherList = "PSK-AES128-CBC-SHA256";
+            #endif
+            if (CyaSSL_CTX_set_cipher_list(ctx,defaultCipherList) !=SSL_SUCCESS)
+                err_sys("client can't set cipher list 2");
+        }
+#endif
+        useClientCert = 0;
+    }
+
+#ifdef OPENSSL_EXTRA
+    CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    if (cipherList == NULL) {
+        /* don't use EDH, can't sniff tmp keys */
+        if (CyaSSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS) {
+            err_sys("client can't set cipher list 3");
+        }
+    }
+#endif
+
+#ifdef USER_CA_CB
+    CyaSSL_CTX_SetCACb(ctx, CaCb);
+#endif
+
+#ifdef VERIFY_CALLBACK
+    CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_PEER, myVerify);
+#endif
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (useClientCert){
+        if (CyaSSL_CTX_use_certificate_chain_file(ctx, ourCert) != SSL_SUCCESS)
+            err_sys("can't load client cert file, check file and run from"
+                    " CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load client private key file, check file and run "
+                    "from CyaSSL home dir");
+    }
+
+    if (!usePsk) {
+        if (CyaSSL_CTX_load_verify_locations(ctx, verifyCert, 0) != SSL_SUCCESS)
+                err_sys("can't load ca file, Please run from CyaSSL home dir");
+    }
+#endif
+#if !defined(NO_CERTS)
+    if (!usePsk && doPeerCheck == 0)
+        CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0);
+#endif
+
+#ifdef HAVE_CAVIUM
+    CyaSSL_CTX_UseCavium(ctx, CAVIUM_DEV_ID);
+#endif
+
+#ifdef HAVE_SNI
+    if (sniHostName)
+        if (CyaSSL_CTX_UseSNI(ctx, 0, sniHostName, XSTRLEN(sniHostName))
+                                                                 != SSL_SUCCESS)
+            err_sys("UseSNI failed");
+#endif
+
+    if (benchmark) {
+        /* time passed in number of connects give average */
+        int times = benchmark;
+        int i = 0;
+
+        double start = current_time(), avg;
+
+        for (i = 0; i < times; i++) {
+            tcp_connect(&sockfd, host, port, doDTLS);
+
+            ssl = CyaSSL_new(ctx);
+            CyaSSL_set_fd(ssl, sockfd);
+            if (CyaSSL_connect(ssl) != SSL_SUCCESS)
+                err_sys("SSL_connect failed");
+
+            CyaSSL_shutdown(ssl);
+            CyaSSL_free(ssl);
+            CloseSocket(sockfd);
+        }
+        avg = current_time() - start;
+        avg /= times;
+        avg *= 1000;   /* milliseconds */
+        printf("CyaSSL_connect avg took: %8.3f milliseconds\n", avg);
+
+        CyaSSL_CTX_free(ctx);
+        ((func_args*)args)->return_code = 0;
+
+        exit(EXIT_SUCCESS);
+    }
+    
+    #if defined(CYASSL_MDK_ARM)
+    CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0);
+    #endif
+    
+    ssl = CyaSSL_new(ctx);
+    if (ssl == NULL)
+        err_sys("unable to get SSL object");
+
+    CyaSSL_set_quiet_shutdown(ssl, 1) ;
+
+    if (doDTLS) {
+        SOCKADDR_IN_T addr;
+        build_addr(&addr, host, port, 1);
+        CyaSSL_dtls_set_peer(ssl, &addr, sizeof(addr));
+        tcp_socket(&sockfd, 1);
+    }
+    else {
+        tcp_connect(&sockfd, host, port, 0);
+    }
+    CyaSSL_set_fd(ssl, sockfd);
+#ifdef HAVE_CRL
+    if (CyaSSL_EnableCRL(ssl, CYASSL_CRL_CHECKALL) != SSL_SUCCESS)
+        err_sys("can't enable crl check");
+    if (CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, 0) != SSL_SUCCESS)
+        err_sys("can't load crl, check crlfile and date validity");
+    if (CyaSSL_SetCRL_Cb(ssl, CRL_CallBack) != SSL_SUCCESS)
+        err_sys("can't set crl callback");
+#endif
+    if (matchName && doPeerCheck)
+        CyaSSL_check_domain_name(ssl, domain);
+#ifndef CYASSL_CALLBACKS
+    if (nonBlocking) {
+        CyaSSL_set_using_nonblock(ssl, 1);
+        tcp_set_nonblocking(&sockfd);
+        NonBlockingSSL_Connect(ssl);
+    }
+    else if (CyaSSL_connect(ssl) != SSL_SUCCESS) {
+        /* see note at top of README */
+        int  err = CyaSSL_get_error(ssl, 0);
+        char buffer[80];
+        printf("err = %d, %s\n", err,
+                                CyaSSL_ERR_error_string(err, buffer));
+        err_sys("SSL_connect failed");
+        /* if you're getting an error here  */
+    }
+#else
+    timeout.tv_sec  = 2;
+    timeout.tv_usec = 0;
+    NonBlockingSSL_Connect(ssl);  /* will keep retrying on timeout */
+#endif
+    showPeer(ssl);
+
+    if (sendGET) {
+        printf("SSL connect ok, sending GET...\n");
+        msgSz = 28;
+        strncpy(msg, "GET / HTTP/1.0\r\n\r\n", msgSz);
+        msg[msgSz] = '\0';
+    }
+    if (CyaSSL_write(ssl, msg, msgSz) != msgSz)
+        err_sys("SSL_write failed");
+
+    input = CyaSSL_read(ssl, reply, sizeof(reply)-1);
+    if (input > 0) {
+        reply[input] = 0;
+        printf("Server response: %s", reply);
+
+        if (sendGET && (input == (sizeof(reply)-1))) {  /* get html */
+            while (1) {
+                input = CyaSSL_read(ssl, reply, sizeof(reply)-1);
+                if (input > 0) {
+                    reply[input] = 0;
+                    printf("%s", reply);
+                    if(input < sizeof(reply)-1)
+                        break ;
+                }
+                else
+                    break;
+            }
+        }
+        printf("\n");
+    }
+    else if (input < 0) {
+        int readErr = CyaSSL_get_error(ssl, 0);
+        if (readErr != SSL_ERROR_WANT_READ)
+            err_sys("CyaSSL_read failed");
+    }
+    
+#ifdef CYASSL_CMSIS_RTOS
+    osDelay(5000) ;
+#endif
+
+#ifndef NO_SESSION_CACHE
+    if (resumeSession) {
+        if (doDTLS) {
+            strncpy(msg, "break", 6);
+            msgSz = (int)strlen(msg);
+            /* try to send session close */
+            CyaSSL_write(ssl, msg, msgSz);
+        }
+        session   = CyaSSL_get_session(ssl);
+        sslResume = CyaSSL_new(ctx);
+    }
+#endif
+
+    if (doDTLS == 0)            /* don't send alert after "break" command */
+        CyaSSL_shutdown(ssl);  /* echoserver will interpret as new conn */
+    CyaSSL_free(ssl);
+    CloseSocket(sockfd);
+
+#ifndef NO_SESSION_CACHE
+    if (resumeSession) {
+        if (doDTLS) {
+            SOCKADDR_IN_T addr;
+            #ifdef USE_WINDOWS_API 
+                Sleep(500);
+            #else
+                sleep(1);
+            #endif
+            build_addr(&addr, host, port, 1);
+            CyaSSL_dtls_set_peer(sslResume, &addr, sizeof(addr));
+            tcp_socket(&sockfd, 1);
+        }
+        else {
+            tcp_connect(&sockfd, host, port, 0);
+        }
+        CyaSSL_set_fd(sslResume, sockfd);
+        CyaSSL_set_session(sslResume, session);
+       
+        showPeer(sslResume);
+#ifndef CYASSL_CALLBACKS
+        if (nonBlocking) {
+            CyaSSL_set_using_nonblock(sslResume, 1);
+            tcp_set_nonblocking(&sockfd);
+            NonBlockingSSL_Connect(sslResume);
+        }
+        else if (CyaSSL_connect(sslResume) != SSL_SUCCESS)
+            err_sys("SSL resume failed");
+#else
+        timeout.tv_sec  = 2;
+        timeout.tv_usec = 0;
+        NonBlockingSSL_Connect(ssl);  /* will keep retrying on timeout */
+#endif
+
+        if (CyaSSL_session_reused(sslResume))
+            printf("reused session id\n");
+        else
+            printf("didn't reuse session id!!!\n");
+
+        if (CyaSSL_write(sslResume, resumeMsg, resumeSz) != resumeSz)
+            err_sys("SSL_write failed");
+
+        if (nonBlocking) {
+            /* give server a chance to bounce a message back to client */
+            #ifdef USE_WINDOWS_API
+                Sleep(500);
+            #else
+                sleep(1);
+            #endif
+        }
+
+        input = CyaSSL_read(sslResume, reply, sizeof(reply)-1);
+        if (input > 0) {
+            reply[input] = 0;
+            printf("Server resume response: %s\n", reply);
+        }
+
+        /* try to send session break */
+        CyaSSL_write(sslResume, msg, msgSz); 
+
+        CyaSSL_shutdown(sslResume);
+        CyaSSL_free(sslResume);
+        CloseSocket(sockfd);
+    }
+#endif /* NO_SESSION_CACHE */
+
+    CyaSSL_CTX_free(ctx);
+
+    ((func_args*)args)->return_code = 0;
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        ShowMemoryTracker();
+#endif /* USE_CYASSL_MEMORY */
+
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("client") || CurrentDir("build"))
+            ChangeDirBack(2);
+  
+#ifdef HAVE_STACK_SIZE
+        StackSizeCheck(&args, client_test);
+#else 
+        client_test(&args);
+#endif
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+    int myoptind = 0;
+    char* myoptarg = NULL;
+
+#endif /* NO_MAIN_DRIVER */
+
+
+
+#ifdef CYASSL_CALLBACKS
+
+    int handShakeCB(HandShakeInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+
+    int timeoutCB(TimeoutInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+#endif
+

IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c

@@ -0,0 +1,287 @@
+/* echoclient.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ctaocrypt/settings.h>
+
+#include <cyassl/openssl/ssl.h>
+
+#if defined(CYASSL_MDK_ARM)
+    #include <stdio.h>
+    #include <string.h>
+    
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+        #include "rl_fs.h" 
+        #include "rl_net.h" 
+    #else
+        #include "rtl.h"
+    #endif
+    
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#include <cyassl/test.h>
+
+#include "examples/echoclient/echoclient.h"
+
+void echoclient_test(void* args)
+{
+    SOCKET_T sockfd = 0;
+
+    FILE* fin   = stdin  ;
+    FILE* fout = stdout;
+
+    int inCreated  = 0;
+    int outCreated = 0;
+
+    char msg[1024];
+    char reply[1024+1];
+
+    SSL_METHOD* method = 0;
+    SSL_CTX*    ctx    = 0;
+    SSL*        ssl    = 0;
+
+    int doDTLS = 0;
+    int doPSK = 0;
+    int sendSz;
+    int argc    = 0;
+    char** argv = 0;
+    int port = yasslPort;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+    
+#ifndef CYASSL_MDK_ARM
+    argc = ((func_args*)args)->argc;
+    argv = ((func_args*)args)->argv;
+#endif
+
+    if (argc >= 2) {
+        fin  = fopen(argv[1], "r"); 
+        inCreated = 1;
+    }
+    if (argc >= 3) {
+        fout = fopen(argv[2], "w");
+        outCreated = 1;
+    }
+
+    if (!fin)  err_sys("can't open input file");
+    if (!fout) err_sys("can't open output file");
+
+#ifdef CYASSL_DTLS
+    doDTLS  = 1;
+#endif
+
+#ifdef CYASSL_LEANPSK 
+    doPSK = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    doPSK = 1;
+#endif
+
+#if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && !defined(CYASSL_MDK_SHELL)
+    port = ((func_args*)args)->signal->port;
+#endif
+#if defined (CYASSL_CALLEE_PORT)
+    port = CYASSL_CALLEE_PORT ;
+#endif
+
+#if defined(CYASSL_DTLS)
+    method  = DTLSv1_client_method();
+#elif  !defined(NO_TLS)
+    method = CyaSSLv23_client_method();
+#else
+    method = SSLv3_client_method();
+#endif
+    ctx    = SSL_CTX_new(method);
+
+#ifndef NO_FILESYSTEM
+    #ifndef NO_RSA
+    if (SSL_CTX_load_verify_locations(ctx, caCert, 0) != SSL_SUCCESS)
+        err_sys("can't load ca file, Please run from CyaSSL home dir");
+    #endif
+    #ifdef HAVE_ECC
+        if (SSL_CTX_load_verify_locations(ctx, eccCert, 0) != SSL_SUCCESS)
+            err_sys("can't load ca file, Please run from CyaSSL home dir");
+    #endif
+#elif !defined(NO_CERTS)
+    if (!doPSK)
+        load_buffer(ctx, caCert, CYASSL_CA);
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    /* don't use EDH, can't sniff tmp keys */
+    SSL_CTX_set_cipher_list(ctx, "AES256-SHA");
+#endif
+    if (doPSK) {
+#ifndef NO_PSK
+        const char *defaultCipherList;
+
+        CyaSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb);
+        #ifdef HAVE_NULL_CIPHER
+            defaultCipherList = "PSK-NULL-SHA256";
+        #else
+            defaultCipherList = "PSK-AES128-CBC-SHA256";
+        #endif
+        if (CyaSSL_CTX_set_cipher_list(ctx,defaultCipherList) !=SSL_SUCCESS)
+            err_sys("client can't set cipher list 2");
+#endif
+    }
+
+#ifdef OPENSSL_EXTRA
+    SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+    #if defined(CYASSL_MDK_ARM)
+    CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0);
+    #endif
+
+    ssl = SSL_new(ctx);
+    CyaSSL_set_quiet_shutdown(ssl, 1) ;
+    
+    if (doDTLS) {
+        SOCKADDR_IN_T addr;
+        build_addr(&addr, yasslIP, port, 1);
+        CyaSSL_dtls_set_peer(ssl, &addr, sizeof(addr));
+        tcp_socket(&sockfd, 1);
+    }
+    else {
+        tcp_connect(&sockfd, yasslIP, port, 0);
+    }
+        
+    SSL_set_fd(ssl, sockfd);
+#if defined(USE_WINDOWS_API) && defined(CYASSL_DTLS) && defined(NO_MAIN_DRIVER)
+    /* let echoserver bind first, TODO: add Windows signal like pthreads does */
+    Sleep(100);
+#endif
+
+    if (SSL_connect(ssl) != SSL_SUCCESS) err_sys("SSL_connect failed");
+
+    while (fgets(msg, sizeof(msg), fin) != 0) {
+     
+        sendSz = (int)strlen(msg);
+
+        if (SSL_write(ssl, msg, sendSz) != sendSz)
+            err_sys("SSL_write failed");
+
+        if (strncmp(msg, "quit", 4) == 0) {
+            fputs("sending server shutdown command: quit!\n", fout);
+            break;
+        }
+
+        if (strncmp(msg, "break", 5) == 0) {
+            fputs("sending server session close: break!\n", fout);
+            break;
+        }
+
+        #ifndef CYASSL_MDK_SHELL
+        while (sendSz) {
+            int got;
+            if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) {
+                reply[got] = 0;
+                fputs(reply, fout);
+                fflush(fout) ;
+                sendSz -= got;
+            }
+            else
+                break;
+        }
+        #else
+        {
+            int got;
+            if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) {
+                reply[got] = 0;
+                fputs(reply, fout);
+                fflush(fout) ;
+                sendSz -= got;
+            }
+        }
+        #endif
+    }
+
+#ifdef CYASSL_CMSIS_RTOS
+    osDelay(5000) ;
+#endif
+
+
+#ifdef CYASSL_DTLS
+    strncpy(msg, "break", 6);
+    sendSz = (int)strlen(msg);
+    /* try to tell server done */
+    SSL_write(ssl, msg, sendSz);
+#else
+    SSL_shutdown(ssl);
+#endif
+
+    SSL_free(ssl);
+    SSL_CTX_free(ctx);
+
+    fflush(fout);
+    if (inCreated)  fclose(fin);
+    if (outCreated) fclose(fout);
+
+    CloseSocket(sockfd);
+    ((func_args*)args)->return_code = 0; 
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+
+        if (CurrentDir("echoclient") || CurrentDir("build"))
+            ChangeDirBack(2);
+        echoclient_test(&args);
+
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+        
+#endif /* NO_MAIN_DRIVER */
+
+

IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c

@@ -0,0 +1,370 @@
+/* echoserver.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ctaocrypt/settings.h>
+
+#if defined(CYASSL_MDK_ARM)
+    #include <stdio.h>
+    #include <string.h>
+
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+        #include "rl_fs.h" 
+        #include "rl_net.h" 
+    #else
+        #include "rtl.h"
+    #endif
+
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#include <cyassl/ssl.h>
+#include <cyassl/test.h>
+
+#ifndef NO_MAIN_DRIVER
+    #define ECHO_OUT
+#endif
+
+#include "examples/echoserver/echoserver.h"
+
+
+#ifdef SESSION_STATS
+    CYASSL_API void PrintSessionStats(void);
+#endif
+
+#define SVR_COMMAND_SIZE 256
+
+static void SignalReady(void* args, int port)
+{
+#if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__)
+    /* signal ready to tcp_accept */
+    func_args* server_args = (func_args*)args;
+    tcp_ready* ready = server_args->signal;
+    pthread_mutex_lock(&ready->mutex);
+    ready->ready = 1;
+    ready->port = port;
+    pthread_cond_signal(&ready->cond);
+    pthread_mutex_unlock(&ready->mutex);
+#endif
+    (void)args;
+    (void)port;
+}
+
+
+THREAD_RETURN CYASSL_THREAD echoserver_test(void* args)
+{
+    SOCKET_T       sockfd = 0;
+    CYASSL_METHOD* method = 0;
+    CYASSL_CTX*    ctx    = 0;
+
+    int    doDTLS = 0;
+    int    doPSK = 0;
+    int    outCreated = 0;
+    int    shutDown = 0;
+    int    useAnyAddr = 0;
+    int    port = yasslPort;
+    int    argc = ((func_args*)args)->argc;
+    char** argv = ((func_args*)args)->argv;
+
+#ifdef ECHO_OUT
+    FILE* fout = stdout;
+    if (argc >= 2) {
+        fout = fopen(argv[1], "w");
+        outCreated = 1;
+    }
+    if (!fout) err_sys("can't open output file");
+#endif
+    (void)outCreated;
+    (void)argc;
+    (void)argv;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef CYASSL_DTLS
+    doDTLS  = 1;
+#endif
+
+#ifdef CYASSL_LEANPSK
+    doPSK = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    doPSK = 1;
+#endif
+
+    #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \
+                      !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_ARM)
+        port = 0;
+    #endif
+    #if defined(USE_ANY_ADDR)
+        useAnyAddr = 1;
+    #endif
+    tcp_listen(&sockfd, &port, useAnyAddr, doDTLS);
+
+#if defined(CYASSL_DTLS)
+    method  = CyaDTLSv1_server_method();
+#elif  !defined(NO_TLS)
+    method = CyaSSLv23_server_method();
+#else
+    method = CyaSSLv3_server_method();
+#endif
+    ctx    = CyaSSL_CTX_new(method);
+    /* CyaSSL_CTX_set_session_cache_mode(ctx, SSL_SESS_CACHE_OFF); */
+
+#ifdef OPENSSL_EXTRA
+    CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+#ifndef NO_FILESYSTEM
+    if (doPSK == 0) {
+    #ifdef HAVE_NTRU
+        /* ntru */
+        if (CyaSSL_CTX_use_certificate_file(ctx, ntruCert, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load ntru cert file, "
+                    "Please run from CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ntruKey)
+                != SSL_SUCCESS)
+            err_sys("can't load ntru key file, "
+                    "Please run from CyaSSL home dir");
+    #elif defined(HAVE_ECC)
+        /* ecc */
+        if (CyaSSL_CTX_use_certificate_file(ctx, eccCert, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server cert file, "
+                    "Please run from CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_PrivateKey_file(ctx, eccKey, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server key file, "
+                    "Please run from CyaSSL home dir");
+    #elif defined(NO_CERTS)
+        /* do nothing, just don't load cert files */
+    #else
+        /* normal */
+        if (CyaSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server cert file, "
+                    "Please run from CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server key file, "
+                    "Please run from CyaSSL home dir");
+    #endif
+    } /* doPSK */
+#elif !defined(NO_CERTS)
+    if (!doPSK) {
+        load_buffer(ctx, svrCert, CYASSL_CERT);
+        load_buffer(ctx, svrKey,  CYASSL_KEY);
+    }
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    /* don't use EDH, can't sniff tmp keys */
+    CyaSSL_CTX_set_cipher_list(ctx, "AES256-SHA");
+#endif
+
+    if (doPSK) {
+#ifndef NO_PSK
+        const char *defaultCipherList;
+
+        CyaSSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb);
+        CyaSSL_CTX_use_psk_identity_hint(ctx, "cyassl server");
+        #ifdef HAVE_NULL_CIPHER
+            defaultCipherList = "PSK-NULL-SHA256";
+        #else
+            defaultCipherList = "PSK-AES128-CBC-SHA256";
+        #endif
+        if (CyaSSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS)
+            err_sys("server can't set cipher list 2");
+#endif
+    }
+
+    SignalReady(args, port);
+
+    while (!shutDown) {
+        CYASSL* ssl = 0;
+        char    command[SVR_COMMAND_SIZE+1];
+        int     echoSz = 0;
+        int     clientfd;
+        int     firstRead = 1;
+        int     gotFirstG = 0;
+                
+#ifndef CYASSL_DTLS 
+        SOCKADDR_IN_T client;
+        socklen_t     client_len = sizeof(client);
+        clientfd = accept(sockfd, (struct sockaddr*)&client,
+                         (ACCEPT_THIRD_T)&client_len);
+#else
+        clientfd = udp_read_connect(sockfd);
+#endif
+        if (clientfd == -1) err_sys("tcp accept failed");
+
+        ssl = CyaSSL_new(ctx);
+        if (ssl == NULL) err_sys("SSL_new failed");
+              CyaSSL_set_quiet_shutdown(ssl, 1) ;
+            
+        CyaSSL_set_fd(ssl, clientfd);
+        #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA)
+            CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM);
+        #elif !defined(NO_CERTS)
+            SetDH(ssl);  /* will repick suites with DHE, higher than PSK */
+        #endif
+        if (CyaSSL_accept(ssl) != SSL_SUCCESS) {
+            printf("SSL_accept failed\n");
+            CyaSSL_free(ssl);
+            CloseSocket(clientfd);
+            continue;
+        }
+#if defined(PEER_INFO)
+        showPeer(ssl);
+#endif
+
+        while ( (echoSz = CyaSSL_read(ssl, command, sizeof(command)-1)) > 0) {
+
+            if (firstRead == 1) {
+                firstRead = 0;  /* browser may send 1 byte 'G' to start */
+                if (echoSz == 1 && command[0] == 'G') {
+                    gotFirstG = 1;
+                    continue;
+                }
+            }
+            else if (gotFirstG == 1 && strncmp(command, "ET /", 4) == 0) {
+                strncpy(command, "GET", 4);
+                /* fall through to normal GET */
+            }
+           
+            if ( strncmp(command, "quit", 4) == 0) {
+                printf("client sent quit command: shutting down!\n");
+                shutDown = 1;
+                break;
+            }
+            if ( strncmp(command, "break", 5) == 0) {
+                printf("client sent break command: closing session!\n");
+                break;
+            }
+#ifdef SESSION_STATS
+            if ( strncmp(command, "printstats", 10) == 0) {
+                PrintSessionStats();
+                break;
+            }
+#endif
+            if ( strncmp(command, "GET", 3) == 0) {
+                char type[]   = "HTTP/1.0 200 ok\r\nContent-type:"
+                                " text/html\r\n\r\n";
+                char header[] = "<html><body BGCOLOR=\"#ffffff\">\n<pre>\n";
+                char body[]   = "greetings from CyaSSL\n";
+                char footer[] = "</body></html>\r\n\r\n";
+            
+                strncpy(command, type, sizeof(type));
+                echoSz = sizeof(type) - 1;
+
+                strncpy(&command[echoSz], header, sizeof(header));
+                echoSz += (int)sizeof(header) - 1;
+                strncpy(&command[echoSz], body, sizeof(body));
+                echoSz += (int)sizeof(body) - 1;
+                strncpy(&command[echoSz], footer, sizeof(footer));
+                echoSz += (int)sizeof(footer);
+
+                if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                    err_sys("SSL_write failed");
+                break;
+            }
+            command[echoSz] = 0;
+
+            #ifdef ECHO_OUT
+                fputs(command, fout);
+            #endif
+
+            if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                err_sys("SSL_write failed");
+        }
+#ifndef CYASSL_DTLS
+        CyaSSL_shutdown(ssl);
+#endif
+        CyaSSL_free(ssl);
+        CloseSocket(clientfd);
+#ifdef CYASSL_DTLS
+        tcp_listen(&sockfd, &port, useAnyAddr, doDTLS);
+        SignalReady(args, port);
+#endif
+    }
+#ifdef CYASSL_CMSIS_RTOS
+    osDelay(5000) ;
+#endif
+    CloseSocket(sockfd);
+    CyaSSL_CTX_free(ctx);
+
+#ifdef ECHO_OUT
+    if (outCreated)
+        fclose(fout);
+#endif
+
+    ((func_args*)args)->return_code = 0;
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("echoserver") || CurrentDir("build"))
+            ChangeDirBack(2);
+        echoserver_test(&args);
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+        
+#endif /* NO_MAIN_DRIVER */
+
+
+
+

IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c

@@ -0,0 +1,94 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ctaocrypt/visibility.h>
+#include <cyassl/ctaocrypt/logging.h>
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+#include "rl_net.h" 
+#include <stdio.h>
+#include "cyassl_MDK_ARM.h"
+#include <cyassl/ssl.h>
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+  int32_t retv;
+
+  retv = finit ("M0:");
+  if (retv == 0) {
+    retv = fmount ("M0:");
+    if (retv == 0) {
+      printf ("Drive M0 ready!\n");
+    }
+    else {
+      printf ("Drive M0 mount failed!\n");
+    }
+  }
+  else {
+    printf ("Drive M0 initialization failed!\n");
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *        TCP/IP tasks
+ *----------------------------------------------------------------------------*/
+void tcp_poll (void const *arg)
+{
+    CYASSL_MSG("TCP polling started.\n") ;
+    while (1) {
+        net_main ();
+        osDelay(1) ;
+    }
+}
+
+extern void shell_main(void * args) ;
+extern void init_time(void) ;
+
+osThreadDef (tcp_poll, osPriorityHigh, 1, 0) ;
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+int myoptind = 0;
+char* myoptarg = NULL;
+
+int main() 
+{
+    void *arg = NULL ;
+    init_time() ;
+    init_filesystem ();
+    net_initialize() ;
+    osThreadCreate (osThread (tcp_poll), NULL); 
+    osDelay(10000) ;  /* wait for DHCP */
+    #if defined(DEBUG_CYASSL)
+         printf("Turning ON Debug message\n") ;
+         CyaSSL_Debugging_ON() ;
+    #endif
+
+    shell_main(arg) ;   
+
+}

IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c

@@ -0,0 +1,561 @@
+/* server.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include <cyassl/ctaocrypt/settings.h>
+
+#if !defined(CYASSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER)
+    /* in case memory tracker wants stats */
+    #define CYASSL_TRACK_MEMORY
+#endif
+
+#if defined(CYASSL_MDK_ARM)
+    #include <stdio.h>
+    #include <string.h>
+    
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+        #include "rl_fs.h" 
+        #include "rl_net.h" 
+    #else
+        #include "rtl.h"
+    #endif
+    
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#include <cyassl/openssl/ssl.h>
+
+#ifdef CYASSL_MDK_SHELL
+extern void exit_command(void) ;
+#define exit(code) exit_command() 
+#endif
+
+#include <cyassl/test.h>
+
+#include "examples/server/server.h"
+
+
+#ifdef CYASSL_CALLBACKS
+    int srvHandShakeCB(HandShakeInfo*);
+    int srvTimeoutCB(TimeoutInfo*);
+    Timeval srvTo;
+#endif
+
+static void NonBlockingSSL_Accept(SSL* ssl)
+{
+#ifndef CYASSL_CALLBACKS
+    int ret = SSL_accept(ssl);
+#else
+    int ret = CyaSSL_accept_ex(ssl, srvHandShakeCB, srvTimeoutCB, srvTo);
+#endif
+    int error = SSL_get_error(ssl, 0);
+    SOCKET_T sockfd = (SOCKET_T)CyaSSL_get_fd(ssl);
+    int select_ret;
+
+    while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ ||
+                                  error == SSL_ERROR_WANT_WRITE)) {
+        int currTimeout = 1;
+
+        if (error == SSL_ERROR_WANT_READ)
+            printf("... server would read block\n");
+        else
+            printf("... server would write block\n");
+
+#ifdef CYASSL_DTLS
+        currTimeout = CyaSSL_dtls_get_current_timeout(ssl);
+#endif
+        select_ret = tcp_select(sockfd, currTimeout);
+
+        if ((select_ret == TEST_RECV_READY) ||
+                                        (select_ret == TEST_ERROR_READY)) {
+            #ifndef CYASSL_CALLBACKS
+                ret = SSL_accept(ssl);
+            #else
+                ret = CyaSSL_accept_ex(ssl,
+                                    srvHandShakeCB, srvTimeoutCB, srvTo);
+            #endif
+            error = SSL_get_error(ssl, 0);
+        }
+        else if (select_ret == TEST_TIMEOUT && !CyaSSL_dtls(ssl)) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#ifdef CYASSL_DTLS
+        else if (select_ret == TEST_TIMEOUT && CyaSSL_dtls(ssl) &&
+                                            CyaSSL_dtls_got_timeout(ssl) >= 0) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#endif
+        else {
+            error = SSL_FATAL_ERROR;
+        }
+    }
+    if (ret != SSL_SUCCESS)
+        err_sys("SSL_accept failed");
+}
+
+
+static void Usage(void)
+{
+    printf("server "    LIBCYASSL_VERSION_STRING
+           " NOTE: All files relative to CyaSSL home dir\n");
+    printf("-?          Help, print this usage\n");
+    printf("-p <num>    Port to listen on, not 0, default %d\n", yasslPort);
+    printf("-v <num>    SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n",
+                                 SERVER_DEFAULT_VERSION);
+    printf("-l <str>    Cipher list\n");
+    printf("-c <file>   Certificate file,           default %s\n", svrCert);
+    printf("-k <file>   Key file,                   default %s\n", svrKey);
+    printf("-A <file>   Certificate Authority file, default %s\n", cliCert);
+    printf("-d          Disable client cert check\n");
+    printf("-b          Bind to any interface instead of localhost only\n");
+    printf("-s          Use pre Shared keys\n");
+    printf("-t          Track CyaSSL memory use\n");
+    printf("-u          Use UDP DTLS,"
+           " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n");
+    printf("-f          Fewer packets/group messages\n");
+    printf("-N          Use Non-blocking sockets\n");
+    printf("-S <str>    Use Host Name Indication\n");
+}
+
+THREAD_RETURN CYASSL_THREAD server_test(void* args)
+{
+    SOCKET_T sockfd   = 0;
+    SOCKET_T clientfd = 0;
+
+    SSL_METHOD* method = 0;
+    SSL_CTX*    ctx    = 0;
+    SSL*        ssl    = 0;
+
+    char   msg[] = "I hear you fa shizzle!";
+    char   input[80];
+    int    idx;
+    int    ch;
+    int    version = SERVER_DEFAULT_VERSION;
+    int    doCliCertCheck = 1;
+    int    useAnyAddr = 0;
+    int    port = yasslPort;
+    int    usePsk = 0;
+    int    doDTLS = 0;
+    int    useNtruKey   = 0;
+    int    nonBlocking  = 0;
+    int    trackMemory  = 0;
+    int    fewerPackets = 0;
+    char*  cipherList = NULL;
+    char*  verifyCert = (char*)cliCert;
+    char*  ourCert    = (char*)svrCert;
+    char*  ourKey     = (char*)svrKey;
+    int    argc = ((func_args*)args)->argc;
+    char** argv = ((func_args*)args)->argv;
+
+#ifdef HAVE_SNI
+    char*  sniHostName = NULL;
+#endif
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef NO_RSA
+    verifyCert = (char*)cliEccCert;
+    ourCert    = (char*)eccCert;
+    ourKey     = (char*)eccKey;
+#endif
+    (void)trackMemory;
+
+    while ((ch = mygetopt(argc, argv, "?dbstnNufp:v:l:A:c:k:S:")) != -1) {
+        switch (ch) {
+            case '?' :
+                Usage();
+                exit(EXIT_SUCCESS);
+
+            case 'd' :
+                doCliCertCheck = 0;
+                break;
+
+            case 'b' :
+                useAnyAddr = 1;
+                break;
+
+            case 's' :
+                usePsk = 1;
+                break;
+
+            case 't' :
+            #ifdef USE_CYASSL_MEMORY
+                trackMemory = 1;
+            #endif
+                break;
+
+            case 'n' :
+                useNtruKey = 1;
+                break;
+
+            case 'u' :
+                doDTLS  = 1;
+                break;
+
+            case 'f' :
+                fewerPackets = 1;
+                break;
+
+            case 'p' :
+                port = atoi(myoptarg);
+                #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API)
+                    if (port == 0)
+                        err_sys("port number cannot be 0");
+                #endif
+                break;
+
+            case 'v' :
+                version = atoi(myoptarg);
+                if (version < 0 || version > 3) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'l' :
+                cipherList = myoptarg;
+                break;
+
+            case 'A' :
+                verifyCert = myoptarg;
+                break;
+
+            case 'c' :
+                ourCert = myoptarg;
+                break;
+
+            case 'k' :
+                ourKey = myoptarg;
+                break;
+
+            case 'N':
+                nonBlocking = 1;
+                break;
+
+            case 'S' :
+                #ifdef HAVE_SNI
+                    sniHostName = myoptarg;
+                #endif
+                break;
+
+            default:
+                Usage();
+                exit(MY_EX_USAGE);
+        }
+    }
+
+    myoptind = 0;      /* reset for test cases */
+
+    /* sort out DTLS versus TLS versions */
+    if (version == CLIENT_INVALID_VERSION) {
+        if (doDTLS)
+            version = CLIENT_DTLS_DEFAULT_VERSION;
+        else
+            version = CLIENT_DEFAULT_VERSION;
+    }
+    else {
+        if (doDTLS) {
+            if (version == 3)
+                version = -2;
+            else
+                version = -1;
+        }
+    }
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        InitMemoryTracker(); 
+#endif
+
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case 0:
+            method = SSLv3_server_method();
+            break;
+
+    #ifndef NO_TLS
+        case 1:
+            method = TLSv1_server_method();
+            break;
+
+
+        case 2:
+            method = TLSv1_1_server_method();
+            break;
+
+        #endif
+#endif
+
+#ifndef NO_TLS
+        case 3:
+            method = TLSv1_2_server_method();
+            break;
+#endif
+                
+#ifdef CYASSL_DTLS
+        case -1:
+            method = DTLSv1_server_method();
+            break;
+
+        case -2:
+            method = DTLSv1_2_server_method();
+            break;
+#endif
+
+        default:
+            err_sys("Bad SSL version");
+    }
+
+    if (method == NULL)
+        err_sys("unable to get method");
+
+    ctx = SSL_CTX_new(method);
+    if (ctx == NULL)
+        err_sys("unable to get ctx");
+
+    if (cipherList)
+        if (SSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS)
+            err_sys("server can't set cipher list 1");
+
+#ifdef CYASSL_LEANPSK
+    usePsk = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    usePsk = 1;
+#endif
+
+#ifdef OPENSSL_EXTRA
+    SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+    if (fewerPackets)
+        CyaSSL_CTX_set_group_messages(ctx);
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!usePsk) {
+        if (SSL_CTX_use_certificate_file(ctx, ourCert, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server cert file, check file and run from"
+                    " CyaSSL home dir");
+    }
+#endif
+
+#ifdef HAVE_NTRU
+    if (useNtruKey) {
+        if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ourKey)
+                                               != SSL_SUCCESS)
+            err_sys("can't load ntru key file, "
+                    "Please run from CyaSSL home dir");
+    }
+#endif
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!useNtruKey && !usePsk) {
+        if (SSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server cert file, check file and run from"
+                " CyaSSL home dir");
+    }
+#endif
+
+    if (usePsk) {
+#ifndef NO_PSK
+        SSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb);
+        SSL_CTX_use_psk_identity_hint(ctx, "cyassl server");
+        if (cipherList == NULL) {
+            const char *defaultCipherList;
+            #ifdef HAVE_NULL_CIPHER
+                defaultCipherList = "PSK-NULL-SHA256";
+            #else
+                defaultCipherList = "PSK-AES128-CBC-SHA256";
+            #endif
+            if (SSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS)
+                err_sys("server can't set cipher list 2");
+        }
+#endif
+    }
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    /* if not using PSK, verify peer with certs */
+    if (doCliCertCheck && usePsk == 0) {
+        SSL_CTX_set_verify(ctx, SSL_VERIFY_PEER |
+                                SSL_VERIFY_FAIL_IF_NO_PEER_CERT,0);
+        if (SSL_CTX_load_verify_locations(ctx, verifyCert, 0) != SSL_SUCCESS)
+            err_sys("can't load ca file, Please run from CyaSSL home dir");
+    }
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    /* don't use EDH, can't sniff tmp keys */
+    if (cipherList == NULL) {
+        if (SSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS)
+            err_sys("server can't set cipher list 3");
+    }
+#endif
+
+#ifdef HAVE_SNI
+    if (sniHostName) {
+        if (CyaSSL_CTX_UseSNI(ctx, CYASSL_SNI_HOST_NAME, sniHostName,
+                                           XSTRLEN(sniHostName)) != SSL_SUCCESS)
+            err_sys("UseSNI failed");
+        else
+            CyaSSL_CTX_SNI_SetOptions(ctx, CYASSL_SNI_HOST_NAME,
+                                                  CYASSL_SNI_ABORT_ON_MISMATCH);
+    }
+#endif
+
+    ssl = SSL_new(ctx);
+    if (ssl == NULL)
+        err_sys("unable to get SSL");
+    CyaSSL_set_quiet_shutdown(ssl, 1) ;
+#ifdef HAVE_CRL
+    CyaSSL_EnableCRL(ssl, 0);
+    CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, CYASSL_CRL_MONITOR |
+                                                     CYASSL_CRL_START_MON);
+    CyaSSL_SetCRL_Cb(ssl, CRL_CallBack);
+#endif
+        osDelay(5000) ;
+    tcp_accept(&sockfd, &clientfd, (func_args*)args, port, useAnyAddr, doDTLS);
+    if (!doDTLS) 
+        CloseSocket(sockfd);
+
+    SSL_set_fd(ssl, clientfd);
+    if (usePsk == 0) {
+        #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA)
+            CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM);
+        #elif !defined(NO_CERTS)
+            SetDH(ssl);  /* repick suites with DHE, higher priority than PSK */
+        #endif
+    }
+        osDelay(5000) ;
+#ifndef CYASSL_CALLBACKS
+    if (nonBlocking) {
+        CyaSSL_set_using_nonblock(ssl, 1);
+        tcp_set_nonblocking(&clientfd);
+        NonBlockingSSL_Accept(ssl);
+    } else if (SSL_accept(ssl) != SSL_SUCCESS) {
+        int err = SSL_get_error(ssl, 0);
+        char buffer[80];
+        printf("error = %d, %s\n", err, ERR_error_string(err, buffer));
+        err_sys("SSL_accept failed");
+    }
+#else
+    NonBlockingSSL_Accept(ssl);
+#endif
+    showPeer(ssl);
+        osDelay(5000) ;
+    idx = SSL_read(ssl, input, sizeof(input)-1);
+    if (idx > 0) {
+        input[idx] = 0;
+        printf("Client message: %s\n", input);
+
+    }
+    else if (idx < 0) {
+        int readErr = SSL_get_error(ssl, 0);
+        if (readErr != SSL_ERROR_WANT_READ)
+            err_sys("SSL_read failed");
+    }
+
+    if (SSL_write(ssl, msg, sizeof(msg)) != sizeof(msg))
+        err_sys("SSL_write failed");
+        
+    SSL_shutdown(ssl);
+    SSL_free(ssl);
+    SSL_CTX_free(ctx);
+    
+    CloseSocket(clientfd);
+    ((func_args*)args)->return_code = 0;
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        ShowMemoryTracker();
+#endif /* USE_CYASSL_MEMORY */
+
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("server") || CurrentDir("build"))
+            ChangeDirBack(2);
+   
+#ifdef HAVE_STACK_SIZE
+        StackSizeCheck(&args, server_test);
+#else 
+        server_test(&args);
+#endif
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+    int myoptind = 0;
+    char* myoptarg = NULL;
+
+#endif /* NO_MAIN_DRIVER */
+
+
+#ifdef CYASSL_CALLBACKS
+
+    int srvHandShakeCB(HandShakeInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+
+    int srvTimeoutCB(TimeoutInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+#endif
+

IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c

@@ -0,0 +1,661 @@
+/*shell.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+ /*** tiny Shell for CyaSSL apps ***/
+ 
+ #ifdef HAVE_CONFIG_H
+    #include <config.h>
+#endif
+
+#include "cyassl/internal.h"
+#undef RNG
+#include <cyassl/ctaocrypt/logging.h>
+
+#if defined(CYASSL_MDK_ARM)
+    #include <stdio.h>
+    #include <string.h>
+    #include <stdlib.h>
+        #if defined(CYASSL_MDK5)
+            #include "cmsis_os.h"
+        #include "rl_fs.h" 
+    #else
+            #include <rtl.h>
+        #endif
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#ifdef CYASSL_KEIL_NET
+#include "cyassl/test.h"
+#else
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+#endif
+
+#ifdef NO_ECHOCLIENT
+#define echoclient_test command_not_found
+#endif
+#ifdef NO_ECHOSERVER
+#define echoserver_test command_not_found
+#endif
+#ifdef NO_SIMPLE_CLIENT
+#define client_test command_not_found
+#endif
+#ifdef NO_SIMPLE_SERVER
+#define server_test command_not_found
+#endif
+#ifdef NO_CRYPT_BENCHMARK
+#define benchmark_test command_not_found
+#endif
+#ifdef NO_CRYPT_TEST
+#define ctaocrypt_test command_not_found
+#endif
+
+#ifndef CYASSL_KEIL_NET
+#define ipaddr_comm command_not_found
+#endif
+
+#if !defined(HAVE_KEIL_RTX)
+#define stack_comm command_not_found
+#endif
+
+
+#if !defined(DEBUG_CYASSL)
+#define dbg_comm command_not_found
+#endif
+
+
+void command_not_found(void *argv) {
+        printf("Command not found\n") ;
+}
+
+extern void echoclient_test(void *args) ;
+extern void echoserver_test(void *args) ;
+extern void benchmark_test(void *args) ;
+extern void ctaocrypt_test(void *args) ;
+extern void client_test(void *args) ;
+extern void server_test(void *args) ;
+extern void kill_task(void *args) ;
+extern void time_main(void *args) ;
+extern void ipaddr_comm(void *args) ;
+extern void stack_comm(void *args) ;
+extern void for_command(void *args) ;
+extern void dbg_comm(void *arg) ;
+extern void help_comm(void *arg) ;
+
+#if !defined(NO_CRYPT_TEST)
+
+#ifndef NO_MD5
+extern void md5_test(void *arg) ;
+#endif
+#ifdef CYASSL_MD2
+extern void md2_test(void *arg) ;
+#endif
+#ifndef NO_MD4
+extern void md4_test(void *arg) ;
+#endif
+
+extern void sha_test(void *arg) ;
+
+#ifndef NO_SHA256
+extern void sha256_test(void *arg) ;
+#endif
+#ifdef CYASSL_SHA384
+extern void sha384_test(void *arg) ;
+#endif
+
+#ifdef CYASSL_SHA512
+extern void sha512_test(void *arg) ;
+#endif
+
+#ifdef CYASSL_RIPEMD
+extern void ripemd_test(void *arg) ;
+#endif
+#ifndef NO_HMAC
+    #ifndef NO_MD5
+extern void hmac_md5_test(void *arg) ;
+    #endif
+extern void hmac_sha_test(void *arg) ;
+
+    #ifndef NO_SHA256
+extern void hmac_sha256_test(void *arg) ;
+    #endif
+
+    #ifdef CYASSL_SHA384
+extern void hmac_sha384_test(void *arg) ;
+    #endif
+#endif
+#ifndef NO_RC4
+extern void arc4_test(void *arg) ;
+#endif
+
+#ifndef NO_HC128
+extern void hc128_test(void *arg) ;
+#endif
+
+#ifndef NO_RABBIT
+extern void rabbit_test(void *arg) ;
+#endif
+
+#ifndef NO_DES3
+extern void des_test(void *arg) ;
+extern void des3_test(void *arg) ;
+#endif
+
+#ifndef NO_AES
+extern void aes_test(void *arg) ;
+#ifdef HAVE_AESGCM
+extern void aesgcm_test(void *arg) ;
+#endif
+
+#ifdef HAVE_AESCCM
+extern void aesccm_test(void *arg) ;
+#endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+extern void camellia_test(void *arg) ;
+#endif
+extern void random_test(void *arg) ;
+
+#ifndef NO_RSA
+extern void rsa_test(void *arg) ;
+#endif
+
+#ifndef NO_DH
+extern void dh_test(void *arg) ;
+#endif
+
+#ifndef NO_DSA
+extern void dsa_test(void *arg) ;
+#endif
+    
+#ifndef NO_PWDBASED
+extern void pwdbased_test(void *arg) ;
+#endif
+
+#ifdef OPENSSL_EXTRA
+extern void openssl_test(void *arg) ;
+#endif
+
+#ifdef HAVE_ECC
+extern void ecc_test(void *arg) ;
+#endif
+
+#endif /* NO_CRYPT_TEST */
+
+static struct {
+  const char *command ;
+    void (*func)(void *args) ;
+}   commandTable[] = {
+    "echoclient", echoclient_test,
+    "echoserver", echoserver_test,
+    "benchmark", benchmark_test,
+    "test", ctaocrypt_test,
+    "client", client_test,
+    "server", server_test,
+    "time", time_main,          /* get/set RTC:  [-d mm/dd/yyyy] [-t hh:mm:ss]*/
+    "ipaddr", ipaddr_comm,      /* TBD */
+    "stack", stack_comm,        /* On/Off check stack size */
+    "for", for_command,         /* iterate next command X times */
+    "debug", dbg_comm,          /* On/Off debug message  */
+    "help", help_comm,          /* Breif description about the commands */
+
+    /** short name **/
+    "ec", echoclient_test,
+    "es", echoserver_test,
+    "bm", benchmark_test,
+    "te", ctaocrypt_test,
+    "cl", client_test,
+    "sv", server_test,
+    "ip", ipaddr_comm,
+    "st", stack_comm,
+  "dbg", dbg_comm,
+    "?",    help_comm,
+
+/*** test suites ****/
+#if !defined(NO_CRYPT_TEST)
+#ifndef NO_MD5
+  "md5",  md5_test,
+#endif
+#ifdef CYASSL_MD2
+  "md2",  md2_test,
+#endif
+#ifndef NO_MD4
+  "md4",  md4_test,
+#endif
+  "sha",  sha_test,
+#ifndef NO_SHA256
+  "sha256",  sha256_test,
+#endif
+#ifdef CYASSL_SHA384
+  "sha384",  sha384_test,
+#endif
+#ifdef CYASSL_SHA512
+  "sha512",  sha512_test,
+#endif
+#ifdef CYASSL_RIPEMD
+  "ripemd",  ripemd_test,
+#endif
+#ifndef NO_HMAC
+  #ifndef NO_MD5
+  "hmac_md5",  hmac_md5_test,
+    #endif
+  "hmac_sha",  hmac_sha_test,
+    #ifndef NO_SHA256
+  "hmac_sha256",  hmac_sha256_test,
+    #endif
+    #ifdef CYASSL_SHA384
+  "hmac_sha384",  hmac_sha384_test,
+  #endif
+#endif
+#ifndef NO_RC4
+    "arc4",  arc4_test,
+#endif
+#ifndef NO_HC128
+  "hc128",  hc128_test,
+#endif
+#ifndef NO_RABBIT
+  "rabbit",  rabbit_test,
+#endif
+#ifndef NO_DES3
+  "des",  des_test,
+  "des3",  des3_test,
+#endif  
+#ifndef NO_AES  
+  "aes",  aes_test,
+    #ifdef HAVE_AESGCM
+  "aesgcm",  aesgcm_test,
+    #endif
+    #ifdef HAVE_AESCCM
+  "aesccm",  aesccm_test,
+    #endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+  "camellia",  camellia_test,
+#endif
+  "random",  random_test,
+#ifndef NO_RSA
+  "rsa",  rsa_test,
+#endif
+#ifndef NO_DH
+  "dh",  dh_test,
+#endif
+#ifndef NO_DSA
+    "dsa",  dsa_test,
+#endif 
+#ifndef NO_PWDBASED
+  "pwdbased",  pwdbased_test,
+#endif  
+#ifdef OPENSSL_EXTRA
+  "openssl",  openssl_test,
+#endif
+#ifdef HAVE_ECC
+  "ecc",  ecc_test,
+#endif
+
+#endif /* NO_CRYPT_TEST */
+
+    "",  NULL
+} ;
+
+enum jobtype { FORGROUND, BACKGROUND }  ;
+
+#define IF_DELIMITER(ch) ((ch) == ' ' || (ch) == '\n')
+
+static int BackGround = 0 ; /* 1: background job is running */
+
+/*******  Get Command Line *****************************/
+static int getline(char * line, int sz, func_args *args, int*bf_flg) 
+{
+    char * ret ;
+    int i ;
+    
+    #define MAXARGS 10
+    #define MAXARGLEN 30
+    static char *argv[MAXARGS] ;
+    args->argv = argv ;
+    
+    putchar('>') ;
+    fflush(stdout) ;
+    ret = fgets(line, sz, stdin) ;
+    
+    #define SHELL_ERROR_FGETS -102
+    if(ret != line) return(SHELL_ERROR_FGETS) ;
+    
+    if(line[strlen(line)-2] == '&') {
+        (*bf_flg) = BACKGROUND ;
+        line[strlen(line)-2] = '\n' ;
+    } else {
+        (*bf_flg) = FORGROUND ;
+    }
+    args->argc = 0 ;
+    for(i=0; i<sz; i++) {
+        args->argv[args->argc] = &(line[i]) ;
+        while(!IF_DELIMITER(line[i])) i++ ;
+        args->argc++ ;
+        if(line[i] == '\n') {
+            line[i]  = '\0' ;
+            break ;
+        } else {
+            line[i]  = '\0' ;
+        }
+    }
+    return i ;
+}
+
+
+/************* Embedded Shell Commands **********************************/
+#define IP_SIZE 16
+
+#ifdef CYASSL_KEIL_NET
+static void ipaddr_comm(void *args) 
+{
+    if(((func_args *)args)->argc == 1) {
+            printf("IP addr: %s, port %d\n", yasslIP, yasslPort) ;
+    } else {
+        if(BackGround != 0) {
+        printf("Cannot change IP addr while background server is running\n") ;
+        } else if(((func_args *)args)->argc == 3 && 
+                  ((func_args *)args)->argv[1][0] == '-'&& 
+                  ((func_args *)args)->argv[1][1] == 'a' ) {
+/*          strcpy(yasslIP, ((func_args *)args)->argv[2]) ; */
+        } else if(((func_args *)args)->argc == 3 && 
+                  ((func_args *)args)->argv[1][0] == '-' && 
+                  ((func_args *)args)->argv[1][1] == 'p' ) {
+/*          yasslPort = atoi(((func_args *)args)->argv[2]) ; */
+        } else printf("Invalid argument\n") ; 
+    }
+}
+
+#endif
+
+
+
+#if defined(HAVE_KEIL_RTX)
+static int stack_ck = 0 ;
+
+void stack_comm(void *args) 
+{
+    if(stack_ck) {
+        printf("Stack Check: Off\n") ;
+        stack_ck = 0 ;
+    } else {
+        printf("Stack Check: On\n") ;
+        stack_ck = 1 ;
+    }
+}
+    
+#define FILL_PATTERN 0xa596695a
+void stack_fill(char * stack, int size)
+{
+    int i ;
+
+    if(stack_ck == 0)return ;
+    for(i=1; i<size/4-10; i++)
+        ((int *)stack)[i] = FILL_PATTERN ;
+}
+
+void stack_check(char * stack, int size) 
+{
+    int i ;
+    
+    if(stack_ck == 0)return ;
+    if(stack_ck == 1) {
+        stack_ck ++ ; return ; 
+    }
+    for(i=1; i<size/4 ; i++) {
+        if(((int *)stack)[i] != FILL_PATTERN) break ;
+    }
+    if(i < size/4) {
+        printf("Stack is used %d bytes out of %d\n", size - i*4, size) ;
+    } else {
+        printf("Stack overflow. Stack size: %d\n", size) ;
+    }
+}
+
+#endif /* HAVE_KEIL_RTX */
+
+static int for_iteration = 1 ;
+
+static void for_command(void *args) 
+{
+    if( args == NULL || ((func_args *)args)->argc == 1) {
+        printf("For %d times\n", for_iteration) ;
+    } else if( args == NULL || ((func_args *)args)->argc == 2) {
+        for_iteration = atoi(((func_args *)args)->argv[1]) ;
+    } else printf("Invalid argument\n") ;
+}
+
+
+#if defined(DEBUG_CYASSL)
+
+static int CyasslDebug = 1 ;
+
+static void dbg_comm(void *args) 
+{
+    if(CyasslDebug == 1) {
+        CyasslDebug = 0 ;
+        printf("Turning OFF Debug message\n") ;
+        CyaSSL_Debugging_OFF() ;
+    } else {
+        CyasslDebug = 1 ;
+        printf("Turning ON Debug message\n") ;
+        CyaSSL_Debugging_ON() ;
+    }
+}
+#endif
+
+static void help_comm(void *args) 
+{
+    static char *commands[] = {
+        "time [-d mm/dd/yyyy][-t hh:mm:ss]  : set/get time, for cert validation",
+        "test", 
+        "benchmark",
+        "echoserver&            : simple echo server in background mode",
+        "echoclient             : simple echo client followed by any input string, or \"quit\", \"break\"",
+        "server&                : simple server in background mode",
+        "client                 : simple client",
+        "client -g -v [0123] -h xxx.xxx.xxx.xxx -p 443  : usage example",
+        "server/client -h        :  help for server/client command",
+        "help",
+        ""  
+    } ;
+
+    int i ;
+    printf("Commands:\n") ;
+    for(i=0; commands[i][0] ; i++)
+        printf("    %s\n", commands[i]) ;
+
+}
+
+
+
+#define BG_JOB_STACK_SIZE 8000
+#if (!defined(NO_SIMPLE_SERVER) && !defined(NO_ECHOSERVER)) && \
+                                                   defined(HAVE_KEIL_RTX)
+#if !defined(CYASSL_CMSIS_RTOS)
+static char bg_job_stack[BG_JOB_STACK_SIZE] ;
+#endif
+
+#endif
+
+#define COMMAND_STACK_SIZE 10000
+#if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+static char command_stack[COMMAND_STACK_SIZE] ;
+#endif
+
+
+#ifdef  HAVE_KEIL_RTX
+static   CyaSSL_Mutex command_mutex ;
+#endif
+
+void exit_command(void) {
+	  printf("Command Aborted\n") ;
+    #ifdef CYASSL_CMSIS_RTOS
+        osThreadTerminate(osThreadGetId()) ;
+    #else
+        os_tsk_delete_self() ;
+    #endif
+}
+
+
+/***********    Invoke Forground Command  *********************/
+static void command_invoke(void const *args) 
+{
+    void (*func)(void const * ) ;
+    int i,iteration ;
+    
+    func = (void(*)(void const *))((func_args *)args)->argv[0] ; 
+    #ifdef  HAVE_KEIL_RTX
+    LockMutex((CyaSSL_Mutex *)&command_mutex) ;
+    #endif
+    iteration = for_iteration ;
+    for(i=0; i< iteration; i++) {
+        if(iteration > 1) printf("--- Start for %d ---->\n", i) ;
+        #if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+        stack_fill(command_stack, COMMAND_STACK_SIZE) ;
+        #endif
+                
+        func(args) ;        /* invoke command */
+                
+        #if defined(HAVE_KEIL_RTX)&& !defined(CYASSL_CMSIS_RTOS)
+        stack_check(command_stack, COMMAND_STACK_SIZE) ;
+        #endif
+    }
+
+    if(iteration > 1) 
+    for_iteration = 1 ;
+    osDelay(20000) ;
+    #ifdef HAVE_KEIL_RTX
+        UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+        #ifdef CYASSL_CMSIS_RTOS
+            osThreadTerminate(osThreadGetId()) ;
+        #else
+            os_tsk_delete_self() ;
+        #endif
+    #endif
+}
+
+#if defined(HAVE_KEIL_RTX)
+/*******  Invoke Background Job   *******************************/
+static void bg_job_invoke(void const *args) 
+{
+    void (*func)(void const * ) ;
+    BackGround = 1 ; 
+    #if defined(HAVE_KEIL_RTX)&& !defined(CYASSL_CMSIS_RTOS)
+    stack_fill(bg_job_stack, BG_JOB_STACK_SIZE) ;
+    #endif
+
+    func = (void(*)(void const *))((func_args *)args)->argv[0] ; 
+    func(args) ;        /* invoke command */
+    #if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+    stack_check(bg_job_stack, BG_JOB_STACK_SIZE) ;
+    #endif
+    
+    osDelay(20000) ;
+    BackGround = 0 ;
+
+    #ifdef CYASSL_CMSIS_RTOS
+        osThreadTerminate(osThreadGetId()) ;
+    #else   
+        os_tsk_delete_self() ; ;
+    #endif
+}
+#endif
+
+#define LINESIZE 100
+static char line[LINESIZE] ;
+
+#if defined(CYASSL_CMSIS_RTOS)
+    osThreadDef (command_invoke, osPriorityAboveNormal , 1, COMMAND_STACK_SIZE) ;
+    osThreadDef (bg_job_invoke, osPriorityNormal , 1 , BG_JOB_STACK_SIZE) ;
+#endif
+/********* SHEULL MAIN LOOP ***********************************/
+void shell_main(void *arg) {
+    int i ; 
+    func_args args ;
+    int bf_flg ;
+   
+    i = BackGround ; 
+        /* Dummy for avoiding warning: BackGround is defined but not used. */
+    
+ #if defined(HAVE_KEIL_RTX)
+    InitMutex(&command_mutex) ;
+#endif
+    time_main(NULL) ;
+    help_comm(NULL) ;
+    
+    printf("Starting Shell\n") ;
+    while(1) {
+        if(getline(line,  LINESIZE, &args, &bf_flg) > 0) {
+        for(i=0; commandTable[i].func != NULL; i++) {
+            if(strcmp(commandTable[i].command, args.argv[0]) == 0) {
+            args.argv[0] = (char *) commandTable[i].func ;
+                if(bf_flg == FORGROUND) {
+                    #if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+                        UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                        os_tsk_create_user_ex( (void(*)(void *))&command_invoke, 7,
+                             command_stack, COMMAND_STACK_SIZE, &args) ;
+                                      #else
+                                            #if defined(CYASSL_CMSIS_RTOS)
+                                UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                          osThreadCreate (osThread (command_invoke) , &args);   
+                          #else
+                          command_invoke(&args) ;
+                                            #endif
+                    #endif
+                    #ifdef  HAVE_KEIL_RTX
+                    LockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                    #endif
+                } else {
+                    #if (!defined(NO_SIMPLE_SERVER) && \
+                         !defined(NO_ECHOSERVER)) && \
+                         defined(HAVE_KEIL_RTX)
+                    if(BackGround != 0) {
+                        printf("Multiple background servers not supported.\n") ;
+                    } else {
+                        printf("\"%s\" is running with the background mode.\n", 
+                                                     commandTable[i].command) ;
+                        #if  defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+                             os_tsk_create_user_ex( (void(*)(void *))&bg_job_invoke, 
+                                   6, bg_job_stack, BG_JOB_STACK_SIZE, &args) ;
+                        #else
+                                osThreadCreate (osThread (bg_job_invoke),  &args); 
+                                osDelay (500) ;
+                        #endif
+                    }
+                    #else
+                    printf("Invalid Command: no background job\n") ;
+                    #endif
+                }
+                break ;
+            }
+        }
+        if(commandTable[i].func == NULL)
+            printf("Command not found\n") ;
+        }
+    }
+}
+

IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt

@@ -0,0 +1,22 @@
+This program is echo client with CyaSSL/wolfCrypt library.
+
+In order to run this program, 
+Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+Set config-EchoClient.h configuration file for the Callee IP or Port number.
+
+For further configuration, refer config-Crypt.h and config-CyaSSL.h.
+
+When testing this client, it is recommended to test against one of the standard 
+CyaSSL example applications running on a desktop machine.  The standard CyaSSL 
+example applications are located in the CyaSSL root directory under the 
+<cyassl_root>/examples directory.
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+
+Support
+-------
+Please send questions or comments to support@wolfssl.com

IDE/MDK5-ARM/Projects/EchoClient/RTE/CMSIS/RTX_Conf_CM.c

@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+//   <o>Number of concurrent running threads <0-250>
+//   <i> Defines max. number of threads that will run at the same time.
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     5
+#endif
+
+//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
+//   <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     250
+#endif
+
+//   <o>Main Thread stack size [bytes] <64-20000:8><#/4>
+//   <i> Defines stack size for main thread.
+//   <i> Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 2000
+#endif
+
+//   <o>Number of threads with user-provided stack size <0-250>
+//   <i> Defines the number of threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     2
+#endif
+
+//   <o>Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4>
+//   <i> Defines the combined stack size for threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 2500
+#endif
+
+// <q>Check for stack overflow
+// <i> Includes the stack checking code for stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// <o>Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// </h>
+
+// <h>RTX Kernel Timer Tick Configuration
+// ======================================
+// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
+// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   <o>Timer clock value [Hz] <1-1000000000>
+//   <i> Defines the timer clock value.
+//   <i> Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   <o>Timer tick value [us] <1-1000000>
+//   <i> Defines the timer tick value.
+//   <i> Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Defines how long a thread will execute before a thread switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// </e>
+
+// <e>User Timers
+// ==============
+//   <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   <o>Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//   <i> Defines priority for Timer Thread
+//   <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   <o>Timer Thread stack size [bytes] <64-64000:8><#/4>
+//   <i> Defines stack size for Timer thread.
+//   <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   <o>Timer Callback Queue size <1-32>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// </e>
+
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the interrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s

@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00007000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c

@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config.c

@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>File System
+// <i>Define File System global parameters
+
+//   <o>Number of open files <4-16>
+//   <i>Define number of files that can be
+//   <i>opened at the same time.
+//   <i>Default: 8
+#define NUM_FILES               8
+
+//   <o>FAT Name Cache Size <0-1000000>
+//   <i>Define number of cached FAT file or directory names.
+//   <i>48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   <e>Relocate FAT Name Cache Buffer
+//   <i>Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   </e>
+
+// </h>
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"

IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config_MC_0.h

@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Memory Card Drive 0
+// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   <o>Connect to hardware via Driver_MCI# <0-255>
+//   <i>Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   <o>Connect to hardware via Driver_SPI# <0-255>
+//   <i>Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   <o>Memory Card Interface Mode <0=>Native <1=>SPI
+//   <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   <i>since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Drive Cache stores data sectors and may be increased to speed-up
+//   <i>file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   <e>Locate Drive Cache and Drive Buffer
+//   <i>Some microcontrollers support DMA only in specific memory areas and
+//   <i>require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   </e>
+
+//   <q>Use FAT Journal
+//   <i>Protect File Allocation Table and Directory Entries for
+//   <i>fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   <q>Default Drive "M0:"
+//   <i>Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// </h>

IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config.c

@@ -0,0 +1,153 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>System Definitions
+// <i> Global Network System definitions
+//   <s.15>Local Host Name
+//   <i> This is the name under which embedded host can be
+//   <i> accessed on a local area network.
+//   <i> Default: "my_host"
+#define NET_HOST_NAME           "my_host"
+
+//   <o>Memory Pool size <1536-262144:4><#/4>
+//   <i> This is the size of a memory pool in bytes. Buffers for
+//   <i> Network packets are allocated from this memory pool.
+//   <i> Default: 12000 bytes
+#define NET_MEM_SIZE            3000
+
+// </h>
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef  RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_PPP_0
+#include "Net_Config_PPP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_PPP_1
+#include "Net_Config_PPP_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_SLIP_0
+#include "Net_Config_SLIP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_SLIP_1
+#include "Net_Config_SLIP_1.h"
+#endif
+
+#ifdef  RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef  RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef  RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef  RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef  RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef  RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef  RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef  RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef  RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef  RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef  RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+  \fn          void net_sys_error (ERROR_CODE error)
+  \ingroup     net_cores
+  \brief       Network system error handler.
+*/
+void net_sys_error (ERROR_CODE error) {
+  /* This function is called when a fatal error is encountered. */
+  /* The normal program execution is not possible anymore.      */
+
+  switch (error) {
+    case ERR_MEM_ALLOC:
+      /* Out of memory */
+      break;
+
+    case ERR_MEM_FREE:
+      /* Trying to release non existing memory block */
+      break;
+
+    case ERR_MEM_CORRUPT:
+      /* Memory Link pointer Corrupted */
+      /* More data written than the size of allocated mem block */
+      break;
+
+    case ERR_MEM_LOCK:
+      /* Locked Memory management function (alloc/free) re-entered */
+      break;
+
+    case ERR_UDP_ALLOC:
+      /* Out of UDP Sockets */
+      break;
+
+    case ERR_TCP_ALLOC:
+      /* Out of TCP Sockets */
+      break;
+
+    case ERR_TCP_STATE:
+      /* TCP State machine in undefined state */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+/**
+@}
+*/

IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_BSD.h

@@ -0,0 +1,36 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_BSD.h
+ * Purpose: Network Configuration BSD Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Berkley (BSD) Sockets
+#define BSD_ENABLE              1
+
+//   <o>Number of BSD Sockets <1-20>
+//   <i> Number of available Berkeley Sockets
+//   <i> Default: 2
+#define BSD_NUM_SOCKS           7
+
+//   <o>Number of Streaming Server Sockets <0-20>
+//   <i> Defines a number of Streaming (TCP) Server sockets,
+//   <i> that listen for an incoming connection from the client.
+//   <i> Default: 1
+#define BSD_SERVER_SOCKS        1
+
+//   <o>Receive Timeout in seconds <0-600>
+//   <i> A timeout for socket receive in blocking mode.
+//   <i> Timeout value of 0 means indefinite timeout.
+//   <i> Default: 20
+#define BSD_RECEIVE_TOUT        20
+
+//   <q>Hostname Resolver
+//   <i> Enable or disable Berkeley style hostname resolver.
+#define BSD_HOSTNAME_ENABLE     0
+
+// </h>

IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h

@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Service
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_DNS_Client.h
+ * Purpose: Network Configuration DNS Client
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>DNS Client
+#define DNS_CLIENT_ENABLE       1
+
+//     <o>Cache Table size <5-100>
+//     <i> Number of cached DNS host names/IP addresses
+//     <i> Default: 20
+#define DNS_CLIENT_TAB_SIZE     20
+
+// </h>