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ARM64 Windows: Add assembly

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Add assembly generated for Windows ARM64.
Add build option to project files.
Add CI loops.
This commit is contained in:
Sean Parkinson
2026-07-04 17:44:36 +10:00
parent af3befef80
commit 2bcb4efb5b
13 changed files with 53858 additions and 53668 deletions
Download Patch File Download Diff File Expand all files Collapse all files
wolfcrypt/src/fe_x25519_asm.asm
+18
View File
@@ -4631,6 +4631,15 @@ L_curve25519_x64_bits:
adc r11, r14
adc r12, r15
adc r13, rdi
mov rbp, 9223372036854775807
mov rax, r13
sar rax, 63
and rax, 19
and r13, rbp
add rcx, rax
adc r11, 0
adc r12, 0
adc r13, 0
; Store
mov QWORD PTR [rsp+64], rcx
mov QWORD PTR [rsp+72], r11
@@ -14299,6 +14308,15 @@ L_curve25519_avx2_bits:
adcx r13, rbx
adox r14, rsi
adcx r14, rcx
mov rcx, 9223372036854775807
mov rdx, r14
sar rdx, 63
and rdx, 19
and r14, rcx
add r11, rdx
adc r12, 0
adc r13, 0
adc r14, 0
; Store
mov QWORD PTR [rsp+64], r11
mov QWORD PTR [rsp+72], r12
wolfcrypt/src/port/arm/armv8-aes-asm.asm
+42673 -42673
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File diff suppressed because it is too large Load Diff
wolfcrypt/src/port/arm/armv8-chacha-asm.asm
+628 -628
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File diff suppressed because it is too large Load Diff
wolfcrypt/src/port/arm/armv8-curve25519.asm
+9 -1
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@@ -1696,7 +1696,7 @@ L_fe_invert8
ret
ENDP
IF :LNOT::DEF:HAVE_ED25519 :LAND: :LNOT::DEF:WOLFSSL_CURVE25519_USE_ED25519
AREA |.rodata|, DATA, READONLY
AREA |.rodata|, DATA, READONLY, ALIGN=4
ALIGN 16
L_curve25519_base_x2
DCQ 0x5cae469cdd684efb, 0x8f3f5ced1e350b5c
@@ -5047,6 +5047,14 @@ L_curve25519_bits
adcs x7, x7, x25
adcs x8, x8, x26
adc x9, x9, x27
; Reduce if top bit set
mov x3, #19
and x4, x3, x9, asr 63
adds x6, x6, x4
adcs x7, x7, xzr
and x9, x9, #0x7fffffffffffffff
adcs x8, x8, xzr
adc x9, x9, xzr
; Square
; A[0] * A[1]
umulh x16, x19, x20
wolfcrypt/src/port/arm/armv8-mlkem-asm.asm
+9107 -9107
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File diff suppressed because it is too large Load Diff
wolfcrypt/src/port/arm/armv8-poly1305-asm.asm
+198 -198
View File
@@ -106,221 +106,221 @@ poly1305_arm64_blocks PROC
stp x29, x30, [sp, #-96]!
add x29, sp, #0
str x17, [x29, #24]
stp d8, d9, [x29, #32]
stp d10, d11, [x29, #48]
stp d12, d13, [x29, #64]
stp d14, d15, [x29, #80]
stp D8, D9, [x29, #32]
stp D10, D11, [x29, #48]
stp D12, D13, [x29, #64]
stp D14, D15, [x29, #80]
cmp x2, #0x40
blt L_poly1305_arm64_blocks_done
; Set mask (0x3ffffff), hi bit and 5 into vector registers
movi v25.16b, #0xff
movi v27.4s, #1, lsl 24
ushr v25.4s, v25.4s, #6
movi v24.4s, #5
uxtl v26.2d, v25.2s
movi V25.16B, #0xff
movi V27.4S, #1, lsl 24
ushr V25.4S, V25.4S, #6
movi V24.4S, #5
ushll V26.2D, V25.2S, #0
add x14, x0, #16
ld4 {v15.4s, v16.4s, v17.4s, v18.4s}, [x14], #0x40
ld1 {v19.4s}, [x14]
ld4 {V15.4S, V16.4S, V17.4S, V18.4S}, [x14], #0x40
ld1 {V19.4S}, [x14]
add x14, x0, #0x60
movi v0.4s, #0
movi v1.4s, #0
movi v2.4s, #0
movi v3.4s, #0
movi v4.4s, #0
ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x14], #16
ld1 {v4.s}[0], [x14]
mul v20.4s, v16.4s, v24.4s
mul v21.4s, v17.4s, v24.4s
mul v22.4s, v18.4s, v24.4s
mul v23.4s, v19.4s, v24.4s
movi V0.4S, #0
movi V1.4S, #0
movi V2.4S, #0
movi V3.4S, #0
movi V4.4S, #0
ld4 {V0.S, V1.S, V2.S, V3.S}[0], [x14], #16
ld1 {V4.S}[0], [x14]
mul V20.4S, V16.4S, V24.4S
mul V21.4S, V17.4S, V24.4S
mul V22.4S, V18.4S, V24.4S
mul V23.4S, V19.4S, V24.4S
L_poly1305_arm64_blocks_loop_64
; Load message of 64 bytes - setting hi bit for not finished
ld4 {v5.4s, v6.4s, v7.4s, v8.4s}, [x1], #0x40
ld4 {V5.4S, V6.4S, V7.4S, V8.4S}, [x1], #0x40
sub x2, x2, #0x40
ushr v9.4s, v8.4s, #8
shl v8.4s, v8.4s, #18
orr v9.16b, v9.16b, v27.16b
sri v8.4s, v7.4s, #14
shl v7.4s, v7.4s, #12
and v8.16b, v8.16b, v25.16b
sri v7.4s, v6.4s, #20
shl v6.4s, v6.4s, #6
and v7.16b, v7.16b, v25.16b
sri v6.4s, v5.4s, #26
and v5.16b, v5.16b, v25.16b
and v6.16b, v6.16b, v25.16b
umull2 v10.2d, v5.4s, v15.4s
umull2 v11.2d, v5.4s, v16.4s
umull2 v12.2d, v5.4s, v17.4s
umull2 v13.2d, v5.4s, v18.4s
umull2 v14.2d, v5.4s, v19.4s
umlal2 v10.2d, v6.4s, v23.4s
umlal2 v11.2d, v6.4s, v15.4s
umlal2 v12.2d, v6.4s, v16.4s
umlal2 v13.2d, v6.4s, v17.4s
umlal2 v14.2d, v6.4s, v18.4s
umlal2 v10.2d, v7.4s, v22.4s
umlal2 v11.2d, v7.4s, v23.4s
umlal2 v12.2d, v7.4s, v15.4s
umlal2 v13.2d, v7.4s, v16.4s
umlal2 v14.2d, v7.4s, v17.4s
umlal2 v10.2d, v8.4s, v21.4s
umlal2 v11.2d, v8.4s, v22.4s
umlal2 v12.2d, v8.4s, v23.4s
umlal2 v13.2d, v8.4s, v15.4s
umlal2 v14.2d, v8.4s, v16.4s
umlal2 v10.2d, v9.4s, v20.4s
umlal2 v11.2d, v9.4s, v21.4s
umlal2 v12.2d, v9.4s, v22.4s
umlal2 v13.2d, v9.4s, v23.4s
umlal2 v14.2d, v9.4s, v15.4s
add v5.4s, v5.4s, v0.4s
add v6.4s, v6.4s, v1.4s
add v7.4s, v7.4s, v2.4s
add v8.4s, v8.4s, v3.4s
add v9.4s, v9.4s, v4.4s
umlal v10.2d, v5.2s, v15.2s
umlal v11.2d, v5.2s, v16.2s
umlal v12.2d, v5.2s, v17.2s
umlal v13.2d, v5.2s, v18.2s
umlal v14.2d, v5.2s, v19.2s
umlal v10.2d, v6.2s, v23.2s
umlal v11.2d, v6.2s, v15.2s
umlal v12.2d, v6.2s, v16.2s
umlal v13.2d, v6.2s, v17.2s
umlal v14.2d, v6.2s, v18.2s
umlal v10.2d, v7.2s, v22.2s
umlal v11.2d, v7.2s, v23.2s
umlal v12.2d, v7.2s, v15.2s
umlal v13.2d, v7.2s, v16.2s
umlal v14.2d, v7.2s, v17.2s
umlal v10.2d, v8.2s, v21.2s
umlal v11.2d, v8.2s, v22.2s
umlal v12.2d, v8.2s, v23.2s
umlal v13.2d, v8.2s, v15.2s
umlal v14.2d, v8.2s, v16.2s
umlal v10.2d, v9.2s, v20.2s
umlal v11.2d, v9.2s, v21.2s
umlal v12.2d, v9.2s, v22.2s
umlal v13.2d, v9.2s, v23.2s
umlal v14.2d, v9.2s, v15.2s
addp d10, v10.2d
addp d11, v11.2d
addp d12, v12.2d
addp d13, v13.2d
addp d14, v14.2d
ushr V9.4S, V8.4S, #8
shl V8.4S, V8.4S, #18
orr V9.16B, V9.16B, V27.16B
sri V8.4S, V7.4S, #14
shl V7.4S, V7.4S, #12
and V8.16B, V8.16B, V25.16B
sri V7.4S, V6.4S, #20
shl V6.4S, V6.4S, #6
and V7.16B, V7.16B, V25.16B
sri V6.4S, V5.4S, #26
and V5.16B, V5.16B, V25.16B
and V6.16B, V6.16B, V25.16B
umull2 V10.2D, V5.4S, V15.4S
umull2 V11.2D, V5.4S, V16.4S
umull2 V12.2D, V5.4S, V17.4S
umull2 V13.2D, V5.4S, V18.4S
umull2 V14.2D, V5.4S, V19.4S
umlal2 V10.2D, V6.4S, V23.4S
umlal2 V11.2D, V6.4S, V15.4S
umlal2 V12.2D, V6.4S, V16.4S
umlal2 V13.2D, V6.4S, V17.4S
umlal2 V14.2D, V6.4S, V18.4S
umlal2 V10.2D, V7.4S, V22.4S
umlal2 V11.2D, V7.4S, V23.4S
umlal2 V12.2D, V7.4S, V15.4S
umlal2 V13.2D, V7.4S, V16.4S
umlal2 V14.2D, V7.4S, V17.4S
umlal2 V10.2D, V8.4S, V21.4S
umlal2 V11.2D, V8.4S, V22.4S
umlal2 V12.2D, V8.4S, V23.4S
umlal2 V13.2D, V8.4S, V15.4S
umlal2 V14.2D, V8.4S, V16.4S
umlal2 V10.2D, V9.4S, V20.4S
umlal2 V11.2D, V9.4S, V21.4S
umlal2 V12.2D, V9.4S, V22.4S
umlal2 V13.2D, V9.4S, V23.4S
umlal2 V14.2D, V9.4S, V15.4S
add V5.4S, V5.4S, V0.4S
add V6.4S, V6.4S, V1.4S
add V7.4S, V7.4S, V2.4S
add V8.4S, V8.4S, V3.4S
add V9.4S, V9.4S, V4.4S
umlal V10.2D, V5.2S, V15.2S
umlal V11.2D, V5.2S, V16.2S
umlal V12.2D, V5.2S, V17.2S
umlal V13.2D, V5.2S, V18.2S
umlal V14.2D, V5.2S, V19.2S
umlal V10.2D, V6.2S, V23.2S
umlal V11.2D, V6.2S, V15.2S
umlal V12.2D, V6.2S, V16.2S
umlal V13.2D, V6.2S, V17.2S
umlal V14.2D, V6.2S, V18.2S
umlal V10.2D, V7.2S, V22.2S
umlal V11.2D, V7.2S, V23.2S
umlal V12.2D, V7.2S, V15.2S
umlal V13.2D, V7.2S, V16.2S
umlal V14.2D, V7.2S, V17.2S
umlal V10.2D, V8.2S, V21.2S
umlal V11.2D, V8.2S, V22.2S
umlal V12.2D, V8.2S, V23.2S
umlal V13.2D, V8.2S, V15.2S
umlal V14.2D, V8.2S, V16.2S
umlal V10.2D, V9.2S, V20.2S
umlal V11.2D, V9.2S, V21.2S
umlal V12.2D, V9.2S, V22.2S
umlal V13.2D, V9.2S, V23.2S
umlal V14.2D, V9.2S, V15.2S
addp D10, V10.2D
addp D11, V11.2D
addp D12, V12.2D
addp D13, V13.2D
addp D14, V14.2D
; Redistribute and handle overflow
usra v11.2d, v10.2d, #26
and v10.16b, v10.16b, v26.16b
usra v14.2d, v13.2d, #26
and v3.16b, v13.16b, v26.16b
ushr v2.2d, v14.2d, #26
usra v12.2d, v11.2d, #26
shl v0.2d, v2.2d, #2
and v1.16b, v11.16b, v26.16b
add v0.2d, v0.2d, v2.2d
and v4.16b, v14.16b, v26.16b
add v10.2d, v10.2d, v0.2d
usra v3.2d, v12.2d, #26
and v2.16b, v12.16b, v26.16b
usra v1.2d, v10.2d, #26
and v0.16b, v10.16b, v26.16b
usra v4.2d, v3.2d, #26
and v3.16b, v3.16b, v26.16b
usra V11.2D, V10.2D, #26
and V10.16B, V10.16B, V26.16B
usra V14.2D, V13.2D, #26
and V3.16B, V13.16B, V26.16B
ushr V2.2D, V14.2D, #26
usra V12.2D, V11.2D, #26
shl V0.2D, V2.2D, #2
and V1.16B, V11.16B, V26.16B
add V0.2D, V0.2D, V2.2D
and V4.16B, V14.16B, V26.16B
add V10.2D, V10.2D, V0.2D
usra V3.2D, V12.2D, #26
and V2.16B, V12.16B, V26.16B
usra V1.2D, V10.2D, #26
and V0.16B, V10.16B, V26.16B
usra V4.2D, V3.2D, #26
and V3.16B, V3.16B, V26.16B
cmp x2, #0x40
bge L_poly1305_arm64_blocks_loop_64
cmp x2, #16
ble L_poly1305_arm64_blocks_done_32
; Start 32
ld4 {v5.2s, v6.2s, v7.2s, v8.2s}, [x1], #32
ld4 {V5.2S, V6.2S, V7.2S, V8.2S}, [x1], #32
sub x2, x2, #32
mov v15.d[0], v15.d[1]
mov v16.d[0], v16.d[1]
mov v17.d[0], v17.d[1]
mov v18.d[0], v18.d[1]
mov v19.d[0], v19.d[1]
mov v20.d[0], v20.d[1]
mov v21.d[0], v21.d[1]
mov v22.d[0], v22.d[1]
mov v23.d[0], v23.d[1]
ushr v9.2s, v8.2s, #8
shl v8.2s, v8.2s, #18
orr v9.8b, v9.8b, v27.8b
sri v8.2s, v7.2s, #14
shl v7.2s, v7.2s, #12
and v8.8b, v8.8b, v25.8b
sri v7.2s, v6.2s, #20
shl v6.2s, v6.2s, #6
and v7.8b, v7.8b, v25.8b
sri v6.2s, v5.2s, #26
and v5.8b, v5.8b, v25.8b
and v6.8b, v6.8b, v25.8b
add v5.2s, v5.2s, v0.2s
add v6.2s, v6.2s, v1.2s
add v7.2s, v7.2s, v2.2s
add v8.2s, v8.2s, v3.2s
add v9.2s, v9.2s, v4.2s
umull v10.2d, v5.2s, v15.2s
umull v11.2d, v5.2s, v16.2s
umull v12.2d, v5.2s, v17.2s
umull v13.2d, v5.2s, v18.2s
umull v14.2d, v5.2s, v19.2s
umlal v10.2d, v6.2s, v23.2s
umlal v11.2d, v6.2s, v15.2s
umlal v12.2d, v6.2s, v16.2s
umlal v13.2d, v6.2s, v17.2s
umlal v14.2d, v6.2s, v18.2s
umlal v10.2d, v7.2s, v22.2s
umlal v11.2d, v7.2s, v23.2s
umlal v12.2d, v7.2s, v15.2s
umlal v13.2d, v7.2s, v16.2s
umlal v14.2d, v7.2s, v17.2s
umlal v10.2d, v8.2s, v21.2s
umlal v11.2d, v8.2s, v22.2s
umlal v12.2d, v8.2s, v23.2s
umlal v13.2d, v8.2s, v15.2s
umlal v14.2d, v8.2s, v16.2s
umlal v10.2d, v9.2s, v20.2s
umlal v11.2d, v9.2s, v21.2s
umlal v12.2d, v9.2s, v22.2s
umlal v13.2d, v9.2s, v23.2s
umlal v14.2d, v9.2s, v15.2s
addp d10, v10.2d
addp d11, v11.2d
addp d12, v12.2d
addp d13, v13.2d
addp d14, v14.2d
mov V15.D[0], V15.D[1]
mov V16.D[0], V16.D[1]
mov V17.D[0], V17.D[1]
mov V18.D[0], V18.D[1]
mov V19.D[0], V19.D[1]
mov V20.D[0], V20.D[1]
mov V21.D[0], V21.D[1]
mov V22.D[0], V22.D[1]
mov V23.D[0], V23.D[1]
ushr V9.2S, V8.2S, #8
shl V8.2S, V8.2S, #18
orr V9.8B, V9.8B, V27.8B
sri V8.2S, V7.2S, #14
shl V7.2S, V7.2S, #12
and V8.8B, V8.8B, V25.8B
sri V7.2S, V6.2S, #20
shl V6.2S, V6.2S, #6
and V7.8B, V7.8B, V25.8B
sri V6.2S, V5.2S, #26
and V5.8B, V5.8B, V25.8B
and V6.8B, V6.8B, V25.8B
add V5.2S, V5.2S, V0.2S
add V6.2S, V6.2S, V1.2S
add V7.2S, V7.2S, V2.2S
add V8.2S, V8.2S, V3.2S
add V9.2S, V9.2S, V4.2S
umull V10.2D, V5.2S, V15.2S
umull V11.2D, V5.2S, V16.2S
umull V12.2D, V5.2S, V17.2S
umull V13.2D, V5.2S, V18.2S
umull V14.2D, V5.2S, V19.2S
umlal V10.2D, V6.2S, V23.2S
umlal V11.2D, V6.2S, V15.2S
umlal V12.2D, V6.2S, V16.2S
umlal V13.2D, V6.2S, V17.2S
umlal V14.2D, V6.2S, V18.2S
umlal V10.2D, V7.2S, V22.2S
umlal V11.2D, V7.2S, V23.2S
umlal V12.2D, V7.2S, V15.2S
umlal V13.2D, V7.2S, V16.2S
umlal V14.2D, V7.2S, V17.2S
umlal V10.2D, V8.2S, V21.2S
umlal V11.2D, V8.2S, V22.2S
umlal V12.2D, V8.2S, V23.2S
umlal V13.2D, V8.2S, V15.2S
umlal V14.2D, V8.2S, V16.2S
umlal V10.2D, V9.2S, V20.2S
umlal V11.2D, V9.2S, V21.2S
umlal V12.2D, V9.2S, V22.2S
umlal V13.2D, V9.2S, V23.2S
umlal V14.2D, V9.2S, V15.2S
addp D10, V10.2D
addp D11, V11.2D
addp D12, V12.2D
addp D13, V13.2D
addp D14, V14.2D
; Redistribute and handle overflow
usra v11.2d, v10.2d, #26
and v10.16b, v10.16b, v26.16b
usra v14.2d, v13.2d, #26
and v3.16b, v13.16b, v26.16b
ushr v2.2d, v14.2d, #26
usra v12.2d, v11.2d, #26
shl v0.2d, v2.2d, #2
and v1.16b, v11.16b, v26.16b
add v0.2d, v0.2d, v2.2d
and v4.16b, v14.16b, v26.16b
add v10.2d, v10.2d, v0.2d
usra v3.2d, v12.2d, #26
and v2.16b, v12.16b, v26.16b
usra v1.2d, v10.2d, #26
and v0.16b, v10.16b, v26.16b
usra v4.2d, v3.2d, #26
and v3.16b, v3.16b, v26.16b
usra V11.2D, V10.2D, #26
and V10.16B, V10.16B, V26.16B
usra V14.2D, V13.2D, #26
and V3.16B, V13.16B, V26.16B
ushr V2.2D, V14.2D, #26
usra V12.2D, V11.2D, #26
shl V0.2D, V2.2D, #2
and V1.16B, V11.16B, V26.16B
add V0.2D, V0.2D, V2.2D
and V4.16B, V14.16B, V26.16B
add V10.2D, V10.2D, V0.2D
usra V3.2D, V12.2D, #26
and V2.16B, V12.16B, V26.16B
usra V1.2D, V10.2D, #26
and V0.16B, V10.16B, V26.16B
usra V4.2D, V3.2D, #26
and V3.16B, V3.16B, V26.16B
L_poly1305_arm64_blocks_done_32
cmp x2, #16
beq L_poly1305_arm64_blocks_transfer
add x14, x0, #0x60
st4 {v0.s, v1.s, v2.s, v3.s}[0], [x14], #16
st1 {v4.s}[0], [x14]
st4 {V0.S, V1.S, V2.S, V3.S}[0], [x14], #16
st1 {V4.S}[0], [x14]
b L_poly1305_arm64_blocks_done_all
L_poly1305_arm64_blocks_transfer
mov w3, v0.s[0]
mov w4, v1.s[0]
mov w5, v2.s[0]
mov w6, v3.s[0]
mov w7, v4.s[0]
mov w3, V0.S[0]
mov w4, V1.S[0]
mov w5, V2.S[0]
mov w6, V3.S[0]
mov w7, V4.S[0]
b L_poly1305_arm64_blocks_start
L_poly1305_arm64_blocks_done
cmp x2, #16
@@ -404,14 +404,14 @@ L_poly1305_arm64_blocks_loop
str w7, [x0, #112]
L_poly1305_arm64_blocks_done_all
ldr x17, [x29, #24]
ldp d8, d9, [x29, #32]
ldp d10, d11, [x29, #48]
ldp d12, d13, [x29, #64]
ldp d14, d15, [x29, #80]
ldp D8, D9, [x29, #32]
ldp D10, D11, [x29, #48]
ldp D12, D13, [x29, #64]
ldp D14, D15, [x29, #80]
ldp x29, x30, [sp], #0x60
ret
ENDP
AREA |.rodata|, DATA, READONLY
AREA |.rodata|, DATA, READONLY, ALIGN=4
ALIGN 8
L_poly1305_set_key_arm64_clamp
DCD 0x0fffffff, 0x0ffffffc, 0x0ffffffc, 0x0ffffffc
wolfcrypt/src/port/arm/armv8-sha256-asm.asm
+311 -311
View File
File diff suppressed because it is too large Load Diff
wolfcrypt/src/port/arm/armv8-sha3-asm.asm
+100 -100
View File
@@ -26,7 +26,7 @@
; ../wolfssl/wolfcrypt/src/port/arm/armv8-sha3-asm.asm
IF :DEF:WOLFSSL_SHA3
IF :DEF:WOLFSSL_ARMASM_CRYPTO_SHA3
AREA |.rodata|, DATA, READONLY
AREA |.rodata|, DATA, READONLY, ALIGN=4
ALIGN 16
L_SHA3_transform_crypto_r
DCQ 0x0000000000000001, 0x0000000000008082
@@ -47,120 +47,120 @@ L_SHA3_transform_crypto_r
BlockSha3_crypto PROC
stp x29, x30, [sp, #-80]!
add x29, sp, #0
stp d8, d9, [x29, #16]
stp d10, d11, [x29, #32]
stp d12, d13, [x29, #48]
stp d14, d15, [x29, #64]
stp D8, D9, [x29, #16]
stp D10, D11, [x29, #32]
stp D12, D13, [x29, #48]
stp D14, D15, [x29, #64]
adrp x1, L_SHA3_transform_crypto_r
add x1, x1, L_SHA3_transform_crypto_r
; .arch_extension sha3
ld4 {v0.d, v1.d, v2.d, v3.d}[0], [x0], #32
ld4 {v4.d, v5.d, v6.d, v7.d}[0], [x0], #32
ld4 {v8.d, v9.d, v10.d, v11.d}[0], [x0], #32
ld4 {v12.d, v13.d, v14.d, v15.d}[0], [x0], #32
ld4 {v16.d, v17.d, v18.d, v19.d}[0], [x0], #32
ld4 {v20.d, v21.d, v22.d, v23.d}[0], [x0], #32
ld1 {v24.1d}, [x0]
ld4 {V0.D, V1.D, V2.D, V3.D}[0], [x0], #32
ld4 {V4.D, V5.D, V6.D, V7.D}[0], [x0], #32
ld4 {V8.D, V9.D, V10.D, V11.D}[0], [x0], #32
ld4 {V12.D, V13.D, V14.D, V15.D}[0], [x0], #32
ld4 {V16.D, V17.D, V18.D, V19.D}[0], [x0], #32
ld4 {V20.D, V21.D, V22.D, V23.D}[0], [x0], #32
ld1 {V24.1D}, [x0]
sub x0, x0, #0xc0
mov x2, #24
; Start of 24 rounds
L_sha3_crypto_begin
; Col Mix
eor3 v31.16b, v0.16b, v5.16b, v10.16b
eor3 v27.16b, v1.16b, v6.16b, v11.16b
eor3 v28.16b, v2.16b, v7.16b, v12.16b
eor3 v29.16b, v3.16b, v8.16b, v13.16b
eor3 v30.16b, v4.16b, v9.16b, v14.16b
eor3 v31.16b, v31.16b, v15.16b, v20.16b
eor3 v27.16b, v27.16b, v16.16b, v21.16b
eor3 v28.16b, v28.16b, v17.16b, v22.16b
eor3 v29.16b, v29.16b, v18.16b, v23.16b
eor3 v30.16b, v30.16b, v19.16b, v24.16b
rax1 v25.2d, v30.2d, v27.2d
rax1 v26.2d, v31.2d, v28.2d
rax1 v27.2d, v27.2d, v29.2d
rax1 v28.2d, v28.2d, v30.2d
rax1 v29.2d, v29.2d, v31.2d
eor v0.16b, v0.16b, v25.16b
xar v30.2d, v1.2d, v26.2d, #63
xar v1.2d, v6.2d, v26.2d, #20
xar v6.2d, v9.2d, v29.2d, #44
xar v9.2d, v22.2d, v27.2d, #3
xar v22.2d, v14.2d, v29.2d, #25
xar v14.2d, v20.2d, v25.2d, #46
xar v20.2d, v2.2d, v27.2d, #2
xar v2.2d, v12.2d, v27.2d, #21
xar v12.2d, v13.2d, v28.2d, #39
xar v13.2d, v19.2d, v29.2d, #56
xar v19.2d, v23.2d, v28.2d, #8
xar v23.2d, v15.2d, v25.2d, #23
xar v15.2d, v4.2d, v29.2d, #37
xar v4.2d, v24.2d, v29.2d, #50
xar v24.2d, v21.2d, v26.2d, #62
xar v21.2d, v8.2d, v28.2d, #9
xar v8.2d, v16.2d, v26.2d, #19
xar v16.2d, v5.2d, v25.2d, #28
xar v5.2d, v3.2d, v28.2d, #36
xar v3.2d, v18.2d, v28.2d, #43
xar v18.2d, v17.2d, v27.2d, #49
xar v17.2d, v11.2d, v26.2d, #54
xar v11.2d, v7.2d, v27.2d, #58
xar v7.2d, v10.2d, v25.2d, #61
eor3 V31.16B, V0.16B, V5.16B, V10.16B
eor3 V27.16B, V1.16B, V6.16B, V11.16B
eor3 V28.16B, V2.16B, V7.16B, V12.16B
eor3 V29.16B, V3.16B, V8.16B, V13.16B
eor3 V30.16B, V4.16B, V9.16B, V14.16B
eor3 V31.16B, V31.16B, V15.16B, V20.16B
eor3 V27.16B, V27.16B, V16.16B, V21.16B
eor3 V28.16B, V28.16B, V17.16B, V22.16B
eor3 V29.16B, V29.16B, V18.16B, V23.16B
eor3 V30.16B, V30.16B, V19.16B, V24.16B
rax1 V25.2D, V30.2D, V27.2D
rax1 V26.2D, V31.2D, V28.2D
rax1 V27.2D, V27.2D, V29.2D
rax1 V28.2D, V28.2D, V30.2D
rax1 V29.2D, V29.2D, V31.2D
eor V0.16B, V0.16B, V25.16B
xar V30.2D, V1.2D, V26.2D, #63
xar V1.2D, V6.2D, V26.2D, #20
xar V6.2D, V9.2D, V29.2D, #44
xar V9.2D, V22.2D, V27.2D, #3
xar V22.2D, V14.2D, V29.2D, #25
xar V14.2D, V20.2D, V25.2D, #46
xar V20.2D, V2.2D, V27.2D, #2
xar V2.2D, V12.2D, V27.2D, #21
xar V12.2D, V13.2D, V28.2D, #39
xar V13.2D, V19.2D, V29.2D, #56
xar V19.2D, V23.2D, V28.2D, #8
xar V23.2D, V15.2D, V25.2D, #23
xar V15.2D, V4.2D, V29.2D, #37
xar V4.2D, V24.2D, V29.2D, #50
xar V24.2D, V21.2D, V26.2D, #62
xar V21.2D, V8.2D, V28.2D, #9
xar V8.2D, V16.2D, V26.2D, #19
xar V16.2D, V5.2D, V25.2D, #28
xar V5.2D, V3.2D, V28.2D, #36
xar V3.2D, V18.2D, V28.2D, #43
xar V18.2D, V17.2D, V27.2D, #49
xar V17.2D, V11.2D, V26.2D, #54
xar V11.2D, V7.2D, V27.2D, #58
xar V7.2D, V10.2D, V25.2D, #61
; Row Mix
mov v25.16b, v0.16b
mov v26.16b, v1.16b
bcax v0.16b, v25.16b, v2.16b, v26.16b
bcax v1.16b, v26.16b, v3.16b, v2.16b
bcax v2.16b, v2.16b, v4.16b, v3.16b
bcax v3.16b, v3.16b, v25.16b, v4.16b
bcax v4.16b, v4.16b, v26.16b, v25.16b
mov v25.16b, v5.16b
mov v26.16b, v6.16b
bcax v5.16b, v25.16b, v7.16b, v26.16b
bcax v6.16b, v26.16b, v8.16b, v7.16b
bcax v7.16b, v7.16b, v9.16b, v8.16b
bcax v8.16b, v8.16b, v25.16b, v9.16b
bcax v9.16b, v9.16b, v26.16b, v25.16b
mov v26.16b, v11.16b
bcax v10.16b, v30.16b, v12.16b, v26.16b
bcax v11.16b, v26.16b, v13.16b, v12.16b
bcax v12.16b, v12.16b, v14.16b, v13.16b
bcax v13.16b, v13.16b, v30.16b, v14.16b
bcax v14.16b, v14.16b, v26.16b, v30.16b
mov v25.16b, v15.16b
mov v26.16b, v16.16b
bcax v15.16b, v25.16b, v17.16b, v26.16b
bcax v16.16b, v26.16b, v18.16b, v17.16b
bcax v17.16b, v17.16b, v19.16b, v18.16b
bcax v18.16b, v18.16b, v25.16b, v19.16b
bcax v19.16b, v19.16b, v26.16b, v25.16b
mov v25.16b, v20.16b
mov v26.16b, v21.16b
bcax v20.16b, v25.16b, v22.16b, v26.16b
bcax v21.16b, v26.16b, v23.16b, v22.16b
bcax v22.16b, v22.16b, v24.16b, v23.16b
bcax v23.16b, v23.16b, v25.16b, v24.16b
bcax v24.16b, v24.16b, v26.16b, v25.16b
ld1r {v30.2d}, [x1], #8
mov V25.16B, V0.16B
mov V26.16B, V1.16B
bcax V0.16B, V25.16B, V2.16B, V26.16B
bcax V1.16B, V26.16B, V3.16B, V2.16B
bcax V2.16B, V2.16B, V4.16B, V3.16B
bcax V3.16B, V3.16B, V25.16B, V4.16B
bcax V4.16B, V4.16B, V26.16B, V25.16B
mov V25.16B, V5.16B
mov V26.16B, V6.16B
bcax V5.16B, V25.16B, V7.16B, V26.16B
bcax V6.16B, V26.16B, V8.16B, V7.16B
bcax V7.16B, V7.16B, V9.16B, V8.16B
bcax V8.16B, V8.16B, V25.16B, V9.16B
bcax V9.16B, V9.16B, V26.16B, V25.16B
mov V26.16B, V11.16B
bcax V10.16B, V30.16B, V12.16B, V26.16B
bcax V11.16B, V26.16B, V13.16B, V12.16B
bcax V12.16B, V12.16B, V14.16B, V13.16B
bcax V13.16B, V13.16B, V30.16B, V14.16B
bcax V14.16B, V14.16B, V26.16B, V30.16B
mov V25.16B, V15.16B
mov V26.16B, V16.16B
bcax V15.16B, V25.16B, V17.16B, V26.16B
bcax V16.16B, V26.16B, V18.16B, V17.16B
bcax V17.16B, V17.16B, V19.16B, V18.16B
bcax V18.16B, V18.16B, V25.16B, V19.16B
bcax V19.16B, V19.16B, V26.16B, V25.16B
mov V25.16B, V20.16B
mov V26.16B, V21.16B
bcax V20.16B, V25.16B, V22.16B, V26.16B
bcax V21.16B, V26.16B, V23.16B, V22.16B
bcax V22.16B, V22.16B, V24.16B, V23.16B
bcax V23.16B, V23.16B, V25.16B, V24.16B
bcax V24.16B, V24.16B, V26.16B, V25.16B
ld1r {V30.2D}, [x1], #8
subs x2, x2, #1
eor v0.16b, v0.16b, v30.16b
eor V0.16B, V0.16B, V30.16B
bne L_sha3_crypto_begin
st4 {v0.d, v1.d, v2.d, v3.d}[0], [x0], #32
st4 {v4.d, v5.d, v6.d, v7.d}[0], [x0], #32
st4 {v8.d, v9.d, v10.d, v11.d}[0], [x0], #32
st4 {v12.d, v13.d, v14.d, v15.d}[0], [x0], #32
st4 {v16.d, v17.d, v18.d, v19.d}[0], [x0], #32
st4 {v20.d, v21.d, v22.d, v23.d}[0], [x0], #32
st1 {v24.1d}, [x0]
ldp d8, d9, [x29, #16]
ldp d10, d11, [x29, #32]
ldp d12, d13, [x29, #48]
ldp d14, d15, [x29, #64]
st4 {V0.D, V1.D, V2.D, V3.D}[0], [x0], #32
st4 {V4.D, V5.D, V6.D, V7.D}[0], [x0], #32
st4 {V8.D, V9.D, V10.D, V11.D}[0], [x0], #32
st4 {V12.D, V13.D, V14.D, V15.D}[0], [x0], #32
st4 {V16.D, V17.D, V18.D, V19.D}[0], [x0], #32
st4 {V20.D, V21.D, V22.D, V23.D}[0], [x0], #32
st1 {V24.1D}, [x0]
ldp D8, D9, [x29, #16]
ldp D10, D11, [x29, #32]
ldp D12, D13, [x29, #48]
ldp D14, D15, [x29, #64]
ldp x29, x30, [sp], #0x50
ret
ENDP
ENDIF
AREA |.rodata|, DATA, READONLY
AREA |.rodata|, DATA, READONLY, ALIGN=4
ALIGN 16
L_SHA3_transform_base_r
DCQ 0x0000000000000001, 0x0000000000008082
wolfcrypt/src/port/arm/armv8-sha512-asm.asm
+648 -648
View File
File diff suppressed because it is too large Load Diff
wolfcrypt/src/wc_mldsa_asm.asm
+160
View File
@@ -27314,6 +27314,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27398,6 +27400,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27482,6 +27486,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27566,6 +27572,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27650,6 +27658,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27734,6 +27744,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27818,6 +27830,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27902,6 +27916,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -27986,6 +28002,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28070,6 +28088,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28154,6 +28174,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28238,6 +28260,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28322,6 +28346,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28406,6 +28432,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28490,6 +28518,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28574,6 +28604,8 @@ L_mldsa_use_hint_88_avx2_hints_done_0_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28659,6 +28691,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28743,6 +28777,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28827,6 +28863,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28911,6 +28949,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -28995,6 +29035,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29079,6 +29121,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29163,6 +29207,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29247,6 +29293,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29331,6 +29379,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29415,6 +29465,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29499,6 +29551,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29583,6 +29637,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29667,6 +29723,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29751,6 +29809,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29835,6 +29895,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -29919,6 +29981,8 @@ L_mldsa_use_hint_88_avx2_hints_done_1_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30004,6 +30068,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30088,6 +30154,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30172,6 +30240,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30256,6 +30326,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30340,6 +30412,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30424,6 +30498,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30508,6 +30584,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30592,6 +30670,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30676,6 +30756,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30760,6 +30842,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30844,6 +30928,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -30928,6 +31014,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31012,6 +31100,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31096,6 +31186,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31180,6 +31272,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31264,6 +31358,8 @@ L_mldsa_use_hint_88_avx2_hints_done_2_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31349,6 +31445,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31433,6 +31531,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31517,6 +31617,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31601,6 +31703,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31685,6 +31789,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31769,6 +31875,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31853,6 +31961,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -31937,6 +32047,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32021,6 +32133,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32105,6 +32219,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32189,6 +32305,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32273,6 +32391,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32357,6 +32477,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32441,6 +32563,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32525,6 +32649,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32609,6 +32735,8 @@ L_mldsa_use_hint_88_avx2_hints_done_3_15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32779,6 +32907,8 @@ L_mldsa_use_hint_32_avx2_hints_done__0:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32851,6 +32981,8 @@ L_mldsa_use_hint_32_avx2_hints_done__1:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32923,6 +33055,8 @@ L_mldsa_use_hint_32_avx2_hints_done__2:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -32995,6 +33129,8 @@ L_mldsa_use_hint_32_avx2_hints_done__3:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33067,6 +33203,8 @@ L_mldsa_use_hint_32_avx2_hints_done__4:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33139,6 +33277,8 @@ L_mldsa_use_hint_32_avx2_hints_done__5:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33211,6 +33351,8 @@ L_mldsa_use_hint_32_avx2_hints_done__6:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33283,6 +33425,8 @@ L_mldsa_use_hint_32_avx2_hints_done__7:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33355,6 +33499,8 @@ L_mldsa_use_hint_32_avx2_hints_done__8:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33427,6 +33573,8 @@ L_mldsa_use_hint_32_avx2_hints_done__9:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33499,6 +33647,8 @@ L_mldsa_use_hint_32_avx2_hints_done__10:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33571,6 +33721,8 @@ L_mldsa_use_hint_32_avx2_hints_done__11:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33643,6 +33795,8 @@ L_mldsa_use_hint_32_avx2_hints_done__12:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33715,6 +33869,8 @@ L_mldsa_use_hint_32_avx2_hints_done__13:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33787,6 +33943,8 @@ L_mldsa_use_hint_32_avx2_hints_done__14:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
@@ -33859,6 +34017,8 @@ L_mldsa_use_hint_32_avx2_hints_done__15:
vpsllvd ymm7, ymm7, ymm13
vpsrad ymm6, ymm6, 31
vpsrad ymm7, ymm7, 31
vpsubd ymm2, ymm2, ymm14
vpsubd ymm3, ymm3, ymm14
vpsrld ymm2, ymm2, 31
vpsrld ymm3, ymm3, 31
vpslld ymm2, ymm2, 1
wolfssl-VS2022.vcxproj
+1 -1
View File
@@ -76,7 +76,7 @@
the WOLFSSL_ARMASM* defines below); a symbol that is left undefined
here simply drops the matching assembly (safe - the C caller then uses
a C fallback), while a symbol enabled here but not in C is dead code. -->
<WolfSSLArmAsmDefs>--predefine "HAVE_AES_CBC SETL {TRUE}" --predefine "HAVE_AESCCM SETL {TRUE}" --predefine "HAVE_AESGCM SETL {TRUE}" --predefine "HAVE_AES_ECB SETL {TRUE}" --predefine "HAVE_AES_DECRYPT SETL {TRUE}" --predefine "WOLFSSL_AES_COUNTER SETL {TRUE}" --predefine "WOLFSSL_AES_DIRECT SETL {TRUE}" --predefine "WOLFSSL_AES_XTS SETL {TRUE}" --predefine "WOLFSSL_AESGCM_STREAM SETL {TRUE}" --predefine "WOLFSSL_SHA224 SETL {TRUE}" --predefine "WOLFSSL_SHA3 SETL {TRUE}" --predefine "WOLFSSL_ARMASM_CRYPTO_SHA3 SETL {TRUE}" --predefine "WOLFSSL_SHA384 SETL {TRUE}" --predefine "WOLFSSL_SHA512 SETL {TRUE}" --predefine "WOLFSSL_ARMASM_CRYPTO_SHA512 SETL {TRUE}" --predefine "HAVE_CHACHA SETL {TRUE}" --predefine "HAVE_CURVE25519 SETL {TRUE}" --predefine "HAVE_ED25519 SETL {TRUE}" --predefine "WOLFSSL_HAVE_MLKEM SETL {TRUE}"</WolfSSLArmAsmDefs>
<WolfSSLArmAsmDefs>-PreDefine "HAVE_AES_CBC SETL {TRUE}" -PreDefine "HAVE_AESCCM SETL {TRUE}" -PreDefine "HAVE_AESGCM SETL {TRUE}" -PreDefine "HAVE_AES_ECB SETL {TRUE}" -PreDefine "HAVE_AES_DECRYPT SETL {TRUE}" -PreDefine "WOLFSSL_AES_COUNTER SETL {TRUE}" -PreDefine "WOLFSSL_AES_DIRECT SETL {TRUE}" -PreDefine "WOLFSSL_AES_XTS SETL {TRUE}" -PreDefine "WOLFSSL_AESGCM_STREAM SETL {TRUE}" -PreDefine "WOLFSSL_SHA224 SETL {TRUE}" -PreDefine "WOLFSSL_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_SHA384 SETL {TRUE}" -PreDefine "WOLFSSL_SHA512 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA512 SETL {TRUE}" -PreDefine "HAVE_CHACHA SETL {TRUE}" -PreDefine "HAVE_CURVE25519 SETL {TRUE}" -PreDefine "HAVE_ED25519 SETL {TRUE}" -PreDefine "WOLFSSL_HAVE_MLKEM SETL {TRUE}"</WolfSSLArmAsmDefs>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
wolfssl.vcxproj
+1 -1
View File
@@ -75,7 +75,7 @@
the WOLFSSL_ARMASM* defines below); a symbol that is left undefined
here simply drops the matching assembly (safe - the C caller then uses
a C fallback), while a symbol enabled here but not in C is dead code. -->
<WolfSSLArmAsmDefs>--predefine "HAVE_AES_CBC SETL {TRUE}" --predefine "HAVE_AESCCM SETL {TRUE}" --predefine "HAVE_AESGCM SETL {TRUE}" --predefine "HAVE_AES_ECB SETL {TRUE}" --predefine "HAVE_AES_DECRYPT SETL {TRUE}" --predefine "WOLFSSL_AES_COUNTER SETL {TRUE}" --predefine "WOLFSSL_AES_DIRECT SETL {TRUE}" --predefine "WOLFSSL_AES_XTS SETL {TRUE}" --predefine "WOLFSSL_AESGCM_STREAM SETL {TRUE}" --predefine "WOLFSSL_SHA224 SETL {TRUE}" --predefine "WOLFSSL_SHA3 SETL {TRUE}" --predefine "WOLFSSL_ARMASM_CRYPTO_SHA3 SETL {TRUE}" --predefine "WOLFSSL_SHA384 SETL {TRUE}" --predefine "WOLFSSL_SHA512 SETL {TRUE}" --predefine "WOLFSSL_ARMASM_CRYPTO_SHA512 SETL {TRUE}" --predefine "HAVE_CHACHA SETL {TRUE}" --predefine "HAVE_CURVE25519 SETL {TRUE}" --predefine "HAVE_ED25519 SETL {TRUE}" --predefine "WOLFSSL_HAVE_MLKEM SETL {TRUE}"</WolfSSLArmAsmDefs>
<WolfSSLArmAsmDefs>-PreDefine "HAVE_AES_CBC SETL {TRUE}" -PreDefine "HAVE_AESCCM SETL {TRUE}" -PreDefine "HAVE_AESGCM SETL {TRUE}" -PreDefine "HAVE_AES_ECB SETL {TRUE}" -PreDefine "HAVE_AES_DECRYPT SETL {TRUE}" -PreDefine "WOLFSSL_AES_COUNTER SETL {TRUE}" -PreDefine "WOLFSSL_AES_DIRECT SETL {TRUE}" -PreDefine "WOLFSSL_AES_XTS SETL {TRUE}" -PreDefine "WOLFSSL_AESGCM_STREAM SETL {TRUE}" -PreDefine "WOLFSSL_SHA224 SETL {TRUE}" -PreDefine "WOLFSSL_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA3 SETL {TRUE}" -PreDefine "WOLFSSL_SHA384 SETL {TRUE}" -PreDefine "WOLFSSL_SHA512 SETL {TRUE}" -PreDefine "WOLFSSL_ARMASM_CRYPTO_SHA512 SETL {TRUE}" -PreDefine "HAVE_CHACHA SETL {TRUE}" -PreDefine "HAVE_CURVE25519 SETL {TRUE}" -PreDefine "HAVE_ED25519 SETL {TRUE}" -PreDefine "WOLFSSL_HAVE_MLKEM SETL {TRUE}"</WolfSSLArmAsmDefs>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
wolfssl/wolfcrypt/wc_port.h
+4
View File
@@ -1897,6 +1897,10 @@ WOLFSSL_ABI WOLFSSL_API int wolfCrypt_Cleanup(void);
#define XFENCE() XASM_VOLATILE("lfence")
#elif defined (__arm__) && (__ARM_ARCH > 6)
#define XFENCE() XASM_VOLATILE("isb")
#elif defined(_MSC_VER) && defined(_M_ARM64)
/* MSVC on ARM64 has no __asm__; use the ISB intrinsic barrier. */
#include <intrin.h>
#define XFENCE() __isb(_ARM64_BARRIER_SY)
#elif defined(__aarch64__)
/* Change ".inst 0xd50330ff" to "sb" when compilers support it. */
#ifdef WOLFSSL_ARMASM_BARRIER_SB