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Add STM32U3 hardware crypto support for AES, Hash and TRNG. Tested on NUCLEO-U385RG-Q.

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This commit is contained in:
David Garske
2026-04-30 07:46:19 -07:00
parent 43e44cb418
commit 31ae5d3efd
5 changed files with 30 additions and 16 deletions
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.wolfssl_known_macro_extras
+1
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@@ -563,6 +563,7 @@ STM32L552xx
STM32L562xx
STM32MP135Fxx
STM32N657xx
STM32U385xx
STM32U575xx
STM32U585xx
STM32U5A9xx
IDE/STM32Cube/README.md
+1
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@@ -97,6 +97,7 @@ The section for "Hardware platform" may need to be adjusted depending on your pr
* To enable STM32WB support define `WOLFSSL_STM32WB`.
* To enable STM32WBA support define `WOLFSSL_STM32WBA`.
* To enable STM32WL support define `WOLFSSL_STM32WL`.
* To enable STM32U3 support define `WOLFSSL_STM32U3`.
* To enable STM32U5 support define `WOLFSSL_STM32U5`.
* To enable STM32H5 support define `WOLFSSL_STM32H5`.
* To enable STM32MP13 support define `WOLFSSL_STM32MP13`.
IDE/STM32Cube/default_conf.ftl
+10 -2
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@@ -206,6 +206,14 @@ extern ${variable.value} ${variable.name};
#elif defined(STM32G491xx)
#define WOLFSSL_STM32G4
#define HAL_CONSOLE_UART hlpuart1
#elif defined(STM32U385xx)
#define WOLFSSL_STM32U3
#define STM32_HAL_V2
#undef NO_STM32_HASH
#undef NO_STM32_CRYPTO
#ifndef HAL_CONSOLE_UART
#define HAL_CONSOLE_UART huart1
#endif
#elif defined(STM32U575xx) || defined(STM32U585xx) || defined(STM32U5A9xx)
#define WOLFSSL_STM32U5
#define STM32_HAL_V2
@@ -250,8 +258,8 @@ extern ${variable.value} ${variable.name};
/* You need to define a CPU type, HW crypto and debug UART */
/* CPU Type: WOLFSSL_STM32F1, WOLFSSL_STM32F2, WOLFSSL_STM32F4,
WOLFSSL_STM32F7, WOLFSSL_STM32H7, WOLFSSL_STM32L4, WOLFSSL_STM32L5,
WOLFSSL_STM32G0, WOLFSSL_STM32G4, WOLFSSL_STM32WB, WOLFSSL_STM32U5 and
WOLFSSL_STM32MP13 */
WOLFSSL_STM32G0, WOLFSSL_STM32G4, WOLFSSL_STM32WB, WOLFSSL_STM32U3,
WOLFSSL_STM32U5 and WOLFSSL_STM32MP13 */
#define WOLFSSL_STM32F4
/* Debug UART used for printf */
wolfssl/wolfcrypt/port/st/stm32.h
+10 -9
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@@ -166,9 +166,10 @@ int wc_Stm32_Hmac_Final(STM32_HASH_Context* stmCtx, word32 algo,
#if !defined(STM32_CRYPTO_AES_GCM) && (defined(WOLFSSL_STM32F4) || \
defined(WOLFSSL_STM32F7) || defined(WOLFSSL_STM32L4) || \
defined(WOLFSSL_STM32L5) || defined(WOLFSSL_STM32H7) || \
defined(WOLFSSL_STM32U5) || defined(WOLFSSL_STM32H5) || \
defined(WOLFSSL_STM32MP13) || defined(WOLFSSL_STM32H7S) || \
defined(WOLFSSL_STM32N6) || defined(WOLFSSL_STM32G0))
defined(WOLFSSL_STM32U5) || defined(WOLFSSL_STM32U3) || \
defined(WOLFSSL_STM32H5) || defined(WOLFSSL_STM32MP13) || \
defined(WOLFSSL_STM32H7S) || defined(WOLFSSL_STM32N6) || \
defined(WOLFSSL_STM32G0))
/* Hardware supports AES GCM acceleration */
#define STM32_CRYPTO_AES_GCM
#endif
@@ -184,10 +185,10 @@ int wc_Stm32_Hmac_Final(STM32_HASH_Context* stmCtx, word32 algo,
#define STM32_HAL_V2
#endif
#if defined(WOLFSSL_STM32L4) || defined(WOLFSSL_STM32L5) || \
defined(WOLFSSL_STM32U5) || defined(WOLFSSL_STM32H5) || \
defined(WOLFSSL_STM32G0)
defined(WOLFSSL_STM32U5) || defined(WOLFSSL_STM32U3) || \
defined(WOLFSSL_STM32H5) || defined(WOLFSSL_STM32G0)
#if defined(WOLFSSL_STM32L4) || defined(WOLFSSL_STM32U5) || \
defined(WOLFSSL_STM32G0)
defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32G0)
#define STM32_CRYPTO_AES_ONLY /* crypto engine only supports AES */
#endif
#if defined(WOLFSSL_STM32H5)
@@ -204,9 +205,9 @@ int wc_Stm32_Hmac_Final(STM32_HASH_Context* stmCtx, word32 algo,
#if !defined(STM32_HAL_V2) && defined(CRYP_AES_GCM) && \
(defined(WOLFSSL_STM32F7) || defined(WOLFSSL_STM32L5) || \
defined(WOLFSSL_STM32H7) || defined(WOLFSSL_STM32U5) || \
defined(WOLFSSL_STM32H5) || defined(WOLFSSL_STM32MP13) || \
defined(WOLFSSL_STM32H7S) || defined(WOLFSSL_STM32N6) || \
defined(WOLFSSL_STM32G0))
defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32H5) || \
defined(WOLFSSL_STM32MP13) || defined(WOLFSSL_STM32H7S) || \
defined(WOLFSSL_STM32N6) || defined(WOLFSSL_STM32G0))
#define STM32_HAL_V2
#endif
wolfssl/wolfcrypt/settings.h
+8 -5
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@@ -2198,10 +2198,10 @@ extern void uITRON4_free(void *p) ;
defined(WOLFSSL_STM32L4) || defined(WOLFSSL_STM32L5) || \
defined(WOLFSSL_STM32WB) || defined(WOLFSSL_STM32H7) || \
defined(WOLFSSL_STM32G0) || defined(WOLFSSL_STM32U5) || \
defined(WOLFSSL_STM32H5) || defined(WOLFSSL_STM32WL) || \
defined(WOLFSSL_STM32G4) || defined(WOLFSSL_STM32MP13) || \
defined(WOLFSSL_STM32H7S) || defined(WOLFSSL_STM32WBA) || \
defined(WOLFSSL_STM32N6)
defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32H5) || \
defined(WOLFSSL_STM32WL) || defined(WOLFSSL_STM32G4) || \
defined(WOLFSSL_STM32MP13) || defined(WOLFSSL_STM32H7S) || \
defined(WOLFSSL_STM32WBA) || defined(WOLFSSL_STM32N6)
#define SIZEOF_LONG_LONG 8
#ifndef CHAR_BIT
@@ -2222,7 +2222,8 @@ extern void uITRON4_free(void *p) ;
#if defined(WOLFSSL_STM32L4) || defined(WOLFSSL_STM32L5) || \
defined(WOLFSSL_STM32WB) || defined(WOLFSSL_STM32U5) || \
defined(WOLFSSL_STM32WL) || defined(WOLFSSL_STM32WBA)
defined(WOLFSSL_STM32U3) || defined(WOLFSSL_STM32WL) || \
defined(WOLFSSL_STM32WBA)
#define NO_AES_192 /* hardware does not support 192-bit */
#endif
#endif
@@ -2267,6 +2268,8 @@ extern void uITRON4_free(void *p) ;
#include "stm32g4xx_hal.h"
#elif defined(WOLFSSL_STM32U5)
#include "stm32u5xx_hal.h"
#elif defined(WOLFSSL_STM32U3)
#include "stm32u3xx_hal.h"
#elif defined(WOLFSSL_STM32H5)
#include "stm32h5xx_hal.h"
#elif defined(WOLFSSL_STM32N6)