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Merge pull request #8965 from SparkiDev/ppc32_sha256_spe

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PPC32 ARM ASM SHA-256: SPE impl, tidy up original
This commit is contained in:
David Garske
2025-07-09 17:00:26 -07:00
committed by GitHub
parent 98adb330ef d6a72e2480
commit b2143a815f
3 changed files with 7599 additions and 2651 deletions
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7
configure.ac
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@@ -3562,6 +3562,9 @@ then
small) small)
ENABLED_PPC32_ASM_SMALL=yes ENABLED_PPC32_ASM_SMALL=yes
;; ;;
spe)
ENABLED_PPC32_ASM_SPE=yes
;;
*) *)
AC_MSG_ERROR([Invalid RISC-V option [yes,inline,small]: $ENABLED_PPC32_ASM.]) AC_MSG_ERROR([Invalid RISC-V option [yes,inline,small]: $ENABLED_PPC32_ASM.])
break break
@@ -3582,6 +3585,10 @@ if test "$ENABLED_PPC32_ASM_SMALL" = "yes"; then
AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM_SMALL" AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM_SMALL"
AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_PPC32_ASM_SMALL" AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_PPC32_ASM_SMALL"
fi fi
if test "$ENABLED_PPC32_ASM_SPE" = "yes"; then
AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM_SPE"
AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_PPC32_ASM_SPE"
fi
# Xilinx hardened crypto # Xilinx hardened crypto
AC_ARG_ENABLE([xilinx], AC_ARG_ENABLE([xilinx],

5152
wolfcrypt/src/port/ppc32/ppc32-sha256-asm.S
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5091
wolfcrypt/src/port/ppc32/ppc32-sha256-asm_c.c
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